URL
https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
Compare Revisions
- This comparison shows the changes necessary to convert path
/System09
- from Rev 113 to Rev 114
- ↔ Reverse comparison
Rev 113 → Rev 114
/trunk/rtl/System09_Xess_XSA-3S1000/my_system09.ut
File deleted
/trunk/rtl/System09_Xess_XSA-3S1000/my_system09.prj
File deleted
/trunk/rtl/System09_Xess_XSA-3S1000/my_system09.lso
File deleted
/trunk/rtl/System09_Xess_XSA-3S1000/my_system09.xst
File deleted
/trunk/rtl/System09_Xess_XSA-3S1000/my_system09.ise
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trunk/rtl/System09_Xess_XSA-3S1000/my_system09.ise
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Index: trunk/rtl/System09_Xess_XSA-3S1000/system09.ut
===================================================================
--- trunk/rtl/System09_Xess_XSA-3S1000/system09.ut (nonexistent)
+++ trunk/rtl/System09_Xess_XSA-3S1000/system09.ut (revision 114)
@@ -0,0 +1,28 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:6
+-g CclkPin:PullNone
+-g M0Pin:PullNone
+-g M1Pin:PullNone
+-g M2Pin:PullNone
+-g ProgPin:PullNone
+-g DonePin:PullNone
+-g TckPin:PullNone
+-g TdiPin:PullNone
+-g TdoPin:PullNone
+-g TmsPin:PullNone
+-g UnusedPin:PullNone
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g DCIUpdateMode:AsRequired
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Match_cycle:Auto
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
Index: trunk/rtl/System09_Xess_XSA-3S1000/system09.prj
===================================================================
--- trunk/rtl/System09_Xess_XSA-3S1000/system09.prj (nonexistent)
+++ trunk/rtl/System09_Xess_XSA-3S1000/system09.prj (revision 114)
@@ -0,0 +1,19 @@
+vhdl work "common.vhd"
+vhdl work "../VHDL/bit_funcs.vhd"
+vhdl work "../VHDL/ACIA_Clock.vhd"
+vhdl work "../Spartan3/keymap_rom512_b4.vhd"
+vhdl work "../../src/sys09bug/sys09xes.vhd"
+vhdl work "../../src/Flex9/flex9ide.vhd"
+vhdl work "../VHDL/ps2_keyboard.vhd"
+vhdl work "sdramcntl.vhd"
+vhdl work "../Spartan3/ram2k_b16.vhd"
+vhdl work "../Spartan3/char_rom2k_b16.vhd"
+vhdl work "../VHDL/vdu8.vhd"
+vhdl work "../VHDL/trap.vhd"
+vhdl work "../VHDL/timer.vhd"
+vhdl work "../VHDL/keyboard.vhd"
+vhdl work "../VHDL/datram.vhd"
+vhdl work "../VHDL/cpu09.vhd"
+vhdl work "../VHDL/acia6850.vhd"
+vhdl work "xsasdramcntl.vhd"
+vhdl work "System09_Xess_XSA-3S1000.vhd"
Index: trunk/rtl/System09_Xess_XSA-3S1000/system09.lso
===================================================================
--- trunk/rtl/System09_Xess_XSA-3S1000/system09.lso (nonexistent)
+++ trunk/rtl/System09_Xess_XSA-3S1000/system09.lso (revision 114)
@@ -0,0 +1 @@
+work
Index: trunk/rtl/System09_Xess_XSA-3S1000/system09.xst
===================================================================
--- trunk/rtl/System09_Xess_XSA-3S1000/system09.xst (nonexistent)
+++ trunk/rtl/System09_Xess_XSA-3S1000/system09.xst (revision 114)
@@ -0,0 +1,53 @@
+set -tmpdir "./xst/projnav.tmp"
+set -xsthdpdir "./xst"
+run
+-ifn system09.prj
+-ifmt mixed
+-ofn system09
+-ofmt NGC
+-p xc3s1000-4-ft256
+-top system09
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-lso system09.lso
+-keep_hierarchy NO
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract YES
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-mux_extract YES
+-resource_sharing YES
+-mult_style auto
+-iobuf YES
+-max_fanout 500
+-bufg 8
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
Index: trunk/rtl/System09_Xess_XSA-3S1000/system09.ise
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/rtl/System09_Xess_XSA-3S1000/system09.ise
===================================================================
--- trunk/rtl/System09_Xess_XSA-3S1000/system09.ise (nonexistent)
+++ trunk/rtl/System09_Xess_XSA-3S1000/system09.ise (revision 114)
trunk/rtl/System09_Xess_XSA-3S1000/system09.ise
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/rtl/System09_Xess_XSA-3S1000/Makefile
===================================================================
--- trunk/rtl/System09_Xess_XSA-3S1000/Makefile (revision 113)
+++ trunk/rtl/System09_Xess_XSA-3S1000/Makefile (revision 114)
@@ -38,7 +38,7 @@
#
# This name must match the name of the design in Xilinx ISE (case
# sensitive).
-DESIGN_NAME := my_system09
+DESIGN_NAME := system09
#
# Constraint file (unfortunately it cannot be extracted from ISE)
UCF_FILE := XSA-3S1000.ucf
Index: trunk/rtl/System09_Xess_XSA-3S1000/System09_Xess_XSA-3S1000.vhd
===================================================================
--- trunk/rtl/System09_Xess_XSA-3S1000/System09_Xess_XSA-3S1000.vhd (revision 113)
+++ trunk/rtl/System09_Xess_XSA-3S1000/System09_Xess_XSA-3S1000.vhd (revision 114)
@@ -136,7 +136,7 @@
library unisim;
use unisim.vcomponents.all;
-entity my_system09 is
+entity system09 is
port(
CLKA : in Std_Logic; -- 100MHz Clock input
SW2_N : in Std_logic; -- Master Reset input (active low)
@@ -206,12 +206,12 @@
-- Disable Flash
FLASH_CE_N : out std_logic
);
-end My_System09;
+end system09;
-------------------------------------------------------------------------------
-- Architecture for System09
-------------------------------------------------------------------------------
-architecture rtl of my_system09 is
+architecture rtl of system09 is
-----------------------------------------------------------------------------
-- constants