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URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

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Rev 7 → Rev 8

/execute.sv File deleted
/pla_decode.sv File deleted
/test_sequencer.sv
21,9 → 21,9
logic hold_clk_busrq_sig=0;
 
wire T6_sig;
wire M6_sig;
assign nextM_sig = T6_sig; // Restart when reaching T6
assign setM1_sig = M6_sig; // Restart when reaching M6
wire M5_sig;
assign nextM_sig = T6_sig; // Restart when reaching T6
assign setM1_sig = M5_sig & T6_sig; // Restart when reaching M5/T6
 
// ----------------- TEST -------------------
initial begin
54,7 → 54,6
.M3(M3_sig) , // output M3_sig
.M4(M4_sig) , // output M4_sig
.M5(M5_sig) , // output M5_sig
.M6(M6_sig) , // output M6_sig
.T1(T1_sig) , // output T1_sig
.T2(T2_sig) , // output T2_sig
.T3(T3_sig) , // output T3_sig
/timing_macros.i
1,20 → 1,21
//=========================================================================================
// This file contains substitute strings for macros used in the Excel timing table and
// is read and processed by genmatrix.py script to generate exec_matrix.vh include file.
// This file contains substitute strings for macro expansions. Macros are defined in an
// Excel timing spreadsheet 'Timings.xlsm' and exported to a .csv file which is then read
// and processed by genmatrix.py script to generate exec_matrix.vh include file.
//
// Format of the file:
// Macro format:
//
// * Each key is prefixed by ':' and corresponds to a spreadsheet column name.
// * A column (key) contains a number of macros, each starting at its own line.
// * A macro may span multiple lines, in which case use the '\' character after the name to
// continue on the next line.
// * Multiline macros end when a line does not _start_ with a space character.
// * Each key is prefixed by ':' and corresponds to a spreadsheet *column* name.
// * A key may contain several different macros, one per line.
// * A macro may span multiple lines; use the '\' character to continue on the next line.
// * Multi-line macros end when a line does not start with a space character.
// //-style comments are wrapped within /* ... */ if they don't start a line.
//=========================================================================================
 
//-----------------------------------------------------------------------------------------
// CPU machine state
//-----------------------------------------------------------------------------------------
:Function
//-----------------------------------------------------------------------------------------
//Fetch is M1
fMFetch
fMRead fMRead=1;
26,24 → 27,24
// Basic timing control
//-----------------------------------------------------------------------------------------
:valid
1 validPLA=1;
Y validPLA=1;
:nextM
1 nextM=1;
Y nextM=1;
mr nextM=1; ctl_mRead=1;
mw nextM=1; ctl_mWrite=1;
ior nextM=1; ctl_iorw=1;
iow nextM=1; ctl_iorw=1;
CC nextM=!flags_cond_true;
CC nextM=~flags_cond_true;
INT nextM=1; ctl_mRead=in_intr & im2; // RST38 interrupt extension
:setM1
1 setM1=1;
SS setM1=!flags_cond_true;
CC setM1=!flags_cond_true;
ZF setM1=flags_zf; // Used in DJNZ
BR setM1=nonRep | !repeat_en;
BRZ setM1=nonRep | !repeat_en | flags_zf;
Y setM1=1;
SS setM1=~flags_cond_true;
CC setM1=~flags_cond_true;
ZF setM1=flags_zf; // Used in DJNZ
BR setM1=nonRep | ~repeat_en;
BRZ setM1=nonRep | ~repeat_en | flags_zf;
BZ setM1=nonRep | flags_zf;
INT setM1=!(in_intr & im2); // RST38 interrupt extension
INT setM1=~(in_intr & im2); // RST38 interrupt extension
 
//-----------------------------------------------------------------------------------------
// Register file, address (downstream) endpoint
58,16 → 59,17
SP ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;// Read 16-bit SP, enable SW4 downstream
 
// System registers
WZ ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; // Select 16-bit WZ
IR ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; // Select 16-bit IR
I* ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4d=1; // Select 8-bit I register
PC ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; // Select 16-bit PC
WZ ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; // Select 16-bit WZ
IR ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; // Select 16-bit IR
I* ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4d=1; // Select 8-bit I register
PC ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; // Select 16-bit PC
 
// Conditional assertions of WZ, HL instead of PC
WZ? \
if (flags_cond_true) begin // If cc is true, use WZ instead of PC (for jumps)
ctl_reg_not_pc=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1;
end
WZ? ctl_reg_not_pc|=flags_cond_true; ctl_reg_sel_wz|=flags_cond_true; ctl_reg_sys_hilo|={flags_cond_true,flags_cond_true}; ctl_sw_4d|=flags_cond_true;
// Alternate format:
// if (flags_cond_true) begin // If cc is true, use WZ instead of PC (for jumps)
// ctl_reg_not_pc=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1;
// end
 
:A:reg wr
// General purpose registers
80,7 → 82,7
WZ ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit WZ, enable SW4 upstream
IR ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; // Write 16-bit IR
// PC will not be incremented if we are in HALT, INTR or NMI state
PC ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); // Write 16-bit PC and control incrementer
PC ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); // Write 16-bit PC and control incrementer
> ctl_sw_4u=1;
 
//-----------------------------------------------------------------------------------------
87,9 → 89,9
// Controls the address latch incrementer, the address latch and the address pin mux
//-----------------------------------------------------------------------------------------
:inc/dec
+ ctl_inc_cy=pc_inc; // Increment
- ctl_inc_cy=pc_inc; ctl_inc_dec=1; // Decrement
op3 ctl_inc_cy=pc_inc; ctl_inc_dec=op3; // Decrement if op3 is set; increment otherwise
+ ctl_inc_cy=~pc_inc_hold; // Increment
- ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; // Decrement
op3 ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; // Decrement if op3 is set; increment otherwise
 
:A:latch
W ctl_al_we=1; // Write a value from the register bus to the address latch
107,16 → 109,16
B ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
H ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
L ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
r8 \ // r8 addressing does not allow reading F register (A and F are also indexed as swapped) (ex. in OUT (c),r)
if (op4 & op5 & !op3) ctl_bus_zero_oe=1; // Trying to read flags? Put 0 on the bus instead.
else begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; end // Read 8-bit GP register
r8' ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};// Read 8-bit GP register selected by op[2:0]
r8 ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};// Read 8-bit GP register selected by op[2:0]
r8' \ // r8 addressing does not allow reading F register (indices of A and F are also swapped) (ex. in OUT (c),r)
if (op4 & op5 & ~op3) begin ctl_bus_zero_oe=1; end // Trying to read flags? Put 0 on the bus instead.
if (~(op4 & op5 & ~op3)) begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; end // Read 8-bit GP register
rh ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; // Read 8-bit GP register high byte
rl ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; // Read 8-bit GP register low byte
//----- System registers -----
WZ ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1;
Z ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1; // Selecting strictly Z
I/R ctl_reg_sel_ir=1; ctl_reg_sys_hilo={!op3,op3}; ctl_sw_4u=1; // Read either I or R based on op3 (0 or 1)
I/R ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4u=1; // Read either I or R based on op3 (0 or 1)
PCh ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
PCl ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
 
126,16 → 128,16
A ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
F ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
B ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
r8 ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; // Write 8-bit GP register
r8' ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0}; // Write 8-bit GP register selected by op[2:0]
r8 ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; // Write 8-bit GP register
r8' ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0}; // Write 8-bit GP register selected by op[2:0]
rh ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; // Write 8-bit GP register high byte
rl ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; // Write 8-bit GP register low byte
//----- System registers -----
I/R ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo={!op3,op3}; ctl_sw_4d=1; // Write either I or R based on op3 (0 or 1)
I/R ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4d=1; // Write either I or R based on op3 (0 or 1)
WZ ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11;
W ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; // Selecting only W
W? ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo[1]=1; // Conditionally selecting only W
Z ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; // Selecting only Z
W ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; // Selecting only W
W? ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; // Conditionally selecting only W
Z ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; // Selecting only Z
 
//-----------------------------------------------------------------------------------------
// Controls the register file gate connecting it with the ALU and data bus
144,10 → 146,16
< ctl_reg_in_hi=1; ctl_reg_in_lo=1; // From the ALU side into the register file
<l ctl_reg_in_lo=1; // From the ALU side into the register file low byte only
<h ctl_reg_in_hi=1; // From the ALU side into the register file high byte only
> ctl_reg_out_hi=1; ctl_reg_out_lo=1; // From the register file into the ALU
>l ctl_reg_out_lo=1; // From the register file into the ALU low byte only
>h ctl_reg_out_hi=1; // From the register file into the ALU high byte only
 
> ctl_reg_out_hi=1; ctl_reg_out_lo=1; // From the register file into the FLAGT and ALU
 
// Enables a register gate (high/low) corresponding to the selected 8-bit register
>r8 ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; // Enable register gate based on the rsel0
>r8' ctl_reg_out_hi=~rsel3; ctl_reg_out_lo=rsel3; ctl_sw_2u=~rsel3; ctl_sw_2d=rsel3; // Enable register gate based on the rsel3
 
>l ctl_reg_out_lo=1; // From the register file onto the db1 (sw2 + FLAGT + sw1)
>h ctl_reg_out_hi=1; // From the register file onto the db2 (sw2 + ALU)
 
//-----------------------------------------------------------------------------------------
// Switches on the data bus for each direction (upstream, downstream)
//-----------------------------------------------------------------------------------------
154,6 → 162,7
:SW2
d ctl_sw_2d=1;
u ctl_sw_2u=1;
- // Controlled by register gate
 
:SW1
< ctl_sw_1d=1;
175,7 → 184,7
// Controls the master ALU output enable and the ALU input, only one can be active at a time
// >bs if set, will override >s0 which is used by bit instructions to override default M1/T3 load
< ctl_alu_oe=1; // Enable ALU onto the data bus
>s0 ctl_alu_shift_oe=!ctl_alu_bs_oe; // Shifter unit without shift-enable
>s0 ctl_alu_shift_oe=~ctl_alu_bs_oe; // Shifter unit without shift-enable
>s1 ctl_alu_shift_oe=1; ctl_shift_en=1; // Shifter unit AND shift enable!
>bs ctl_alu_bs_oe=1; // Bit-selector unit
 
198,65 → 207,62
0 ctl_alu_op1_sel_zero=1; // Zero
 
:operation
// Sets the ALU core operation
//--------------------------------------------------------------------------------------------------------------------------
CP \
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1;
end else begin
ctl_alu_core_hf=1;
end
//--------------------------------------------------------------------------------------------------------------------------
SUB \
 
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1;
end else begin
ctl_alu_core_hf=1;
end
//--------------------------------------------------------------------------------------------------------------------------
SBC \
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
//--------------------------------------------------------------------------------------------------------------------------
SBCh \
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
//--------------------------------------------------------------------------------------------------------------------------
ADC \
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
//--------------------------------------------------------------------------------------------------------------------------
ADD \
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
//--------------------------------------------------------------------------------------------------------------------------
AND ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1;
// Defines the ALU core compute operation
// The listing is also showing their alternate formats (using if/then)
//-----------------------------------------------------------------------------------------
CP ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
// ctl_alu_sel_op2_neg=1;
// if (ctl_alu_op_low) begin
// ctl_flags_cf_set=1;
// end else begin
// ctl_alu_core_hf=1;
// end
//-----------------------------------------------------------------------------------------
SUB ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
// ctl_alu_sel_op2_neg=1;
// if (ctl_alu_op_low) begin
// ctl_flags_cf_set=1;
// end else begin
// ctl_alu_core_hf=1;
// end
//-----------------------------------------------------------------------------------------
SBC ctl_alu_sel_op2_neg=1; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
// ctl_alu_sel_op2_neg=1;
// if (ctl_alu_op_low) begin
// ctl_flags_cf_cpl=1;
// end else begin
// ctl_alu_core_hf=1;
// end
//-----------------------------------------------------------------------------------------
SBCh ctl_alu_sel_op2_neg=1; ctl_alu_core_hf|=~ctl_alu_op_low;
// ctl_alu_sel_op2_neg=1;
// if (~ctl_alu_op_low) begin
// ctl_alu_core_hf=1;
// end
//-----------------------------------------------------------------------------------------
ADC ctl_alu_core_hf|=~ctl_alu_op_low;
// if (~ctl_alu_op_low) begin
// ctl_alu_core_hf=1;
// end
//-----------------------------------------------------------------------------------------
ADD ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
// if (ctl_alu_op_low) begin
// ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
// end else begin
// ctl_alu_core_hf=1;
// end
//-----------------------------------------------------------------------------------------
AND ctl_alu_core_S=1; ctl_flags_cf_set=1;
OR ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
XOR ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
 
NAND ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1;
XOR ctl_alu_core_R=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
NAND ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1;
NOR ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; ctl_alu_sel_op2_neg=1;
//--------------------------------------------------------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------
 
PLA ctl_state_alu=1; // Assert the ALU PLA modifier to determine operation
 
:nibble
// ALU computational phase: low nibble or high nibble
// ALU compute phase: working on low nibble or high nibble
L ctl_alu_op_low=1; // Activate ALU operation on low nibble
H ctl_alu_sel_op2_high=1; // Activate ALU operation on high nibble
 
297,14 → 303,13
^ ctl_flags_cf_we=1; ctl_flags_cf_cpl=1; // CCF
:CF2
R ctl_flags_use_cf2=1;
W ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0;
W.sh ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1;
W.daa ctl_flags_cf2_we=1; ctl_flags_cf2_sel=2;
W.0 ctl_flags_cf2_we=1; ctl_flags_cf2_sel=3;
W ctl_flags_cf2_we=1;
W.sh ctl_flags_cf2_we=1; ctl_flags_cf2_sel_shift=1;
W.daa ctl_flags_cf2_we=1; ctl_flags_cf2_sel_daa=1;
 
//-----------------------------------------------------------------------------------------
// Special sequence macros for some instructions make it simpler for all other entries
//-----------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------
// Macros for some special cases; also simplifies control logic for a number of instructions
//------------------------------------------------------------------------------------------
:Special
USE_SP ctl_reg_use_sp=1; // For 16-bit loads: use SP instead of AF
 
318,24 → 323,25
 
WZ=IX+d ixy_d=1; // Compute WZ=IX+d
IX_IY ctl_state_ixiy_we=1; ctl_state_iy_set=op5; setIXIY=1; // IX/IY prefix
CLR_IX_IY ctl_state_ixiy_we=1; ctl_state_ixiy_clr=!setIXIY; // Clear IX/IY flag
CLR_IX_IY ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY; // Clear IX/IY flag
 
CB ctl_state_tbl_cb_set=1; setCBED=1; // CB-table prefix
ED ctl_state_tbl_ed_set=1; setCBED=1; // ED-table prefix
CLR_CB_ED ctl_state_tbl_clr=!setCBED; // Clear CB/ED prefix
CLR_CB_ED ctl_state_tbl_clr=~setCBED; // Clear CB/ED prefix
 
// If the NF is set, complement HF and CF on the way out to the bus
// This is used to correctly set those flags after subtraction operations
?NF_HF_CF ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf;
?NF_HF ctl_flags_hf_cpl=flags_nf;
?~CF_HF ctl_flags_hf_cpl=!flags_cf; // Used for CCF
?~CF_HF ctl_flags_hf_cpl=~flags_cf; // Used for CCF
?SF_NEG ctl_alu_sel_op2_neg=flags_sf;
NEG_OP2 ctl_alu_sel_op2_neg=1;
?NF_SUB ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=!flags_nf;
?NF_SUB ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=~flags_nf;
 
// M1 opcode read cycle and the refresh register increment cycle
// Write opcode into the instruction register through internal db0 bus:
OpcodeToIR ctl_ir_we=1;
 
// At the common instruction load M1/T3, override opcode byte when servicing interrupts:
// 1. We are in HALT mode: push NOP (0x00) instead
// 2. We are in INTR mode (IM1 or IM2): push RST38 (0xFF) instead
342,14 → 348,14
// 3. We are in NMI mode: push RST38 (0xFF) instead
OverrideIR ctl_bus_zero_oe=in_halt; ctl_bus_ff_oe=(in_intr & (im1 | im2)) | in_nmi;
 
// RST instruction uses opcode[5:3] to specify a vector and this control passes those 3 bits through
MASK_543 ctl_sw_mask543_en=!((in_intr & im2) | in_nmi);
// Based on the in_nmi state, several things are set:
// RST instruction uses opcode[5:3] to specify a vector and this macro passes those 3 bits through
MASK_543 ctl_sw_mask543_en=~((in_intr & im2) | in_nmi);
// Based on the in_nmi state:
// 1. Disable SW1 so the opcode will not get onto db1 bus
// 2. Generate 0x66 on the db1 bus which will be used as the target vector address
// 3. Clear IFF1 (done by the nmi logic on posedge of in_nmi)
RST_NMI ctl_sw_1d=!in_nmi; ctl_66_oe=in_nmi;
// Based on the in_intr state, several things are set:
RST_NMI ctl_sw_1d=~in_nmi; ctl_66_oe=in_nmi;
// Based on the in_intr state:
// 1. IM1 mode, force 0xFF on the db0 bus
// 2. Clear IFF1 and IFF2 (done by the intr logic on posedge of in_intr)
RST_INT ctl_bus_ff_oe=in_intr & im1;
/ir.bsf
20,9 → 20,9
*/
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/interrupts.v
14,7 → 14,7
 
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sun Nov 09 09:11:22 2014"
// CREATED "Sat Feb 13 19:23:03 2016"
 
module interrupts(
ctl_iff1_iff2,
28,7 → 28,6
ctl_no_ints,
nreset,
db,
iff1,
iff2,
im1,
im2,
48,7 → 47,6
input wire ctl_no_ints;
input wire nreset;
input wire [1:0] db;
output wire iff1;
output wire iff2;
output reg im1;
output reg im2;
55,7 → 53,7
output wire in_nmi;
output wire in_intr;
 
reg iff_ALTERA_SYNTHESIZED1;
reg iff1;
wire in_intr_ALTERA_SYNTHESIZED;
reg in_nmi_ALTERA_SYNTHESIZED;
reg int_armed;
114,7 → 112,7
 
assign SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_7;
 
assign SYNTHESIZED_WIRE_13 = iff_ALTERA_SYNTHESIZED1 & intr;
assign SYNTHESIZED_WIRE_13 = iff1 & intr;
 
assign test1 = setM1 & SYNTHESIZED_WIRE_8;
 
183,12 → 181,12
begin
if (!SYNTHESIZED_WIRE_15)
begin
iff_ALTERA_SYNTHESIZED1 <= 0;
iff1 <= 0;
end
else
if (SYNTHESIZED_WIRE_17)
begin
iff_ALTERA_SYNTHESIZED1 <= SYNTHESIZED_WIRE_16;
iff1 <= SYNTHESIZED_WIRE_16;
end
end
 
242,7 → 240,6
 
assign SYNTHESIZED_WIRE_14 = ~in_nmi_ALTERA_SYNTHESIZED;
 
assign iff1 = iff_ALTERA_SYNTHESIZED1;
assign in_nmi = in_nmi_ALTERA_SYNTHESIZED;
assign in_intr = in_intr_ALTERA_SYNTHESIZED;
 
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37,7 → 37,7
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(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
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(drawing
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(text "Q" (rect 44 20 48 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
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(drawing
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(text "Q" (rect 44 20 48 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
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(drawing
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(pt 64 24)
(output)
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 48 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
(line (pt 53 24)(pt 64 24))
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(drawing
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(pt 64 24)
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(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
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(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
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(drawing
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(pt 64 24)
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(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 48 32)(font "Courier New" (bold)))
(line (pt 53 24)(pt 64 24))
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(drawing
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(port
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(input)
(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
(line (pt 32 4)(pt 32 0))
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(port
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(input)
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(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
(line (pt 32 80)(pt 32 76))
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(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
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(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
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(text "ENA" (rect 14 50 31 62)(font "Courier New" (bold)))
(line (pt 0 56)(pt 12 56))
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(port
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(text "Q" (rect 44 20 48 32)(font "Courier New" (bold)))
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(drawing
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(pt 64 24)
(output)
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(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
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(drawing
1262,7 → 1189,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
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(drawing
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(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
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(drawing
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(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
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(text "inst11" (rect 3 37 32 49)(font "Arial" ))
(port
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(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
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(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
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(drawing
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(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
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(drawing
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(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(line (pt 54 24)(pt 64 24))
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(drawing
1434,9 → 1329,38
(circle (rect 46 20 54 28))
)
)
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(pt 1360 48)
(pt 512 48)
(symbol
(rect 224 336 288 384)
(text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6)))
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(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
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(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 15 16))
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(drawing
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(line (pt 14 13)(pt 25 13))
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(arc (pt 49 24)(pt 25 13)(rect -6 13 57 76))
(arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36))
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1443,38 → 1367,18
(pt 512 184)
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(pt 1360 72)
(pt 680 72)
)
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(pt 672 184)
(pt 680 184)
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(connector
(pt 1360 96)
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(pt 1360 144)
(pt 1184 144)
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(connector
(pt 1176 184)
(pt 1184 184)
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(connector
(pt 608 184)
(pt 592 184)
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1491,78 → 1395,22
(pt 1112 184)
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(connector
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(pt 1280 184)
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(connector
(pt 528 176)
(pt 512 176)
)
(connector
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(pt 512 176)
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(connector
(pt 512 176)
(pt 512 48)
)
(connector
(pt 696 176)
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(connector
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(connector
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(pt 680 72)
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(connector
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(connector
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(connector
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(connector
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(connector
(pt 1016 184)
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(connector
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(connector
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(connector
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(connector
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(connector
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(pt 1360 184)
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(connector
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(pt 304 448)
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(connector
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(pt 512 472)
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1663,11 → 1511,6
(color 128 0 128)
)
(connector
(pt 1312 240)
(pt 1312 320)
(color 128 0 128)
)
(connector
(pt 528 192)
(pt 520 192)
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1700,14 → 1543,6
(pt 1024 304)
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(connector
(pt 1200 192)
(pt 1192 192)
)
(connector
(pt 1192 192)
(pt 1192 304)
)
(connector
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(pt 680 472)
)
1754,11 → 1589,6
(color 128 0 128)
)
(connector
(pt 1144 320)
(pt 1312 320)
(color 128 0 128)
)
(connector
(pt 440 304)
(pt 520 304)
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1775,10 → 1605,6
(pt 1024 304)
)
(connector
(pt 1024 304)
(pt 1192 304)
)
(connector
(pt 640 320)
(pt 808 320)
(color 128 0 128)
1804,10 → 1630,6
(pt 1312 608)
)
(connector
(pt 304 448)
(pt 304 608)
)
(connector
(pt 640 608)
(pt 808 608)
(color 128 0 128)
1846,18 → 1668,10
(pt 304 392)
)
(connector
(pt 304 392)
(pt 304 448)
)
(connector
(pt 472 160)
(pt 472 144)
)
(connector
(pt 472 144)
(pt 304 144)
)
(connector
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1866,22 → 1680,10
(pt 344 184)
)
(connector
(pt 200 304)
(pt 344 304)
)
(connector
(pt 344 304)
(pt 392 304)
)
(connector
(pt 304 144)
(pt 304 320)
)
(connector
(pt 304 320)
(pt 304 392)
)
(connector
(pt 680 360)
(pt 1360 360)
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1989,16 → 1791,6
(pt 584 552)
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(connector
(pt 1256 200)
(pt 1256 264)
(color 128 0 128)
)
(connector
(pt 1280 200)
(pt 1256 200)
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(connector
(pt 1088 264)
(pt 1088 200)
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2009,10 → 1801,6
(color 128 0 128)
)
(connector
(pt 1088 264)
(pt 1256 264)
)
(connector
(pt 920 264)
(pt 920 200)
(color 128 0 128)
2023,10 → 1811,6
(color 128 0 128)
)
(connector
(pt 920 264)
(pt 1088 264)
)
(connector
(pt 752 264)
(pt 752 200)
(color 128 0 128)
2169,38 → 1953,140
(color 85 170 0)
)
(connector
(pt 200 472)
(pt 320 472)
(color 255 0 0)
(pt 528 480)
(pt 520 480)
(color 0 85 255)
)
(connector
(pt 320 472)
(pt 440 472)
(color 255 0 0)
(pt 520 480)
(pt 520 592)
(color 0 85 255)
)
(connector
(pt 320 592)
(pt 392 592)
(color 255 0 0)
(pt 696 480)
(pt 688 480)
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)
(connector
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(pt 320 472)
(color 255 0 0)
(pt 688 480)
(pt 688 592)
(color 0 85 255)
)
(connector
(pt 320 472)
(pt 320 592)
(color 255 0 0)
(pt 864 480)
(pt 856 480)
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)
(connector
(pt 1272 216)
(pt 1272 280)
(pt 856 480)
(pt 856 592)
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(connector
(pt 1032 480)
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(connector
(pt 1024 480)
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(connector
(pt 1200 480)
(pt 1192 480)
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(connector
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(connector
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(connector
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(connector
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(connector
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(connector
(pt 216 560)
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(connector
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(pt 216 560)
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(connector
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(pt 216 592)
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(connector
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(connector
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(pt 1088 264)
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(connector
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(connector
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(connector
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2214,11 → 2100,6
(color 255 0 0)
)
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(connector
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2229,11 → 2110,6
(color 255 0 0)
)
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(pt 1104 280)
(color 255 0 0)
)
(connector
(pt 768 280)
(pt 768 216)
(color 255 0 0)
2285,113 → 2161,106
(color 255 0 0)
)
(connector
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(pt 520 480)
(color 0 85 255)
(pt 936 280)
(pt 1104 280)
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(connector
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(pt 288 360)
(pt 320 360)
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)
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(pt 320 360)
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(junction (pt 848 176))
(junction (pt 1016 176))
(junction (pt 1184 176))
(junction (pt 680 464))
(junction (pt 512 464))
(junction (pt 848 464))
2400,12 → 2269,9
(junction (pt 640 320))
(junction (pt 808 320))
(junction (pt 976 320))
(junction (pt 1144 320))
(junction (pt 520 304))
(junction (pt 688 304))
(junction (pt 856 304))
(junction (pt 1024 304))
(junction (pt 304 448))
(junction (pt 320 472))
(junction (pt 368 424))
(junction (pt 520 592))
2430,8 → 2296,6
(junction (pt 584 552))
(junction (pt 432 568))
(junction (pt 416 552))
(junction (pt 1104 280))
(junction (pt 1088 264))
(junction (pt 936 280))
(junction (pt 920 264))
(junction (pt 768 280))
2440,14 → 2304,17
(junction (pt 584 264))
(junction (pt 432 280))
(junction (pt 416 264))
(junction (pt 208 304))
(junction (pt 320 360))
(junction (pt 304 144))
(title_block
(rect 24 32 345 93)
(name "title-custom-medium")
(section (rect 0 41 240 60)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "July 5, 2014, 2016" (rect 56 3 181 19)(font "Arial" (font_size 10)))(border))
(section (rect 0 21 320 40)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 151 19)(font "Arial" (font_size 11)))(border))
(section (rect 130 0 320 20)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "sequencer" (rect 43 2 138 21)(font "Arial" (font_size 12)(bold)))(border))
(section (rect 0 0 320 20)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 106 21)(font "Arial" (font_size 12)(bold)))(border))
(section (rect 130 0 320 20)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "sequencer" (rect 43 2 138 21)(font "Arial" (font_size 12)(bold)))(border))
(section (rect 0 21 320 40)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 151 19)(font "Arial" (font_size 11)))(border))
(section (rect 0 41 240 60)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "July 5, 2014" (rect 56 3 138 19)(font "Arial" (font_size 10)))(border))
(section (rect 241 41 320 60)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.2" (rect 43 3 64 19)(font "Arial" (font_size 10)))(border))
(section (rect 241 41 320 60)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.4" (rect 43 3 64 19)(font "Arial" (font_size 10)))(border))
(drawing
)
)
/sequencer.v
14,7 → 14,7
 
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sun Nov 16 23:11:10 2014"
// CREATED "Sat Feb 13 17:56:57 2016"
 
module sequencer(
clk,
29,7 → 29,6
M3,
M4,
M5,
M6,
T1,
T2,
T3,
51,8 → 50,7
output wire M2;
output wire M3;
output wire M4;
output wire M5;
output reg M6;
output reg M5;
output wire T1;
output wire T2;
output wire T3;
64,10 → 62,9
wire ena_M;
wire ena_T;
reg DFFE_M4_ff;
wire SYNTHESIZED_WIRE_20;
reg DFFE_M5_ff;
wire SYNTHESIZED_WIRE_18;
reg DFFE_T1_ff;
wire SYNTHESIZED_WIRE_21;
wire SYNTHESIZED_WIRE_19;
reg DFFE_T2_ff;
reg DFFE_T3_ff;
reg DFFE_T4_ff;
75,6 → 72,7
reg DFFE_M1_ff;
reg DFFE_M2_ff;
reg DFFE_M3_ff;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_10;
wire SYNTHESIZED_WIRE_11;
wire SYNTHESIZED_WIRE_12;
83,14 → 81,11
wire SYNTHESIZED_WIRE_15;
wire SYNTHESIZED_WIRE_16;
wire SYNTHESIZED_WIRE_17;
wire SYNTHESIZED_WIRE_18;
wire SYNTHESIZED_WIRE_19;
 
assign M1 = DFFE_M1_ff;
assign M2 = DFFE_M2_ff;
assign M3 = DFFE_M3_ff;
assign M4 = DFFE_M4_ff;
assign M5 = DFFE_M5_ff;
assign T1 = DFFE_T1_ff;
assign T2 = DFFE_T2_ff;
assign T3 = DFFE_T3_ff;
99,25 → 94,25
 
 
 
assign SYNTHESIZED_WIRE_13 = DFFE_M4_ff & SYNTHESIZED_WIRE_20;
assign ena_M = nextM | setM1;
 
assign SYNTHESIZED_WIRE_14 = DFFE_M5_ff & SYNTHESIZED_WIRE_20;
assign SYNTHESIZED_WIRE_12 = DFFE_M4_ff & SYNTHESIZED_WIRE_18;
 
assign SYNTHESIZED_WIRE_15 = DFFE_T1_ff & SYNTHESIZED_WIRE_21;
assign SYNTHESIZED_WIRE_13 = DFFE_T1_ff & SYNTHESIZED_WIRE_19;
 
assign SYNTHESIZED_WIRE_16 = DFFE_T2_ff & SYNTHESIZED_WIRE_21;
assign SYNTHESIZED_WIRE_14 = DFFE_T2_ff & SYNTHESIZED_WIRE_19;
 
assign SYNTHESIZED_WIRE_17 = DFFE_T3_ff & SYNTHESIZED_WIRE_21;
assign SYNTHESIZED_WIRE_15 = DFFE_T3_ff & SYNTHESIZED_WIRE_19;
 
assign SYNTHESIZED_WIRE_18 = DFFE_T4_ff & SYNTHESIZED_WIRE_21;
assign SYNTHESIZED_WIRE_16 = DFFE_T4_ff & SYNTHESIZED_WIRE_19;
 
assign SYNTHESIZED_WIRE_19 = DFFE_T5_ff & SYNTHESIZED_WIRE_21;
assign SYNTHESIZED_WIRE_17 = DFFE_T5_ff & SYNTHESIZED_WIRE_19;
 
assign SYNTHESIZED_WIRE_10 = DFFE_M1_ff & SYNTHESIZED_WIRE_20;
assign SYNTHESIZED_WIRE_9 = DFFE_M1_ff & SYNTHESIZED_WIRE_18;
 
assign SYNTHESIZED_WIRE_11 = DFFE_M2_ff & SYNTHESIZED_WIRE_20;
assign SYNTHESIZED_WIRE_10 = DFFE_M2_ff & SYNTHESIZED_WIRE_18;
 
assign SYNTHESIZED_WIRE_12 = DFFE_M3_ff & SYNTHESIZED_WIRE_20;
assign SYNTHESIZED_WIRE_11 = DFFE_M3_ff & SYNTHESIZED_WIRE_18;
 
assign ena_T = ~(hold_clk_iorq | hold_clk_wait | hold_clk_busrq);
 
145,7 → 140,7
else
if (ena_M)
begin
DFFE_M2_ff <= SYNTHESIZED_WIRE_10;
DFFE_M2_ff <= SYNTHESIZED_WIRE_9;
end
end
 
159,7 → 154,7
else
if (ena_M)
begin
DFFE_M3_ff <= SYNTHESIZED_WIRE_11;
DFFE_M3_ff <= SYNTHESIZED_WIRE_10;
end
end
 
173,7 → 168,7
else
if (ena_M)
begin
DFFE_M4_ff <= SYNTHESIZED_WIRE_12;
DFFE_M4_ff <= SYNTHESIZED_WIRE_11;
end
end
 
182,34 → 177,20
begin
if (!nreset)
begin
DFFE_M5_ff <= 0;
M5 <= 0;
end
else
if (ena_M)
begin
DFFE_M5_ff <= SYNTHESIZED_WIRE_13;
M5 <= SYNTHESIZED_WIRE_12;
end
end
 
assign SYNTHESIZED_WIRE_19 = ~ena_M;
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
M6 <= 0;
end
else
if (ena_M)
begin
M6 <= SYNTHESIZED_WIRE_14;
end
end
assign SYNTHESIZED_WIRE_18 = ~setM1;
 
assign SYNTHESIZED_WIRE_21 = ~ena_M;
 
assign SYNTHESIZED_WIRE_20 = ~setM1;
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
233,7 → 214,7
else
if (ena_T)
begin
DFFE_T2_ff <= SYNTHESIZED_WIRE_15;
DFFE_T2_ff <= SYNTHESIZED_WIRE_13;
end
end
 
247,7 → 228,7
else
if (ena_T)
begin
DFFE_T3_ff <= SYNTHESIZED_WIRE_16;
DFFE_T3_ff <= SYNTHESIZED_WIRE_14;
end
end
 
261,7 → 242,7
else
if (ena_T)
begin
DFFE_T4_ff <= SYNTHESIZED_WIRE_17;
DFFE_T4_ff <= SYNTHESIZED_WIRE_15;
end
end
 
275,7 → 256,7
else
if (ena_T)
begin
DFFE_T5_ff <= SYNTHESIZED_WIRE_18;
DFFE_T5_ff <= SYNTHESIZED_WIRE_16;
end
end
 
289,11 → 270,10
else
if (ena_T)
begin
T6 <= SYNTHESIZED_WIRE_19;
T6 <= SYNTHESIZED_WIRE_17;
end
end
 
assign ena_M = nextM;
assign timings_en = ena_T;
 
endmodule
/resets.bdf
101,7 → 101,7
)
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(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "clrpc" (rect 90 0 113 12)(font "Arial" ))
(pt 0 8)
518,6 → 518,205
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(port
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(line (pt 0 16)(pt 13 16))
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622,10 → 821,6
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646,10 → 841,6
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687,10 → 878,6
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702,6 → 889,125
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(pt 384 488)
)
(connector
(pt 384 488)
(pt 384 544)
)
(connector
(pt 360 544)
(pt 384 544)
)
(connector
(pt 384 544)
(pt 408 544)
)
(connector
(text "clrpc_int" (rect 630 456 671 468)(font "Arial" ))
(pt 680 472)
(pt 624 472)
)
(connector
(pt 744 496)
(pt 776 496)
)
(connector
(pt 712 296)
(pt 712 336)
)
(connector
(pt 712 336)
(pt 712 424)
)
(connector
(pt 712 424)
(pt 272 424)
)
(connector
(pt 272 424)
(pt 272 544)
)
(connector
(pt 296 544)
(pt 272 544)
)
(connector
(pt 520 560)
(pt 496 560)
)
(connector
(pt 496 560)
(pt 496 616)
)
(connector
(pt 232 320)
(pt 232 352)
)
(connector
(pt 408 560)
(pt 384 560)
)
(connector
(pt 384 560)
(pt 384 616)
)
(connector
(pt 496 616)
(pt 384 616)
)
(connector
(pt 296 560)
(pt 272 560)
)
(connector
(pt 272 560)
(pt 272 616)
)
(connector
(pt 272 616)
(pt 384 616)
)
(connector
(text "nclk" (rect 216 600 236 612)(font "Arial" ))
(pt 208 616)
(pt 272 616)
)
(junction (pt 232 144))
(junction (pt 368 96))
(junction (pt 336 272))
710,16 → 1016,24
(junction (pt 320 320))
(junction (pt 232 352))
(junction (pt 712 224))
(junction (pt 496 544))
(junction (pt 384 544))
(junction (pt 712 336))
(junction (pt 384 616))
(junction (pt 272 616))
(text "Needed only for FPGAs" (rect 40 72 174 86)(font "Arial" (font_size 8)))
(text "Special reset, USPTO 4,486,827 by Shima et al." (rect 40 24 371 40)(font "Arial" (font_size 10))(border))
(text "Required 3 clock reset cycles to clear PC and IR" (rect 304 464 576 478)(font "Arial" (font_size 8)))
(text "(End of patented circuit)" (rect 64 384 242 400)(font "Arial" (font_size 10)(bold)))
(line (pt 32 408)(pt 952 408)(color 0 255 0))
(title_block
(rect 32 400 289 452)
(rect 696 584 953 636)
(name "title-custom-small")
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "September 6, 2014, 2016" (rect 56 3 198 17)(font "Arial" (font_size 8)))(border))
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "resets" (rect 43 2 86 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "resets" (rect 43 2 86 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "September 6, 2014" (rect 56 3 163 17)(font "Arial" (font_size 8)))(border))
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.2" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.3" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
(drawing
)
)
/ir.bdf
68,8 → 68,24
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 40 120 216 136)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "nreset" (rect 9 0 39 12)(font "Arial" ))
(pt 176 8)
(drawing
(line (pt 92 12)(pt 117 12))
(line (pt 92 4)(pt 117 4))
(line (pt 121 8)(pt 176 8))
(line (pt 92 12)(pt 92 4))
(line (pt 117 4)(pt 121 8))
(line (pt 117 12)(pt 121 8))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 376 48 552 64)
(rect 504 48 680 64)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "opcode[7..0]" (rect 90 0 151 12)(font "Arial" ))
(pt 0 8)
84,7 → 100,7
)
)
(symbol
(rect 264 32 328 112)
(rect 392 32 456 112)
(text "DFFE" (rect 1 0 25 10)(font "Arial" (font_size 6)))
(text "ir" (rect 3 68 8 80)(font "Arial" ))
(port
126,7 → 142,7
(pt 64 24)
(output)
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 48 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
(line (pt 53 24)(pt 64 24))
)
(drawing
142,31 → 158,39
)
(connector
(pt 216 56)
(pt 264 56)
(pt 392 56)
(bus)
)
(connector
(pt 216 88)
(pt 264 88)
(pt 216 72)
(pt 392 72)
)
(connector
(pt 328 56)
(pt 376 56)
(pt 456 56)
(pt 504 56)
(bus)
)
(connector
(pt 216 72)
(pt 264 72)
(pt 216 88)
(pt 392 88)
)
(text "8 latches implement the opcode Instruction Register" (rect 160 136 451 150)(font "Arial" (font_size 8)))
(connector
(pt 216 128)
(pt 424 128)
)
(connector
(pt 424 128)
(pt 424 112)
)
(text "8 latches implement the opcode Instruction Register" (rect 352 160 643 174)(font "Arial" (font_size 8)))
(title_block
(rect 40 176 297 228)
(rect 40 160 297 212)
(name "title-custom-small")
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 3, 2014, 2016" (rect 56 3 161 17)(font "Arial" (font_size 8)))(border))
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "ir" (rect 43 2 52 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "ir" (rect 43 2 52 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 3, 2014" (rect 56 3 125 17)(font "Arial" (font_size 8)))(border))
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.1" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.3" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
(drawing
)
)
/Timings.csv
2,31 → 2,31
// 8-bit Load Group
"#if pla[17] && !pla[50] : ld r,n" "4,3"
"#if pla[17] & ~pla[50] : ld r,n" "4,3"
#001H T1 AB:000 DB:-- M1 1 1 fMFetch r8 < d < R
#002H T2 AB:000 DB:46 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:001 DB:-- 2 1 fMRead PC W
#006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead 1 1
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead Y
#end
"#if pla[61] && !pla[58] && !pla[59] : ld r,r'" 4
"#if pla[61] & ~pla[58] & ~pla[59] : ld r,r'" 4
#001H T1 AB:000 DB:-- M1 1 1 fMFetch r8 < u < op1
#002H T2 AB:000 DB:05 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1 r8' > d >s0 bus
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y r8 >r8 - >s0 bus
#end
"#if use_ixiy && pla[58] : ld r,(ix+d)" "4,3,5,3"
"#if use_ixiy & pla[58] : ld r,(ix+d)" "4,3,5,3"
#005H T1 AB:001 DB:-- M1 1 1 fMFetch r8 < d < R
#006H T2 AB:001 DB:4E M1 MREQ RD 1 2 fMFetch
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#009H T5 AB:002 DB:-- 2 1 fMRead PC W
#010H T6 AB:002 DB:01 MREQ RD 2 2 fMRead PC + R
#011H T7 AB:002 DB:01 MREQ RD 2 3 fMRead 1
#011H T7 AB:002 DB:01 MREQ RD 2 3 fMRead Y
#012H T8 AB:002 DB:-- 3 1 WZ=IX+d
#013H T9 AB:002 DB:-- 3 2 WZ=IX+d
#014H T10 AB:002 DB:-- 3 3 WZ=IX+d
34,28 → 34,28
#016H T12 AB:002 DB:-- 3 5 mr WZ=IX+d Clears the IX/IY and ...
#end
"#if ~use_ixiy && pla[58] : ld r,(hl)" "4,3"
"#if ~use_ixiy & pla[58] : ld r,(hl)" "4,3"
#001H T1 AB:000 DB:-- M1 1 1 fMFetch r8 < d < R
#002H T2 AB:000 DB:46 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:003 DB:-- 2 1 fMRead HL W
#006H T6 AB:003 DB:03 MREQ RD 2 2 fMRead
#007H T7 AB:003 DB:03 MREQ RD 2 3 fMRead 1 1
#007H T7 AB:003 DB:03 MREQ RD 2 3 fMRead Y
#017H T13 AB:001 DB:-- 4 1 fMRead R ...continues here
#018H T14 AB:001 DB:4E MREQ RD 4 2 fMRead
#019H T15 AB:001 DB:4E MREQ RD 4 3 fMRead 1 1
#019H T15 AB:001 DB:4E MREQ RD 4 3 fMRead Y
#end
"#if use_ixiy && pla[59] : ld (ix+d),r" "4,3,5,3"
"#if use_ixiy & pla[59] : ld (ix+d),r" "4,3,5,3"
#005H T1 AB:001 DB:-- M1 1 1 fMFetch
#006H T2 AB:001 DB:70 M1 MREQ RD 1 2 fMFetch
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#009H T5 AB:002 DB:-- 2 1 fMRead PC W
#010H T6 AB:002 DB:01 MREQ RD 2 2 fMRead PC + R
#011H T7 AB:002 DB:01 MREQ RD 2 3 fMRead 1
#011H T7 AB:002 DB:01 MREQ RD 2 3 fMRead Y
#012H T8 AB:002 DB:-- 3 1 WZ=IX+d
#013H T9 AB:002 DB:-- 3 2 WZ=IX+d
#014H T10 AB:002 DB:-- 3 3 WZ=IX+d
63,18 → 63,18
#016H T12 AB:002 DB:-- 3 5 mw WZ=IX+d Clears the IX/IY and ...
#end
"#if ~use_ixiy && pla[59] : ld (hl),r" "4,3"
"#if ~use_ixiy & pla[59] : ld (hl),r" "4,3"
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:70 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mw r8' > u > W
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mw r8 >r8 - > W
#005H T5 AB:001 DB:-- 2 1 fMWrite HL W
#006H T6 AB:001 DB:01 MREQ 2 2 fMWrite
#007H T7 AB:001 DB:01 MREQ WR 2 3 fMWrite 1 1
#007H T7 AB:001 DB:01 MREQ WR 2 3 fMWrite Y
#017H T13 AB:000 DB:-- 4 1 fMWrite R r8' > u > W ...continues here
#017H T13 AB:000 DB:-- 4 1 fMWrite R r8 >r8 - > W ...continues here
#018H T14 AB:000 DB:46 MREQ 4 2 fMWrite
#019H T15 AB:000 DB:46 MREQ WR 4 3 fMWrite 1 1
#019H T15 AB:000 DB:46 MREQ WR 4 3 fMWrite Y
#end
"#if pla[40] : ld (ix+d),n" "4,3,5,3"
81,7 → 81,7
#005H T1 AB:001 DB:-- M1 1 1 fMFetch
#006H T2 AB:001 DB:36 M1 MREQ RD 1 2 fMFetch
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#009H T5 AB:002 DB:-- 2 1 fMRead PC W
#010H T6 AB:002 DB:01 MREQ RD 2 2 fMRead PC + R
#011H T7 AB:002 DB:01 MREQ RD 2 3 fMRead mr
92,48 → 92,48
#016H T12 AB:003 DB:-- 3 5 mw WZ=IX+d Clears the IX/IY and ...
#end
"#if pla[50] && !pla[40] : ld (hl),n" "4,3,3"
"#if pla[50] & ~pla[40] : ld (hl),n" "4,3,3"
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:36 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:001 DB:-- 2 1 fMRead PC W
#006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mw
#008H T8 AB:001 DB:-- 3 1 fMWrite HL W
#009H T9 AB:001 DB:01 MREQ 3 2 fMWrite
#010H T10 AB:001 DB:01 MREQ WR 3 3 fMWrite 1 1
#010H T10 AB:001 DB:01 MREQ WR 3 3 fMWrite Y
#017H T13 AB:002 DB:-- 4 1 fMWrite R ...continues here
#018H T14 AB:002 DB:02 MREQ 4 2 fMWrite
#019H T15 AB:002 DB:02 MREQ WR 4 3 fMWrite 1 1
#019H T15 AB:002 DB:02 MREQ WR 4 3 fMWrite Y
#end
"#if pla[8] && pla[13] : ld (rr),a" "4,3"
"#if pla[8] & pla[13] : ld (rr),a" "4,3"
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:02 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mw A > u > W
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mw A >h u > W
#005H T5 AB:001 DB:-- 2 1 fMWrite r16 W
#006H T6 AB:001 DB:FF MREQ 2 2 fMWrite WZ + R
#007H T7 AB:001 DB:FF MREQ WR 2 3 fMWrite 1 1
#007H T7 AB:001 DB:FF MREQ WR 2 3 fMWrite Y
#end
"#if pla[8] && !pla[13] : ld a,(rr)" "4,3"
"#if pla[8] & ~pla[13] : ld a,(rr)" "4,3"
#001H T1 AB:000 DB:-- M1 1 1 fMFetch A < d < R
#002H T2 AB:000 DB:0A M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:002 DB:-- 2 1 fMRead r16 W
#006H T6 AB:002 DB:02 MREQ RD 2 2 fMRead WZ + R
#007H T7 AB:002 DB:02 MREQ RD 2 3 fMRead 1 1
#007H T7 AB:002 DB:02 MREQ RD 2 3 fMRead Y
#end
"#if pla[38] && pla[13] : ld (nn),a" "4,3,3,3"
"#if pla[38] & pla[13] : ld (nn),a" "4,3,3,3"
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:32 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:001 DB:-- 2 1 fMRead PC W
#006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mr Z <l d < R
140,16 → 140,16
#008H T8 AB:002 DB:-- 3 1 fMRead PC W
#009H T9 AB:002 DB:02 MREQ RD 3 2 fMRead PC + R
#010H T10 AB:002 DB:02 MREQ RD 3 3 fMRead mw WZ W W <h d < R
#011H T11 AB:001 DB:-- 4 1 fMWrite R A > u > W
#011H T11 AB:001 DB:-- 4 1 fMWrite R A >h u > W
#012H T12 AB:001 DB:FE MREQ 4 2 fMWrite WZ + R
#013H T13 AB:001 DB:FE MREQ WR 4 3 fMWrite 1 1
#013H T13 AB:001 DB:FE MREQ WR 4 3 fMWrite Y
#end
"#if pla[38] && !pla[13] : ld a,(nn)" "4,3,3,3"
"#if pla[38] & ~pla[13] : ld a,(nn)" "4,3,3,3"
#001H T1 AB:000 DB:-- M1 1 1 fMFetch A < d < R
#002H T2 AB:000 DB:3A M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:001 DB:-- 2 1 fMRead PC W
#006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mr Z <l d < R
158,7 → 158,7
#010H T10 AB:002 DB:02 MREQ RD 3 3 fMRead mr W <h d < R
#011H T11 AB:001 DB:-- 4 1 fMRead WZ W
#012H T12 AB:001 DB:01 MREQ RD 4 2 fMRead WZ + R
#013H T13 AB:001 DB:01 MREQ RD 4 3 fMRead 1 1
#013H T13 AB:001 DB:01 MREQ RD 4 3 fMRead Y
#end
"#if pla[83] : ld a,i/a,r" 5
165,8 → 165,8
#005H T1 AB:001 DB:-- M1 1 1 fMFetch A < alu < res H OR * * * iff2 0
#006H T2 AB:001 DB:57 M1 MREQ RD 1 2 fMFetch F < <
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 I/R > d alu >s0 bus bus L OR * * * 0
#009H T5 AB:001 DB:-- 1 5 1 1
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y I/R >r8' - alu >s0 bus bus L OR * * * 0
#009H T5 AB:001 DB:-- 1 5 Y
#end
"#if pla[57] : ld i,a/r,a" 5
173,8 → 173,8
#005H T1 AB:001 DB:-- M1 1 1 fMFetch
#006H T2 AB:001 DB:47 M1 MREQ RD 1 2 fMFetch
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 I/R < u < op1
#009H T5 AB:001 DB:-- 1 5 1 1
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y I/R < u < op1
#009H T5 AB:001 DB:-- 1 5 Y
#end
// 16-bit Load Group
183,20 → 183,20
#001H T1 AB:000 DB:-- M1 1 1 fMFetch rh < d < R USE_SP
#002H T2 AB:000 DB:01 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:001 DB:-- 2 1 fMRead PC W
#006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mr
#008H T8 AB:002 DB:-- 3 1 fMRead PC W rl < d < R USE_SP
#009H T9 AB:002 DB:02 MREQ RD 3 2 fMRead PC + R
#010H T10 AB:002 DB:02 MREQ RD 3 3 fMRead 1 1
#010H T10 AB:002 DB:02 MREQ RD 3 3 fMRead Y
#end
"#if pla[30] && pla[13] : ld (nn),hl" "4,3,3,3,3"
"#if pla[30] & pla[13] : ld (nn),hl" "4,3,3,3,3"
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:22 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:001 DB:-- 2 1 fMRead PC W
#006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mr Z <l d < R
203,19 → 203,19
#008H T8 AB:002 DB:-- 3 1 fMRead PC W
#009H T9 AB:002 DB:02 MREQ RD 3 2 fMRead PC + R
#010H T10 AB:002 DB:02 MREQ RD 3 3 fMRead mw WZ W W <h d < R
#011H T11 AB:001 DB:-- 4 1 fMWrite R rl > u > W
#011H T11 AB:001 DB:-- 4 1 fMWrite R rl >l > W
#012H T12 AB:001 DB:01 MREQ 4 2 fMWrite WZ + R
#013H T13 AB:001 DB:01 MREQ WR 4 3 fMWrite mw WZ W
#014H T14 AB:002 DB:-- 5 1 fMWrite R rh > u > W
#014H T14 AB:002 DB:-- 5 1 fMWrite R rh >h u > W
#015H T15 AB:002 DB:02 MREQ 5 2 fMWrite WZ + R
#016H T16 AB:002 DB:02 MREQ WR 5 3 fMWrite 1 1
#016H T16 AB:002 DB:02 MREQ WR 5 3 fMWrite Y
#end
"#if pla[30] && !pla[13] : ld hl,(nn)" "4,3,3,3,3"
"#if pla[30] & ~pla[13] : ld hl,(nn)" "4,3,3,3,3"
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:2A M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:001 DB:-- 2 1 fMRead PC W
#006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mr Z <l d < R
227,14 → 227,14
#013H T13 AB:001 DB:01 MREQ RD 4 3 fMRead mr rl < d < R
#014H T14 AB:002 DB:-- 5 1 fMRead WZ W
#015H T15 AB:002 DB:02 MREQ RD 5 2 fMRead WZ + R
#016H T16 AB:002 DB:02 MREQ RD 5 3 fMRead 1 1 rh < d < R
#016H T16 AB:002 DB:02 MREQ RD 5 3 fMRead Y rh < d < R
#end
"#if pla[31] && pla[33] : ld (nn),rr" "4,3,3,3,3"
"#if pla[31] & pla[33] : ld (nn),rr" "4,3,3,3,3"
#005H T1 AB:001 DB:-- M1 1 1 fMFetch
#006H T2 AB:001 DB:43 M1 MREQ RD 1 2 fMFetch
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#009H T5 AB:002 DB:-- 2 1 fMRead PC W
#010H T6 AB:002 DB:01 MREQ RD 2 2 fMRead PC + R
#011H T7 AB:002 DB:01 MREQ RD 2 3 fMRead mr Z <l d < R
241,19 → 241,19
#012H T8 AB:003 DB:-- 3 1 fMRead PC W
#013H T9 AB:003 DB:02 MREQ RD 3 2 fMRead PC + R
#014H T10 AB:003 DB:02 MREQ RD 3 3 fMRead mw WZ W W <h d < R
#015H T11 AB:001 DB:-- 4 1 fMWrite R rl > u > W USE_SP
#015H T11 AB:001 DB:-- 4 1 fMWrite R rl >l > W USE_SP
#016H T12 AB:001 DB:FF MREQ 4 2 fMWrite WZ + R
#017H T13 AB:001 DB:FF MREQ WR 4 3 fMWrite mw WZ W
#018H T14 AB:002 DB:-- 5 1 fMWrite R rh > u > W USE_SP
#018H T14 AB:002 DB:-- 5 1 fMWrite R rh >h u > W USE_SP
#019H T15 AB:002 DB:C3 MREQ 5 2 fMWrite WZ + R
#020H T16 AB:002 DB:C3 MREQ WR 5 3 fMWrite 1 1
#020H T16 AB:002 DB:C3 MREQ WR 5 3 fMWrite Y
#end
"#if pla[31] && !pla[33] : ld rr,(nn)" "4,3,3,3,3"
"#if pla[31] & ~pla[33] : ld rr,(nn)" "4,3,3,3,3"
#005H T1 AB:001 DB:-- M1 1 1 fMFetch
#006H T2 AB:001 DB:43 M1 MREQ RD 1 2 fMFetch
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#009H T5 AB:002 DB:-- 2 1 fMRead PC W
#010H T6 AB:002 DB:01 MREQ RD 2 2 fMRead PC + R
#011H T7 AB:002 DB:01 MREQ RD 2 3 fMRead mr Z <l d < R
265,7 → 265,7
#017H T13 AB:001 DB:FF MREQ RD 4 3 fMRead mr rl < d < R USE_SP
#018H T14 AB:002 DB:-- 5 1 fMRead WZ W
#019H T15 AB:002 DB:C3 MREQ RD 5 2 fMRead WZ + R
#020H T16 AB:002 DB:C3 MREQ RD 5 3 fMRead 1 1 rh < d < R USE_SP
#020H T16 AB:002 DB:C3 MREQ RD 5 3 fMRead Y rh < d < R USE_SP
#end
"#if pla[5] : ld sp,hl" 6
272,36 → 272,36
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:F9 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 HL W
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y HL W
#005H T5 AB:000 DB:-- 1 5 SP R
#006H T6 AB:000 DB:-- 1 6 1 1
#006H T6 AB:000 DB:-- 1 6 Y
#end
#if pla[23] && pla[16] : push qq "5,3,3"
#if pla[23] & pla[16] : push qq "5,3,3"
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:C5 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y
#005H T5 AB:000 DB:-- 1 5 mw SP - W
#006H T6 AB:002 DB:-- 2 1 fMWrite - P rh > u > W
#006H T6 AB:002 DB:-- 2 1 fMWrite - P rh >h u > W
#007H T7 AB:002 DB:02 MREQ 2 2 fMWrite SP - R
#008H T8 AB:002 DB:02 MREQ WR 2 3 fMWrite mw SP - W
#009H T9 AB:001 DB:-- 3 1 fMWrite - P rl > u > W
#009H T9 AB:001 DB:-- 3 1 fMWrite - P rl >l > W
#010H T10 AB:001 DB:01 MREQ 3 2 fMWrite SP - R
#011H T11 AB:001 DB:01 MREQ WR 3 3 fMWrite 1 1
#011H T11 AB:001 DB:01 MREQ WR 3 3 fMWrite Y
#end
#if pla[23] && !pla[16] : pop qq "4,3,3"
#if pla[23] & ~pla[16] : pop qq "4,3,3"
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:C1 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:001 DB:-- 2 1 fMRead SP W
#006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead SP + R
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mr rl < d < R
#008H T8 AB:002 DB:-- 3 1 fMRead SP W
#009H T9 AB:002 DB:02 MREQ RD 3 2 fMRead SP + R
#010H T10 AB:002 DB:02 MREQ RD 3 3 fMRead 1 1 rh < d < R
#010H T10 AB:002 DB:02 MREQ RD 3 3 fMRead Y rh < d < R
#end
"// Exchange, Block Transfer and Search Groups"
310,7 → 310,7
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:EB M1 MREQ RD 1 2 fMFetch Ex_DE_HL
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y
#end
"#if pla[39] : ex af,af'" 4
317,7 → 317,7
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:08 M1 MREQ RD 1 2 fMFetch Ex_AF_AF'
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y
#end
#if pla[1] : exx 4
324,7 → 324,7
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:D9 M1 MREQ RD 1 2 fMFetch EXX
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y
#end
"#if pla[10] : ex (sp),hl" "4,3,4,3,5"
331,7 → 331,7
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:E3 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:0FD DB:-- 2 1 fMRead SP W
#006H T6 AB:0FD DB:03 MREQ RD 2 2 fMRead SP + R
#007H T7 AB:0FD DB:03 MREQ RD 2 3 fMRead mr Z <l d < R
339,14 → 339,14
#009H T9 AB:0FE DB:D1 MREQ RD 3 2 fMRead SP + R
#010H T10 AB:0FE DB:D1 MREQ RD 3 3 fMRead W <h d < R
#011H T11 AB:0FE DB:-- 3 4 mw SP - W
#012H T12 AB:0FE DB:-- 4 1 fMWrite - P rh > u > W
#012H T12 AB:0FE DB:-- 4 1 fMWrite - P rh >h u > W
#013H T13 AB:0FE DB:00 MREQ 4 2 fMWrite SP - R
#014H T14 AB:0FE DB:00 MREQ WR 4 3 fMWrite mw SP - W
#015H T15 AB:0FD DB:-- 5 1 fMWrite - P rl > u > W
#015H T15 AB:0FD DB:-- 5 1 fMWrite - P rl >l > W
#016H T16 AB:0FD DB:01 MREQ 5 2 fMWrite SP - R
#017H T17 AB:0FD DB:01 MREQ WR 5 3 fMWrite WZ W
#018H T18 AB:0FD DB:01 5 4 HL R
#019H T19 AB:0FD DB:01 5 5 1 1
#019H T19 AB:0FD DB:01 5 5 Y
#end
#if pla[0] : Non-repeating version of a block instruction "4,3,5,(5)"
357,7 → 357,7
#035H T1 AB:00A DB:-- M1 1 1 fMFetch alu res H OR * * REP 0 R
#036H T2 AB:00A DB:B0 M1 MREQ RD 1 2 fMFetch F < <
#037H T3 AB:004 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#038H T4 AB:004 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#038H T4 AB:004 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#039H T5 AB:000 DB:-- 2 1 fMRead HL W
#040H T6 AB:000 DB:21 MREQ RD 2 2 fMRead HL op3 R
#041H T7 AB:000 DB:21 MREQ RD 2 3 fMRead mw d < R alu >s0 bus L ADD * W
365,12 → 365,12
#043H T9 AB:000 DB:21 MREQ 3 2 fMWrite DE op3 R
#044H T10 AB:000 DB:21 MREQ WR 3 3 fMWrite BC W
#045H T11 AB:000 DB:21 3 4 BC - R WriteBC=1 Update repeat flag latch
#046H T12 AB:000 DB:21 3 5 1 BR
#046H T12 AB:000 DB:21 3 5 Y BR
#047H T13 AB:000 DB:-- 4 1 PC W
#048H T14 AB:000 DB:-- 4 2 PC - R
#049H T15 AB:000 DB:-- 4 3 PC W
#050H T16 AB:000 DB:-- 4 4 PC - R
#051H T17 AB:000 DB:-- 4 5 1 1
#051H T17 AB:000 DB:-- 4 5 Y
#end
#if pla[11] : cpi/cpir/cpd/cpdr "4,3,5,(5)"
377,29 → 377,29
#035H T1 AB:00A DB:-- M1 1 1 fMFetch alu < res 0 H SUB * REP 1 R
#036H T2 AB:00A DB:B1 M1 MREQ RD 1 2 fMFetch F < < ?NF_HF
#037H T3 AB:004 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#038H T4 AB:004 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#038H T4 AB:004 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#039H T5 AB:000 DB:-- 2 1 fMRead HL W
#040H T6 AB:000 DB:21 MREQ RD 2 2 fMRead HL op3 R
#041H T7 AB:000 DB:21 MREQ RD 2 3 fMRead 1 d < R alu >s0 bus L SUB * W
#041H T7 AB:000 DB:21 MREQ RD 2 3 fMRead Y d < R alu >s0 bus L SUB * W
#042H T8 AB:000 DB:-- 3 1 alu < res H SUB * R
#043H T9 AB:000 DB:-- 3 2
#044H T10 AB:000 DB:-- 3 3 BC W
#045H T11 AB:000 DB:-- 3 4 BC - R WriteBC=1 Update repeat flag latch
#046H T12 AB:000 DB:-- 3 5 1 BRZ
#046H T12 AB:000 DB:-- 3 5 Y BRZ
#047H T13 AB:000 DB:-- 4 1 PC W
#048H T14 AB:000 DB:-- 4 2 PC - R
#049H T15 AB:000 DB:-- 4 3 PC W
#050H T16 AB:000 DB:-- 4 4 PC - R
#051H T17 AB:000 DB:-- 4 5 1 1
#051H T17 AB:000 DB:-- 4 5 Y
#end
// 8-bit Arithmetic and Logic Group
"#if pla[65] && !pla[52] : add/sub/and/or/xor/cmp a,r" 4
"#if pla[65] & ~pla[52] : add/sub/and/or/xor/cmp a,r" 4
#001H T1 AB:000 DB:-- M1 1 1 fMFetch ? < u alu < res H PLA * ? ? ? * A is stored in each ALU PLA below
#002H T2 AB:000 DB:80 M1 MREQ RD 1 2 fMFetch F < < PLA ?NF_HF_CF "If (NF), complement HF, CF"
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1 r8' > d alu >s0 bus L PLA * * * ?
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y r8 >r8 - alu >s0 bus L PLA * * * ?
#end
"#if pla[64] : add/sub/and/or/xor/cmp a,n" "4,3"
406,20 → 406,20
#001H T1 AB:000 DB:-- M1 1 1 fMFetch ? < u alu < res H PLA * ? ? ? * A is stored in each ALU PLA below
#002H T2 AB:000 DB:C6 M1 MREQ RD 1 2 fMFetch F < < PLA ?NF_HF_CF "If (NF), complement HF, CF"
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr r8' > d alu >s0 bus L PLA * * * ?
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr r8 >r8 - alu >s0 bus L PLA * * * ?
#005H T5 AB:001 DB:-- 2 1 fMRead PC W PLA
#006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead 1 1 d < R alu >s0 bus L PLA * * * ?
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead Y d < R alu >s0 bus L PLA * * * ?
#end
#if use_ixiy && pla[52] : add/sub/and/or/xor/cp (ix+d) "4,3,5,3"
#if use_ixiy & pla[52] : add/sub/and/or/xor/cp (ix+d) "4,3,5,3"
#005H T1 AB:001 DB:-- M1 1 1 fMFetch
#006H T2 AB:001 DB:86 M1 MREQ RD 1 2 fMFetch
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#009H T5 AB:002 DB:-- 2 1 fMRead PC W
#010H T6 AB:002 DB:01 MREQ RD 2 2 fMRead PC + R
#011H T7 AB:002 DB:01 MREQ RD 2 3 fMRead 1
#011H T7 AB:002 DB:01 MREQ RD 2 3 fMRead Y
#012H T8 AB:002 DB:-- 3 1 WZ=IX+d
#013H T9 AB:002 DB:-- 3 2 WZ=IX+d
#014H T10 AB:002 DB:-- 3 3 WZ=IX+d "Reads ""n"" at the same time"
427,25 → 427,25
#016H T12 AB:002 DB:-- 3 5 mr WZ=IX+d Clears the IX/IY and ...
#end
#if !use_ixiy && pla[52] : add/sub/and/or/xor/cp (hl) "4,3"
#if ~use_ixiy & pla[52] : add/sub/and/or/xor/cp (hl) "4,3"
#001H T1 AB:000 DB:-- M1 1 1 fMFetch ? < u alu < res H PLA * ? ? ? * A is stored in each ALU PLA below
#002H T2 AB:000 DB:86 M1 MREQ RD 1 2 fMFetch F < < PLA ?NF_HF_CF "If (NF), complement HF, CF"
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:001 DB:-- 2 1 fMRead HL W
#006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead WZ + R
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead 1 1 d < R alu >s0 bus L PLA * * * ?
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead Y d < R alu >s0 bus L PLA * * * ?
#017H T13 AB:000 DB:-- 4 1 fMRead R ...continues here
#018H T14 AB:000 DB:DD MREQ RD 4 2 fMRead AF > > >s0 bus bus * * * * * Reloads AF since (IX+d) used ALU core
#019H T15 AB:000 DB:DD MREQ RD 4 3 fMRead 1 1 d < R alu >s0 bus L PLA * * * ?
#019H T15 AB:000 DB:DD MREQ RD 4 3 fMRead Y d < R alu >s0 bus L PLA * * * ?
#end
#if pla[66] && !pla[53] : inc/dec r 4
#if pla[66] & ~pla[53] : inc/dec r 4
#001H T1 AB:000 DB:-- M1 1 1 fMFetch r8 < u alu < res H ADC * * V R
#002H T2 AB:000 DB:05 M1 MREQ RD 1 2 fMFetch F < < ?NF_HF "If (NF), complement HF"
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1 r8 > d alu >s0 0 bus L ADC * * * 0 1 W
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y r8' >r8' - alu >s0 0 bus L ADC * * * 0 1 W
#end
#if pla[75] : dec
453,18 → 453,18
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 0 NEG_OP2
#end
#if (M2 || M4) && pla[75] : dec
#if (M2 | M4) & pla[75] : dec
#always 1 0 NEG_OP2
#end
#if use_ixiy && pla[53] : inc/dec (ix+d) "4,3,5,4,3"
#if use_ixiy & pla[53] : inc/dec (ix+d) "4,3,5,4,3"
#005H T1 AB:001 DB:-- M1 1 1 fMFetch
#006H T2 AB:001 DB:34 M1 MREQ RD 1 2 fMFetch
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#009H T5 AB:002 DB:-- 2 1 fMRead PC W
#010H T6 AB:002 DB:01 MREQ RD 2 2 fMRead PC + R
#011H T7 AB:002 DB:01 MREQ RD 2 3 fMRead 1
#011H T7 AB:002 DB:01 MREQ RD 2 3 fMRead Y
#012H T8 AB:002 DB:-- 3 1 WZ=IX+d
#013H T9 AB:002 DB:-- 3 2 WZ=IX+d
#014H T10 AB:002 DB:-- 3 3 WZ=IX+d
472,11 → 472,11
#016H T12 AB:002 DB:-- 3 5 mr WZ=IX+d Clears the IX/IY and ...
#end
#if !use_ixiy && pla[53] : inc/dec (hl) "4,4,3"
#if ~use_ixiy & pla[53] : inc/dec (hl) "4,4,3"
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:34 M1 MREQ RD 1 2 fMFetch F < < ?NF_HF "If (NF), complement HF"
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:001 DB:-- 2 1 fMRead HL W
#006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead d < R alu >s0 0 bus L ADC * 0 1 W
483,7 → 483,7
#008H T8 AB:001 DB:-- 2 4 mw u > W alu < res H ADC * * V R
#009H T9 AB:001 DB:-- 3 1 fMWrite R
#010H T10 AB:001 DB:02 MREQ 3 2 fMWrite
#011H T11 AB:001 DB:02 MREQ WR 3 3 fMWrite 1 1
#011H T11 AB:001 DB:02 MREQ WR 3 3 fMWrite Y
#017H T13 AB:002 DB:-- 4 1 fMRead R ...continues here
#018H T14 AB:002 DB:01 MREQ RD 4 2 fMRead
491,7 → 491,7
#020H T16 AB:002 DB:-- 4 4 mw u > W alu < res H ADC * * V R
#021H T17 AB:002 DB:-- 5 1 fMWrite R
#022H T18 AB:002 DB:02 MREQ 5 2 fMWrite
#023H T19 AB:002 DB:02 MREQ WR 5 3 fMWrite 1 1
#023H T19 AB:002 DB:02 MREQ WR 5 3 fMWrite Y
#end
// 16-bit Arithmetic Group
500,42 → 500,42
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:09 M1 MREQ RD 1 2 fMFetch F < <
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * 0 *
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 1 L > d >s0 bus
#005H T5 AB:000 DB:-- 2 1 rl > d alu >s0 bus L ADD * USE_SP
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y L >l d >s0 bus
#005H T5 AB:000 DB:-- 2 1 rl >l d alu >s0 bus L ADD * USE_SP
#006H T6 AB:000 DB:-- 2 2 Z <l u alu < res H ADC * *
#007H T7 AB:000 DB:-- 2 3 H > d >s0 bus
#008H T8 AB:000 DB:-- 2 4 1 rh > d alu >s0 bus L ADC * USE_SP
#007H T7 AB:000 DB:-- 2 3 H > >s0 bus
#008H T8 AB:000 DB:-- 2 4 Y rh > alu >s0 bus L ADC * USE_SP
#009H T9 AB:000 DB:-- 3 1 WZ W W <h u alu < res H ADC * *
#010H T10 AB:000 DB:-- 3 2 HL R
#011H T11 AB:000 DB:-- 3 3 1 1
#011H T11 AB:000 DB:-- 3 3 Y
#end
"#if op3 && pla[68] : adc hl,ss" "4,4,3"
"#if op3 & pla[68] : adc hl,ss" "4,4,3"
#005H T1 AB:001 DB:-- M1 1 1 fMFetch
#006H T2 AB:001 DB:42 M1 MREQ RD 1 2 fMFetch F < <
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * 0 *
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 1 L > d >s0 bus
#009H T5 AB:001 DB:-- 2 1 rl > d alu >s0 bus L ADC * USE_SP
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y Y L >l d >s0 bus
#009H T5 AB:001 DB:-- 2 1 rl >l d alu >s0 bus L ADC * USE_SP
#010H T6 AB:001 DB:-- 2 2 Z <l u alu < res H ADC * * *
#011H T7 AB:001 DB:-- 2 3 H > d >s0 bus
#012H T8 AB:001 DB:-- 2 4 1 rh > d alu >s0 bus L ADC * USE_SP
#011H T7 AB:001 DB:-- 2 3 H > >s0 bus
#012H T8 AB:001 DB:-- 2 4 Y rh > alu >s0 bus L ADC * USE_SP
#013H T9 AB:001 DB:-- 3 1 WZ W W <h u alu < res H ADC * * V * ZERO_16BIT
#014H T10 AB:001 DB:-- 3 2 HL R
#015H T11 AB:001 DB:-- 3 3 1 1
#015H T11 AB:001 DB:-- 3 3 Y
#end
"#if !op3 && pla[68] : sbc hl,ss" "4,4,3"
"#if ~op3 & pla[68] : sbc hl,ss" "4,4,3"
#005H T1 AB:001 DB:-- M1 1 1 fMFetch
#006H T2 AB:001 DB:42 M1 MREQ RD 1 2 fMFetch F < < ?NF_HF_CF
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * 1 *
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 1 L > d >s0 bus
#009H T5 AB:001 DB:-- 2 1 rl > d alu >s0 bus L SBC * USE_SP
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y Y L >l d >s0 bus
#009H T5 AB:001 DB:-- 2 1 rl >l d alu >s0 bus L SBC * USE_SP
#010H T6 AB:001 DB:-- 2 2 Z <l u alu < res H SBC * * *
#011H T7 AB:001 DB:-- 2 3 H > d >s0 bus
#012H T8 AB:001 DB:-- 2 4 1 rh > d alu >s0 bus L SBCh * USE_SP
#011H T7 AB:001 DB:-- 2 3 H > >s0 bus
#012H T8 AB:001 DB:-- 2 4 Y rh > alu >s0 bus L SBCh * USE_SP
#013H T9 AB:001 DB:-- 3 1 WZ W W <h u alu < res H SBC * * V * ZERO_16BIT
#014H T10 AB:001 DB:-- 3 2 HL R
#015H T11 AB:001 DB:-- 3 3 1 1
#015H T11 AB:001 DB:-- 3 3 Y
#end
#if pla[9] : inc/dec ss 6
542,9 → 542,9
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:03 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 r16 W USE_SP
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y r16 W USE_SP
#005H T5 AB:000 DB:-- 1 5 r16 op3 R USE_SP
#006H T6 AB:000 DB:-- 1 6 1 1
#006H T6 AB:000 DB:-- 1 6 Y
#end
// General Purpose Arithmetic and CPU Control Groups
553,7 → 553,7
#001H T1 AB:000 DB:-- M1 1 1 fMFetch A < alu < res H ADC * * P * ?NF_SUB
#002H T2 AB:000 DB:27 M1 MREQ RD 1 2 fMFetch F < < R ?NF_HF
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * W2 * * * "Only for DAA, write HF2 flag"
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1 d alu >s0 bus L ADC * * * 0 W.daa "DAA,?NF_SUB"
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y d alu >s0 bus L ADC * * * 1 W.daa "DAA,?NF_SUB"
#end
#if pla[81] : cpl 4
560,7 → 560,7
#001H T1 AB:000 DB:-- M1 1 1 fMFetch A < alu < res H OR * 1 NEG_OP2
#002H T2 AB:000 DB:2F M1 MREQ RD 1 2 fMFetch F < < ?NF_HF
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1 alu 0 L OR * * 1 NEG_OP2
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y alu 0 L OR * * 1 NEG_OP2
#end
#if pla[82] : neg 4
567,7 → 567,7
#005H T1 AB:001 DB:-- M1 1 1 fMFetch A < alu < res H SUB * * V 1 *
#006H T2 AB:001 DB:44 M1 MREQ RD 1 2 fMFetch F < < ?NF_HF_CF
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1 alu 0 L SUB * * * 1 *
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y Y alu 0 L SUB * * * 1 *
#end
#if pla[89] : ccf 4
574,7 → 574,7
#001H T1 AB:000 DB:-- M1 1 1 fMFetch alu < res H OR * 0
#002H T2 AB:000 DB:3F M1 MREQ RD 1 2 fMFetch F < < ^ ?~CF_HF
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1 alu L OR * * 0
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y alu L OR * * 0
#end
#if pla[92] : scf 4
581,7 → 581,7
#001H T1 AB:000 DB:-- M1 1 1 fMFetch alu < res H OR * 0
#002H T2 AB:000 DB:37 M1 MREQ RD 1 2 fMFetch F < < 1
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1 alu L OR * * 0
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y alu L OR * * 0
#end
#if pla[95] : halt 4
588,7 → 588,7
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:76 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch HALT
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y
#end
#if pla[97] : di/ei 4
595,7 → 595,7
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:F3 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch DI_EI
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1 NO_INTS "At last M/T, inhibit interrupts"
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y NO_INTS "At last M/T, inhibit interrupts"
#end
#if pla[96] : im n 4
602,7 → 602,7
#005H T1 AB:001 DB:-- M1 1 1 fMFetch
#006H T2 AB:001 DB:46 M1 MREQ RD 1 2 fMFetch
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch < R IM M1/T3 reads in mode # from opcode[4:3]
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y Y
#end
// Rotate and Shift Group
611,14 → 611,14
#001H T1 AB:000 DB:-- M1 1 1 fMFetch A < alu < res H OR * * 0 *
#002H T2 AB:000 DB:07 M1 MREQ RD 1 2 fMFetch F < < R
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1 A > alu >s1 bus bus L OR * * 0 W.sh
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y A > alu >s1 bus bus L OR * * 0 W.sh
#end
#if ~use_ixiy && pla[70] && !pla[55] : rlc r 4
#if ~use_ixiy & pla[70] & ~pla[55] : rlc r 4
#005H T1 AB:001 DB:-- M1 1 1 fMFetch r8' < u alu < res H OR * * * P 0 *
#006H T2 AB:001 DB:00 M1 MREQ RD 1 2 fMFetch F < < R
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1 r8' > d alu >s1 bus bus L OR * * * 0 W.sh
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y Y r8 >r8 - alu >s1 bus bus L OR * * * 0 W.sh
#017H T13 AB:000 DB:-- 4 1 fMRead WZ W R OpcodeToIR ...continues here from the (ix+d) addressing mode
#018H T14 AB:000 DB:DD MREQ RD 4 2 fMRead
625,14 → 625,14
#019H T15 AB:000 DB:DD MREQ RD 4 3 fMRead mw d < R alu >s1 bus bus L OR 0 W.sh
#029H T17 AB:002 DB:-- 5 1 fMWrite R u > W alu < res H OR * * * P 0 *
#030H T18 AB:002 DB:BB MREQ 5 2 fMWrite
#031H T19 AB:002 DB:BB MREQ WR 5 3 fMWrite 1 1
#031H T19 AB:002 DB:BB MREQ WR 5 3 fMWrite Y
#end
#if ~use_ixiy && pla[70] && pla[55] : rlc (hl) "4,4,3"
#if ~use_ixiy & pla[70] & pla[55] : rlc (hl) "4,4,3"
#005H T1 AB:001 DB:-- M1 1 1 fMFetch
#006H T2 AB:001 DB:00 M1 MREQ RD 1 2 fMFetch F < < R
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#009H T5 AB:006 DB:-- 2 1 fMRead HL W
#010H T6 AB:006 DB:05 MREQ RD 2 2 fMRead
#011H T7 AB:006 DB:05 MREQ RD 2 3 fMRead
639,7 → 639,7
#012H T8 AB:006 DB:-- 2 4 mw d < R alu >s1 bus bus L OR 0 W.sh
#013H T9 AB:006 DB:-- 3 1 fMWrite R u > W alu < res H OR * * * P 0 *
#014H T10 AB:006 DB:0A MREQ 3 2 fMWrite
#015H T11 AB:006 DB:0A MREQ WR 3 3 fMWrite 1 1
#015H T11 AB:006 DB:0A MREQ WR 3 3 fMWrite Y
#017H T13 AB:000 DB:-- 4 1 fMRead WZ W R OpcodeToIR ...continues here from the (ix+d) addressing mode
#018H T14 AB:000 DB:DD MREQ RD 4 2 fMRead
646,17 → 646,17
#019H T15 AB:000 DB:DD MREQ RD 4 3 fMRead mw d < R alu >s1 bus bus L OR 0 W.sh
#029H T17 AB:002 DB:-- 5 1 fMWrite R u > W alu < res H OR * * * P 0 *
#030H T18 AB:002 DB:BB MREQ 5 2 fMWrite
#031H T19 AB:002 DB:BB MREQ WR 5 3 fMWrite 1 1
#031H T19 AB:002 DB:BB MREQ WR 5 3 fMWrite Y
#end
#if pla[15] && op3 : rld "4,3,4,3"
#if pla[15] & op3 : rld "4,3,4,3"
#005H T1 AB:001 DB:-- M1 1 1 fMFetch A < alu < res H OR * * P 0
#006H T2 AB:001 DB:67 M1 MREQ RD 1 2 fMFetch F < <
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#009H T5 AB:000 DB:-- 2 1 fMRead HL W
#010H T6 AB:000 DB:ED MREQ RD 2 2 fMRead WZ + R
#011H T7 AB:000 DB:ED MREQ RD 2 3 fMRead 1
#011H T7 AB:000 DB:ED MREQ RD 2 3 fMRead Y
#012H T8 AB:000 DB:-- 3 1 d < R >s0 lq L
#013H T9 AB:000 DB:-- 3 2
#014H T10 AB:000 DB:-- 3 3
663,17 → 663,17
#015H T11 AB:000 DB:-- 3 4 mw d < R >s0 low H
#016H T12 AB:000 DB:-- 4 1 fMWrite R u > W < op2
#017H T13 AB:000 DB:EE MREQ 4 2 fMWrite op1 bus
#018H T14 AB:000 DB:EE MREQ WR 4 3 fMWrite 1 1 alu L OR * * * 0
#018H T14 AB:000 DB:EE MREQ WR 4 3 fMWrite Y alu L OR * * * 0
#end
#if pla[15] && !op3 : rrd "4,3,4,3"
#if pla[15] & ~op3 : rrd "4,3,4,3"
#005H T1 AB:001 DB:-- M1 1 1 fMFetch A < alu < res H OR * * P 0
#006H T2 AB:001 DB:67 M1 MREQ RD 1 2 fMFetch F < <
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#009H T5 AB:000 DB:-- 2 1 fMRead HL W
#010H T6 AB:000 DB:ED MREQ RD 2 2 fMRead WZ + R
#011H T7 AB:000 DB:ED MREQ RD 2 3 fMRead 1
#011H T7 AB:000 DB:ED MREQ RD 2 3 fMRead Y
#012H T8 AB:000 DB:-- 3 1 d < R >s0 lq low L
#013H T9 AB:000 DB:-- 3 2 u > W < op2
#014H T10 AB:000 DB:-- 3 3 A > >s0 lq L
680,44 → 680,44
#015H T11 AB:000 DB:-- 3 4 mw d < R >s0 low H
#016H T12 AB:000 DB:-- 4 1 fMWrite R u > W < op2
#017H T13 AB:000 DB:EE MREQ 4 2 fMWrite op1 bus
#018H T14 AB:000 DB:EE MREQ WR 4 3 fMWrite 1 1 alu L OR * * * 0
#018H T14 AB:000 DB:EE MREQ WR 4 3 fMWrite Y alu L OR * * * 0
#end
// Bit Manipulation Group
"#if ~use_ixiy && pla[72] && !pla[55] : bit b,r" 4
"#if ~use_ixiy & pla[72] & ~pla[55] : bit b,r" 4
#005H T1 AB:001 DB:-- M1 1 1 fMFetch alu < res H AND * * P 0
#006H T2 AB:001 DB:40 M1 MREQ RD 1 2 fMFetch F < <
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > R > >bs bus bus * * * * * * Override M1/T3 load with a bit select
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1 r8' > d alu >s0 bus L AND * * * 0
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y Y r8 >r8 - alu >s0 bus L AND * * * 0
#017H T13 AB:000 DB:-- 4 1 fMRead R R >bs bus bus OpcodeToIR ...continues here from the (ix+d) addressing mode
#018H T14 AB:000 DB:DD MREQ RD 4 2 fMRead
#019H T15 AB:000 DB:DD MREQ RD 4 3 fMRead
#020H T16 AB:000 DB:-- 4 4 1 1 d < R alu >s0 bus L AND * * 0
#020H T16 AB:000 DB:-- 4 4 Y d < R alu >s0 bus L AND * * 0
#end
"#if ~use_ixiy && pla[72] && pla[55] : bit b,(hl)" "4,4"
"#if ~use_ixiy & pla[72] & pla[55] : bit b,(hl)" "4,4"
#005H T1 AB:001 DB:-- M1 1 1 fMFetch alu < res H AND * * P 0
#006H T2 AB:001 DB:06 M1 MREQ RD 1 2 fMFetch F < <
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > R > >bs bus bus * * * * * * Override M1/T3 load with a bit select
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#009H T5 AB:006 DB:-- 2 1 fMRead HL W
#010H T6 AB:006 DB:05 MREQ RD 2 2 fMRead
#011H T7 AB:006 DB:05 MREQ RD 2 3 fMRead WZ > > * "BIT n,(HL) saves WZ in X,Y (""MEMPTR"")"
#012H T8 AB:006 DB:-- 2 4 1 1 d < R alu >s0 bus L AND * * 0
#012H T8 AB:006 DB:-- 2 4 Y d < R alu >s0 bus L AND * * 0
#017H T13 AB:000 DB:-- 4 1 fMRead WZ W R >bs bus bus OpcodeToIR ...continues here from the (ix+d) addressing mode
#018H T14 AB:000 DB:DD MREQ RD 4 2 fMRead
#019H T15 AB:000 DB:DD MREQ RD 4 3 fMRead
#020H T16 AB:000 DB:-- 4 4 1 1 d < R alu >s0 bus L AND * * 0
#020H T16 AB:000 DB:-- 4 4 Y d < R alu >s0 bus L AND * * 0
#end
"#if ~use_ixiy && pla[74] && !pla[55] : set b,r" 4
"#if ~use_ixiy & pla[74] & ~pla[55] : set b,r" 4
#005H T1 AB:001 DB:-- M1 1 1 fMFetch r8' < u < res H OR
#006H T2 AB:001 DB:40 M1 MREQ RD 1 2 fMFetch
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > R > >bs bus bus * * * * * * Override M1/T3 load with a bit select
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1 r8' > d >s0 bus L OR
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y Y r8 >r8 - >s0 bus L OR
#017H T13 AB:000 DB:-- 4 1 fMRead WZ W R >bs bus bus OpcodeToIR ...continues here from the (ix+d) addressing mode
#018H T14 AB:000 DB:DD MREQ RD 4 2 fMRead
724,14 → 724,14
#019H T15 AB:000 DB:DD MREQ RD 4 3 fMRead mw d < R alu >s0 bus L OR
#029H T17 AB:002 DB:-- 5 1 fMWrite R u > W < res H OR
#030H T18 AB:002 DB:BB MREQ 5 2 fMWrite
#031H T19 AB:002 DB:BB MREQ WR 5 3 fMWrite 1 1
#031H T19 AB:002 DB:BB MREQ WR 5 3 fMWrite Y
#end
"#if ~use_ixiy && pla[74] && pla[55] : set b,(hl)" "4,4,3"
"#if ~use_ixiy & pla[74] & pla[55] : set b,(hl)" "4,4,3"
#005H T1 AB:001 DB:-- M1 1 1 fMFetch
#006H T2 AB:001 DB:06 M1 MREQ RD 1 2 fMFetch
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > R > >bs bus bus * * * * * * Override M1/T3 load with a bit select
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#009H T5 AB:006 DB:-- 2 1 fMRead HL W
#010H T6 AB:006 DB:05 MREQ RD 2 2 fMRead
#011H T7 AB:006 DB:05 MREQ RD 2 3 fMRead d < R >s0 bus L OR
738,7 → 738,7
#012H T8 AB:006 DB:-- 2 4 mw u > W < res H OR
#013H T9 AB:006 DB:-- 3 1 fMWrite R
#014H T10 AB:006 DB:0A MREQ 3 2 fMWrite
#015H T11 AB:006 DB:0A MREQ WR 3 3 fMWrite 1 1
#015H T11 AB:006 DB:0A MREQ WR 3 3 fMWrite Y
#017H T13 AB:000 DB:-- 4 1 fMRead WZ W R >bs bus bus OpcodeToIR ...continues here from the (ix+d) addressing mode
#018H T14 AB:000 DB:DD MREQ RD 4 2 fMRead
745,14 → 745,14
#019H T15 AB:000 DB:DD MREQ RD 4 3 fMRead mw d < R alu >s0 bus L OR
#029H T17 AB:002 DB:-- 5 1 fMWrite R u > W < res H OR
#030H T18 AB:002 DB:BB MREQ 5 2 fMWrite
#031H T19 AB:002 DB:BB MREQ WR 5 3 fMWrite 1 1
#031H T19 AB:002 DB:BB MREQ WR 5 3 fMWrite Y
#end
"#if ~use_ixiy && pla[73] && !pla[55] : res b,r" 4
"#if ~use_ixiy & pla[73] & ~pla[55] : res b,r" 4
#005H T1 AB:001 DB:-- M1 1 1 fMFetch r8' < u < res H NAND
#006H T2 AB:001 DB:40 M1 MREQ RD 1 2 fMFetch
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > R > >bs bus bus * * * * * * Override M1/T3 load with a bit select
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1 r8' > d >s0 bus L NAND
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y Y r8 >r8 - >s0 bus L NAND
#017H T13 AB:000 DB:-- 4 1 fMRead WZ W R >bs bus bus OpcodeToIR ...continues here from the (ix+d) addressing mode
#018H T14 AB:000 DB:DD MREQ RD 4 2 fMRead
759,14 → 759,14
#019H T15 AB:000 DB:DD MREQ RD 4 3 fMRead mw d < R alu >s0 bus L NAND
#029H T17 AB:002 DB:-- 5 1 fMWrite R u > W < res H NAND
#030H T18 AB:002 DB:BB MREQ 5 2 fMWrite
#031H T19 AB:002 DB:BB MREQ WR 5 3 fMWrite 1 1
#031H T19 AB:002 DB:BB MREQ WR 5 3 fMWrite Y
#end
"#if ~use_ixiy && pla[73] && pla[55] : res b,(hl)" "4,4,3"
"#if ~use_ixiy & pla[73] & pla[55] : res b,(hl)" "4,4,3"
#005H T1 AB:001 DB:-- M1 1 1 fMFetch
#006H T2 AB:001 DB:06 M1 MREQ RD 1 2 fMFetch
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > R > >bs bus bus * * * * * * Override M1/T3 load with a bit select
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#009H T5 AB:006 DB:-- 2 1 fMRead HL W
#010H T6 AB:006 DB:05 MREQ RD 2 2 fMRead
#011H T7 AB:006 DB:05 MREQ RD 2 3 fMRead d < R >s0 bus L NAND
773,7 → 773,7
#012H T8 AB:006 DB:-- 2 4 mw u > W < res H NAND
#013H T9 AB:006 DB:-- 3 1 fMWrite R
#014H T10 AB:006 DB:0A MREQ 3 2 fMWrite
#015H T11 AB:006 DB:0A MREQ WR 3 3 fMWrite 1 1
#015H T11 AB:006 DB:0A MREQ WR 3 3 fMWrite Y
#017H T13 AB:000 DB:-- 4 1 fMRead WZ W R >bs bus bus OpcodeToIR ...continues here from the (ix+d) addressing mode
#018H T14 AB:000 DB:DD MREQ RD 4 2 fMRead
780,16 → 780,16
#019H T15 AB:000 DB:DD MREQ RD 4 3 fMRead mw d < R alu >s0 bus L NAND
#029H T17 AB:002 DB:-- 5 1 fMWrite R u > W < res H NAND
#030H T18 AB:002 DB:BB MREQ 5 2 fMWrite
#031H T19 AB:002 DB:BB MREQ WR 5 3 fMWrite 1 1
#031H T19 AB:002 DB:BB MREQ WR 5 3 fMWrite Y
#end
// Input and Output Groups
"#if pla[37] && !pla[28] : in a,(n)" "4,3,4"
"#if pla[37] & ~pla[28] : in a,(n)" "4,3,4"
#001H T1 AB:000 DB:-- M1 1 1 fMFetch A < d < R
#002H T2 AB:000 DB:DB M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:001 DB:-- 2 1 fMRead PC W
#006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead ior
796,50 → 796,50
#008H T8 AB:001 DB:-- 3 1 fIORead A W ? < < R
#009H T9 AB:001 DB:-- RD IORQ 3 2 fIORead
#010H T10 AB:001 DB:-- RD IORQ 3 3 fIORead
#011H T11 AB:001 DB:-- RD IORQ 3 4 fIORead 1 1
#011H T11 AB:001 DB:-- RD IORQ 3 4 fIORead Y
#end
"#if pla[27] && !pla[34] : in r,(c)" "4,4"
"#if pla[27] & ~pla[34] : in r,(c)" "4,4"
#005H T1 AB:001 DB:-- M1 1 1 fMFetch r8 < d < R alu res H OR * * P 0
#006H T2 AB:001 DB:40 M1 MREQ RD 1 2 fMFetch F < <
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 ior
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y ior
#009H T5 AB:0FF DB:-- 2 1 fIORead BC W
#010H T6 AB:0FF DB:-- RD IORQ 2 2 fIORead
#011H T7 AB:0FF DB:-- RD IORQ 2 3 fIORead
#012H T8 AB:0FF DB:-- RD IORQ 2 4 fIORead 1 1 d < R alu >s0 bus bus L OR * * * 0
#012H T8 AB:0FF DB:-- RD IORQ 2 4 fIORead Y d < R alu >s0 bus bus L OR * * * 0
#end
"#if pla[37] && pla[28] : out (n),a" "4,3,4"
"#if pla[37] & pla[28] : out (n),a" "4,3,4"
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:D3 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:001 DB:-- 2 1 fMRead PC W
#006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead iow A W <l < R
#008H T8 AB:001 DB:-- 3 1 fIOWrite R A > u > W
#008H T8 AB:001 DB:-- 3 1 fIOWrite R A >h u > W
#009H T9 AB:001 DB:03 WR IORQ 3 2 fIOWrite
#010H T10 AB:001 DB:03 WR IORQ 3 3 fIOWrite
#011H T11 AB:001 DB:03 WR IORQ 3 4 fIOWrite 1 1
#011H T11 AB:001 DB:03 WR IORQ 3 4 fIOWrite Y
#end
"#if pla[27] && pla[34] : out (c),r" "4,4"
"#if pla[27] & pla[34] : out (c),r" "4,4"
#005H T1 AB:001 DB:-- M1 1 1 fMFetch
#006H T2 AB:001 DB:41 M1 MREQ RD 1 2 fMFetch
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 iow r8 > u > W
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y iow r8' >r8' - > W
#009H T5 AB:0FF DB:-- 2 1 fIOWrite BC W
#010H T6 AB:0FF DB:C3 WR IORQ 2 2 fIOWrite
#011H T7 AB:0FF DB:C3 WR IORQ 2 3 fIOWrite
#012H T8 AB:0FF DB:C3 WR IORQ 2 4 fIOWrite 1 1
#012H T8 AB:0FF DB:C3 WR IORQ 2 4 fIOWrite Y
#end
#if pla[91] && pla[21] : ini/inir/ind/indr "5,4,3,(5)"
#if pla[91] & pla[21] : ini/inir/ind/indr "5,4,3,(5)"
#035H T1 AB:00A DB:-- M1 1 1 fMFetch < res H XOR P
#036H T2 AB:00A DB:B2 M1 MREQ RD 1 2 fMFetch F < <
#037H T3 AB:004 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#038H T4 AB:004 DB:-- RFSH MREQ 1 4 fMFetch 1
#038H T4 AB:004 DB:-- RFSH MREQ 1 4 fMFetch Y
#039H T5 AB:004 DB:-- 1 5 ior
#040H T6 AB:000 DB:-- 2 1 fIORead BC W
#041H T7 AB:000 DB:-- RD IORQ 2 2 fIORead B > alu >s0 0 bus L ADD * NEG_OP2
847,32 → 847,32
#043H T9 AB:000 DB:-- RD IORQ 2 4 fIORead mw d < R alu >s0 bus S NEG_OP2
#044H T10 AB:000 DB:-- 3 1 fMWrite HL W
#045H T11 AB:000 DB:B1 MREQ 3 2 fMWrite HL op3 R
#046H T12 AB:000 DB:B1 MREQ WR 3 3 fMWrite 1 BZ
#046H T12 AB:000 DB:B1 MREQ WR 3 3 fMWrite Y BZ
#047H T13 AB:000 DB:-- 4 1 PC W
#048H T14 AB:000 DB:-- 4 2 PC - R
#049H T15 AB:000 DB:-- 4 3 PC W
#050H T16 AB:000 DB:-- 4 4 PC - R
#051H T17 AB:000 DB:-- 4 5 1 1
#051H T17 AB:000 DB:-- 4 5 Y
#end
#if pla[91] && pla[20] : outi/outir/outd/outdr "5,4,3,(5)"
#if pla[91] & pla[20] : outi/outir/outd/outdr "5,4,3,(5)"
#035H T1 AB:00A DB:-- M1 1 1 fMFetch alu < res H XOR P
#036H T2 AB:00A DB:B3 M1 MREQ RD 1 2 fMFetch F < <
#037H T3 AB:004 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#038H T4 AB:004 DB:-- RFSH MREQ 1 4 fMFetch 1 B > alu >s0 0 bus L ADD * NEG_OP2
#038H T4 AB:004 DB:-- RFSH MREQ 1 4 fMFetch Y B > alu >s0 0 bus L ADD * NEG_OP2
#039H T5 AB:004 DB:-- 1 5 mr B < alu < res H ADD * * NEG_OP2
#040H T6 AB:000 DB:-- 2 1 fMRead HL W
#041H T7 AB:000 DB:21 MREQ RD 2 2 fMRead HL op3 R
#042H T8 AB:000 DB:21 MREQ RD 2 3 fMRead iow L > d >s0 bus
#042H T8 AB:000 DB:21 MREQ RD 2 3 fMRead iow L >l d >s0 bus
#043H T9 AB:000 DB:-- 3 1 fIOWrite BC W
#044H T10 AB:000 DB:21 WR IORQ 3 2 fIOWrite d < R alu >s0 bus L ADD * S
#045H T11 AB:000 DB:21 WR IORQ 3 3 fIOWrite alu < res H ADD *
#046H T12 AB:000 DB:21 WR IORQ 3 4 fIOWrite 1 BZ
#046H T12 AB:000 DB:21 WR IORQ 3 4 fIOWrite Y BZ
#047H T13 AB:000 DB:-- 4 1 PC W
#048H T14 AB:000 DB:-- 4 2 PC - R
#049H T15 AB:000 DB:-- 4 3 PC W
#050H T16 AB:000 DB:-- 4 4 PC - R
#051H T17 AB:000 DB:-- 4 5 1 1
#051H T17 AB:000 DB:-- 4 5 Y
#end
// Jump Group
881,13 → 881,13
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:C3 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:001 DB:-- 2 1 fMRead PC W
#006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mr Z <l d < R
#008H T8 AB:002 DB:-- 3 1 fMRead PC W
#009H T9 AB:002 DB:02 MREQ RD 3 2 fMRead PC + R
#010H T10 AB:002 DB:02 MREQ RD 3 3 fMRead 1 1 WZ W W <h d < R NOT_PC!
#010H T10 AB:002 DB:02 MREQ RD 3 3 fMRead Y WZ W W <h d < R NOT_PC!
#end
"#if pla[43] : jp cc,nn" "4,3,3"
894,13 → 894,13
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:C2 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:001 DB:-- 2 1 fMRead PC W
#006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mr Z <l d < R
#008H T8 AB:002 DB:-- 3 1 fMRead PC W
#009H T9 AB:002 DB:02 MREQ RD 3 2 fMRead PC + R
#010H T10 AB:002 DB:02 MREQ RD 3 3 fMRead 1 1 WZ? W W? <h d < R Select WZ if condition is true
#010H T10 AB:002 DB:02 MREQ RD 3 3 fMRead Y WZ? W W? <h d < R Select WZ if condition is true
#end
#if pla[47] : jr e "4,3,5"
907,15 → 907,15
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:18 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:001 DB:-- 2 1 fMRead PC W
#006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead 1
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead Y
#008H T8 AB:001 DB:-- 3 1 d < R alu >s0 bus * "Reads ""e"" from the data latch"
#009H T9 AB:001 DB:-- 3 2 PCl > d alu >s0 bus L ADD *
#009H T9 AB:001 DB:-- 3 2 PCl >l d alu >s0 bus L ADD *
#010H T10 AB:001 DB:-- 3 3 Z <l u alu < res H ADD *
#011H T11 AB:001 DB:-- 3 4 PCh > alu >s0 0 bus L ADC * ?SF_NEG
#012H T12 AB:001 DB:-- 3 5 1 1 WZ W W <h alu < res H ADC "?SF_NEG, NOT_PC!"
#012H T12 AB:001 DB:-- 3 5 Y WZ W W <h alu < res H ADC "?SF_NEG, NOT_PC!"
#end
"#if pla[48] : jr ss,e" "4,3,(5)"
922,15 → 922,15
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:20 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr CondShort M1/T4 evaluates a condition: force short
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr CondShort M1/T4 evaluates a condition: force short
#005H T5 AB:001 DB:-- 2 1 fMRead PC W
#006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead 1 SS
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead Y SS
#008H T8 AB:001 DB:-- 3 1 d < R alu >s0 bus * "Reads ""e"" from the data latch"
#009H T9 AB:001 DB:-- 3 2 PCl > d alu >s0 bus L ADD *
#009H T9 AB:001 DB:-- 3 2 PCl >l d alu >s0 bus L ADD *
#010H T10 AB:001 DB:-- 3 3 Z <l u alu < res H ADD *
#011H T11 AB:001 DB:-- 3 4 PCh > alu >s0 0 bus L ADC * ?SF_NEG
#012H T12 AB:001 DB:-- 3 5 1 1 WZ W W <h alu < res H ADC "?SF_NEG, NOT_PC!"
#012H T12 AB:001 DB:-- 3 5 Y WZ W W <h alu < res H ADC "?SF_NEG, NOT_PC!"
#end
#if pla[6] : jp hl 4
937,7 → 937,7
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:E9 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1 HL W NOT_PC!
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y HL W NOT_PC!
#end
#if pla[26] : djnz e "5,3,(5)"
944,16 → 944,16
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:10 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 B > d alu >s0 0 bus L ADD * NEG_OP2 B=B-1
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y B >h alu >s0 0 bus L ADD * NEG_OP2 B=B-1
#005H T5 AB:000 DB:-- 1 5 mr B < alu < res H ADD * NEG_OP2
#006H T6 AB:001 DB:-- 2 1 fMRead PC W
#007H T7 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R
#008H T8 AB:001 DB:01 MREQ RD 2 3 fMRead 1 ZF
#008H T8 AB:001 DB:01 MREQ RD 2 3 fMRead Y ZF
#009H T9 AB:001 DB:-- 3 1 d < R alu >s0 bus * "Reads ""e"" from the data latch"
#010H T10 AB:001 DB:-- 3 2 PCl > d alu >s0 bus L ADD *
#010H T10 AB:001 DB:-- 3 2 PCl >l d alu >s0 bus L ADD *
#011H T11 AB:001 DB:-- 3 3 Z <l u alu < res H ADD *
#012H T12 AB:001 DB:-- 3 4 PCh > alu >s0 0 bus L ADC * ?SF_NEG
#013H T13 AB:001 DB:-- 3 5 1 1 WZ W W <h alu < res H ADC "?SF_NEG, NOT_PC!"
#012H T12 AB:001 DB:-- 3 4 PCh >h alu >s0 0 bus L ADC * ?SF_NEG
#013H T13 AB:001 DB:-- 3 5 Y WZ W W <h alu < res H ADC "?SF_NEG, NOT_PC!"
#end
// Call and Return Group
962,7 → 962,7
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:CD M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:001 DB:-- 2 1 fMRead PC W
#006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mr Z <l d < R
970,12 → 970,12
#009H T9 AB:002 DB:02 MREQ RD 3 2 fMRead PC + R
#010H T10 AB:002 DB:02 MREQ RD 3 3 fMRead W <h d < R
#011H T11 AB:002 DB:-- 3 4 mw SP - W
#012H T12 AB:000 DB:-- 4 1 fMWrite - P PCh > u > W
#012H T12 AB:000 DB:-- 4 1 fMWrite - P PCh >h u > W
#013H T13 AB:000 DB:00 MREQ 4 2 fMWrite SP - R
#014H T14 AB:000 DB:00 MREQ WR 4 3 fMWrite mw SP - W
#015H T15 AB:0FF DB:-- 5 1 fMWrite - P PCl > u > W
#015H T15 AB:0FF DB:-- 5 1 fMWrite - P PCl >l > W
#016H T16 AB:0FF DB:03 MREQ 5 2 fMWrite SP - R
#017H T17 AB:0FF DB:03 MREQ WR 5 3 fMWrite 1 1 WZ W NOT_PC!
#017H T17 AB:0FF DB:03 MREQ WR 5 3 fMWrite Y WZ W NOT_PC!
#end
"#if pla[42] : call cc,nn" "4,3,3/(4,3,4,3,3)"
982,7 → 982,7
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:C4 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:001 DB:-- 2 1 fMRead PC W
#006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R
#007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mr Z <l d < R
990,12 → 990,12
#009H T9 AB:002 DB:02 MREQ RD 3 2 fMRead PC + R
#010H T10 AB:002 DB:02 MREQ RD 3 3 fMRead CC CC W? <h d < R Load W only if condition is true
#011H T11 AB:002 DB:-- 3 4 mw SP - W
#012H T12 AB:000 DB:-- 4 1 fMWrite - P PCh > u > W
#012H T12 AB:000 DB:-- 4 1 fMWrite - P PCh >h u > W
#013H T13 AB:000 DB:00 MREQ 4 2 fMWrite SP - R
#014H T14 AB:000 DB:00 MREQ WR 4 3 fMWrite mw SP - W
#015H T15 AB:0FF DB:-- 5 1 fMWrite - P PCl > u > W
#015H T15 AB:0FF DB:-- 5 1 fMWrite - P PCl >l > W
#016H T16 AB:0FF DB:03 MREQ 5 2 fMWrite SP - R
#017H T17 AB:0FF DB:03 MREQ WR 5 3 fMWrite 1 1 WZ W NOT_PC!
#017H T17 AB:0FF DB:03 MREQ WR 5 3 fMWrite Y WZ W NOT_PC!
#end
#if pla[35] : ret "4,3,3"
1002,13 → 1002,13
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:C9 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#005H T5 AB:0FF DB:-- 2 1 fMRead SP W
#006H T6 AB:0FF DB:01 MREQ RD 2 2 fMRead SP + R
#007H T7 AB:0FF DB:01 MREQ RD 2 3 fMRead mr Z <l d < R
#008H T8 AB:000 DB:-- 3 1 fMRead SP W
#009H T9 AB:000 DB:C9 MREQ RD 3 2 fMRead SP + R
#010H T10 AB:000 DB:C9 MREQ RD 3 3 fMRead 1 1 WZ W W <h d < R NOT_PC!
#010H T10 AB:000 DB:C9 MREQ RD 3 3 fMRead Y WZ W W <h d < R NOT_PC!
#end
#if pla[45] : ret cc "5/(5,3,3)"
1015,7 → 1015,7
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:C0 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * *
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y
#005H T5 AB:000 DB:-- 1 5 mr CC
#006H T6 AB:001 DB:-- 2 1 fMRead SP W
#007H T7 AB:001 DB:01 MREQ RD 2 2 fMRead SP + R
1022,7 → 1022,7
#008H T8 AB:001 DB:01 MREQ RD 2 3 fMRead mr Z <l d < R
#009H T9 AB:002 DB:-- 3 1 fMRead SP W
#010H T10 AB:002 DB:02 MREQ RD 3 2 fMRead SP + R
#011H T11 AB:002 DB:02 MREQ RD 3 3 fMRead 1 1 WZ W W <h d < R NOT_PC!
#011H T11 AB:002 DB:02 MREQ RD 3 3 fMRead Y WZ W W <h d < R NOT_PC!
#end
#if pla[46] : reti/retn "4,3,3"
1029,13 → 1029,13
#005H T1 AB:001 DB:-- M1 1 1 fMFetch
#006H T2 AB:001 DB:45 M1 MREQ RD 1 2 fMFetch
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 mr RETN IFF1<=IFF2
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr RETN IFF1<=IFF2
#009H T5 AB:001 DB:-- 2 1 fMRead SP W
#010H T6 AB:001 DB:45 MREQ RD 2 2 fMRead SP + R
#011H T7 AB:001 DB:45 MREQ RD 2 3 fMRead mr Z <l d < R
#012H T8 AB:002 DB:-- 3 1 fMRead SP W
#013H T9 AB:002 DB:01 MREQ RD 3 2 fMRead SP + R
#014H T10 AB:002 DB:01 MREQ RD 3 3 fMRead 1 1 WZ W W <h d < R NOT_PC!
#014H T10 AB:002 DB:01 MREQ RD 3 3 fMRead Y WZ W W <h d < R NOT_PC!
#end
#if pla[56] : rst p "5,3,3"
1042,12 → 1042,12
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:C7 M1 MREQ RD 1 2 fMFetch
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch WZ < R < op1 0 "MASK_543, RST_NMI, RST_INT" RST instruction also executes on NMI and INT
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y
#005H T5 AB:000 DB:-- 1 5 mw SP - W d < R >s0 bus Store im2 vector into the ALU op1
#006H T6 AB:000 DB:-- 2 1 fMWrite - P PCh >h u > W
#007H T7 AB:000 DB:00 MREQ 2 2 fMWrite SP - R
#008H T8 AB:000 DB:00 MREQ WR 2 3 fMWrite mw SP - W
#009H T9 AB:0FF DB:-- 3 1 fMWrite - P PCl >l u > W
#009H T9 AB:0FF DB:-- 3 1 fMWrite - P PCl >l > W
#010H T10 AB:0FF DB:01 MREQ 3 2 fMWrite SP - R
#011H T11 AB:0FF DB:01 MREQ WR 3 3 fMWrite INT INT WZ W NOT_PC! Value on the bus into ALU OP
// INTR IM2 continues here... Extension for IM2 interrupt mode
1056,7 → 1056,7
#014H T14 AB:001 DB:01 MREQ RD 4 3 fMRead mr Z <l d < R
#015H T15 AB:002 DB:-- 5 1 fMRead I* W <l u < op1
#016H T16 AB:002 DB:02 MREQ RD 5 2 fMRead + R
#017H T17 AB:002 DB:02 MREQ RD 5 3 fMRead 1 1 WZ W W <h d < R NOT_PC!
#017H T17 AB:002 DB:02 MREQ RD 5 3 fMRead Y WZ W W <h d < R NOT_PC!
#end
// CB-Table opcodes
1065,7 → 1065,7
#005H T1 AB:001 DB:-- M1 1 1 fMFetch
#006H T2 AB:001 DB:CB M1 MREQ RD 1 2 fMFetch
#007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * CB
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch 1 mr
#008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr
#009H T5 AB:002 DB:-- 2 1 fMRead PC W
#010H T6 AB:002 DB:01 MREQ RD 2 2 fMRead PC + R
#011H T7 AB:002 DB:01 MREQ RD 2 3 fMRead mr
1084,7 → 1084,7
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:DD M1 MREQ RD 1 2 fMFetch IX_IY
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1 NO_INTS "At last M/T, inhibit interrupts"
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y NO_INTS "At last M/T, inhibit interrupts"
#end
#if pla[44] : CB prefix 4
1091,7 → 1091,7
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:CB M1 MREQ RD 1 2 fMFetch CB
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1 NO_INTS "At last M/T, inhibit interrupts"
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y NO_INTS "At last M/T, inhibit interrupts"
"#end Only set CB ff and clear ED, XX ff"
#if pla[51] : ED prefix 4
1098,7 → 1098,7
#001H T1 AB:000 DB:-- M1 1 1 fMFetch
#002H T2 AB:000 DB:ED M1 MREQ RD 1 2 fMFetch ED
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 1 1 NO_INTS "At last M/T, inhibit interrupts"
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y NO_INTS "At last M/T, inhibit interrupts"
"#end Only set ED ff and clear CB, XX ff"
#if pla[76] : ALU CP
1147,7 → 1147,7
// State machine to compute (IX+d)
#if ixy_d : Compute WZ=IX+d
#001H T1 any M-cycle ? 1 d < R alu >s0 bus * "Reads ""d"" from the data latch"
#002H T2 ? 2 L > d alu >s0 bus L ADD *
#002H T2 ? 2 L >l d alu >s0 bus L ADD *
#003H T3 ? 3 Z <l u alu < res H ADC W
#004H T4 ? 4 H > alu >s0 0 bus L ADC * R ?SF_NEG Stores result into WZ
#005H T5 ? 5 WZ W W <h alu < res H ADC * "?SF_NEG, CLR_IX_IY" and disables any further use of IX/IY
1154,9 → 1154,19
#end
// Default instruction fetch (M1) state machine
#if M1 :
#001H T1 AB:000 DB:-- M1 1 1 fMFetch PC + RL
#if 1 :
#001H T1 AB:000 DB:-- M1 1 1 fMFetch PC + RL Fetch/execute overlap
#002H T2 AB:000 DB:CB M1 MREQ RD 1 2 fMFetch IR W R "CLR_IX_IY, CLR_CB_ED, OpcodeToIR, OverrideIR" Prepares for the next execution cycle
#003H T3 AB:000 DB:-- RFSH 1 3 fMFetch IR + RL Limit6 "Fetch opcode, evaluate flags"
#004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch EvalCond
#end
"// For all undecoded instructions, at M1/T4 advance a byte to the next opcode"
#if ~validPLA : A catch-all case
#001H 1 4 Y
#end
// The last cycle of an instruction is also the first cycle of the next one
#if setM1 :
#always PC W Fetch/execute overlap
#end
/exec_module.vh
1,127 → 1,127
// Automatically generated by genref.py
 
// Module: control/decode_state.v
output logic ctl_state_iy_set,
output logic ctl_state_ixiy_clr,
output logic ctl_state_ixiy_we,
output logic ctl_state_halt_set,
output logic ctl_state_tbl_clr,
output logic ctl_state_tbl_ed_set,
output logic ctl_state_tbl_cb_set,
output logic ctl_state_alu,
output logic ctl_repeat_we,
output reg ctl_state_iy_set,
output reg ctl_state_ixiy_clr,
output reg ctl_state_ixiy_we,
output reg ctl_state_halt_set,
output reg ctl_state_tbl_clr,
output reg ctl_state_tbl_ed_set,
output reg ctl_state_tbl_cb_set,
output reg ctl_state_alu,
output reg ctl_repeat_we,
 
// Module: control/interrupts.v
output logic ctl_iff1_iff2,
output logic ctl_iffx_we,
output logic ctl_iffx_bit,
output logic ctl_im_we,
output logic ctl_no_ints,
output reg ctl_iff1_iff2,
output reg ctl_iffx_we,
output reg ctl_iffx_bit,
output reg ctl_im_we,
output reg ctl_no_ints,
 
// Module: control/ir.v
output logic ctl_ir_we,
output reg ctl_ir_we,
 
// Module: control/memory_ifc.v
output logic ctl_mRead,
output logic ctl_mWrite,
output logic ctl_iorw,
output reg ctl_mRead,
output reg ctl_mWrite,
output reg ctl_iorw,
 
// Module: alu/alu_control.v
output logic ctl_shift_en,
output logic ctl_daa_oe,
output logic ctl_alu_op_low,
output logic ctl_cond_short,
output logic ctl_alu_core_hf,
output logic ctl_eval_cond,
output logic ctl_66_oe,
output logic [1:0] ctl_pf_sel,
output reg ctl_shift_en,
output reg ctl_daa_oe,
output reg ctl_alu_op_low,
output reg ctl_cond_short,
output reg ctl_alu_core_hf,
output reg ctl_eval_cond,
output reg ctl_66_oe,
output reg [1:0] ctl_pf_sel,
 
// Module: alu/alu_select.v
output logic ctl_alu_oe,
output logic ctl_alu_shift_oe,
output logic ctl_alu_op2_oe,
output logic ctl_alu_res_oe,
output logic ctl_alu_op1_oe,
output logic ctl_alu_bs_oe,
output logic ctl_alu_op1_sel_bus,
output logic ctl_alu_op1_sel_low,
output logic ctl_alu_op1_sel_zero,
output logic ctl_alu_op2_sel_zero,
output logic ctl_alu_op2_sel_bus,
output logic ctl_alu_op2_sel_lq,
output logic ctl_alu_sel_op2_neg,
output logic ctl_alu_sel_op2_high,
output logic ctl_alu_core_R,
output logic ctl_alu_core_V,
output logic ctl_alu_core_S,
output reg ctl_alu_oe,
output reg ctl_alu_shift_oe,
output reg ctl_alu_op2_oe,
output reg ctl_alu_res_oe,
output reg ctl_alu_op1_oe,
output reg ctl_alu_bs_oe,
output reg ctl_alu_op1_sel_bus,
output reg ctl_alu_op1_sel_low,
output reg ctl_alu_op1_sel_zero,
output reg ctl_alu_op2_sel_zero,
output reg ctl_alu_op2_sel_bus,
output reg ctl_alu_op2_sel_lq,
output reg ctl_alu_sel_op2_neg,
output reg ctl_alu_sel_op2_high,
output reg ctl_alu_core_R,
output reg ctl_alu_core_V,
output reg ctl_alu_core_S,
 
// Module: alu/alu_flags.v
output logic ctl_flags_oe,
output logic ctl_flags_bus,
output logic ctl_flags_alu,
output logic ctl_flags_nf_set,
output logic ctl_flags_cf_set,
output logic ctl_flags_cf_cpl,
output logic ctl_flags_cf_we,
output logic ctl_flags_sz_we,
output logic ctl_flags_xy_we,
output logic ctl_flags_hf_we,
output logic ctl_flags_pf_we,
output logic ctl_flags_nf_we,
output logic ctl_flags_cf2_we,
output logic ctl_flags_hf_cpl,
output logic ctl_flags_use_cf2,
output logic ctl_flags_hf2_we,
output logic ctl_flags_nf_clr,
output logic ctl_alu_zero_16bit,
output logic [1:0] ctl_flags_cf2_sel,
output reg ctl_flags_oe,
output reg ctl_flags_bus,
output reg ctl_flags_alu,
output reg ctl_flags_nf_set,
output reg ctl_flags_cf_set,
output reg ctl_flags_cf_cpl,
output reg ctl_flags_cf_we,
output reg ctl_flags_sz_we,
output reg ctl_flags_xy_we,
output reg ctl_flags_hf_we,
output reg ctl_flags_pf_we,
output reg ctl_flags_nf_we,
output reg ctl_flags_cf2_we,
output reg ctl_flags_hf_cpl,
output reg ctl_flags_use_cf2,
output reg ctl_flags_hf2_we,
output reg ctl_flags_nf_clr,
output reg ctl_alu_zero_16bit,
output reg ctl_flags_cf2_sel_shift,
output reg ctl_flags_cf2_sel_daa,
 
// Module: registers/reg_file.v
output logic ctl_sw_4d,
output logic ctl_sw_4u,
output logic ctl_reg_in_hi,
output logic ctl_reg_in_lo,
output logic ctl_reg_out_lo,
output logic ctl_reg_out_hi,
output reg ctl_sw_4u,
output reg ctl_reg_in_hi,
output reg ctl_reg_in_lo,
output reg ctl_reg_out_lo,
output reg ctl_reg_out_hi,
 
// Module: registers/reg_control.v
output logic ctl_reg_exx,
output logic ctl_reg_ex_af,
output logic ctl_reg_ex_de_hl,
output logic ctl_reg_use_sp,
output logic ctl_reg_sel_pc,
output logic ctl_reg_sel_ir,
output logic ctl_reg_sel_wz,
output logic ctl_reg_gp_we,
output logic ctl_reg_not_pc,
output logic ctl_reg_sys_we_lo,
output logic ctl_reg_sys_we_hi,
output logic ctl_reg_sys_we,
output logic [1:0] ctl_reg_gp_hilo,
output logic [1:0] ctl_reg_gp_sel,
output logic [1:0] ctl_reg_sys_hilo,
output reg ctl_reg_exx,
output reg ctl_reg_ex_af,
output reg ctl_reg_ex_de_hl,
output reg ctl_reg_use_sp,
output reg ctl_reg_sel_pc,
output reg ctl_reg_sel_ir,
output reg ctl_reg_sel_wz,
output reg ctl_reg_gp_we,
output reg ctl_reg_not_pc,
output reg ctl_reg_sys_we_lo,
output reg ctl_reg_sys_we_hi,
output reg ctl_reg_sys_we,
output reg ctl_sw_4d,
output reg [1:0] ctl_reg_gp_hilo,
output reg [1:0] ctl_reg_gp_sel,
output reg [1:0] ctl_reg_sys_hilo,
 
// Module: bus/address_latch.v
output logic ctl_inc_cy,
output logic ctl_inc_dec,
output logic ctl_inc_zero,
output logic ctl_al_we,
output logic ctl_inc_limit6,
output logic ctl_bus_inc_oe,
output logic ctl_apin_mux,
output logic ctl_apin_mux2,
output reg ctl_inc_cy,
output reg ctl_inc_dec,
output reg ctl_al_we,
output reg ctl_inc_limit6,
output reg ctl_bus_inc_oe,
output reg ctl_apin_mux,
output reg ctl_apin_mux2,
 
// Module: bus/bus_control.v
output logic ctl_bus_ff_oe,
output logic ctl_bus_zero_oe,
output logic ctl_bus_db_oe,
output reg ctl_bus_ff_oe,
output reg ctl_bus_zero_oe,
 
// Module: bus/bus_switch.sv
output logic ctl_sw_1u,
output logic ctl_sw_1d,
output logic ctl_sw_2u,
output logic ctl_sw_2d,
output logic ctl_sw_mask543_en,
// Module: bus/bus_switch.v
output reg ctl_sw_1u,
output reg ctl_sw_1d,
output reg ctl_sw_2u,
output reg ctl_sw_2d,
output reg ctl_sw_mask543_en,
 
// Module: bus/data_pins.v
output logic ctl_bus_db_we,
output reg ctl_bus_db_we,
output reg ctl_bus_db_oe,
/gencompile.py
0,0 → 1,146
#!/usr/bin/env python3
#
# This script reads 'exec_matrix.vh' file and compiles it into an alternate format
# that can be used with Xilinx toolchain.
#
# Xilinx synthesis tool is effectively not capable of processing that file.
# Altera Quartus has no problems compiling it.
#
#-------------------------------------------------------------------------------
# Copyright (C) 2016 Goran Devic
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the Free
# Software Foundation; either version 2 of the License, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details.
#-------------------------------------------------------------------------------
import os
import io
import copy
import tokenize
from io import BytesIO
from tokenize import NAME, INDENT, DEDENT, ENCODING
 
# Input file to process
fname = "exec_matrix.vh"
 
# Output file to contain compiled version of the input
oname = "exec_matrix_compiled.vh"
 
# Output file to contain a list of temporary wires used by the compiled Verilog file
tname = "temp_wires.vh"
 
# Define a list of control signals that are 2-bits wide
ctls_wide = ['ctl_reg_gp_sel', 'ctl_reg_gp_hilo', 'ctl_reg_sys_hilo', 'ctl_pf_sel']
 
# Help recognizing control signal names
def is_ctl(name):
return name.startswith('ctl_') or name=='validPLA' or name=='nextM' or name=='setM1' \
or name=='fFetch' or name=='fMRead' or name=='fMWrite' or name=='fIORead' or name=='fIOWrite' \
or name=='ixy_d' or name=='setIXIY' or name=='setCBED' or name=='nonRep' or name=='pc_inc_hold'
 
def str2tok(s):
t = io.BytesIO(bytes(s.encode()))
return list(tokenize.tokenize(t.readline))[1:-1]
 
def tok2str(tokens):
line = [ tokens[n][m].string for n in range(len(tokens)) for m in range(len(tokens[n])) ]
return ''.join(line)
 
def get_rval(tokens, i):
assert (tokens[i+1].string=='=' or tokens[i+1].string=='|=')
paren = list(str2tok('()'))
rval = paren[:1]
while (tokens[i+2].string!=';'):
rval.append(tokens[i+2])
i += 1
rval.extend(paren[1:2])
return [rval]
 
def decomment(s):
i = s.find('//') # Remove trailing comments from a line
if i>=0:
return s[:i]
i = s.find('/*') # Remove comments within a line
j = s.find('*/')
if i>=0 and j>=0:
return decomment(s[:i] + s[j+2:])
return s
 
#--------------------------------------------------------------------------------
# Generate a sequential-or form for all control wires
#--------------------------------------------------------------------------------
def sequential_or(f, t, tokens):
incond = False # Inside an "if" condition state
cond = [] # Condition nested lists
ccond = [] # Currently scanned condition list
ctls = {} # Dictionary of control wires and their equations
ccwires = [] # List of wires at the current condition list level
i = 0 # Current index into the tokens list
while i < len(tokens):
tok = tokens[i]
(toknum, tokval, _, _, _) = tok
if incond and not (toknum==NAME and tokval=='begin'):
if toknum != DEDENT and toknum != INDENT:
ccond.append(tok)
if toknum==NAME:
if tokval=='if':
incond = True
if tokval=='begin': # Push a condition list
incond = False
cond.append(copy.deepcopy(ccond))
ccond.clear()
ccwires.clear()
if tokval=='end': # Pop a condition list
cond.pop()
if is_ctl(tokval) and not incond:
rval = get_rval(tokens, i)
linesub = tok2str(cond)
rhs = tok2str(rval)
line = "{0} = {0} | ".format(tokval)
if tokval in ccwires: # Check for duplicate assignments
hint = [ cond[n][m].string for n in range(len(cond)) for m in range(len(cond[n])) ]
print ("WARNING: {0}: Multiple assignment of {1}".format(''.join(hint), tokval))
ccwires.append(tokval) # Track this wire as assigned at this condition level
if tokval in ctls_wide:
tr = linesub.translate(str.maketrans(dict.fromkeys('~','n'))) # Make temporary name
tmpname = "{0}_{1}_{2}".format(tokval, tr.translate(str.maketrans(dict.fromkeys('[]()&',None))), len(ccwires))
t.write("reg {0};\n".format(tmpname))
line = "{0} = {1};\n".format(tmpname, linesub) + line
line += "({{{0},{0}}}){1}".format(tmpname, rhs)
else:
line += linesub + rhs
line = line.replace(')(', ')&(')
line = line.replace('&&', '&')
line = line.replace('(1)&', '')
line = line.replace('&(1)', '')
i += len(rval[0])
f.write ('{0};\n'.format(line))
i += 1
 
#--------------------------------------------------------------------------------
tokens = []
# Input file which we are processing
with open(fname) as f:
lines = f.readlines()
 
for line in lines:
src = decomment(line)
src = bytes(src.encode())
src = io.BytesIO(src)
toklist = list(tokenize.tokenize(src.readline))
tokens.extend(toklist)
 
with open(oname, 'w') as f:
with open(tname, 'w') as t:
f.write("// Automatically generated by gencompile.py\n\n")
t.write("// Automatically generated by gencompile.py\n\n")
sequential_or(f, t, tokens)
 
# Touch a file that includes 'exec_matrix_compiled.vh' to ensure it will recompile correctly
os.utime("execute.v", None)
/test_decode.sv
132,7 → 132,6
.M3(M3_sig) , // input M3_sig
.M4(M4_sig) , // input M4_sig
.M5(M5_sig) , // input M5_sig
.M6(M6_sig) , // input M6_sig
.T1(T1_sig) , // input T1_sig
.T2(T2_sig) , // input T2_sig
.T3(T3_sig) , // input T3_sig
/resets.v
14,7 → 14,7
 
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sun Nov 09 09:13:38 2014"
// CREATED "Sat Feb 27 08:32:59 2016"
 
module resets(
reset_in,
32,9 → 32,10
input wire M1;
input wire T2;
input wire fpga_reset;
output reg clrpc;
output wire clrpc;
output wire nreset;
 
reg clrpc_int;
wire nclk;
reg x1;
wire x2;
41,9 → 42,12
wire x3;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_9;
reg SYNTHESIZED_WIRE_9;
reg DFF_res3;
reg SYNTHESIZED_WIRE_10;
wire SYNTHESIZED_WIRE_11;
wire SYNTHESIZED_WIRE_3;
reg DFF_res;
reg SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_6;
 
assign nreset = SYNTHESIZED_WIRE_6;
63,17 → 67,19
end
end
 
assign clrpc = clrpc_int | SYNTHESIZED_WIRE_9 | DFF_res3 | SYNTHESIZED_WIRE_10;
 
assign SYNTHESIZED_WIRE_1 = ~reset_in;
 
assign x2 = x1 & SYNTHESIZED_WIRE_9;
assign x2 = x1 & SYNTHESIZED_WIRE_11;
 
assign SYNTHESIZED_WIRE_9 = M1 & T2;
assign SYNTHESIZED_WIRE_11 = M1 & T2;
 
assign x3 = x1 & SYNTHESIZED_WIRE_3;
 
assign SYNTHESIZED_WIRE_6 = ~DFF_res;
assign SYNTHESIZED_WIRE_6 = ~SYNTHESIZED_WIRE_12;
 
assign SYNTHESIZED_WIRE_3 = ~SYNTHESIZED_WIRE_9;
assign SYNTHESIZED_WIRE_3 = ~SYNTHESIZED_WIRE_11;
 
assign nclk = ~clk;
 
84,24 → 90,48
begin
if (!SYNTHESIZED_WIRE_8)
begin
DFF_res <= 1;
SYNTHESIZED_WIRE_12 <= 1;
end
else
begin
DFF_res <= x3;
SYNTHESIZED_WIRE_12 <= x3;
end
end
 
 
always@(posedge nclk)
begin
begin
SYNTHESIZED_WIRE_10 <= SYNTHESIZED_WIRE_12;
end
end
 
 
always@(posedge nclk)
begin
begin
SYNTHESIZED_WIRE_9 <= SYNTHESIZED_WIRE_10;
end
end
 
 
always@(posedge nclk)
begin
begin
DFF_res3 <= SYNTHESIZED_WIRE_9;
end
end
 
 
always@(posedge nclk or negedge SYNTHESIZED_WIRE_6)
begin
if (!SYNTHESIZED_WIRE_6)
begin
clrpc <= 0;
clrpc_int <= 0;
end
else
begin
clrpc <= ~clrpc & x2 | clrpc & ~SYNTHESIZED_WIRE_9;
clrpc_int <= ~clrpc_int & x2 | clrpc_int & ~SYNTHESIZED_WIRE_11;
end
end
 
/execute.bsf
18,957 → 18,936
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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/ir.v
14,11 → 14,12
 
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Fri Oct 31 20:07:47 2014"
// CREATED "Fri Feb 26 22:23:08 2016"
 
module ir(
ctl_ir_we,
clk,
nreset,
db,
opcode
);
26,6 → 27,7
 
input wire ctl_ir_we;
input wire clk;
input wire nreset;
input wire [7:0] db;
output reg [7:0] opcode;
 
34,8 → 36,13
 
 
 
always@(posedge clk)
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
opcode[7:0] <= 8'b00000000;
end
else
if (ctl_ir_we)
begin
opcode[7:0] <= db[7:0];
/clk_delay.bdf
580,63 → 580,6
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783,6 → 726,56
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/pla_decode.v
0,0 → 1,121
//=====================================================================================
// This file is automatically generated by the z80_pla_checker tool. Do not edit!
//=====================================================================================
module pla_decode
(
input wire [6:0] prefix,
input wire [7:0] opcode,
output wire [104:0] pla
);
 
assign pla[ 0] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110100) == 15'b0000001_10100000) ? 1'b1 : 1'b0; // ldx/cpx/inx/outx brk
assign pla[ 1] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11011001) ? 1'b1 : 1'b0; // exx
assign pla[ 2] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11101011) ? 1'b1 : 1'b0; // ex de,hl
assign pla[ 3] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11011111) == 15'b0000100_11011101) ? 1'b1 : 1'b0; // IX/IY prefix
assign pla[ 5] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11111001) ? 1'b1 : 1'b0; // ld sp,hl
assign pla[ 6] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11101001) ? 1'b1 : 1'b0; // jp hl
assign pla[ 7] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_00000001) ? 1'b1 : 1'b0; // ld rr,nn
assign pla[ 8] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11100111) == 15'b0000100_00000010) ? 1'b1 : 1'b0; // ld (rr),a/a,(rr)
assign pla[ 9] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_00000011) ? 1'b1 : 1'b0; // inc/dec rr
assign pla[ 10] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11100011) ? 1'b1 : 1'b0; // ex (sp),hl
assign pla[ 11] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100001) ? 1'b1 : 1'b0; // cpi/cpir/cpd/cpdr
assign pla[ 12] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100000) ? 1'b1 : 1'b0; // ldi/ldir/ldd/lddr
assign pla[ 13] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_00000010) ? 1'b1 : 1'b0; // ld direction
assign pla[ 15] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110111) == 15'b0000001_01100111) ? 1'b1 : 1'b0; // rrd/rld
assign pla[ 16] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_11000101) ? 1'b1 : 1'b0; // push rr
assign pla[ 17] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_00000110) ? 1'b1 : 1'b0; // ld r,n
assign pla[ 20] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100011) ? 1'b1 : 1'b0; // outx/otxr
assign pla[ 21] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100010) ? 1'b1 : 1'b0; // inx/inxr
assign pla[ 23] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001011) == 15'b0000100_11000001) ? 1'b1 : 1'b0; // push/pop
assign pla[ 24] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11001101) ? 1'b1 : 1'b0; // call nn
assign pla[ 25] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11100111) == 15'b0000100_00000111) ? 1'b1 : 1'b0; // rlca/rla/rrca/rra
assign pla[ 26] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00010000) ? 1'b1 : 1'b0; // djnz e
assign pla[ 27] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000110) == 15'b0000001_01000000) ? 1'b1 : 1'b0; // in/out r,(c)
assign pla[ 28] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11010011) ? 1'b1 : 1'b0; // out (n),a
assign pla[ 29] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11000011) ? 1'b1 : 1'b0; // jp nn
assign pla[ 30] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_00100010) ? 1'b1 : 1'b0; // ld hl,(nn)/(nn),hl
assign pla[ 31] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000011) ? 1'b1 : 1'b0; // ld rr,(nn)/(nn),rr
assign pla[ 33] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11001111) == 15'b0000001_01000011) ? 1'b1 : 1'b0; // ld direction
assign pla[ 34] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000001) ? 1'b1 : 1'b0; // out (c),r
assign pla[ 35] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11001001) ? 1'b1 : 1'b0; // ret
assign pla[ 37] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_11010011) ? 1'b1 : 1'b0; // out (n),a/a,(n)
assign pla[ 38] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_00110010) ? 1'b1 : 1'b0; // ld (nn),a/a,(nn)
assign pla[ 39] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00001000) ? 1'b1 : 1'b0; // ex af,af'
assign pla[ 40] = (({prefix[6:0], opcode[7:0]} & 15'b0100100_11111111) == 15'b0100100_00110110) ? 1'b1 : 1'b0; // ld (ix+d),n
assign pla[ 42] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000100) ? 1'b1 : 1'b0; // call cc,nn
assign pla[ 43] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000010) ? 1'b1 : 1'b0; // jp cc,nn
assign pla[ 44] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11001011) ? 1'b1 : 1'b0; // CB prefix
assign pla[ 45] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000000) ? 1'b1 : 1'b0; // ret cc
assign pla[ 46] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000101) ? 1'b1 : 1'b0; // reti/retn
assign pla[ 47] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00011000) ? 1'b1 : 1'b0; // jr e
assign pla[ 48] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11100111) == 15'b0000100_00100000) ? 1'b1 : 1'b0; // jr ss,e
assign pla[ 49] = (({prefix[6:0], opcode[7:0]} & 15'b0100000_11111111) == 15'b0100000_11001011) ? 1'b1 : 1'b0; // CB prefix with IX/IY
assign pla[ 50] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00110110) ? 1'b1 : 1'b0; // ld (hl),n
assign pla[ 51] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11101101) ? 1'b1 : 1'b0; // ED prefix
assign pla[ 52] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_10000110) ? 1'b1 : 1'b0; // add/sub/and/or/xor/cp (hl)
assign pla[ 53] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111110) == 15'b0000100_00110100) ? 1'b1 : 1'b0; // inc/dec (hl)
assign pla[ 55] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_00000111) == 15'b0000010_00000110) ? 1'b1 : 1'b0; // Every CB op (hl)
assign pla[ 56] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000111) ? 1'b1 : 1'b0; // rst p
assign pla[ 57] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110111) == 15'b0000001_01000111) ? 1'b1 : 1'b0; // ld i,a/r,a
assign pla[ 58] = (({prefix[6:0], opcode[7:0]} & 15'b0010100_11000111) == 15'b0010100_01000110) ? 1'b1 : 1'b0; // ld r,(hl)
assign pla[ 59] = (({prefix[6:0], opcode[7:0]} & 15'b0010100_11111000) == 15'b0010100_01110000) ? 1'b1 : 1'b0; // ld (hl),r
assign pla[ 61] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000000) == 15'b0000100_01000000) ? 1'b1 : 1'b0; // ld r,r'
assign pla[ 64] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000110) ? 1'b1 : 1'b0; // add/sub/and/or/xor/cmp a,imm
assign pla[ 65] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000000) == 15'b0000100_10000000) ? 1'b1 : 1'b0; // add/sub/and/or/xor/cmp a,r
assign pla[ 66] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000110) == 15'b0000100_00000100) ? 1'b1 : 1'b0; // inc/dec r
assign pla[ 68] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000010) ? 1'b1 : 1'b0; // adc/sbc hl,rr
assign pla[ 69] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_00001001) ? 1'b1 : 1'b0; // add hl,rr
assign pla[ 70] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_00000000) ? 1'b1 : 1'b0; // rlc r
assign pla[ 72] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_01000000) ? 1'b1 : 1'b0; // bit b,r
assign pla[ 73] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_10000000) ? 1'b1 : 1'b0; // res b,r
assign pla[ 74] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_11000000) ? 1'b1 : 1'b0; // set b,r
assign pla[ 75] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_00000101) ? 1'b1 : 1'b0; // dec r
assign pla[ 76] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00111000) ? 1'b1 : 1'b0; // 111 (CP)
assign pla[ 77] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00100111) ? 1'b1 : 1'b0; // daa
assign pla[ 78] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00010000) ? 1'b1 : 1'b0; // 010 (SUB)
assign pla[ 79] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00011000) ? 1'b1 : 1'b0; // 011 (SBC)
assign pla[ 80] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00001000) ? 1'b1 : 1'b0; // 001 (ADC)
assign pla[ 81] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00101111) ? 1'b1 : 1'b0; // cpl
assign pla[ 82] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000100) ? 1'b1 : 1'b0; // neg
assign pla[ 83] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110111) == 15'b0000001_01010111) ? 1'b1 : 1'b0; // ld a,i/a,r
assign pla[ 84] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00000000) ? 1'b1 : 1'b0; // 000 (ADD)
assign pla[ 85] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00100000) ? 1'b1 : 1'b0; // 100 (AND)
assign pla[ 86] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00110000) ? 1'b1 : 1'b0; // 110 (OR)
assign pla[ 88] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00101000) ? 1'b1 : 1'b0; // 101 (XOR)
assign pla[ 89] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00111111) ? 1'b1 : 1'b0; // ccf
assign pla[ 91] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100110) == 15'b0000001_10100010) ? 1'b1 : 1'b0; // inx/outx/inxr/otxr
assign pla[ 92] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00110111) ? 1'b1 : 1'b0; // scf
assign pla[ 95] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_01110110) ? 1'b1 : 1'b0; // halt
assign pla[ 96] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000110) ? 1'b1 : 1'b0; // im n
assign pla[ 97] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_11110011) ? 1'b1 : 1'b0; // di/ei
assign pla[ 99] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00000001) == 15'b0000000_00000001) ? 1'b1 : 1'b0; // opcode[0]
assign pla[100] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00000010) == 15'b0000000_00000010) ? 1'b1 : 1'b0; // opcode[1]
assign pla[101] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00000100) == 15'b0000000_00000100) ? 1'b1 : 1'b0; // opcode[2]
assign pla[102] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00001000) == 15'b0000000_00001000) ? 1'b1 : 1'b0; // opcode[3]
assign pla[103] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00010000) == 15'b0000000_00010000) ? 1'b1 : 1'b0; // opcode[4]
assign pla[104] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00100000) == 15'b0000000_00100000) ? 1'b1 : 1'b0; // opcode[5]
 
// Entries not used by our timing matrix
assign pla[ 67] = 1'b0; // in
assign pla[ 62] = 1'b0; // For all CB opcodes
assign pla[ 54] = 1'b0; // Every CB with IX/IY
assign pla[ 22] = 1'b0; // CB prefix w/o IX/IY
assign pla[ 14] = 1'b0; // dec rr
assign pla[ 4] = 1'b0; // ld x,a/a,x
 
// Duplicate entries
assign pla[ 18] = 1'b0; // ldi/ldir/ldd/lddr
assign pla[ 19] = 1'b0; // cpi/cpir/cpd/cpdr
assign pla[ 32] = 1'b0; // ld i,a/a,i/r,a/a,r
assign pla[ 36] = 1'b0; // ld(rr),a/a,(rr)
assign pla[ 41] = 1'b0; // IX/IY
assign pla[ 60] = 1'b0; // rrd/rld
assign pla[ 63] = 1'b0; // ld r,*
assign pla[ 71] = 1'b0; // rlca/rla/rrca/rra
assign pla[ 87] = 1'b0; // ld a,i / ld a,r
assign pla[ 90] = 1'b0; // djnz *
assign pla[ 93] = 1'b0; // cpi/cpir/cpd/cpdr
assign pla[ 94] = 1'b0; // ldi/ldir/ldd/lddr
assign pla[ 98] = 1'b0; // out (*),a/in a,(*)
 
endmodule
/simulation/modelsim/test_control.mpf
2,9 → 2,9
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
;
 
[Library]
std = $MODEL_TECH/../std
129,7 → 129,7
 
work = work
[vcom]
; VHDL93 variable selects language version as the default.
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
272,7 → 272,7
BreakOnAssertion = 4
 
; Assertion Message Format
; %S - Severity Level
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
424,10 → 424,10
; description of a message.
 
; Control transcripting of elaboration/runtime messages.
; The default is to have messages appear in the transcript and
; The default is to have messages appear in the transcript and
; recorded in the wlf file (messages that are recorded in the
; wlf file can be viewed in the MsgViewer). The other settings
; are to send messages only to the transcript or only to the
; are to send messages only to the transcript or only to the
; wlf file. The valid values are
; both {default}
; tran {transcript only}
483,42 → 483,42
ForceSoftPaths = 1
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
VERILOG_CustomDoubleClick =
SYSTEMVERILOG_DoubleClick = Edit
SYSTEMVERILOG_CustomDoubleClick =
SYSTEMVERILOG_CustomDoubleClick =
VHDL_DoubleClick = Edit
VHDL_CustomDoubleClick =
VHDL_CustomDoubleClick =
PSL_DoubleClick = Edit
PSL_CustomDoubleClick =
PSL_CustomDoubleClick =
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick =
TEXT_CustomDoubleClick =
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick =
SYSTEMC_CustomDoubleClick =
TCL_DoubleClick = Edit
TCL_CustomDoubleClick =
TCL_CustomDoubleClick =
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick =
MACRO_CustomDoubleClick =
VCD_DoubleClick = Edit
VCD_CustomDoubleClick =
VCD_CustomDoubleClick =
SDF_DoubleClick = Edit
SDF_CustomDoubleClick =
SDF_CustomDoubleClick =
XML_DoubleClick = Edit
XML_CustomDoubleClick =
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
UCDB_CustomDoubleClick =
UPF_DoubleClick = Edit
UPF_CustomDoubleClick =
UPF_CustomDoubleClick =
PCF_DoubleClick = Edit
PCF_CustomDoubleClick =
PCF_CustomDoubleClick =
PROJECT_DoubleClick = Edit
PROJECT_CustomDoubleClick =
PROJECT_CustomDoubleClick =
VRM_DoubleClick = Edit
VRM_CustomDoubleClick =
VRM_CustomDoubleClick =
DEBUGDATABASE_DoubleClick = Edit
DEBUGDATABASE_CustomDoubleClick =
DEBUGDATABASE_CustomDoubleClick =
DEBUGARCHIVE_DoubleClick = Edit
DEBUGARCHIVE_CustomDoubleClick =
DEBUGARCHIVE_CustomDoubleClick =
Project_Major_Version = 10
Project_Minor_Version = 1
/simulation/modelsim/wave_sequencer.do
13,7 → 13,6
add wave -noupdate -color Aquamarine /test_sequencer/M3_sig
add wave -noupdate -color Aquamarine /test_sequencer/M4_sig
add wave -noupdate -color Aquamarine /test_sequencer/M5_sig
add wave -noupdate -color Aquamarine /test_sequencer/M6_sig
add wave -noupdate -divider T-STATE
add wave -noupdate -color Pink /test_sequencer/T1_sig
add wave -noupdate -color Pink /test_sequencer/T2_sig
/exec_matrix.vh
1,288 → 1,286
// Automatically generated by genmatrix.py
 
// 8-bit Load Group
if (pla[17] && !pla[50]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */
if (pla[17] & ~pla[50]) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; setM1=1; end
if (M2 & T3) begin fMRead=1; setM1=1; end
end
 
if (pla[61] && !pla[58] && !pla[59]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */
if (pla[61] & ~pla[58] & ~pla[59]) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2u=1;
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_op1_oe=1; /* OP1 latch */ end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
if (M1 & T4) begin validPLA=1; setM1=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */ end
end
 
if (use_ixiy && pla[58]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */
if (use_ixiy & pla[58]) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; end
if (M3 && T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
if (M2 & T3) begin fMRead=1; nextM=1; end
if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
end
 
if (~use_ixiy && pla[58]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */
if (~use_ixiy & pla[58]) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1; end
if (M2 && T3) begin fMRead=1; nextM=1; setM1=1; end
if (M4 && T1) begin fMRead=1;
if (M2 & T2) begin fMRead=1; end
if (M2 & T3) begin fMRead=1; setM1=1; end
if (M4 & T1) begin fMRead=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T2) begin fMRead=1; end
if (M4 && T3) begin fMRead=1; nextM=1; setM1=1; end
if (M4 & T2) begin fMRead=1; end
if (M4 & T3) begin fMRead=1; setM1=1; end
end
 
if (use_ixiy && pla[59]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (use_ixiy & pla[59]) begin
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; end
if (M3 && T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T5) begin nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end
if (M2 & T3) begin fMRead=1; nextM=1; end
if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T5) begin nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end
end
 
if (~use_ixiy && pla[59]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mWrite=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
if (~use_ixiy & pla[59]) begin
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mWrite=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M2 && T1) begin fMWrite=1;
if (M2 & T1) begin fMWrite=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMWrite=1; end
if (M2 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M4 && T1) begin fMWrite=1;
if (M2 & T2) begin fMWrite=1; end
if (M2 & T3) begin fMWrite=1; setM1=1; end
if (M4 & T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M4 && T2) begin fMWrite=1; end
if (M4 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M4 & T2) begin fMWrite=1; end
if (M4 & T3) begin fMWrite=1; setM1=1; end
end
 
if (pla[40]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; end
if (M3 && T1) begin fMRead=1;
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1; end
if (M3 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M3 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T3) begin fMRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T5) begin nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T3) begin fMRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T5) begin nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end
end
 
if (pla[50] && !pla[40]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (pla[50] & ~pla[40]) begin
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; end
if (M3 && T1) begin fMWrite=1;
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1; end
if (M3 & T1) begin fMWrite=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMWrite=1; end
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M4 && T1) begin fMWrite=1;
if (M3 & T2) begin fMWrite=1; end
if (M3 & T3) begin fMWrite=1; setM1=1; end
if (M4 & T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T2) begin fMWrite=1; end
if (M4 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M4 & T2) begin fMWrite=1; end
if (M4 & T3) begin fMWrite=1; setM1=1; end
end
 
if (pla[8] && pla[13]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mWrite=1;
if (pla[8] & pla[13]) begin
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mWrite=1;
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M2 && T1) begin fMWrite=1;
if (M2 & T1) begin fMWrite=1;
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMWrite=1;
if (M2 & T2) begin fMWrite=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M2 & T3) begin fMWrite=1; setM1=1; end
end
 
if (pla[8] && !pla[13]) begin
if (M1 && T1) begin
if (pla[8] & ~pla[13]) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; setM1=1; end
if (M2 & T3) begin fMRead=1; setM1=1; end
end
 
if (pla[38] && pla[13]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (pla[38] & pla[13]) begin
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
if (M3 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M3 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
if (M3 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M4 && T1) begin fMWrite=1;
if (M4 & T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M4 && T2) begin fMWrite=1;
if (M4 & T2) begin fMWrite=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M4 & T3) begin fMWrite=1; setM1=1; end
end
 
if (pla[38] && !pla[13]) begin
if (M1 && T1) begin
if (pla[38] & ~pla[13]) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
if (M3 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M3 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
if (M3 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M4 && T1) begin fMRead=1;
if (M4 & T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T2) begin fMRead=1;
if (M4 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin fMRead=1; nextM=1; setM1=1; end
if (M4 & T3) begin fMRead=1; setM1=1; end
end
 
if (pla[83]) begin
if (M1 && T1) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
295,15 → 293,15
ctl_flags_hf_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_IFF2;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
312,12 → 310,11
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1;
ctl_reg_sel_ir=1; ctl_reg_sys_hilo={!op3,op3}; ctl_sw_4u=1; /* Read either I or R based on op3 (0 or 1) */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
if (M1 & T4) begin validPLA=1;
ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4u=1; /* Read either I or R based on op3 (0 or 1) */
ctl_reg_out_hi=~rsel3; ctl_reg_out_lo=rsel3; ctl_sw_2u=~rsel3; ctl_sw_2d=rsel3; /* Enable register gate based on the rsel3 */ /* Controlled by register gate */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
326,15 → 323,15
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T5) begin nextM=1; setM1=1; end
if (M1 & T5) begin setM1=1; end
end
 
if (pla[57]) begin
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
343,18 → 340,18
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1;
ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo={!op3,op3}; ctl_sw_4d=1; /* Write either I or R based on op3 (0 or 1) */
if (M1 & T4) begin validPLA=1;
ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4d=1; /* Write either I or R based on op3 (0 or 1) */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2u=1;
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_op1_oe=1; /* OP1 latch */ end
if (M1 && T5) begin nextM=1; setM1=1; end
if (M1 & T5) begin setM1=1; end
end
 
// 16-bit Load Group
if (pla[7]) begin
if (M1 && T1) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
361,16 → 358,16
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; end
if (M3 && T1) begin fMRead=1;
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1; end
if (M3 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
379,120 → 376,119
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M3 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1; end
if (M3 & T3) begin fMRead=1; setM1=1; end
end
 
if (pla[30] && pla[13]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (pla[30] & pla[13]) begin
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
if (M3 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M3 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
if (M3 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M4 && T1) begin fMWrite=1;
if (M4 & T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M4 && T2) begin fMWrite=1;
if (M4 & T2) begin fMWrite=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M5 && T1) begin fMWrite=1;
if (M5 & T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M5 && T2) begin fMWrite=1;
if (M5 & T2) begin fMWrite=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M5 & T3) begin fMWrite=1; setM1=1; end
end
 
if (pla[30] && !pla[13]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (pla[30] & ~pla[13]) begin
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
if (M3 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M3 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
if (M3 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M4 && T1) begin fMRead=1;
if (M4 & T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T2) begin fMRead=1;
if (M4 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
if (M4 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M5 && T1) begin fMRead=1;
if (M5 & T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M5 && T2) begin fMRead=1;
if (M5 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M5 && T3) begin fMRead=1; nextM=1; setM1=1;
if (M5 & T3) begin fMRead=1; setM1=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
500,102 → 496,101
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
end
 
if (pla[31] && pla[33]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (pla[31] & pla[33]) begin
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
if (M3 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M3 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
if (M3 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M4 && T1) begin fMWrite=1;
if (M4 & T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M4 && T2) begin fMWrite=1;
if (M4 & T2) begin fMWrite=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M5 && T1) begin fMWrite=1;
if (M5 & T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M5 && T2) begin fMWrite=1;
if (M5 & T2) begin fMWrite=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M5 & T3) begin fMWrite=1; setM1=1; end
end
 
if (pla[31] && !pla[33]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (pla[31] & ~pla[33]) begin
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
if (M3 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M3 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
if (M3 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M4 && T1) begin fMRead=1;
if (M4 & T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T2) begin fMRead=1;
if (M4 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
if (M4 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
602,14 → 597,14
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M5 && T1) begin fMRead=1;
if (M5 & T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M5 && T2) begin fMRead=1;
if (M5 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M5 && T3) begin fMRead=1; nextM=1; setM1=1;
if (M5 & T3) begin fMRead=1; setM1=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
619,75 → 614,74
end
 
if (pla[5]) begin
if (M1 && T4) begin validPLA=1;
if (M1 & T4) begin validPLA=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M1 && T5) begin
if (M1 & T5) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M1 && T6) begin nextM=1; setM1=1; end
if (M1 & T6) begin setM1=1; end
end
 
if (pla[23] && pla[16]) begin
if (M1 && T4) begin validPLA=1; end
if (M1 && T5) begin nextM=1; ctl_mWrite=1;
if (pla[23] & pla[16]) begin
if (M1 & T4) begin validPLA=1; end
if (M1 & T5) begin nextM=1; ctl_mWrite=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T1) begin fMWrite=1;
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
if (M2 & T1) begin fMWrite=1;
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_apin_mux=1; /* Apin sourced from incrementer */
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M2 && T2) begin fMWrite=1;
if (M2 & T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
if (M2 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T1) begin fMWrite=1;
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
if (M3 & T1) begin fMWrite=1;
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_apin_mux=1; /* Apin sourced from incrementer */
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M3 && T2) begin fMWrite=1;
if (M3 & T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M3 & T3) begin fMWrite=1; setM1=1; end
end
 
if (pla[23] && !pla[16]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (pla[23] & ~pla[16]) begin
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
if (M2 & T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
if (M3 & T1) begin fMRead=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
if (M3 & T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1;
if (M3 & T3) begin fMRead=1; setM1=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
697,98 → 691,97
 
// Exchange, Block Transfer and Search Groups
if (pla[2]) begin
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_ex_de_hl=1; /* EX DE,HL */ end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; end
if (M1 & T4) begin validPLA=1; setM1=1; end
end
 
if (pla[39]) begin
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_ex_af=1; /* EX AF,AF' */ end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; end
if (M1 & T4) begin validPLA=1; setM1=1; end
end
 
if (pla[1]) begin
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_exx=1; /* EXX */ end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; end
if (M1 & T4) begin validPLA=1; setM1=1; end
end
 
if (pla[10]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
if (M2 & T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
if (M3 & T1) begin fMRead=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
if (M3 & T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1;
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
if (M3 & T3) begin fMRead=1;
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T4) begin nextM=1; ctl_mWrite=1;
if (M3 & T4) begin nextM=1; ctl_mWrite=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T1) begin fMWrite=1;
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
if (M4 & T1) begin fMWrite=1;
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_apin_mux=1; /* Apin sourced from incrementer */
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M4 && T2) begin fMWrite=1;
if (M4 & T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M5 && T1) begin fMWrite=1;
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
if (M5 & T1) begin fMWrite=1;
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_apin_mux=1; /* Apin sourced from incrementer */
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M5 && T2) begin fMWrite=1;
if (M5 & T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M5 && T3) begin fMWrite=1;
if (M5 & T3) begin fMWrite=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M5 && T4) begin
if (M5 & T4) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M5 && T5) begin nextM=1; setM1=1; end
if (M5 & T5) begin setM1=1; end
end
 
if (pla[0]) begin
begin nonRep=1; /* Non-repeating block instruction */ end
begin nonRep=1; /* Non-repeating block instruction */ end
end
 
if (pla[12]) begin
if (M1 && T1) begin
if (M1 & T1) begin
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
798,15 → 791,15
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_use_cf2=1; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
815,32 → 808,26
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
if (M2 & T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1;
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end
if (M3 && T1) begin fMWrite=1;
ctl_flags_cf2_we=1; end
if (M3 & T1) begin fMWrite=1;
ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit DE, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
847,72 → 834,60
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_use_cf2=1; end
if (M3 && T2) begin fMWrite=1;
if (M3 & T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMWrite=1;
if (M3 & T3) begin fMWrite=1;
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T4) begin
if (M3 & T4) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_repeat_we=1; /* Update repeating flag latch with BC=1 status */ end
if (M3 && T5) begin nextM=1; setM1=nonRep | !repeat_en; end
if (M4 && T1) begin
if (M3 & T5) begin nextM=1; setM1=nonRep | ~repeat_en; end
if (M4 & T1) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T2) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
if (M4 & T2) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin
if (M4 & T3) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T4) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
if (M4 & T4) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T5) begin nextM=1; setM1=1; end
if (M4 & T5) begin setM1=1; end
end
 
if (pla[11]) begin
if (M1 && T1) begin
if (M1 & T1) begin
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_op1_sel_zero=1; /* Zero */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP;
ctl_flags_nf_we=1; ctl_flags_nf_set=1;
ctl_flags_use_cf2=1; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_hf_cpl=flags_nf; end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
921,74 → 896,62
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
if (M2 & T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1;
if (M2 & T3) begin fMRead=1; nextM=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1;
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end
if (M3 && T1) begin
ctl_flags_cf2_we=1; end
if (M3 & T1) begin
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_sz_we=1;
ctl_flags_use_cf2=1; end
if (M3 && T3) begin
if (M3 & T3) begin
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T4) begin
if (M3 & T4) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_repeat_we=1; /* Update repeating flag latch with BC=1 status */ end
if (M3 && T5) begin nextM=1; setM1=nonRep | !repeat_en | flags_zf; end
if (M4 && T1) begin
if (M3 & T5) begin nextM=1; setM1=nonRep | ~repeat_en | flags_zf; end
if (M4 & T1) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T2) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
if (M4 & T2) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin
if (M4 & T3) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T4) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
if (M4 & T4) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T5) begin nextM=1; setM1=1; end
if (M4 & T5) begin setM1=1; end
end
 
// 8-bit Arithmetic and Logic Group
if (pla[65] && !pla[52]) begin
if (M1 && T1) begin /* Which register to be written is decided elsewhere */
if (pla[65] & ~pla[52]) begin
if (M1 & T1) begin /* Which register to be written is decided elsewhere */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
998,17 → 961,17
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
ctl_flags_sz_we=1;
ctl_flags_cf_we=1; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
1017,12 → 980,11
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
if (M1 & T4) begin validPLA=1; setM1=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1032,7 → 994,7
end
 
if (pla[64]) begin
if (M1 && T1) begin /* Which register to be written is decided elsewhere */
if (M1 & T1) begin /* Which register to be written is decided elsewhere */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
1042,17 → 1004,17
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
ctl_flags_sz_we=1;
ctl_flags_cf_we=1; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
1061,12 → 1023,11
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1073,20 → 1034,20
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1; end
if (M2 && T1) begin fMRead=1;
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; setM1=1;
if (M2 & T3) begin fMRead=1; setM1=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1095,12 → 1056,12
ctl_flags_hf_we=1; end
end
 
if (use_ixiy && pla[52]) begin
if (M1 && T3) begin
if (use_ixiy & pla[52]) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
1109,24 → 1070,24
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; end
if (M3 && T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
if (M2 & T3) begin fMRead=1; nextM=1; end
if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
end
 
if (!use_ixiy && pla[52]) begin
if (M1 && T1) begin /* Which register to be written is decided elsewhere */
if (~use_ixiy & pla[52]) begin
if (M1 & T1) begin /* Which register to be written is decided elsewhere */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
1136,17 → 1097,17
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
ctl_flags_sz_we=1;
ctl_flags_cf_we=1; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
1155,20 → 1116,20
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; setM1=1;
if (M2 & T3) begin fMRead=1; setM1=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1175,13 → 1136,13
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1; end
if (M4 && T1) begin fMRead=1;
if (M4 & T1) begin fMRead=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T2) begin fMRead=1;
if (M4 & T2) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
1189,12 → 1150,12
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M4 && T3) begin fMRead=1; nextM=1; setM1=1;
if (M4 & T3) begin fMRead=1; setM1=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1203,9 → 1164,9
ctl_flags_hf_we=1; end
end
 
if (pla[66] && !pla[53]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */
if (pla[66] & ~pla[53]) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
1212,25 → 1173,21
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
ctl_flags_use_cf2=1; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_hf_cpl=flags_nf; end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
1239,53 → 1196,48
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
if (op4 & op5 & !op3) ctl_bus_zero_oe=1; /* Trying to read flags? Put 0 on the bus instead. */
else begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; end /* Read 8-bit GP register */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
if (M1 & T4) begin validPLA=1; setM1=1;
if (op4 & op5 & ~op3) begin ctl_bus_zero_oe=1; end /* Trying to read flags? Put 0 on the bus instead. */
if (~(op4 & op5 & ~op3)) begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; end /* Read 8-bit GP register */
ctl_reg_out_hi=~rsel3; ctl_reg_out_lo=rsel3; ctl_sw_2u=~rsel3; ctl_sw_2d=rsel3; /* Enable register gate based on the rsel3 */ /* Controlled by register gate */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_zero=1; /* Zero */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf_set=1; /* Set CF going into the ALU core */
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end
ctl_flags_cf2_we=1; end
end
 
if (pla[75]) begin
if (M1 && T1) begin
if (M1 & T1) begin
ctl_flags_nf_we=1; ctl_flags_nf_set=1;
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */
ctl_alu_sel_op2_neg=1; end
if (M1 && T4) begin
if (M1 & T4) begin
ctl_flags_nf_we=1; ctl_flags_nf_set=1;
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */
ctl_alu_sel_op2_neg=1; end
end
 
if ((M2 || M4) && pla[75]) begin
begin
if ((M2 | M4) & pla[75]) begin
begin
ctl_flags_nf_we=1; ctl_flags_nf_set=1;
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */
ctl_alu_sel_op2_neg=1; end
end
 
if (use_ixiy && pla[53]) begin
if (M1 && T3) begin
if (use_ixiy & pla[53]) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
1294,33 → 1246,33
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; end
if (M3 && T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
if (M2 & T3) begin fMRead=1; nextM=1; end
if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
end
 
if (!use_ixiy && pla[53]) begin
if (M1 && T2) begin
if (~use_ixiy & pla[53]) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_hf_cpl=flags_nf; end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
1329,30 → 1281,26
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1; end
if (M2 && T3) begin fMRead=1;
if (M2 & T2) begin fMRead=1; end
if (M2 & T3) begin fMRead=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_zero=1; /* Zero */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf_set=1; /* Set CF going into the ALU core */
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end
if (M2 && T4) begin nextM=1; ctl_mWrite=1;
ctl_flags_cf2_we=1; end
if (M2 & T4) begin nextM=1; ctl_mWrite=1;
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
1360,41 → 1308,33
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
ctl_flags_use_cf2=1; end
if (M3 && T1) begin fMWrite=1;
if (M3 & T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T2) begin fMWrite=1; end
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M4 && T1) begin fMRead=1;
if (M3 & T2) begin fMWrite=1; end
if (M3 & T3) begin fMWrite=1; setM1=1; end
if (M4 & T1) begin fMRead=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T2) begin fMRead=1; end
if (M4 && T3) begin fMRead=1;
if (M4 & T2) begin fMRead=1; end
if (M4 & T3) begin fMRead=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_zero=1; /* Zero */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf_set=1; /* Set CF going into the ALU core */
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end
if (M4 && T4) begin nextM=1; ctl_mWrite=1;
ctl_flags_cf2_we=1; end
if (M4 & T4) begin nextM=1; ctl_mWrite=1;
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
1402,32 → 1342,28
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
ctl_flags_use_cf2=1; end
if (M5 && T1) begin fMWrite=1;
if (M5 & T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M5 && T2) begin fMWrite=1; end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M5 & T2) begin fMWrite=1; end
if (M5 & T3) begin fMWrite=1; setM1=1; end
end
 
// 16-bit Arithmetic Group
if (pla[69]) begin
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
1436,31 → 1372,25
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1;
if (M1 & T4) begin validPLA=1; nextM=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */ end
if (M2 && T1) begin
if (M2 & T1) begin
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1;
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M2 && T2) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M2 & T2) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
1467,38 → 1397,28
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_xy_we=1;
ctl_flags_cf_we=1; end
if (M2 && T3) begin
if (M2 & T3) begin
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */ end
if (M2 && T4) begin nextM=1;
if (M2 & T4) begin nextM=1;
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1;
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M3 && T1) begin
if (M3 & T1) begin
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
1505,29 → 1425,25
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_xy_we=1;
ctl_flags_cf_we=1; end
if (M3 && T2) begin
if (M3 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin nextM=1; setM1=1; end
if (M3 & T3) begin setM1=1; end
end
 
if (op3 && pla[68]) begin
if (M1 && T2) begin
if (op3 & pla[68]) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
1536,29 → 1452,25
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1;
if (M1 & T4) begin validPLA=1; nextM=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */ end
if (M2 && T1) begin
if (M2 & T1) begin
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1;
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M2 && T2) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M2 & T2) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
1565,39 → 1477,29
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_cf_we=1; end
if (M2 && T3) begin
if (M2 & T3) begin
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */ end
if (M2 && T4) begin nextM=1;
if (M2 & T4) begin nextM=1;
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1;
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M3 && T1) begin
if (M3 & T1) begin
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
1604,33 → 1506,29
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
ctl_flags_cf_we=1;
ctl_alu_zero_16bit=1; /* 16-bit arithmetic operation uses ZF calculated over 2 bytes */ end
if (M3 && T2) begin
if (M3 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin nextM=1; setM1=1; end
if (M3 & T3) begin setM1=1; end
end
 
if (!op3 && pla[68]) begin
if (M1 && T2) begin
if (~op3 & pla[68]) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
1639,31 → 1537,25
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_set=1;
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1;
if (M1 & T4) begin validPLA=1; nextM=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */ end
if (M2 && T1) begin
if (M2 & T1) begin
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_alu_sel_op2_neg=1; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1;
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M2 && T2) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M2 & T2) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
1670,41 → 1562,29
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_alu_sel_op2_neg=1; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_cf_we=1; end
if (M2 && T3) begin
if (M2 & T3) begin
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */ end
if (M2 && T4) begin nextM=1;
if (M2 & T4) begin nextM=1;
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_sel_op2_neg=1; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1;
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M3 && T1) begin
if (M3 & T1) begin
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
1711,40 → 1591,34
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_alu_sel_op2_neg=1; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
ctl_flags_cf_we=1;
ctl_alu_zero_16bit=1; /* 16-bit arithmetic operation uses ZF calculated over 2 bytes */ end
if (M3 && T2) begin
if (M3 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin nextM=1; setM1=1; end
if (M3 & T3) begin setM1=1; end
end
 
if (pla[9]) begin
if (M1 && T4) begin validPLA=1;
if (M1 & T4) begin validPLA=1;
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M1 && T5) begin
if (M1 & T5) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit general purpose register, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M1 && T6) begin nextM=1; setM1=1; end
if (M1 & T6) begin setM1=1; end
end
 
// General Purpose Arithmetic and CPU Control Groups
if (pla[77]) begin
if (M1 && T1) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
1751,27 → 1625,23
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
ctl_flags_cf_we=1;
ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=!flags_nf; end
if (M1 && T2) begin
ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=~flags_nf; end
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_use_cf2=1;
ctl_flags_hf_cpl=flags_nf; end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
1780,28 → 1650,24
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
if (M1 & T4) begin validPLA=1; setM1=1;
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=2;
ctl_flags_cf_set=1; /* Set CF going into the ALU core */
ctl_flags_cf2_we=1; ctl_flags_cf2_sel_daa=1;
ctl_daa_oe=1; /* Write DAA correction factor to the bus */
ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=!flags_nf; end
ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=~flags_nf; end
end
 
if (pla[81]) begin
if (M1 && T1) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
1812,16 → 1678,16
ctl_flags_xy_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_set=1;
ctl_alu_sel_op2_neg=1; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_hf_cpl=flags_nf; end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
1830,7 → 1696,7
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
if (M1 & T4) begin validPLA=1; setM1=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_op1_sel_zero=1; /* Zero */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1842,7 → 1708,7
end
 
if (pla[82]) begin
if (M1 && T1) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
1849,28 → 1715,22
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
ctl_flags_nf_we=1; ctl_flags_nf_set=1;
ctl_flags_cf_we=1; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
1879,17 → 1739,11
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
if (M1 & T4) begin validPLA=1; setM1=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_op1_sel_zero=1; /* Zero */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
1898,7 → 1752,7
end
 
if (pla[89]) begin
if (M1 && T1) begin
if (M1 & T1) begin
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
1906,17 → 1760,17
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_xy_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_cf_we=1; ctl_flags_cf_cpl=1; /* CCF */
ctl_flags_hf_cpl=!flags_cf; /* Used for CCF */ end
if (M1 && T3) begin
ctl_flags_hf_cpl=~flags_cf; /* Used for CCF */ end
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
1925,7 → 1779,7
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
if (M1 & T4) begin validPLA=1; setM1=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1935,7 → 1789,7
end
 
if (pla[92]) begin
if (M1 && T1) begin
if (M1 & T1) begin
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
1943,16 → 1797,16
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_xy_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_cf_set=1; /* Set CF going into the ALU core */ end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
1961,7 → 1815,7
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
if (M1 & T4) begin validPLA=1; setM1=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1971,29 → 1825,29
end
 
if (pla[95]) begin
if (M1 && T3) begin
if (M1 & T3) begin
ctl_state_halt_set=1; /* Enter HALT state */ end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; end
if (M1 & T4) begin validPLA=1; setM1=1; end
end
 
if (pla[97]) begin
if (M1 && T3) begin
if (M1 & T3) begin
ctl_iffx_bit=op3; ctl_iffx_we=1; /* DI/EI */ end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
if (M1 & T4) begin validPLA=1; setM1=1;
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
end
 
if (pla[96]) begin
if (M1 && T3) begin
if (M1 & T3) begin
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_im_we=1; /* IM n ('n' is read by opcode[4:3]) */ end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; end
if (M1 & T4) begin validPLA=1; setM1=1; end
end
 
// Rotate and Shift Group
if (pla[25]) begin
if (M1 && T1) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
2005,16 → 1859,16
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf_we=1; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_use_cf2=1; end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
2023,9 → 1877,9
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
if (M1 & T4) begin validPLA=1; setM1=1;
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */
ctl_alu_op2_sel_bus=1; /* Internal bus */
2035,12 → 1889,12
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end
ctl_flags_cf2_we=1; ctl_flags_cf2_sel_shift=1; end
end
 
if (~use_ixiy && pla[70] && !pla[55]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */
if (~use_ixiy & pla[70] & ~pla[55]) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
2054,16 → 1908,16
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf_we=1; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_use_cf2=1; end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
2072,10 → 1926,9
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
if (M1 & T4) begin validPLA=1; setM1=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */
ctl_alu_op2_sel_bus=1; /* Internal bus */
2086,14 → 1939,14
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end
if (M4 && T1) begin fMRead=1;
ctl_flags_cf2_we=1; ctl_flags_cf2_sel_shift=1; end
if (M4 & T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_ir_we=1; end
if (M4 && T2) begin fMRead=1; end
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
if (M4 & T2) begin fMRead=1; end
if (M4 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2104,8 → 1957,8
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end
if (M5 && T1) begin fMWrite=1;
ctl_flags_cf2_we=1; ctl_flags_cf2_sel_shift=1; end
if (M5 & T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_sw_2u=1;
ctl_sw_1u=1;
2121,21 → 1974,21
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf_we=1; end
if (M5 && T2) begin fMWrite=1; end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M5 & T2) begin fMWrite=1; end
if (M5 & T3) begin fMWrite=1; setM1=1; end
end
 
if (~use_ixiy && pla[70] && pla[55]) begin
if (M1 && T2) begin
if (~use_ixiy & pla[70] & pla[55]) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_use_cf2=1; end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
2144,13 → 1997,13
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1; end
if (M2 && T3) begin fMRead=1; end
if (M2 && T4) begin nextM=1; ctl_mWrite=1;
if (M2 & T2) begin fMRead=1; end
if (M2 & T3) begin fMRead=1; end
if (M2 & T4) begin nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2161,8 → 2014,8
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end
if (M3 && T1) begin fMWrite=1;
ctl_flags_cf2_we=1; ctl_flags_cf2_sel_shift=1; end
if (M3 & T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_sw_2u=1;
ctl_sw_1u=1;
2178,15 → 2031,15
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf_we=1; end
if (M3 && T2) begin fMWrite=1; end
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M4 && T1) begin fMRead=1;
if (M3 & T2) begin fMWrite=1; end
if (M3 & T3) begin fMWrite=1; setM1=1; end
if (M4 & T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_ir_we=1; end
if (M4 && T2) begin fMRead=1; end
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
if (M4 & T2) begin fMRead=1; end
if (M4 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2197,8 → 2050,8
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end
if (M5 && T1) begin fMWrite=1;
ctl_flags_cf2_we=1; ctl_flags_cf2_sel_shift=1; end
if (M5 & T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_sw_2u=1;
ctl_sw_1u=1;
2214,12 → 2067,12
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf_we=1; end
if (M5 && T2) begin fMWrite=1; end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M5 & T2) begin fMWrite=1; end
if (M5 & T3) begin fMWrite=1; setM1=1; end
end
 
if (pla[15] && op3) begin
if (M1 && T1) begin
if (pla[15] & op3) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
2231,15 → 2084,15
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
2248,30 → 2101,30
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; end
if (M3 && T1) begin
if (M2 & T3) begin fMRead=1; nextM=1; end
if (M3 & T1) begin
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_lq=1; /* Cross-bus wire (see schematic) */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ end
if (M3 && T4) begin nextM=1; ctl_mWrite=1;
if (M3 & T4) begin nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_low=1; /* Write low nibble with a high nibble */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ end
if (M4 && T1) begin fMWrite=1;
if (M4 & T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_sw_2u=1;
ctl_sw_1u=1;
2278,10 → 2131,10
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_op2_oe=1; /* OP2 latch */ end
if (M4 && T2) begin fMWrite=1;
if (M4 & T2) begin fMWrite=1;
ctl_alu_op1_oe=1; /* OP1 latch */
ctl_alu_op2_sel_bus=1; /* Internal bus */ end
if (M4 && T3) begin fMWrite=1; nextM=1; setM1=1;
if (M4 & T3) begin fMWrite=1; setM1=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
2291,8 → 2144,8
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
end
 
if (pla[15] && !op3) begin
if (M1 && T1) begin
if (pla[15] & ~op3) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
2304,15 → 2157,15
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
2321,43 → 2174,43
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; end
if (M3 && T1) begin
if (M2 & T3) begin fMRead=1; nextM=1; end
if (M3 & T1) begin
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_lq=1; /* Cross-bus wire (see schematic) */
ctl_alu_op1_sel_low=1; /* Write low nibble with a high nibble */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ end
if (M3 && T2) begin
if (M3 & T2) begin
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_op2_oe=1; /* OP2 latch */ end
if (M3 && T3) begin
if (M3 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_lq=1; /* Cross-bus wire (see schematic) */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ end
if (M3 && T4) begin nextM=1; ctl_mWrite=1;
if (M3 & T4) begin nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_low=1; /* Write low nibble with a high nibble */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ end
if (M4 && T1) begin fMWrite=1;
if (M4 & T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_sw_2u=1;
ctl_sw_1u=1;
2364,10 → 2217,10
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_op2_oe=1; /* OP2 latch */ end
if (M4 && T2) begin fMWrite=1;
if (M4 & T2) begin fMWrite=1;
ctl_alu_op1_oe=1; /* OP1 latch */
ctl_alu_op2_sel_bus=1; /* Internal bus */ end
if (M4 && T3) begin fMWrite=1; nextM=1; setM1=1;
if (M4 & T3) begin fMWrite=1; setM1=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
2378,24 → 2231,24
end
 
// Bit Manipulation Group
if (~use_ixiy && pla[72] && !pla[55]) begin
if (M1 && T1) begin
if (~use_ixiy & pla[72] & ~pla[55]) begin
if (M1 & T1) begin
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1;
ctl_alu_core_S=1; ctl_flags_cf_set=1;
ctl_flags_sz_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
2407,20 → 2260,19
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
if (M1 & T4) begin validPLA=1; setM1=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1;
ctl_alu_core_S=1; ctl_flags_cf_set=1;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M4 && T1) begin fMRead=1;
if (M4 & T1) begin fMRead=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
2427,40 → 2279,40
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_ir_we=1; end
if (M4 && T2) begin fMRead=1; end
if (M4 && T3) begin fMRead=1; end
if (M4 && T4) begin nextM=1; setM1=1;
if (M4 & T2) begin fMRead=1; end
if (M4 & T3) begin fMRead=1; end
if (M4 & T4) begin setM1=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1;
ctl_alu_core_S=1; ctl_flags_cf_set=1;
ctl_flags_sz_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
end
 
if (~use_ixiy && pla[72] && pla[55]) begin
if (M1 && T1) begin
if (~use_ixiy & pla[72] & pla[55]) begin
if (M1 & T1) begin
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1;
ctl_alu_core_S=1; ctl_flags_cf_set=1;
ctl_flags_sz_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
2472,29 → 2324,29
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1; end
if (M2 && T3) begin fMRead=1;
if (M2 & T2) begin fMRead=1; end
if (M2 & T3) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_flags_xy_we=1; end
if (M2 && T4) begin nextM=1; setM1=1;
if (M2 & T4) begin setM1=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1;
ctl_alu_core_S=1; ctl_flags_cf_set=1;
ctl_flags_sz_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M4 && T1) begin fMRead=1;
if (M4 & T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2502,25 → 2354,25
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_ir_we=1; end
if (M4 && T2) begin fMRead=1; end
if (M4 && T3) begin fMRead=1; end
if (M4 && T4) begin nextM=1; setM1=1;
if (M4 & T2) begin fMRead=1; end
if (M4 & T3) begin fMRead=1; end
if (M4 & T4) begin setM1=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1;
ctl_alu_core_S=1; ctl_flags_cf_set=1;
ctl_flags_sz_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
end
 
if (~use_ixiy && pla[74] && !pla[55]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */
if (~use_ixiy & pla[74] & ~pla[55]) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2u=1;
ctl_alu_oe=1; /* Enable ALU onto the data bus */
2527,9 → 2379,9
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
2541,15 → 2393,14
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
if (M1 & T4) begin validPLA=1; setM1=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
if (M4 && T1) begin fMRead=1;
if (M4 & T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2557,17 → 2408,17
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_ir_we=1; end
if (M4 && T2) begin fMRead=1; end
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
if (M4 & T2) begin fMRead=1; end
if (M4 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
if (M5 && T1) begin fMWrite=1;
if (M5 & T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_sw_2u=1;
ctl_sw_1u=1;
2576,14 → 2427,14
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
if (M5 && T2) begin fMWrite=1; end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M5 & T2) begin fMWrite=1; end
if (M5 & T3) begin fMWrite=1; setM1=1; end
end
 
if (~use_ixiy && pla[74] && pla[55]) begin
if (M1 && T3) begin
if (~use_ixiy & pla[74] & pla[55]) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
2595,20 → 2446,20
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1; end
if (M2 && T3) begin fMRead=1;
if (M2 & T2) begin fMRead=1; end
if (M2 & T3) begin fMRead=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
if (M2 && T4) begin nextM=1; ctl_mWrite=1;
if (M2 & T4) begin nextM=1; ctl_mWrite=1;
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
2616,11 → 2467,11
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
if (M3 && T1) begin fMWrite=1;
if (M3 & T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T2) begin fMWrite=1; end
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M4 && T1) begin fMRead=1;
if (M3 & T2) begin fMWrite=1; end
if (M3 & T3) begin fMWrite=1; setM1=1; end
if (M4 & T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2628,17 → 2479,17
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_ir_we=1; end
if (M4 && T2) begin fMRead=1; end
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
if (M4 & T2) begin fMRead=1; end
if (M4 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
if (M5 && T1) begin fMWrite=1;
if (M5 & T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_sw_2u=1;
ctl_sw_1u=1;
2647,22 → 2498,22
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
if (M5 && T2) begin fMWrite=1; end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M5 & T2) begin fMWrite=1; end
if (M5 & T3) begin fMWrite=1; setM1=1; end
end
 
if (~use_ixiy && pla[73] && !pla[55]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */
if (~use_ixiy & pla[73] & ~pla[55]) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2u=1;
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M1 && T3) begin
ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
2674,15 → 2525,14
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
if (M1 & T4) begin validPLA=1; setM1=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M4 && T1) begin fMRead=1;
ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M4 & T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2690,17 → 2540,17
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_ir_we=1; end
if (M4 && T2) begin fMRead=1; end
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
if (M4 & T2) begin fMRead=1; end
if (M4 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M5 && T1) begin fMWrite=1;
ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M5 & T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_sw_2u=1;
ctl_sw_1u=1;
2708,15 → 2558,15
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M5 && T2) begin fMWrite=1; end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end
ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M5 & T2) begin fMWrite=1; end
if (M5 & T3) begin fMWrite=1; setM1=1; end
end
 
if (~use_ixiy && pla[73] && pla[55]) begin
if (M1 && T3) begin
if (~use_ixiy & pla[73] & pla[55]) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
2728,20 → 2578,20
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1; end
if (M2 && T3) begin fMRead=1;
if (M2 & T2) begin fMRead=1; end
if (M2 & T3) begin fMRead=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M2 && T4) begin nextM=1; ctl_mWrite=1;
ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M2 & T4) begin nextM=1; ctl_mWrite=1;
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
2748,12 → 2598,12
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M3 && T1) begin fMWrite=1;
ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M3 & T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T2) begin fMWrite=1; end
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M4 && T1) begin fMRead=1;
if (M3 & T2) begin fMWrite=1; end
if (M3 & T3) begin fMWrite=1; setM1=1; end
if (M4 & T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2761,17 → 2611,17
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_ir_we=1; end
if (M4 && T2) begin fMRead=1; end
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
if (M4 & T2) begin fMRead=1; end
if (M4 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M5 && T1) begin fMWrite=1;
ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M5 & T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_sw_2u=1;
ctl_sw_1u=1;
2779,42 → 2629,42
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M5 && T2) begin fMWrite=1; end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end
ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M5 & T2) begin fMWrite=1; end
if (M5 & T3) begin fMWrite=1; setM1=1; end
end
 
// Input and Output Groups
if (pla[37] && !pla[28]) begin
if (M1 && T1) begin
if (pla[37] & ~pla[28]) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_iorw=1; end
if (M3 && T1) begin fIORead=1;
if (M2 & T3) begin fMRead=1; nextM=1; ctl_iorw=1; end
if (M3 & T1) begin fIORead=1;
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; ctl_sw_4d=1; /* Read 8-bit general purpose A register, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ /* Which register to be written is decided elsewhere */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T2) begin fIORead=1; end
if (M3 && T3) begin fIORead=1; end
if (M3 && T4) begin fIORead=1; nextM=1; setM1=1; end
if (M3 & T2) begin fIORead=1; end
if (M3 & T3) begin fIORead=1; end
if (M3 & T4) begin fIORead=1; setM1=1; end
end
 
if (pla[27] && !pla[34]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */
if (pla[27] & ~pla[34]) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
2827,15 → 2677,15
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
2844,18 → 2694,18
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_iorw=1; end
if (M2 && T1) begin fIORead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_iorw=1; end
if (M2 & T1) begin fIORead=1;
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fIORead=1; end
if (M2 && T3) begin fIORead=1; end
if (M2 && T4) begin fIORead=1; nextM=1; setM1=1;
if (M2 & T2) begin fIORead=1; end
if (M2 & T3) begin fIORead=1; end
if (M2 & T4) begin fIORead=1; setM1=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2866,65 → 2716,64
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
end
 
if (pla[37] && pla[28]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (pla[37] & pla[28]) begin
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_iorw=1;
if (M2 & T3) begin fMRead=1; nextM=1; ctl_iorw=1;
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; ctl_sw_4d=1; /* Read 8-bit general purpose A register, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fIOWrite=1;
if (M3 & T1) begin fIOWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M3 && T2) begin fIOWrite=1; end
if (M3 && T3) begin fIOWrite=1; end
if (M3 && T4) begin fIOWrite=1; nextM=1; setM1=1; end
if (M3 & T2) begin fIOWrite=1; end
if (M3 & T3) begin fIOWrite=1; end
if (M3 & T4) begin fIOWrite=1; setM1=1; end
end
 
if (pla[27] && pla[34]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_iorw=1;
if (op4 & op5 & !op3) ctl_bus_zero_oe=1; /* Trying to read flags? Put 0 on the bus instead. */
else begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; end /* Read 8-bit GP register */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
if (pla[27] & pla[34]) begin
if (M1 & T4) begin validPLA=1; nextM=1; ctl_iorw=1;
if (op4 & op5 & ~op3) begin ctl_bus_zero_oe=1; end /* Trying to read flags? Put 0 on the bus instead. */
if (~(op4 & op5 & ~op3)) begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; end /* Read 8-bit GP register */
ctl_reg_out_hi=~rsel3; ctl_reg_out_lo=rsel3; ctl_sw_2u=~rsel3; ctl_sw_2d=rsel3; /* Enable register gate based on the rsel3 */ /* Controlled by register gate */
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M2 && T1) begin fIOWrite=1;
if (M2 & T1) begin fIOWrite=1;
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fIOWrite=1; end
if (M2 && T3) begin fIOWrite=1; end
if (M2 && T4) begin fIOWrite=1; nextM=1; setM1=1; end
if (M2 & T2) begin fIOWrite=1; end
if (M2 & T3) begin fIOWrite=1; end
if (M2 & T4) begin fIOWrite=1; setM1=1; end
end
 
if (pla[91] && pla[21]) begin
if (M1 && T1) begin
if (pla[91] & pla[21]) begin
if (M1 & T1) begin
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_alu_core_R=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
2933,29 → 2782,23
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; end
if (M1 && T5) begin nextM=1; ctl_iorw=1; end
if (M2 && T1) begin fIORead=1;
if (M1 & T4) begin validPLA=1; end
if (M1 & T5) begin nextM=1; ctl_iorw=1; end
if (M2 & T1) begin fIORead=1;
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fIORead=1;
if (M2 & T2) begin fIORead=1;
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_zero=1; /* Zero */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1;
ctl_alu_sel_op2_neg=1; end
if (M2 && T3) begin fIORead=1;
if (M2 & T3) begin fIORead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
2962,68 → 2805,62
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_cf_we=1;
ctl_alu_sel_op2_neg=1; end
if (M2 && T4) begin fIORead=1; nextM=1; ctl_mWrite=1;
if (M2 & T4) begin fIORead=1; nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_nf_we=1; /* Sign bit, to be used with FLAGT source set to "alu" */
ctl_alu_sel_op2_neg=1; end
if (M3 && T1) begin fMWrite=1;
if (M3 & T1) begin fMWrite=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMWrite=1;
if (M3 & T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=nonRep | flags_zf; end
if (M4 && T1) begin
if (M3 & T3) begin fMWrite=1; nextM=1; setM1=nonRep | flags_zf; end
if (M4 & T1) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T2) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
if (M4 & T2) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin
if (M4 & T3) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T4) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
if (M4 & T4) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T5) begin nextM=1; setM1=1; end
if (M4 & T5) begin setM1=1; end
end
 
if (pla[91] && pla[20]) begin
if (M1 && T1) begin
if (pla[91] & pla[20]) begin
if (M1 & T1) begin
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_alu_core_R=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
3032,24 → 2869,18
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1;
if (M1 & T4) begin validPLA=1;
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_zero=1; /* Zero */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1;
ctl_alu_sel_op2_neg=1; end
if (M1 && T5) begin nextM=1; ctl_mRead=1;
if (M1 & T5) begin nextM=1; ctl_mRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
3056,107 → 2887,89
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_alu_sel_op2_neg=1; end
if (M2 && T1) begin fMRead=1;
if (M2 & T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
if (M2 & T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_iorw=1;
if (M2 & T3) begin fMRead=1; nextM=1; ctl_iorw=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */ end
if (M3 && T1) begin fIOWrite=1;
if (M3 & T1) begin fIOWrite=1;
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fIOWrite=1;
if (M3 & T2) begin fIOWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; /* Sign bit, to be used with FLAGT source set to "alu" */ end
if (M3 && T3) begin fIOWrite=1;
if (M3 & T3) begin fIOWrite=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_cf_we=1; end
if (M3 && T4) begin fIOWrite=1; nextM=1; setM1=nonRep | flags_zf; end
if (M4 && T1) begin
if (M3 & T4) begin fIOWrite=1; nextM=1; setM1=nonRep | flags_zf; end
if (M4 & T1) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T2) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
if (M4 & T2) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin
if (M4 & T3) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T4) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
if (M4 & T4) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T5) begin nextM=1; setM1=1; end
if (M4 & T5) begin setM1=1; end
end
 
// Jump Group
if (pla[29]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
if (M3 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M3 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1;
if (M3 & T3) begin fMRead=1; setM1=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
3165,11 → 2978,11
end
 
if (pla[43]) begin
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
3178,33 → 2991,31
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
if (M3 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M3 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1;
if (flags_cond_true) begin /* If cc is true, use WZ instead of PC (for jumps) */
ctl_reg_not_pc=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1;
end
if (M3 & T3) begin fMRead=1; setM1=1;
ctl_reg_not_pc|=flags_cond_true; ctl_reg_sel_wz|=flags_cond_true; ctl_reg_sys_hilo|={flags_cond_true,flags_cond_true}; ctl_sw_4d|=flags_cond_true;
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo[1]=1; /* Conditionally selecting only W */
ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Conditionally selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
3212,11 → 3023,11
end
 
if (pla[47]) begin
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
3225,41 → 3036,35
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; end
if (M3 && T1) begin
if (M2 & T3) begin fMRead=1; nextM=1; end
if (M3 & T1) begin
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1; end
if (M3 && T2) begin
if (M3 & T2) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1; end
if (M3 && T3) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M3 & T3) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
3266,53 → 3071,39
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_cf_we=1; end
if (M3 && T4) begin
if (M3 & T4) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_zero=1; /* Zero */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1;
ctl_alu_sel_op2_neg=flags_sf; end
if (M3 && T5) begin nextM=1; setM1=1;
if (M3 & T5) begin setM1=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_alu_sel_op2_neg=flags_sf;
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
end
 
if (pla[48]) begin
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
3321,42 → 3112,36
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1;
ctl_cond_short=1; /* M1/T3 only: force a short flags condition (SS) */ end
if (M2 && T1) begin fMRead=1;
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; setM1=!flags_cond_true; end
if (M3 && T1) begin
if (M2 & T3) begin fMRead=1; nextM=1; setM1=~flags_cond_true; end
if (M3 & T1) begin
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1; end
if (M3 && T2) begin
if (M3 & T2) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1; end
if (M3 && T3) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M3 & T3) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
3363,49 → 3148,35
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_cf_we=1; end
if (M3 && T4) begin
if (M3 & T4) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_zero=1; /* Zero */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1;
ctl_alu_sel_op2_neg=flags_sf; end
if (M3 && T5) begin nextM=1; setM1=1;
if (M3 & T5) begin setM1=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_alu_sel_op2_neg=flags_sf;
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
end
 
if (pla[6]) begin
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
if (M1 & T4) begin validPLA=1; setM1=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
3412,11 → 3183,11
end
 
if (pla[26]) begin
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
3425,25 → 3196,18
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1;
if (M1 & T4) begin validPLA=1;
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_zero=1; /* Zero */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1;
ctl_alu_sel_op2_neg=1; end
if (M1 && T5) begin nextM=1; ctl_mRead=1;
if (M1 & T5) begin nextM=1; ctl_mRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
3450,49 → 3214,37
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_sz_we=1;
ctl_alu_sel_op2_neg=1; end
if (M2 && T1) begin fMRead=1;
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; setM1=flags_zf; /* Used in DJNZ */ end
if (M3 && T1) begin
if (M2 & T3) begin fMRead=1; nextM=1; setM1=flags_zf; /* Used in DJNZ */ end
if (M3 & T1) begin
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1; end
if (M3 && T2) begin
if (M3 & T2) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1; end
if (M3 && T3) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M3 & T3) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
3499,43 → 3251,29
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_cf_we=1; end
if (M3 && T4) begin
if (M3 & T4) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_zero=1; /* Zero */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1;
ctl_alu_sel_op2_neg=flags_sf; end
if (M3 && T5) begin nextM=1; setM1=1;
if (M3 & T5) begin setM1=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_alu_sel_op2_neg=flags_sf;
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
end
3542,66 → 3280,65
 
// Call and Return Group
if (pla[24]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
if (M3 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M3 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1;
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
if (M3 & T3) begin fMRead=1;
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T4) begin nextM=1; ctl_mWrite=1;
if (M3 & T4) begin nextM=1; ctl_mWrite=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T1) begin fMWrite=1;
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
if (M4 & T1) begin fMWrite=1;
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_apin_mux=1; /* Apin sourced from incrementer */
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M4 && T2) begin fMWrite=1;
if (M4 & T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M5 && T1) begin fMWrite=1;
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
if (M5 & T1) begin fMWrite=1;
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_apin_mux=1; /* Apin sourced from incrementer */
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M5 && T2) begin fMWrite=1;
if (M5 & T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1;
if (M5 & T3) begin fMWrite=1; setM1=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
3608,11 → 3345,11
end
 
if (pla[42]) begin
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
3621,66 → 3358,65
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
if (M3 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M3 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=!flags_cond_true; setM1=!flags_cond_true;
ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo[1]=1; /* Conditionally selecting only W */
if (M3 & T3) begin fMRead=1; nextM=~flags_cond_true; setM1=~flags_cond_true;
ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Conditionally selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T4) begin nextM=1; ctl_mWrite=1;
if (M3 & T4) begin nextM=1; ctl_mWrite=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T1) begin fMWrite=1;
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
if (M4 & T1) begin fMWrite=1;
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_apin_mux=1; /* Apin sourced from incrementer */
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M4 && T2) begin fMWrite=1;
if (M4 & T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M5 && T1) begin fMWrite=1;
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
if (M5 & T1) begin fMWrite=1;
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_apin_mux=1; /* Apin sourced from incrementer */
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M5 && T2) begin fMWrite=1;
if (M5 & T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1;
if (M5 & T3) begin fMWrite=1; setM1=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
3687,31 → 3423,31
end
 
if (pla[35]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
if (M2 & T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
if (M3 & T1) begin fMRead=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
if (M3 & T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1;
if (M3 & T3) begin fMRead=1; setM1=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
3720,11 → 3456,11
end
 
if (pla[45]) begin
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
3733,32 → 3469,32
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; end
if (M1 && T5) begin nextM=1; ctl_mRead=1; setM1=!flags_cond_true; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; end
if (M1 & T5) begin nextM=1; ctl_mRead=1; setM1=~flags_cond_true; end
if (M2 & T1) begin fMRead=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
if (M2 & T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
if (M3 & T1) begin fMRead=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
if (M3 & T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1;
if (M3 & T3) begin fMRead=1; setM1=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
3767,32 → 3503,32
end
 
if (pla[46]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1;
ctl_iff1_iff2=1; /* RETN copies IFF2 into IFF1 */ end
if (M2 && T1) begin fMRead=1;
if (M2 & T1) begin fMRead=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
if (M2 & T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
if (M3 & T1) begin fMRead=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
if (M3 & T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1;
if (M3 & T3) begin fMRead=1; setM1=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
3801,7 → 3537,7
end
 
if (pla[56]) begin
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
3808,53 → 3544,52
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_op1_oe=1; /* OP1 latch */
ctl_alu_op1_sel_zero=1; /* Zero */
ctl_sw_mask543_en=!((in_intr & im2) | in_nmi);
ctl_sw_1d=!in_nmi; ctl_66_oe=in_nmi;
ctl_sw_mask543_en=~((in_intr & im2) | in_nmi);
ctl_sw_1d=~in_nmi; ctl_66_oe=in_nmi;
ctl_bus_ff_oe=in_intr & im1; end
if (M1 && T4) begin validPLA=1; end
if (M1 && T5) begin nextM=1; ctl_mWrite=1;
if (M1 & T4) begin validPLA=1; end
if (M1 & T5) begin nextM=1; ctl_mWrite=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */ end
if (M2 && T1) begin fMWrite=1;
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
if (M2 & T1) begin fMWrite=1;
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_apin_mux=1; /* Apin sourced from incrementer */
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
ctl_reg_out_hi=1; /* From the register file into the ALU high byte only */
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M2 && T2) begin fMWrite=1;
if (M2 & T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
if (M2 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T1) begin fMWrite=1;
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
if (M3 & T1) begin fMWrite=1;
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_apin_mux=1; /* Apin sourced from incrementer */
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
ctl_reg_out_lo=1; /* From the register file into the ALU low byte only */
ctl_sw_2u=1;
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M3 && T2) begin fMWrite=1;
if (M3 & T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMWrite=1; nextM=1; ctl_mRead=in_intr & im2; /* RST38 interrupt extension */ setM1=!(in_intr & im2); /* RST38 interrupt extension */
if (M3 & T3) begin fMWrite=1; nextM=1; ctl_mRead=in_intr & im2; /* RST38 interrupt extension */ setM1=~(in_intr & im2); /* RST38 interrupt extension */
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
// INTR IM2 continues here...
if (M4 && T1) begin fMRead=1;
if (M4 & T1) begin fMRead=1;
ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4d=1; /* Select 8-bit I register */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
3861,21 → 3596,21
ctl_sw_2u=1;
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_op1_oe=1; /* OP1 latch */ end
if (M4 && T2) begin fMRead=1;
if (M4 & T2) begin fMRead=1;
ctl_sw_4u=1;
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_reg_out_lo=1; /* From the register file into the ALU low byte only */
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */ end
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (M4 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M5 && T1) begin fMRead=1;
if (M5 & T1) begin fMRead=1;
ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4d=1; /* Select 8-bit I register */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
3882,13 → 3617,13
ctl_sw_2u=1;
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_op1_oe=1; /* OP1 latch */ end
if (M5 && T2) begin fMRead=1;
ctl_inc_cy=pc_inc; /* Increment */
if (M5 & T2) begin fMRead=1;
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M5 && T3) begin fMRead=1; nextM=1; setM1=1;
if (M5 & T3) begin fMRead=1; setM1=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
3898,11 → 3633,11
 
// CB-Table opcodes
if (pla[49]) begin
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
3912,26 → 3647,26
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1;
ctl_state_tbl_cb_set=1; setCBED=1; /* CB-table prefix */ end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M2 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; end
if (M3 && T1) begin fMRead=1;
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1; end
if (M3 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (M3 & T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T3) begin fMRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
if (M4 && T1) begin
if (M3 & T3) begin fMRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 & T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
if (M4 & T1) begin
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
ctl_alu_op2_sel_bus=1; /* Internal bus */
3942,51 → 3677,39
 
// Special Purposes PLA Entries
if (pla[3]) begin
if (M1 && T2) begin
if (M1 & T2) begin
ctl_state_ixiy_we=1; ctl_state_iy_set=op5; setIXIY=1; /* IX/IY prefix */ end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
if (M1 & T4) begin validPLA=1; setM1=1;
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
end
 
if (pla[44]) begin
if (M1 && T2) begin
if (M1 & T2) begin
ctl_state_tbl_cb_set=1; setCBED=1; /* CB-table prefix */ end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
if (M1 & T4) begin validPLA=1; setM1=1;
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
end
 
if (pla[51]) begin
if (M1 && T2) begin
if (M1 & T2) begin
ctl_state_tbl_ed_set=1; setCBED=1; /* ED-table prefix */ end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
if (M1 & T4) begin validPLA=1; setM1=1;
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
end
 
if (pla[76]) begin
begin
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1;
end else begin
ctl_alu_core_hf=1;
end
begin
ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_nf_we=1; ctl_flags_nf_set=1; end
if (M1 && T1) begin
if (M1 & T1) begin
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end
end
 
if (pla[78]) begin
begin
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1;
end else begin
ctl_alu_core_hf=1;
end
begin
ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_nf_we=1; ctl_flags_nf_set=1; end
if (M1 && T1) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_xy_we=1;
3994,16 → 3717,10
end
 
if (pla[79]) begin
begin
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
begin
ctl_alu_sel_op2_neg=1; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_nf_we=1; ctl_flags_nf_set=1; end
if (M1 && T1) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_xy_we=1;
4011,14 → 3728,10
end
 
if (pla[80]) begin
begin
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
begin
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T1) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_xy_we=1;
4026,16 → 3739,10
end
 
if (pla[84]) begin
begin
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
begin
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T1) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_xy_we=1;
4043,72 → 3750,66
end
 
if (pla[85]) begin
begin
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1;
begin
ctl_alu_core_S=1; ctl_flags_cf_set=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T1) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ end
end
 
if (pla[86]) begin
begin
begin
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T1) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ end
end
 
if (pla[88]) begin
begin
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
begin
ctl_alu_core_R=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T1) begin
if (M1 & T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ end
end
 
// State machine to compute (IX+d)
if (ixy_d) begin
if (T1) begin
if (T1) begin
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1; end
if (T2) begin
if (T2) begin
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1; end
if (T3) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
if (T3) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
4115,67 → 3816,67
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end
if (T4) begin
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_cf2_we=1; end
if (T4) begin
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_zero=1; /* Zero */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_hf_we=1;
ctl_flags_use_cf2=1;
ctl_alu_sel_op2_neg=flags_sf; end
if (T5) begin
if (T5) begin
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_xy_we=1;
ctl_alu_sel_op2_neg=flags_sf;
ctl_state_ixiy_we=1; ctl_state_ixiy_clr=!setIXIY; /* Clear IX/IY flag */ end
ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY; /* Clear IX/IY flag */ end
end
 
// Default instruction fetch (M1) state machine
if (M1) begin
if (M1 && T1) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
if (1) begin
if (M1 & T1) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; ctl_apin_mux2=1; /* Apin sourced from AL */ end
if (M1 && T2) begin
if (M1 & T2) begin
ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit IR */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_state_ixiy_we=1; ctl_state_ixiy_clr=!setIXIY; /* Clear IX/IY flag */
ctl_state_tbl_clr=!setCBED; /* Clear CB/ED prefix */
ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY; /* Clear IX/IY flag */
ctl_state_tbl_clr=~setCBED; /* Clear CB/ED prefix */
ctl_ir_we=1;
ctl_bus_zero_oe=in_halt; ctl_bus_ff_oe=(in_intr & (im1 | im2)) | in_nmi; end
if (M1 && T3) begin
if (M1 & T3) begin
ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; /* Write 16-bit IR */
ctl_inc_cy=pc_inc; /* Increment */
ctl_inc_cy=~pc_inc_hold; /* Increment */
ctl_bus_inc_oe=1; ctl_apin_mux2=1; /* Apin sourced from AL */
ctl_inc_limit6=1; /* Limit the incrementer to 6 bits */ end
if (M1 && T4) begin
if (M1 & T4) begin
ctl_eval_cond=1; /* Evaluate flags condition based on the opcode[5:3] */ end
end
 
// For all undecoded instructions, at M1/T4 advance a byte to the next opcode
if (~validPLA) begin
if (M1 & T4) begin setM1=1; end
end
 
// The last cycle of an instruction is also the first cycle of the next one
if (setM1) begin
begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
end
 
/genmatrix.py
1,14 → 1,13
#!/usr/bin/env python
#!/usr/bin/env python3
#
# This script reads A-Z80 instruction timing data from a spreadsheet text file
# 'Timings.csv' (which is a TAB-delimited text file exported from 'Timings.xlsm')
# and generates a Verilog include file defining the control block execution matrix.
# Token keywords in the timing spreadsheet are substituted using a list of keys
# stored in the macros file. See the macro file for the format information.
# defined in 'timing_macros.i'.
#
# Input timing file is exported from the Excel file as a TAB-delimited text file.
#
#-------------------------------------------------------------------------------
# Copyright (C) 2014 Goran Devic
# Copyright (C) 2014,2016 Goran Devic
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the Free
25,7 → 24,7
import csv
import os
 
# Input file exported from a timing spreadsheet:
# Input file (exported from 'Timings.xlsm'):
fname = "Timings.csv"
 
# Input file containing macro substitution keys
34,6 → 33,9
# Set this to 1 if you want abbreviated matrix (no-action lines removed)
abbr = 1
 
# Set this to 0 if you want to strip all comments from the resulting file
comment = 1
 
# Set this to 1 if you want debug $display() printout on each PLA line
debug = 0
 
48,8 → 50,12
if len(line.strip())>0 and line[0]!='/':
# Wrap up non-starting //-style comments into /* ... */ so the
# line can be concatenated while preserving comments
if line.find("//")>0:
macros.append( line.rstrip().replace("//", "/*", 1) + " */" )
i = line.find("//")
if i>0:
if comment==1:
macros.append( line.rstrip().replace("//", "/*", 1) + " */" )
else:
macros.append( line.rstrip()[0:i] )
else:
macros.append(line.rstrip())
 
70,11 → 76,11
if multiline==True:
# Multiline copies lines until a char at [0] is not a space
if len(l.strip())==0 or l[0]!=' ':
return '\n' + "\n".join(subst)
return '\n' + "\n".join(subst).rstrip()
else:
subst.append(l)
subst.append(l.rstrip())
lx = l.split(' ') # Split the string and then ignore (duplicate)
lx = filter(None, lx) # spaces in the list left by the split()
lx = list(filter(None, lx)) # spaces in the list left by the split()
if l.startswith(":"): # Find and recognize a matching set (key) section
if validset: # Error if there is a new section going from the macthing one
break # meaning we did not find our macro in there
96,7 → 102,7
 
# Read the content of a file and using the csv reader and remove any quotes from the input fields
content = [] # Content of the spreadsheet timing file
with open(fname, 'rb') as csvFile:
with open(fname, 'r') as csvFile:
reader = csv.reader(csvFile, delimiter='\t', quotechar='"')
for row in reader:
content.append('\t'.join(row))
113,12 → 119,12
imatrix = [] # Verilog execution matrix code
for line in content:
col = line.split('\t') # Split the string into a list of columns
col_clean = filter(None, col) # Removed all empty fields (between the separators)
col_clean = list(filter(None, col)) # Removed all empty fields (between the separators)
if len(col_clean)==0: # Ignore completely empty lines
continue
 
if col_clean[0].startswith('//'): # Print comment lines
imatrix.append(col_clean[0])
if col_clean[0].startswith('//') and comment==1:
imatrix.append(col_clean[0]) # Optionally print comment lines
 
if col_clean[0].startswith("#end"): # Print the end of a condition
imatrix.append("end\n")
138,11 → 144,11
# M and T states are hard-coded in the table at the index 1 and 2
if col_clean[0].startswith('#0'):
if col[1]=='?': # M is optional, use '?' to skip it
state = " if (T{0}) begin ".format(col[2])
state = " if (T{0}) begin".format(col[2])
else:
state = " if (M{0} && T{1}) begin ".format(col[1], col[2])
state = " if (M{0} & T{1}) begin".format(col[1], col[2])
else:
state = " begin "
state = " begin"
 
# Loop over all other columns and perform verbatim substitution
action = ""
149,7 → 155,7
for i in range(3,len(col)):
# There may be multiple tokens separated by commas
tokList = col[i].strip().split(',')
tokList = filter(None, tokList) # Filter out empty lines
tokList = list(filter(None, tokList)) # Filter out empty lines
for token in tokList:
token = token.strip()
if i in tkeys and len(token)>0:
158,7 → 164,7
action += ctl_prefix
action += macro
if state.find("ERROR")>=0:
print "{0} {1}".format(state, action)
print ("{0} {1}".format(state, action))
break
 
# Complete and write out a line
168,11 → 174,12
 
# Create a file containing the logic matrix code
with open('exec_matrix.vh', 'w') as file:
file.write("// Automatically generated by genmatrix.py\n")
if comment==1:
file.write("// Automatically generated by genmatrix.py\n\n")
# If there were errors, print them first (and output to the console)
if len(errors)>0:
for error in errors:
print error
print (error)
file.write(error + "\n")
file.write("-" * 80 + "\n")
for item in imatrix:
179,4 → 186,4
file.write("{}\n".format(item))
 
# Touch a file that includes 'exec_matrix.vh' to ensure it will recompile correctly
os.utime("execute.sv", None)
os.utime("execute.v", None)
/interrupts.bsf
20,7 → 20,7
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 168 240)
(rect 64 64 216 288)
(text "interrupts" (rect 5 0 59 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 208 25 220)(font "Arial" ))
(port
103,45 → 103,38
(port
(pt 152 32)
(output)
(text "iff1" (rect 0 0 18 14)(font "Arial" (font_size 8)))
(text "iff1" (rect 113 27 131 41)(font "Arial" (font_size 8)))
(text "iff2" (rect 0 0 18 14)(font "Arial" (font_size 8)))
(text "iff2" (rect 113 27 131 41)(font "Arial" (font_size 8)))
(line (pt 152 32)(pt 136 32))
)
(port
(pt 152 48)
(output)
(text "iff2" (rect 0 0 18 14)(font "Arial" (font_size 8)))
(text "iff2" (rect 113 43 131 57)(font "Arial" (font_size 8)))
(text "in_nmi" (rect 0 0 35 14)(font "Arial" (font_size 8)))
(text "in_nmi" (rect 96 43 131 57)(font "Arial" (font_size 8)))
(line (pt 152 48)(pt 136 48))
)
(port
(pt 152 64)
(output)
(text "in_nmi" (rect 0 0 35 14)(font "Arial" (font_size 8)))
(text "in_nmi" (rect 96 59 131 73)(font "Arial" (font_size 8)))
(text "in_intr" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "in_intr" (rect 97 59 131 73)(font "Arial" (font_size 8)))
(line (pt 152 64)(pt 136 64))
)
(port
(pt 152 80)
(output)
(text "in_intr" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "in_intr" (rect 97 75 131 89)(font "Arial" (font_size 8)))
(text "im1" (rect 0 0 18 14)(font "Arial" (font_size 8)))
(text "im1" (rect 113 75 131 89)(font "Arial" (font_size 8)))
(line (pt 152 80)(pt 136 80))
)
(port
(pt 152 96)
(output)
(text "im1" (rect 0 0 18 14)(font "Arial" (font_size 8)))
(text "im1" (rect 113 91 131 105)(font "Arial" (font_size 8)))
(text "im2" (rect 0 0 18 14)(font "Arial" (font_size 8)))
(text "im2" (rect 113 91 131 105)(font "Arial" (font_size 8)))
(line (pt 152 96)(pt 136 96))
)
(port
(pt 152 112)
(output)
(text "im2" (rect 0 0 18 14)(font "Arial" (font_size 8)))
(text "im2" (rect 113 107 131 121)(font "Arial" (font_size 8)))
(line (pt 152 112)(pt 136 112))
)
(drawing
(rectangle (rect 16 16 136 208))
)
/temp_wires.vh
0,0 → 1,694
// Automatically generated by gencompile.py
 
reg ctl_reg_gp_sel_pla17npla50M1T1_2;
reg ctl_reg_gp_hilo_pla17npla50M1T1_3;
reg ctl_reg_sys_hilo_pla17npla50M2T1_3;
reg ctl_reg_sys_hilo_pla17npla50M2T2_4;
reg ctl_reg_gp_sel_pla61npla58npla59M1T1_2;
reg ctl_reg_gp_hilo_pla61npla58npla59M1T1_3;
reg ctl_reg_gp_sel_pla61npla58npla59M1T4_3;
reg ctl_reg_gp_hilo_pla61npla58npla59M1T4_4;
reg ctl_reg_gp_sel_use_ixiypla58M1T1_2;
reg ctl_reg_gp_hilo_use_ixiypla58M1T1_3;
reg ctl_reg_sys_hilo_use_ixiypla58M2T1_3;
reg ctl_reg_sys_hilo_use_ixiypla58M2T2_4;
reg ctl_reg_gp_sel_nuse_ixiypla58M1T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla58M1T1_3;
reg ctl_reg_gp_sel_nuse_ixiypla58M2T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla58M2T1_3;
reg ctl_reg_sys_hilo_use_ixiypla59M2T1_3;
reg ctl_reg_sys_hilo_use_ixiypla59M2T2_4;
reg ctl_reg_gp_sel_nuse_ixiypla59M1T4_4;
reg ctl_reg_gp_hilo_nuse_ixiypla59M1T4_5;
reg ctl_reg_gp_sel_nuse_ixiypla59M2T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla59M2T1_3;
reg ctl_reg_gp_sel_nuse_ixiypla59M4T1_3;
reg ctl_reg_gp_hilo_nuse_ixiypla59M4T1_4;
reg ctl_reg_sys_hilo_pla40M2T1_3;
reg ctl_reg_sys_hilo_pla40M2T2_4;
reg ctl_reg_sys_hilo_pla40M3T1_3;
reg ctl_reg_sys_hilo_pla40M3T2_4;
reg ctl_reg_sys_hilo_pla50npla40M2T1_3;
reg ctl_reg_sys_hilo_pla50npla40M2T2_4;
reg ctl_reg_gp_sel_pla50npla40M3T1_2;
reg ctl_reg_gp_hilo_pla50npla40M3T1_3;
reg ctl_reg_gp_sel_pla8pla13M1T4_4;
reg ctl_reg_gp_hilo_pla8pla13M1T4_5;
reg ctl_reg_gp_sel_pla8pla13M2T1_2;
reg ctl_reg_gp_hilo_pla8pla13M2T1_3;
reg ctl_reg_sys_hilo_pla8pla13M2T2_4;
reg ctl_reg_gp_sel_pla8npla13M1T1_2;
reg ctl_reg_gp_hilo_pla8npla13M1T1_3;
reg ctl_reg_gp_sel_pla8npla13M2T1_2;
reg ctl_reg_gp_hilo_pla8npla13M2T1_3;
reg ctl_reg_sys_hilo_pla8npla13M2T2_4;
reg ctl_reg_sys_hilo_pla38pla13M2T1_3;
reg ctl_reg_sys_hilo_pla38pla13M2T2_4;
reg ctl_reg_sys_hilo_pla38pla13M2T3_6;
reg ctl_reg_sys_hilo_pla38pla13M3T1_3;
reg ctl_reg_sys_hilo_pla38pla13M3T2_4;
reg ctl_reg_sys_hilo_pla38pla13M3T3_5;
reg ctl_reg_sys_hilo_pla38pla13M3T3_10;
reg ctl_reg_gp_sel_pla38pla13M4T1_3;
reg ctl_reg_gp_hilo_pla38pla13M4T1_4;
reg ctl_reg_sys_hilo_pla38pla13M4T2_4;
reg ctl_reg_gp_sel_pla38npla13M1T1_2;
reg ctl_reg_gp_hilo_pla38npla13M1T1_3;
reg ctl_reg_sys_hilo_pla38npla13M2T1_3;
reg ctl_reg_sys_hilo_pla38npla13M2T2_4;
reg ctl_reg_sys_hilo_pla38npla13M2T3_6;
reg ctl_reg_sys_hilo_pla38npla13M3T1_3;
reg ctl_reg_sys_hilo_pla38npla13M3T2_4;
reg ctl_reg_sys_hilo_pla38npla13M3T3_6;
reg ctl_reg_sys_hilo_pla38npla13M4T1_3;
reg ctl_reg_sys_hilo_pla38npla13M4T2_4;
reg ctl_reg_gp_sel_pla83M1T1_2;
reg ctl_reg_gp_hilo_pla83M1T1_3;
reg ctl_pf_sel_pla83M1T1_19;
reg ctl_reg_gp_sel_pla83M1T2_2;
reg ctl_reg_gp_hilo_pla83M1T2_3;
reg ctl_reg_gp_sel_pla83M1T3_1;
reg ctl_reg_gp_hilo_pla83M1T3_2;
reg ctl_reg_sys_hilo_pla83M1T4_3;
reg ctl_reg_gp_sel_pla57M1T3_1;
reg ctl_reg_gp_hilo_pla57M1T3_2;
reg ctl_reg_sys_hilo_pla57M1T4_4;
reg ctl_reg_gp_sel_pla7M1T1_2;
reg ctl_reg_gp_hilo_pla7M1T1_3;
reg ctl_reg_sys_hilo_pla7M2T1_3;
reg ctl_reg_sys_hilo_pla7M2T2_4;
reg ctl_reg_sys_hilo_pla7M3T1_3;
reg ctl_reg_gp_sel_pla7M3T1_6;
reg ctl_reg_gp_hilo_pla7M3T1_7;
reg ctl_reg_sys_hilo_pla7M3T2_4;
reg ctl_reg_sys_hilo_pla30pla13M2T1_3;
reg ctl_reg_sys_hilo_pla30pla13M2T2_4;
reg ctl_reg_sys_hilo_pla30pla13M2T3_6;
reg ctl_reg_sys_hilo_pla30pla13M3T1_3;
reg ctl_reg_sys_hilo_pla30pla13M3T2_4;
reg ctl_reg_sys_hilo_pla30pla13M3T3_5;
reg ctl_reg_sys_hilo_pla30pla13M3T3_10;
reg ctl_reg_gp_sel_pla30pla13M4T1_3;
reg ctl_reg_gp_hilo_pla30pla13M4T1_4;
reg ctl_reg_sys_hilo_pla30pla13M4T2_4;
reg ctl_reg_sys_hilo_pla30pla13M4T3_5;
reg ctl_reg_gp_sel_pla30pla13M5T1_3;
reg ctl_reg_gp_hilo_pla30pla13M5T1_4;
reg ctl_reg_sys_hilo_pla30pla13M5T2_4;
reg ctl_reg_sys_hilo_pla30npla13M2T1_3;
reg ctl_reg_sys_hilo_pla30npla13M2T2_4;
reg ctl_reg_sys_hilo_pla30npla13M2T3_6;
reg ctl_reg_sys_hilo_pla30npla13M3T1_3;
reg ctl_reg_sys_hilo_pla30npla13M3T2_4;
reg ctl_reg_sys_hilo_pla30npla13M3T3_6;
reg ctl_reg_sys_hilo_pla30npla13M4T1_3;
reg ctl_reg_sys_hilo_pla30npla13M4T2_4;
reg ctl_reg_gp_sel_pla30npla13M4T3_5;
reg ctl_reg_gp_hilo_pla30npla13M4T3_6;
reg ctl_reg_sys_hilo_pla30npla13M5T1_3;
reg ctl_reg_sys_hilo_pla30npla13M5T2_4;
reg ctl_reg_gp_sel_pla30npla13M5T3_4;
reg ctl_reg_gp_hilo_pla30npla13M5T3_5;
reg ctl_reg_sys_hilo_pla31pla33M2T1_3;
reg ctl_reg_sys_hilo_pla31pla33M2T2_4;
reg ctl_reg_sys_hilo_pla31pla33M2T3_6;
reg ctl_reg_sys_hilo_pla31pla33M3T1_3;
reg ctl_reg_sys_hilo_pla31pla33M3T2_4;
reg ctl_reg_sys_hilo_pla31pla33M3T3_5;
reg ctl_reg_sys_hilo_pla31pla33M3T3_10;
reg ctl_reg_gp_sel_pla31pla33M4T1_3;
reg ctl_reg_gp_hilo_pla31pla33M4T1_4;
reg ctl_reg_sys_hilo_pla31pla33M4T2_4;
reg ctl_reg_sys_hilo_pla31pla33M4T3_5;
reg ctl_reg_gp_sel_pla31pla33M5T1_3;
reg ctl_reg_gp_hilo_pla31pla33M5T1_4;
reg ctl_reg_sys_hilo_pla31pla33M5T2_4;
reg ctl_reg_sys_hilo_pla31npla33M2T1_3;
reg ctl_reg_sys_hilo_pla31npla33M2T2_4;
reg ctl_reg_sys_hilo_pla31npla33M2T3_6;
reg ctl_reg_sys_hilo_pla31npla33M3T1_3;
reg ctl_reg_sys_hilo_pla31npla33M3T2_4;
reg ctl_reg_sys_hilo_pla31npla33M3T3_6;
reg ctl_reg_sys_hilo_pla31npla33M4T1_3;
reg ctl_reg_sys_hilo_pla31npla33M4T2_4;
reg ctl_reg_gp_sel_pla31npla33M4T3_5;
reg ctl_reg_gp_hilo_pla31npla33M4T3_6;
reg ctl_reg_sys_hilo_pla31npla33M5T1_3;
reg ctl_reg_sys_hilo_pla31npla33M5T2_4;
reg ctl_reg_gp_sel_pla31npla33M5T3_4;
reg ctl_reg_gp_hilo_pla31npla33M5T3_5;
reg ctl_reg_gp_sel_pla5M1T4_2;
reg ctl_reg_gp_hilo_pla5M1T4_3;
reg ctl_reg_gp_sel_pla5M1T5_2;
reg ctl_reg_gp_hilo_pla5M1T5_3;
reg ctl_reg_gp_sel_pla23pla16M1T5_4;
reg ctl_reg_gp_hilo_pla23pla16M1T5_5;
reg ctl_reg_gp_sel_pla23pla16M2T1_5;
reg ctl_reg_gp_hilo_pla23pla16M2T1_6;
reg ctl_reg_gp_sel_pla23pla16M2T2_3;
reg ctl_reg_gp_hilo_pla23pla16M2T2_4;
reg ctl_reg_gp_sel_pla23pla16M2T3_5;
reg ctl_reg_gp_hilo_pla23pla16M2T3_6;
reg ctl_reg_gp_sel_pla23pla16M3T1_5;
reg ctl_reg_gp_hilo_pla23pla16M3T1_6;
reg ctl_reg_gp_sel_pla23pla16M3T2_3;
reg ctl_reg_gp_hilo_pla23pla16M3T2_4;
reg ctl_reg_gp_sel_pla23npla16M2T1_3;
reg ctl_reg_gp_hilo_pla23npla16M2T1_4;
reg ctl_reg_gp_sel_pla23npla16M2T2_3;
reg ctl_reg_gp_hilo_pla23npla16M2T2_4;
reg ctl_reg_gp_sel_pla23npla16M2T3_5;
reg ctl_reg_gp_hilo_pla23npla16M2T3_6;
reg ctl_reg_gp_sel_pla23npla16M3T1_3;
reg ctl_reg_gp_hilo_pla23npla16M3T1_4;
reg ctl_reg_gp_sel_pla23npla16M3T2_3;
reg ctl_reg_gp_hilo_pla23npla16M3T2_4;
reg ctl_reg_gp_sel_pla23npla16M3T3_4;
reg ctl_reg_gp_hilo_pla23npla16M3T3_5;
reg ctl_reg_gp_sel_pla10M2T1_3;
reg ctl_reg_gp_hilo_pla10M2T1_4;
reg ctl_reg_gp_sel_pla10M2T2_3;
reg ctl_reg_gp_hilo_pla10M2T2_4;
reg ctl_reg_sys_hilo_pla10M2T3_6;
reg ctl_reg_gp_sel_pla10M3T1_3;
reg ctl_reg_gp_hilo_pla10M3T1_4;
reg ctl_reg_gp_sel_pla10M3T2_3;
reg ctl_reg_gp_hilo_pla10M3T2_4;
reg ctl_reg_sys_hilo_pla10M3T3_4;
reg ctl_reg_gp_sel_pla10M3T4_4;
reg ctl_reg_gp_hilo_pla10M3T4_5;
reg ctl_reg_gp_sel_pla10M4T1_5;
reg ctl_reg_gp_hilo_pla10M4T1_6;
reg ctl_reg_gp_sel_pla10M4T2_3;
reg ctl_reg_gp_hilo_pla10M4T2_4;
reg ctl_reg_gp_sel_pla10M4T3_5;
reg ctl_reg_gp_hilo_pla10M4T3_6;
reg ctl_reg_gp_sel_pla10M5T1_5;
reg ctl_reg_gp_hilo_pla10M5T1_6;
reg ctl_reg_gp_sel_pla10M5T2_3;
reg ctl_reg_gp_hilo_pla10M5T2_4;
reg ctl_reg_sys_hilo_pla10M5T3_3;
reg ctl_reg_gp_sel_pla10M5T4_2;
reg ctl_reg_gp_hilo_pla10M5T4_3;
reg ctl_pf_sel_pla12M1T1_12;
reg ctl_reg_gp_sel_pla12M1T2_2;
reg ctl_reg_gp_hilo_pla12M1T2_3;
reg ctl_reg_gp_sel_pla12M1T3_1;
reg ctl_reg_gp_hilo_pla12M1T3_2;
reg ctl_reg_gp_sel_pla12M2T1_2;
reg ctl_reg_gp_hilo_pla12M2T1_3;
reg ctl_reg_gp_sel_pla12M2T2_3;
reg ctl_reg_gp_hilo_pla12M2T2_4;
reg ctl_reg_gp_sel_pla12M3T1_2;
reg ctl_reg_gp_hilo_pla12M3T1_3;
reg ctl_reg_gp_sel_pla12M3T2_3;
reg ctl_reg_gp_hilo_pla12M3T2_4;
reg ctl_reg_gp_sel_pla12M3T3_2;
reg ctl_reg_gp_hilo_pla12M3T3_3;
reg ctl_reg_gp_sel_pla12M3T4_2;
reg ctl_reg_gp_hilo_pla12M3T4_3;
reg ctl_reg_sys_hilo_pla12M4T1_2;
reg ctl_reg_sys_hilo_pla12M4T2_3;
reg ctl_reg_sys_hilo_pla12M4T3_2;
reg ctl_reg_sys_hilo_pla12M4T4_3;
reg ctl_pf_sel_pla11M1T1_11;
reg ctl_reg_gp_sel_pla11M1T2_2;
reg ctl_reg_gp_hilo_pla11M1T2_3;
reg ctl_reg_gp_sel_pla11M1T3_1;
reg ctl_reg_gp_hilo_pla11M1T3_2;
reg ctl_reg_gp_sel_pla11M2T1_2;
reg ctl_reg_gp_hilo_pla11M2T1_3;
reg ctl_reg_gp_sel_pla11M2T2_3;
reg ctl_reg_gp_hilo_pla11M2T2_4;
reg ctl_reg_gp_sel_pla11M3T3_1;
reg ctl_reg_gp_hilo_pla11M3T3_2;
reg ctl_reg_gp_sel_pla11M3T4_2;
reg ctl_reg_gp_hilo_pla11M3T4_3;
reg ctl_reg_sys_hilo_pla11M4T1_2;
reg ctl_reg_sys_hilo_pla11M4T2_3;
reg ctl_reg_sys_hilo_pla11M4T3_2;
reg ctl_reg_sys_hilo_pla11M4T4_3;
reg ctl_reg_gp_sel_pla65npla52M1T2_2;
reg ctl_reg_gp_hilo_pla65npla52M1T2_3;
reg ctl_reg_gp_sel_pla65npla52M1T3_1;
reg ctl_reg_gp_hilo_pla65npla52M1T3_2;
reg ctl_reg_gp_sel_pla65npla52M1T4_3;
reg ctl_reg_gp_hilo_pla65npla52M1T4_4;
reg ctl_reg_gp_sel_pla64M1T2_2;
reg ctl_reg_gp_hilo_pla64M1T2_3;
reg ctl_reg_gp_sel_pla64M1T3_1;
reg ctl_reg_gp_hilo_pla64M1T3_2;
reg ctl_reg_gp_sel_pla64M1T4_4;
reg ctl_reg_gp_hilo_pla64M1T4_5;
reg ctl_reg_sys_hilo_pla64M2T1_3;
reg ctl_reg_sys_hilo_pla64M2T2_4;
reg ctl_reg_gp_sel_use_ixiypla52M1T3_1;
reg ctl_reg_gp_hilo_use_ixiypla52M1T3_2;
reg ctl_reg_sys_hilo_use_ixiypla52M2T1_3;
reg ctl_reg_sys_hilo_use_ixiypla52M2T2_4;
reg ctl_reg_gp_sel_nuse_ixiypla52M1T2_2;
reg ctl_reg_gp_hilo_nuse_ixiypla52M1T2_3;
reg ctl_reg_gp_sel_nuse_ixiypla52M1T3_1;
reg ctl_reg_gp_hilo_nuse_ixiypla52M1T3_2;
reg ctl_reg_gp_sel_nuse_ixiypla52M2T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla52M2T1_3;
reg ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4;
reg ctl_reg_gp_sel_nuse_ixiypla52M4T2_2;
reg ctl_reg_gp_hilo_nuse_ixiypla52M4T2_3;
reg ctl_reg_gp_sel_pla66npla53M1T1_2;
reg ctl_reg_gp_hilo_pla66npla53M1T1_3;
reg ctl_pf_sel_pla66npla53M1T1_15;
reg ctl_reg_gp_sel_pla66npla53M1T2_2;
reg ctl_reg_gp_hilo_pla66npla53M1T2_3;
reg ctl_reg_gp_sel_pla66npla53M1T3_1;
reg ctl_reg_gp_hilo_pla66npla53M1T3_2;
reg ctl_reg_gp_sel_pla66npla53M1T4nop4op5nop3_1;
reg ctl_reg_gp_hilo_pla66npla53M1T4nop4op5nop3_2;
reg ctl_reg_gp_sel_use_ixiypla53M1T3_1;
reg ctl_reg_gp_hilo_use_ixiypla53M1T3_2;
reg ctl_reg_sys_hilo_use_ixiypla53M2T1_3;
reg ctl_reg_sys_hilo_use_ixiypla53M2T2_4;
reg ctl_reg_gp_sel_nuse_ixiypla53M1T2_2;
reg ctl_reg_gp_hilo_nuse_ixiypla53M1T2_3;
reg ctl_reg_gp_sel_nuse_ixiypla53M1T3_1;
reg ctl_reg_gp_hilo_nuse_ixiypla53M1T3_2;
reg ctl_reg_gp_sel_nuse_ixiypla53M2T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla53M2T1_3;
reg ctl_pf_sel_nuse_ixiypla53M2T4_14;
reg ctl_pf_sel_nuse_ixiypla53M4T4_14;
reg ctl_reg_gp_sel_pla69M1T2_2;
reg ctl_reg_gp_hilo_pla69M1T2_3;
reg ctl_reg_gp_sel_pla69M1T3_1;
reg ctl_reg_gp_hilo_pla69M1T3_2;
reg ctl_reg_gp_sel_pla69M1T4_3;
reg ctl_reg_gp_hilo_pla69M1T4_4;
reg ctl_reg_gp_sel_pla69M2T1_1;
reg ctl_reg_gp_hilo_pla69M2T1_2;
reg ctl_reg_sys_hilo_pla69M2T2_3;
reg ctl_reg_gp_sel_pla69M2T3_1;
reg ctl_reg_gp_hilo_pla69M2T3_2;
reg ctl_reg_gp_sel_pla69M2T4_2;
reg ctl_reg_gp_hilo_pla69M2T4_3;
reg ctl_reg_sys_hilo_pla69M3T1_2;
reg ctl_reg_sys_hilo_pla69M3T1_7;
reg ctl_reg_gp_sel_pla69M3T2_2;
reg ctl_reg_gp_hilo_pla69M3T2_3;
reg ctl_reg_gp_sel_op3pla68M1T2_2;
reg ctl_reg_gp_hilo_op3pla68M1T2_3;
reg ctl_reg_gp_sel_op3pla68M1T3_1;
reg ctl_reg_gp_hilo_op3pla68M1T3_2;
reg ctl_reg_gp_sel_op3pla68M1T4_3;
reg ctl_reg_gp_hilo_op3pla68M1T4_4;
reg ctl_reg_gp_sel_op3pla68M2T1_1;
reg ctl_reg_gp_hilo_op3pla68M2T1_2;
reg ctl_reg_sys_hilo_op3pla68M2T2_3;
reg ctl_reg_gp_sel_op3pla68M2T3_1;
reg ctl_reg_gp_hilo_op3pla68M2T3_2;
reg ctl_reg_gp_sel_op3pla68M2T4_2;
reg ctl_reg_gp_hilo_op3pla68M2T4_3;
reg ctl_reg_sys_hilo_op3pla68M3T1_2;
reg ctl_reg_sys_hilo_op3pla68M3T1_7;
reg ctl_pf_sel_op3pla68M3T1_18;
reg ctl_reg_gp_sel_op3pla68M3T2_2;
reg ctl_reg_gp_hilo_op3pla68M3T2_3;
reg ctl_reg_gp_sel_nop3pla68M1T2_2;
reg ctl_reg_gp_hilo_nop3pla68M1T2_3;
reg ctl_reg_gp_sel_nop3pla68M1T3_1;
reg ctl_reg_gp_hilo_nop3pla68M1T3_2;
reg ctl_reg_gp_sel_nop3pla68M1T4_3;
reg ctl_reg_gp_hilo_nop3pla68M1T4_4;
reg ctl_reg_gp_sel_nop3pla68M2T1_1;
reg ctl_reg_gp_hilo_nop3pla68M2T1_2;
reg ctl_reg_sys_hilo_nop3pla68M2T2_3;
reg ctl_reg_gp_sel_nop3pla68M2T3_1;
reg ctl_reg_gp_hilo_nop3pla68M2T3_2;
reg ctl_reg_gp_sel_nop3pla68M2T4_2;
reg ctl_reg_gp_hilo_nop3pla68M2T4_3;
reg ctl_reg_sys_hilo_nop3pla68M3T1_2;
reg ctl_reg_sys_hilo_nop3pla68M3T1_7;
reg ctl_pf_sel_nop3pla68M3T1_20;
reg ctl_reg_gp_sel_nop3pla68M3T2_2;
reg ctl_reg_gp_hilo_nop3pla68M3T2_3;
reg ctl_reg_gp_sel_pla9M1T4_2;
reg ctl_reg_gp_hilo_pla9M1T4_3;
reg ctl_reg_gp_sel_pla9M1T5_2;
reg ctl_reg_gp_hilo_pla9M1T5_3;
reg ctl_reg_gp_sel_pla77M1T1_2;
reg ctl_reg_gp_hilo_pla77M1T1_3;
reg ctl_pf_sel_pla77M1T1_14;
reg ctl_reg_gp_sel_pla77M1T2_2;
reg ctl_reg_gp_hilo_pla77M1T2_3;
reg ctl_reg_gp_sel_pla77M1T3_1;
reg ctl_reg_gp_hilo_pla77M1T3_2;
reg ctl_reg_gp_sel_pla81M1T1_2;
reg ctl_reg_gp_hilo_pla81M1T1_3;
reg ctl_reg_gp_sel_pla81M1T2_2;
reg ctl_reg_gp_hilo_pla81M1T2_3;
reg ctl_reg_gp_sel_pla81M1T3_1;
reg ctl_reg_gp_hilo_pla81M1T3_2;
reg ctl_reg_gp_sel_pla82M1T1_2;
reg ctl_reg_gp_hilo_pla82M1T1_3;
reg ctl_pf_sel_pla82M1T1_16;
reg ctl_reg_gp_sel_pla82M1T2_2;
reg ctl_reg_gp_hilo_pla82M1T2_3;
reg ctl_reg_gp_sel_pla82M1T3_1;
reg ctl_reg_gp_hilo_pla82M1T3_2;
reg ctl_reg_gp_sel_pla89M1T2_2;
reg ctl_reg_gp_hilo_pla89M1T2_3;
reg ctl_reg_gp_sel_pla89M1T3_1;
reg ctl_reg_gp_hilo_pla89M1T3_2;
reg ctl_reg_gp_sel_pla92M1T2_2;
reg ctl_reg_gp_hilo_pla92M1T2_3;
reg ctl_reg_gp_sel_pla92M1T3_1;
reg ctl_reg_gp_hilo_pla92M1T3_2;
reg ctl_reg_gp_sel_pla25M1T1_2;
reg ctl_reg_gp_hilo_pla25M1T1_3;
reg ctl_reg_gp_sel_pla25M1T2_2;
reg ctl_reg_gp_hilo_pla25M1T2_3;
reg ctl_reg_gp_sel_pla25M1T3_1;
reg ctl_reg_gp_hilo_pla25M1T3_2;
reg ctl_reg_gp_sel_pla25M1T4_3;
reg ctl_reg_gp_hilo_pla25M1T4_4;
reg ctl_reg_gp_sel_nuse_ixiypla70npla55M1T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T1_3;
reg ctl_pf_sel_nuse_ixiypla70npla55M1T1_20;
reg ctl_reg_gp_sel_nuse_ixiypla70npla55M1T2_2;
reg ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T2_3;
reg ctl_reg_gp_sel_nuse_ixiypla70npla55M1T3_1;
reg ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T3_2;
reg ctl_reg_gp_sel_nuse_ixiypla70npla55M1T4_3;
reg ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T4_4;
reg ctl_reg_sys_hilo_nuse_ixiypla70npla55M4T1_3;
reg ctl_pf_sel_nuse_ixiypla70npla55M5T1_19;
reg ctl_reg_gp_sel_nuse_ixiypla70pla55M1T2_2;
reg ctl_reg_gp_hilo_nuse_ixiypla70pla55M1T2_3;
reg ctl_reg_gp_sel_nuse_ixiypla70pla55M1T3_1;
reg ctl_reg_gp_hilo_nuse_ixiypla70pla55M1T3_2;
reg ctl_reg_gp_sel_nuse_ixiypla70pla55M2T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla70pla55M2T1_3;
reg ctl_pf_sel_nuse_ixiypla70pla55M3T1_19;
reg ctl_reg_sys_hilo_nuse_ixiypla70pla55M4T1_3;
reg ctl_pf_sel_nuse_ixiypla70pla55M5T1_19;
reg ctl_reg_gp_sel_pla15op3M1T1_2;
reg ctl_reg_gp_hilo_pla15op3M1T1_3;
reg ctl_pf_sel_pla15op3M1T1_18;
reg ctl_reg_gp_sel_pla15op3M1T2_2;
reg ctl_reg_gp_hilo_pla15op3M1T2_3;
reg ctl_reg_gp_sel_pla15op3M1T3_1;
reg ctl_reg_gp_hilo_pla15op3M1T3_2;
reg ctl_reg_gp_sel_pla15op3M2T1_2;
reg ctl_reg_gp_hilo_pla15op3M2T1_3;
reg ctl_reg_sys_hilo_pla15op3M2T2_4;
reg ctl_reg_gp_sel_pla15nop3M1T1_2;
reg ctl_reg_gp_hilo_pla15nop3M1T1_3;
reg ctl_pf_sel_pla15nop3M1T1_18;
reg ctl_reg_gp_sel_pla15nop3M1T2_2;
reg ctl_reg_gp_hilo_pla15nop3M1T2_3;
reg ctl_reg_gp_sel_pla15nop3M1T3_1;
reg ctl_reg_gp_hilo_pla15nop3M1T3_2;
reg ctl_reg_gp_sel_pla15nop3M2T1_2;
reg ctl_reg_gp_hilo_pla15nop3M2T1_3;
reg ctl_reg_sys_hilo_pla15nop3M2T2_4;
reg ctl_reg_gp_sel_pla15nop3M3T3_1;
reg ctl_reg_gp_hilo_pla15nop3M3T3_2;
reg ctl_pf_sel_nuse_ixiypla72npla55M1T1_10;
reg ctl_reg_gp_sel_nuse_ixiypla72npla55M1T2_2;
reg ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T2_3;
reg ctl_reg_gp_sel_nuse_ixiypla72npla55M1T3_1;
reg ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T3_2;
reg ctl_reg_gp_sel_nuse_ixiypla72npla55M1T4_3;
reg ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4;
reg ctl_pf_sel_nuse_ixiypla72pla55M1T1_10;
reg ctl_reg_gp_sel_nuse_ixiypla72pla55M1T2_2;
reg ctl_reg_gp_hilo_nuse_ixiypla72pla55M1T2_3;
reg ctl_reg_gp_sel_nuse_ixiypla72pla55M1T3_1;
reg ctl_reg_gp_hilo_nuse_ixiypla72pla55M1T3_2;
reg ctl_reg_gp_sel_nuse_ixiypla72pla55M2T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla72pla55M2T1_3;
reg ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3;
reg ctl_reg_sys_hilo_nuse_ixiypla72pla55M4T1_3;
reg ctl_reg_gp_sel_nuse_ixiypla74npla55M1T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T1_3;
reg ctl_reg_gp_sel_nuse_ixiypla74npla55M1T3_1;
reg ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T3_2;
reg ctl_reg_gp_sel_nuse_ixiypla74npla55M1T4_3;
reg ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T4_4;
reg ctl_reg_sys_hilo_nuse_ixiypla74npla55M4T1_3;
reg ctl_reg_gp_sel_nuse_ixiypla74pla55M1T3_1;
reg ctl_reg_gp_hilo_nuse_ixiypla74pla55M1T3_2;
reg ctl_reg_gp_sel_nuse_ixiypla74pla55M2T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla74pla55M2T1_3;
reg ctl_reg_sys_hilo_nuse_ixiypla74pla55M4T1_3;
reg ctl_reg_gp_sel_nuse_ixiypla73npla55M1T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T1_3;
reg ctl_reg_gp_sel_nuse_ixiypla73npla55M1T3_1;
reg ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T3_2;
reg ctl_reg_gp_sel_nuse_ixiypla73npla55M1T4_3;
reg ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T4_4;
reg ctl_reg_sys_hilo_nuse_ixiypla73npla55M4T1_3;
reg ctl_reg_gp_sel_nuse_ixiypla73pla55M1T3_1;
reg ctl_reg_gp_hilo_nuse_ixiypla73pla55M1T3_2;
reg ctl_reg_gp_sel_nuse_ixiypla73pla55M2T1_2;
reg ctl_reg_gp_hilo_nuse_ixiypla73pla55M2T1_3;
reg ctl_reg_sys_hilo_nuse_ixiypla73pla55M4T1_3;
reg ctl_reg_gp_sel_pla37npla28M1T1_2;
reg ctl_reg_gp_hilo_pla37npla28M1T1_3;
reg ctl_reg_sys_hilo_pla37npla28M2T1_3;
reg ctl_reg_sys_hilo_pla37npla28M2T2_4;
reg ctl_reg_gp_sel_pla37npla28M3T1_2;
reg ctl_reg_gp_hilo_pla37npla28M3T1_3;
reg ctl_reg_gp_sel_pla27npla34M1T1_2;
reg ctl_reg_gp_hilo_pla27npla34M1T1_3;
reg ctl_pf_sel_pla27npla34M1T1_20;
reg ctl_reg_gp_sel_pla27npla34M1T2_2;
reg ctl_reg_gp_hilo_pla27npla34M1T2_3;
reg ctl_reg_gp_sel_pla27npla34M1T3_1;
reg ctl_reg_gp_hilo_pla27npla34M1T3_2;
reg ctl_reg_gp_sel_pla27npla34M2T1_2;
reg ctl_reg_gp_hilo_pla27npla34M2T1_3;
reg ctl_reg_sys_hilo_pla37pla28M2T1_3;
reg ctl_reg_sys_hilo_pla37pla28M2T2_4;
reg ctl_reg_gp_sel_pla37pla28M2T3_4;
reg ctl_reg_gp_hilo_pla37pla28M2T3_5;
reg ctl_reg_gp_sel_pla37pla28M3T1_3;
reg ctl_reg_gp_hilo_pla37pla28M3T1_4;
reg ctl_reg_gp_sel_pla27pla34M1T4nop4op5nop3_1;
reg ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2;
reg ctl_reg_gp_sel_pla27pla34M2T1_2;
reg ctl_reg_gp_hilo_pla27pla34M2T1_3;
reg ctl_pf_sel_pla91pla21M1T1_8;
reg ctl_reg_gp_sel_pla91pla21M1T2_2;
reg ctl_reg_gp_hilo_pla91pla21M1T2_3;
reg ctl_reg_gp_sel_pla91pla21M1T3_1;
reg ctl_reg_gp_hilo_pla91pla21M1T3_2;
reg ctl_reg_gp_sel_pla91pla21M2T1_2;
reg ctl_reg_gp_hilo_pla91pla21M2T1_3;
reg ctl_reg_gp_sel_pla91pla21M2T2_2;
reg ctl_reg_gp_hilo_pla91pla21M2T2_3;
reg ctl_reg_gp_sel_pla91pla21M2T3_3;
reg ctl_reg_gp_hilo_pla91pla21M2T3_4;
reg ctl_reg_gp_sel_pla91pla21M3T1_2;
reg ctl_reg_gp_hilo_pla91pla21M3T1_3;
reg ctl_reg_gp_sel_pla91pla21M3T2_3;
reg ctl_reg_gp_hilo_pla91pla21M3T2_4;
reg ctl_reg_sys_hilo_pla91pla21M4T1_2;
reg ctl_reg_sys_hilo_pla91pla21M4T2_3;
reg ctl_reg_sys_hilo_pla91pla21M4T3_2;
reg ctl_reg_sys_hilo_pla91pla21M4T4_3;
reg ctl_pf_sel_pla91pla20M1T1_9;
reg ctl_reg_gp_sel_pla91pla20M1T2_2;
reg ctl_reg_gp_hilo_pla91pla20M1T2_3;
reg ctl_reg_gp_sel_pla91pla20M1T3_1;
reg ctl_reg_gp_hilo_pla91pla20M1T3_2;
reg ctl_reg_gp_sel_pla91pla20M1T4_2;
reg ctl_reg_gp_hilo_pla91pla20M1T4_3;
reg ctl_reg_gp_sel_pla91pla20M1T5_4;
reg ctl_reg_gp_hilo_pla91pla20M1T5_5;
reg ctl_reg_gp_sel_pla91pla20M2T1_2;
reg ctl_reg_gp_hilo_pla91pla20M2T1_3;
reg ctl_reg_gp_sel_pla91pla20M2T2_3;
reg ctl_reg_gp_hilo_pla91pla20M2T2_4;
reg ctl_reg_gp_sel_pla91pla20M2T3_4;
reg ctl_reg_gp_hilo_pla91pla20M2T3_5;
reg ctl_reg_gp_sel_pla91pla20M3T1_2;
reg ctl_reg_gp_hilo_pla91pla20M3T1_3;
reg ctl_reg_sys_hilo_pla91pla20M4T1_2;
reg ctl_reg_sys_hilo_pla91pla20M4T2_3;
reg ctl_reg_sys_hilo_pla91pla20M4T3_2;
reg ctl_reg_sys_hilo_pla91pla20M4T4_3;
reg ctl_reg_sys_hilo_pla29M2T1_3;
reg ctl_reg_sys_hilo_pla29M2T2_4;
reg ctl_reg_sys_hilo_pla29M2T3_6;
reg ctl_reg_sys_hilo_pla29M3T1_3;
reg ctl_reg_sys_hilo_pla29M3T2_4;
reg ctl_reg_sys_hilo_pla29M3T3_4;
reg ctl_reg_sys_hilo_pla29M3T3_9;
reg ctl_reg_gp_sel_pla43M1T3_1;
reg ctl_reg_gp_hilo_pla43M1T3_2;
reg ctl_reg_sys_hilo_pla43M2T1_3;
reg ctl_reg_sys_hilo_pla43M2T2_4;
reg ctl_reg_sys_hilo_pla43M2T3_6;
reg ctl_reg_sys_hilo_pla43M3T1_3;
reg ctl_reg_sys_hilo_pla43M3T2_4;
reg ctl_reg_sys_hilo_pla43M3T3_5;
reg ctl_reg_sys_hilo_pla43M3T3_10;
reg ctl_reg_gp_sel_pla47M1T3_1;
reg ctl_reg_gp_hilo_pla47M1T3_2;
reg ctl_reg_sys_hilo_pla47M2T1_3;
reg ctl_reg_sys_hilo_pla47M2T2_4;
reg ctl_reg_sys_hilo_pla47M3T2_2;
reg ctl_reg_sys_hilo_pla47M3T3_3;
reg ctl_reg_sys_hilo_pla47M3T4_2;
reg ctl_reg_sys_hilo_pla47M3T5_3;
reg ctl_reg_sys_hilo_pla47M3T5_8;
reg ctl_reg_gp_sel_pla48M1T3_1;
reg ctl_reg_gp_hilo_pla48M1T3_2;
reg ctl_reg_sys_hilo_pla48M2T1_3;
reg ctl_reg_sys_hilo_pla48M2T2_4;
reg ctl_reg_sys_hilo_pla48M3T2_2;
reg ctl_reg_sys_hilo_pla48M3T3_3;
reg ctl_reg_sys_hilo_pla48M3T4_2;
reg ctl_reg_sys_hilo_pla48M3T5_3;
reg ctl_reg_sys_hilo_pla48M3T5_8;
reg ctl_reg_gp_sel_pla6M1T4_3;
reg ctl_reg_gp_hilo_pla6M1T4_4;
reg ctl_reg_gp_sel_pla26M1T3_1;
reg ctl_reg_gp_hilo_pla26M1T3_2;
reg ctl_reg_gp_sel_pla26M1T4_2;
reg ctl_reg_gp_hilo_pla26M1T4_3;
reg ctl_reg_gp_sel_pla26M1T5_4;
reg ctl_reg_gp_hilo_pla26M1T5_5;
reg ctl_reg_sys_hilo_pla26M2T1_3;
reg ctl_reg_sys_hilo_pla26M2T2_4;
reg ctl_reg_sys_hilo_pla26M3T2_2;
reg ctl_reg_sys_hilo_pla26M3T3_3;
reg ctl_reg_sys_hilo_pla26M3T4_2;
reg ctl_reg_sys_hilo_pla26M3T5_3;
reg ctl_reg_sys_hilo_pla26M3T5_8;
reg ctl_reg_sys_hilo_pla24M2T1_3;
reg ctl_reg_sys_hilo_pla24M2T2_4;
reg ctl_reg_sys_hilo_pla24M2T3_6;
reg ctl_reg_sys_hilo_pla24M3T1_3;
reg ctl_reg_sys_hilo_pla24M3T2_4;
reg ctl_reg_sys_hilo_pla24M3T3_4;
reg ctl_reg_gp_sel_pla24M3T4_4;
reg ctl_reg_gp_hilo_pla24M3T4_5;
reg ctl_reg_sys_hilo_pla24M4T1_6;
reg ctl_reg_gp_sel_pla24M4T2_3;
reg ctl_reg_gp_hilo_pla24M4T2_4;
reg ctl_reg_gp_sel_pla24M4T3_5;
reg ctl_reg_gp_hilo_pla24M4T3_6;
reg ctl_reg_sys_hilo_pla24M5T1_6;
reg ctl_reg_gp_sel_pla24M5T2_3;
reg ctl_reg_gp_hilo_pla24M5T2_4;
reg ctl_reg_sys_hilo_pla24M5T3_4;
reg ctl_reg_gp_sel_pla42M1T3_1;
reg ctl_reg_gp_hilo_pla42M1T3_2;
reg ctl_reg_sys_hilo_pla42M2T1_3;
reg ctl_reg_sys_hilo_pla42M2T2_4;
reg ctl_reg_sys_hilo_pla42M2T3_6;
reg ctl_reg_sys_hilo_pla42M3T1_3;
reg ctl_reg_sys_hilo_pla42M3T2_4;
reg ctl_reg_sys_hilo_pla42M3T3_6;
reg ctl_reg_gp_sel_pla42M3T4_4;
reg ctl_reg_gp_hilo_pla42M3T4_5;
reg ctl_reg_sys_hilo_pla42M4T1_6;
reg ctl_reg_gp_sel_pla42M4T2_3;
reg ctl_reg_gp_hilo_pla42M4T2_4;
reg ctl_reg_gp_sel_pla42M4T3_5;
reg ctl_reg_gp_hilo_pla42M4T3_6;
reg ctl_reg_sys_hilo_pla42M5T1_6;
reg ctl_reg_gp_sel_pla42M5T2_3;
reg ctl_reg_gp_hilo_pla42M5T2_4;
reg ctl_reg_sys_hilo_pla42M5T3_4;
reg ctl_reg_gp_sel_pla35M2T1_3;
reg ctl_reg_gp_hilo_pla35M2T1_4;
reg ctl_reg_gp_sel_pla35M2T2_3;
reg ctl_reg_gp_hilo_pla35M2T2_4;
reg ctl_reg_sys_hilo_pla35M2T3_6;
reg ctl_reg_gp_sel_pla35M3T1_3;
reg ctl_reg_gp_hilo_pla35M3T1_4;
reg ctl_reg_gp_sel_pla35M3T2_3;
reg ctl_reg_gp_hilo_pla35M3T2_4;
reg ctl_reg_sys_hilo_pla35M3T3_4;
reg ctl_reg_sys_hilo_pla35M3T3_9;
reg ctl_reg_gp_sel_pla45M1T3_1;
reg ctl_reg_gp_hilo_pla45M1T3_2;
reg ctl_reg_gp_sel_pla45M2T1_3;
reg ctl_reg_gp_hilo_pla45M2T1_4;
reg ctl_reg_gp_sel_pla45M2T2_3;
reg ctl_reg_gp_hilo_pla45M2T2_4;
reg ctl_reg_sys_hilo_pla45M2T3_6;
reg ctl_reg_gp_sel_pla45M3T1_3;
reg ctl_reg_gp_hilo_pla45M3T1_4;
reg ctl_reg_gp_sel_pla45M3T2_3;
reg ctl_reg_gp_hilo_pla45M3T2_4;
reg ctl_reg_sys_hilo_pla45M3T3_4;
reg ctl_reg_sys_hilo_pla45M3T3_9;
reg ctl_reg_gp_sel_pla46M2T1_3;
reg ctl_reg_gp_hilo_pla46M2T1_4;
reg ctl_reg_gp_sel_pla46M2T2_3;
reg ctl_reg_gp_hilo_pla46M2T2_4;
reg ctl_reg_sys_hilo_pla46M2T3_6;
reg ctl_reg_gp_sel_pla46M3T1_3;
reg ctl_reg_gp_hilo_pla46M3T1_4;
reg ctl_reg_gp_sel_pla46M3T2_3;
reg ctl_reg_gp_hilo_pla46M3T2_4;
reg ctl_reg_sys_hilo_pla46M3T3_4;
reg ctl_reg_sys_hilo_pla46M3T3_9;
reg ctl_reg_sys_hilo_pla56M1T3_3;
reg ctl_reg_gp_sel_pla56M1T5_4;
reg ctl_reg_gp_hilo_pla56M1T5_5;
reg ctl_reg_sys_hilo_pla56M2T1_6;
reg ctl_reg_gp_sel_pla56M2T2_3;
reg ctl_reg_gp_hilo_pla56M2T2_4;
reg ctl_reg_gp_sel_pla56M2T3_5;
reg ctl_reg_gp_hilo_pla56M2T3_6;
reg ctl_reg_sys_hilo_pla56M3T1_6;
reg ctl_reg_gp_sel_pla56M3T2_3;
reg ctl_reg_gp_hilo_pla56M3T2_4;
reg ctl_reg_sys_hilo_pla56M3T3_6;
reg ctl_reg_sys_hilo_pla56M4T1_3;
reg ctl_reg_sys_hilo_pla56M4T3_6;
reg ctl_reg_sys_hilo_pla56M5T1_3;
reg ctl_reg_sys_hilo_pla56M5T3_4;
reg ctl_reg_sys_hilo_pla56M5T3_9;
reg ctl_reg_gp_sel_pla49M1T3_1;
reg ctl_reg_gp_hilo_pla49M1T3_2;
reg ctl_reg_sys_hilo_pla49M2T1_3;
reg ctl_reg_sys_hilo_pla49M2T2_4;
reg ctl_reg_sys_hilo_pla49M3T1_3;
reg ctl_reg_sys_hilo_pla49M3T2_4;
reg ctl_pf_sel_pla76M1T1_2;
reg ctl_reg_gp_sel_pla78M1T1_2;
reg ctl_reg_gp_hilo_pla78M1T1_3;
reg ctl_pf_sel_pla78M1T1_8;
reg ctl_reg_gp_sel_pla79M1T1_2;
reg ctl_reg_gp_hilo_pla79M1T1_3;
reg ctl_pf_sel_pla79M1T1_8;
reg ctl_reg_gp_sel_pla80M1T1_2;
reg ctl_reg_gp_hilo_pla80M1T1_3;
reg ctl_pf_sel_pla80M1T1_8;
reg ctl_reg_gp_sel_pla84M1T1_2;
reg ctl_reg_gp_hilo_pla84M1T1_3;
reg ctl_pf_sel_pla84M1T1_8;
reg ctl_reg_gp_sel_pla85M1T1_2;
reg ctl_reg_gp_hilo_pla85M1T1_3;
reg ctl_pf_sel_pla85M1T1_8;
reg ctl_reg_gp_sel_pla86M1T1_2;
reg ctl_reg_gp_hilo_pla86M1T1_3;
reg ctl_pf_sel_pla86M1T1_8;
reg ctl_reg_gp_sel_pla88M1T1_2;
reg ctl_reg_gp_hilo_pla88M1T1_3;
reg ctl_pf_sel_pla88M1T1_8;
reg ctl_reg_gp_sel_ixy_dT2_1;
reg ctl_reg_gp_hilo_ixy_dT2_2;
reg ctl_reg_sys_hilo_ixy_dT3_3;
reg ctl_reg_gp_sel_ixy_dT4_1;
reg ctl_reg_gp_hilo_ixy_dT4_2;
reg ctl_reg_sys_hilo_ixy_dT5_2;
reg ctl_reg_sys_hilo_ixy_dT5_7;
reg ctl_reg_sys_hilo_1M1T1_3;
reg ctl_reg_sys_hilo_1M1T2_2;
reg ctl_reg_sys_hilo_1M1T3_3;
reg ctl_reg_sys_hilo_setM1_2;
/Timings.xlsm Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/genref.py
1,4 → 1,4
#!/usr/bin/env python
#!/usr/bin/env python3
#
# This script reads and parses selected Verilog and SystemVerilog modules
# and generates a set of Verilog include files for the control block.
22,9 → 22,9
with open('../top-level-files.txt') as f:
files = f.read().splitlines()
 
# Create 2 files that should be included in the execution engine block:
# 1. A module arguments section
# 2. A file containing the code to initialize control wires to zero
# Create 2 files that should be included by the execution engine:
# 1. A file listing all control signals
# 2. A file containing statements initializing control signals to zero
with open('exec_module.vh', 'w') as file1, open('exec_zero.vh', 'w') as file0:
file1.write("// Automatically generated by genref.py\n")
file0.write("// Automatically generated by genref.py\n")
39,25 → 39,23
info = line.split()
# input wire register case
if len(info)>2 and info[0]=="input" and info[1]=="wire" and info[2].startswith("ctl_"):
wires.append(info[2].translate(None, ';,'))
# input wire [1:0] bus case
wires.append(info[2].strip(';,'))
# input wire bus case (ex. "[1:0]")
if len(info)>3 and info[0]=="input" and info[1]=="wire" and info[2].startswith("[") and info[3].startswith("ctl_"):
wires.append(info[2] + " " + info[3].translate(None, ';,'))
wires.append(info[2] + " " + info[3].strip(';,'))
 
if len(wires)>0:
with open('exec_module.vh', 'a') as file1, open('exec_zero.vh', 'a') as file0:
print "MODULE: " + infile
print ("MODULE:", infile)
file0.write("\n// Module: " + infile + "\n")
file1.write("\n// Module: " + infile + "\n")
for wire in wires:
print " " + wire
file1.write("output logic " + wire + ",\n")
# To the exec include, write bus with the length field (if the wire is a bus)
# To the zero include, skip bus width field
print (" ", wire)
file1.write("output reg " + wire + ",\n")
if "[" in wire:
file0.write(wire.split()[1] + " = 0;\n")
else:
file0.write(wire + " = 0;\n")
file0.write(wire + " = 0;\n")
 
# Touch a file that includes 'exec_module.vh' and 'exec_zero.vh' to ensure it will recompile correctly
os.utime("execute.sv", None)
os.utime("execute.v", None)
/exec_zero.vh
74,10 → 74,10
ctl_flags_hf2_we = 0;
ctl_flags_nf_clr = 0;
ctl_alu_zero_16bit = 0;
ctl_flags_cf2_sel = 0;
ctl_flags_cf2_sel_shift = 0;
ctl_flags_cf2_sel_daa = 0;
 
// Module: registers/reg_file.v
ctl_sw_4d = 0;
ctl_sw_4u = 0;
ctl_reg_in_hi = 0;
ctl_reg_in_lo = 0;
97,6 → 97,7
ctl_reg_sys_we_lo = 0;
ctl_reg_sys_we_hi = 0;
ctl_reg_sys_we = 0;
ctl_sw_4d = 0;
ctl_reg_gp_hilo = 0;
ctl_reg_gp_sel = 0;
ctl_reg_sys_hilo = 0;
104,7 → 105,6
// Module: bus/address_latch.v
ctl_inc_cy = 0;
ctl_inc_dec = 0;
ctl_inc_zero = 0;
ctl_al_we = 0;
ctl_inc_limit6 = 0;
ctl_bus_inc_oe = 0;
114,9 → 114,8
// Module: bus/bus_control.v
ctl_bus_ff_oe = 0;
ctl_bus_zero_oe = 0;
ctl_bus_db_oe = 0;
 
// Module: bus/bus_switch.sv
// Module: bus/bus_switch.v
ctl_sw_1u = 0;
ctl_sw_1d = 0;
ctl_sw_2u = 0;
125,3 → 124,4
 
// Module: bus/data_pins.v
ctl_bus_db_we = 0;
ctl_bus_db_oe = 0;
/exec_matrix_compiled.vh
0,0 → 1,5812
// Automatically generated by gencompile.py
 
ctl_reg_gp_we = ctl_reg_gp_we | (pla[17]&~pla[50])&(M1&T1);
ctl_reg_gp_sel_pla17npla50M1T1_2 = (pla[17]&~pla[50])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla17npla50M1T1_2,ctl_reg_gp_sel_pla17npla50M1T1_2})&(op54);
ctl_reg_gp_hilo_pla17npla50M1T1_3 = (pla[17]&~pla[50])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla17npla50M1T1_3,ctl_reg_gp_hilo_pla17npla50M1T1_3})&({~rsel3,rsel3});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[17]&~pla[50])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[17]&~pla[50])&(M1&T1);
ctl_sw_2d = ctl_sw_2d | (pla[17]&~pla[50])&(M1&T1);
ctl_sw_1d = ctl_sw_1d | (pla[17]&~pla[50])&(M1&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[17]&~pla[50])&(M1&T1);
validPLA = validPLA | (pla[17]&~pla[50])&(M1&T4);
nextM = nextM | (pla[17]&~pla[50])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[17]&~pla[50])&(M1&T4);
fMRead = fMRead | (pla[17]&~pla[50])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[17]&~pla[50])&(M2&T1);
ctl_reg_sys_hilo_pla17npla50M2T1_3 = (pla[17]&~pla[50])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla17npla50M2T1_3,ctl_reg_sys_hilo_pla17npla50M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[17]&~pla[50])&(M2&T1);
fMRead = fMRead | (pla[17]&~pla[50])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[17]&~pla[50])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[17]&~pla[50])&(M2&T2);
ctl_reg_sys_hilo_pla17npla50M2T2_4 = (pla[17]&~pla[50])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla17npla50M2T2_4,ctl_reg_sys_hilo_pla17npla50M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[17]&~pla[50])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[17]&~pla[50])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[17]&~pla[50])&(M2&T2);
fMRead = fMRead | (pla[17]&~pla[50])&(M2&T3);
setM1 = setM1 | (pla[17]&~pla[50])&(M2&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[61]&~pla[58]&~pla[59])&(M1&T1);
ctl_reg_gp_sel_pla61npla58npla59M1T1_2 = (pla[61]&~pla[58]&~pla[59])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla61npla58npla59M1T1_2,ctl_reg_gp_sel_pla61npla58npla59M1T1_2})&(op54);
ctl_reg_gp_hilo_pla61npla58npla59M1T1_3 = (pla[61]&~pla[58]&~pla[59])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla61npla58npla59M1T1_3,ctl_reg_gp_hilo_pla61npla58npla59M1T1_3})&({~rsel3,rsel3});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[61]&~pla[58]&~pla[59])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[61]&~pla[58]&~pla[59])&(M1&T1);
ctl_sw_2u = ctl_sw_2u | (pla[61]&~pla[58]&~pla[59])&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (pla[61]&~pla[58]&~pla[59])&(M1&T1);
ctl_alu_op1_oe = ctl_alu_op1_oe | (pla[61]&~pla[58]&~pla[59])&(M1&T1);
validPLA = validPLA | (pla[61]&~pla[58]&~pla[59])&(M1&T4);
setM1 = setM1 | (pla[61]&~pla[58]&~pla[59])&(M1&T4);
ctl_reg_gp_sel_pla61npla58npla59M1T4_3 = (pla[61]&~pla[58]&~pla[59])&(M1&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla61npla58npla59M1T4_3,ctl_reg_gp_sel_pla61npla58npla59M1T4_3})&(op21);
ctl_reg_gp_hilo_pla61npla58npla59M1T4_4 = (pla[61]&~pla[58]&~pla[59])&(M1&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla61npla58npla59M1T4_4,ctl_reg_gp_hilo_pla61npla58npla59M1T4_4})&({~rsel0,rsel0});
ctl_reg_out_hi = ctl_reg_out_hi | (pla[61]&~pla[58]&~pla[59])&(M1&T4)&(~rsel0);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[61]&~pla[58]&~pla[59])&(M1&T4)&(rsel0);
ctl_sw_2u = ctl_sw_2u | (pla[61]&~pla[58]&~pla[59])&(M1&T4)&(~rsel0);
ctl_sw_2d = ctl_sw_2d | (pla[61]&~pla[58]&~pla[59])&(M1&T4)&(rsel0);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[61]&~pla[58]&~pla[59])&(M1&T4)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[61]&~pla[58]&~pla[59])&(M1&T4);
ctl_reg_gp_we = ctl_reg_gp_we | (use_ixiy&pla[58])&(M1&T1);
ctl_reg_gp_sel_use_ixiypla58M1T1_2 = (use_ixiy&pla[58])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_use_ixiypla58M1T1_2,ctl_reg_gp_sel_use_ixiypla58M1T1_2})&(op54);
ctl_reg_gp_hilo_use_ixiypla58M1T1_3 = (use_ixiy&pla[58])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_use_ixiypla58M1T1_3,ctl_reg_gp_hilo_use_ixiypla58M1T1_3})&({~rsel3,rsel3});
ctl_reg_in_hi = ctl_reg_in_hi | (use_ixiy&pla[58])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (use_ixiy&pla[58])&(M1&T1);
ctl_sw_2d = ctl_sw_2d | (use_ixiy&pla[58])&(M1&T1);
ctl_sw_1d = ctl_sw_1d | (use_ixiy&pla[58])&(M1&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (use_ixiy&pla[58])&(M1&T1);
validPLA = validPLA | (use_ixiy&pla[58])&(M1&T4);
nextM = nextM | (use_ixiy&pla[58])&(M1&T4);
ctl_mRead = ctl_mRead | (use_ixiy&pla[58])&(M1&T4);
fMRead = fMRead | (use_ixiy&pla[58])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (use_ixiy&pla[58])&(M2&T1);
ctl_reg_sys_hilo_use_ixiypla58M2T1_3 = (use_ixiy&pla[58])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_use_ixiypla58M2T1_3,ctl_reg_sys_hilo_use_ixiypla58M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (use_ixiy&pla[58])&(M2&T1);
fMRead = fMRead | (use_ixiy&pla[58])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (use_ixiy&pla[58])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (use_ixiy&pla[58])&(M2&T2);
ctl_reg_sys_hilo_use_ixiypla58M2T2_4 = (use_ixiy&pla[58])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_use_ixiypla58M2T2_4,ctl_reg_sys_hilo_use_ixiypla58M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (use_ixiy&pla[58])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (use_ixiy&pla[58])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (use_ixiy&pla[58])&(M2&T2);
fMRead = fMRead | (use_ixiy&pla[58])&(M2&T3);
nextM = nextM | (use_ixiy&pla[58])&(M2&T3);
ixy_d = ixy_d | (use_ixiy&pla[58])&(M3&T1);
ixy_d = ixy_d | (use_ixiy&pla[58])&(M3&T2);
ixy_d = ixy_d | (use_ixiy&pla[58])&(M3&T3);
ixy_d = ixy_d | (use_ixiy&pla[58])&(M3&T4);
nextM = nextM | (use_ixiy&pla[58])&(M3&T5);
ctl_mRead = ctl_mRead | (use_ixiy&pla[58])&(M3&T5);
ixy_d = ixy_d | (use_ixiy&pla[58])&(M3&T5);
ctl_reg_gp_we = ctl_reg_gp_we | (~use_ixiy&pla[58])&(M1&T1);
ctl_reg_gp_sel_nuse_ixiypla58M1T1_2 = (~use_ixiy&pla[58])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla58M1T1_2,ctl_reg_gp_sel_nuse_ixiypla58M1T1_2})&(op54);
ctl_reg_gp_hilo_nuse_ixiypla58M1T1_3 = (~use_ixiy&pla[58])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla58M1T1_3,ctl_reg_gp_hilo_nuse_ixiypla58M1T1_3})&({~rsel3,rsel3});
ctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[58])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[58])&(M1&T1);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[58])&(M1&T1);
ctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[58])&(M1&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[58])&(M1&T1);
validPLA = validPLA | (~use_ixiy&pla[58])&(M1&T4);
nextM = nextM | (~use_ixiy&pla[58])&(M1&T4);
ctl_mRead = ctl_mRead | (~use_ixiy&pla[58])&(M1&T4);
fMRead = fMRead | (~use_ixiy&pla[58])&(M2&T1);
ctl_reg_gp_sel_nuse_ixiypla58M2T1_2 = (~use_ixiy&pla[58])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla58M2T1_2,ctl_reg_gp_sel_nuse_ixiypla58M2T1_2})&(`GP_REG_HL);
ctl_reg_gp_hilo_nuse_ixiypla58M2T1_3 = (~use_ixiy&pla[58])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla58M2T1_3,ctl_reg_gp_hilo_nuse_ixiypla58M2T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[58])&(M2&T1);
ctl_al_we = ctl_al_we | (~use_ixiy&pla[58])&(M2&T1);
fMRead = fMRead | (~use_ixiy&pla[58])&(M2&T2);
fMRead = fMRead | (~use_ixiy&pla[58])&(M2&T3);
setM1 = setM1 | (~use_ixiy&pla[58])&(M2&T3);
fMRead = fMRead | (~use_ixiy&pla[58])&(M4&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[58])&(M4&T1);
fMRead = fMRead | (~use_ixiy&pla[58])&(M4&T2);
fMRead = fMRead | (~use_ixiy&pla[58])&(M4&T3);
setM1 = setM1 | (~use_ixiy&pla[58])&(M4&T3);
validPLA = validPLA | (use_ixiy&pla[59])&(M1&T4);
nextM = nextM | (use_ixiy&pla[59])&(M1&T4);
ctl_mRead = ctl_mRead | (use_ixiy&pla[59])&(M1&T4);
fMRead = fMRead | (use_ixiy&pla[59])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (use_ixiy&pla[59])&(M2&T1);
ctl_reg_sys_hilo_use_ixiypla59M2T1_3 = (use_ixiy&pla[59])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_use_ixiypla59M2T1_3,ctl_reg_sys_hilo_use_ixiypla59M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (use_ixiy&pla[59])&(M2&T1);
fMRead = fMRead | (use_ixiy&pla[59])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (use_ixiy&pla[59])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (use_ixiy&pla[59])&(M2&T2);
ctl_reg_sys_hilo_use_ixiypla59M2T2_4 = (use_ixiy&pla[59])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_use_ixiypla59M2T2_4,ctl_reg_sys_hilo_use_ixiypla59M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (use_ixiy&pla[59])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (use_ixiy&pla[59])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (use_ixiy&pla[59])&(M2&T2);
fMRead = fMRead | (use_ixiy&pla[59])&(M2&T3);
nextM = nextM | (use_ixiy&pla[59])&(M2&T3);
ixy_d = ixy_d | (use_ixiy&pla[59])&(M3&T1);
ixy_d = ixy_d | (use_ixiy&pla[59])&(M3&T2);
ixy_d = ixy_d | (use_ixiy&pla[59])&(M3&T3);
ixy_d = ixy_d | (use_ixiy&pla[59])&(M3&T4);
nextM = nextM | (use_ixiy&pla[59])&(M3&T5);
ctl_mWrite = ctl_mWrite | (use_ixiy&pla[59])&(M3&T5);
ixy_d = ixy_d | (use_ixiy&pla[59])&(M3&T5);
validPLA = validPLA | (~use_ixiy&pla[59])&(M1&T4);
nextM = nextM | (~use_ixiy&pla[59])&(M1&T4);
ctl_mWrite = ctl_mWrite | (~use_ixiy&pla[59])&(M1&T4);
ctl_reg_gp_sel_nuse_ixiypla59M1T4_4 = (~use_ixiy&pla[59])&(M1&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla59M1T4_4,ctl_reg_gp_sel_nuse_ixiypla59M1T4_4})&(op21);
ctl_reg_gp_hilo_nuse_ixiypla59M1T4_5 = (~use_ixiy&pla[59])&(M1&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla59M1T4_5,ctl_reg_gp_hilo_nuse_ixiypla59M1T4_5})&({~rsel0,rsel0});
ctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[59])&(M1&T4)&(~rsel0);
ctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[59])&(M1&T4)&(rsel0);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[59])&(M1&T4)&(~rsel0);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[59])&(M1&T4)&(rsel0);
ctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[59])&(M1&T4);
ctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[59])&(M1&T4);
fMWrite = fMWrite | (~use_ixiy&pla[59])&(M2&T1);
ctl_reg_gp_sel_nuse_ixiypla59M2T1_2 = (~use_ixiy&pla[59])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla59M2T1_2,ctl_reg_gp_sel_nuse_ixiypla59M2T1_2})&(`GP_REG_HL);
ctl_reg_gp_hilo_nuse_ixiypla59M2T1_3 = (~use_ixiy&pla[59])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla59M2T1_3,ctl_reg_gp_hilo_nuse_ixiypla59M2T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[59])&(M2&T1);
ctl_al_we = ctl_al_we | (~use_ixiy&pla[59])&(M2&T1);
fMWrite = fMWrite | (~use_ixiy&pla[59])&(M2&T2);
fMWrite = fMWrite | (~use_ixiy&pla[59])&(M2&T3);
setM1 = setM1 | (~use_ixiy&pla[59])&(M2&T3);
fMWrite = fMWrite | (~use_ixiy&pla[59])&(M4&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[59])&(M4&T1);
ctl_reg_gp_sel_nuse_ixiypla59M4T1_3 = (~use_ixiy&pla[59])&(M4&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla59M4T1_3,ctl_reg_gp_sel_nuse_ixiypla59M4T1_3})&(op21);
ctl_reg_gp_hilo_nuse_ixiypla59M4T1_4 = (~use_ixiy&pla[59])&(M4&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla59M4T1_4,ctl_reg_gp_hilo_nuse_ixiypla59M4T1_4})&({~rsel0,rsel0});
ctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[59])&(M4&T1)&(~rsel0);
ctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[59])&(M4&T1)&(rsel0);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[59])&(M4&T1)&(~rsel0);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[59])&(M4&T1)&(rsel0);
ctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[59])&(M4&T1);
ctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[59])&(M4&T1);
fMWrite = fMWrite | (~use_ixiy&pla[59])&(M4&T2);
fMWrite = fMWrite | (~use_ixiy&pla[59])&(M4&T3);
setM1 = setM1 | (~use_ixiy&pla[59])&(M4&T3);
validPLA = validPLA | (pla[40])&(M1&T4);
nextM = nextM | (pla[40])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[40])&(M1&T4);
fMRead = fMRead | (pla[40])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[40])&(M2&T1);
ctl_reg_sys_hilo_pla40M2T1_3 = (pla[40])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla40M2T1_3,ctl_reg_sys_hilo_pla40M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[40])&(M2&T1);
fMRead = fMRead | (pla[40])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[40])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[40])&(M2&T2);
ctl_reg_sys_hilo_pla40M2T2_4 = (pla[40])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla40M2T2_4,ctl_reg_sys_hilo_pla40M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[40])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[40])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[40])&(M2&T2);
fMRead = fMRead | (pla[40])&(M2&T3);
nextM = nextM | (pla[40])&(M2&T3);
ctl_mRead = ctl_mRead | (pla[40])&(M2&T3);
fMRead = fMRead | (pla[40])&(M3&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[40])&(M3&T1);
ctl_reg_sys_hilo_pla40M3T1_3 = (pla[40])&(M3&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla40M3T1_3,ctl_reg_sys_hilo_pla40M3T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[40])&(M3&T1);
ixy_d = ixy_d | (pla[40])&(M3&T1);
fMRead = fMRead | (pla[40])&(M3&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[40])&(M3&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[40])&(M3&T2);
ctl_reg_sys_hilo_pla40M3T2_4 = (pla[40])&(M3&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla40M3T2_4,ctl_reg_sys_hilo_pla40M3T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[40])&(M3&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[40])&(M3&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[40])&(M3&T2);
ixy_d = ixy_d | (pla[40])&(M3&T2);
fMRead = fMRead | (pla[40])&(M3&T3);
ixy_d = ixy_d | (pla[40])&(M3&T3);
ixy_d = ixy_d | (pla[40])&(M3&T4);
nextM = nextM | (pla[40])&(M3&T5);
ctl_mWrite = ctl_mWrite | (pla[40])&(M3&T5);
ixy_d = ixy_d | (pla[40])&(M3&T5);
validPLA = validPLA | (pla[50]&~pla[40])&(M1&T4);
nextM = nextM | (pla[50]&~pla[40])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[50]&~pla[40])&(M1&T4);
fMRead = fMRead | (pla[50]&~pla[40])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[50]&~pla[40])&(M2&T1);
ctl_reg_sys_hilo_pla50npla40M2T1_3 = (pla[50]&~pla[40])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla50npla40M2T1_3,ctl_reg_sys_hilo_pla50npla40M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[50]&~pla[40])&(M2&T1);
fMRead = fMRead | (pla[50]&~pla[40])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[50]&~pla[40])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[50]&~pla[40])&(M2&T2);
ctl_reg_sys_hilo_pla50npla40M2T2_4 = (pla[50]&~pla[40])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla50npla40M2T2_4,ctl_reg_sys_hilo_pla50npla40M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[50]&~pla[40])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[50]&~pla[40])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[50]&~pla[40])&(M2&T2);
fMRead = fMRead | (pla[50]&~pla[40])&(M2&T3);
nextM = nextM | (pla[50]&~pla[40])&(M2&T3);
ctl_mWrite = ctl_mWrite | (pla[50]&~pla[40])&(M2&T3);
fMWrite = fMWrite | (pla[50]&~pla[40])&(M3&T1);
ctl_reg_gp_sel_pla50npla40M3T1_2 = (pla[50]&~pla[40])&(M3&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla50npla40M3T1_2,ctl_reg_gp_sel_pla50npla40M3T1_2})&(`GP_REG_HL);
ctl_reg_gp_hilo_pla50npla40M3T1_3 = (pla[50]&~pla[40])&(M3&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla50npla40M3T1_3,ctl_reg_gp_hilo_pla50npla40M3T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[50]&~pla[40])&(M3&T1);
ctl_al_we = ctl_al_we | (pla[50]&~pla[40])&(M3&T1);
fMWrite = fMWrite | (pla[50]&~pla[40])&(M3&T2);
fMWrite = fMWrite | (pla[50]&~pla[40])&(M3&T3);
setM1 = setM1 | (pla[50]&~pla[40])&(M3&T3);
fMWrite = fMWrite | (pla[50]&~pla[40])&(M4&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[50]&~pla[40])&(M4&T1);
fMWrite = fMWrite | (pla[50]&~pla[40])&(M4&T2);
fMWrite = fMWrite | (pla[50]&~pla[40])&(M4&T3);
setM1 = setM1 | (pla[50]&~pla[40])&(M4&T3);
validPLA = validPLA | (pla[8]&pla[13])&(M1&T4);
nextM = nextM | (pla[8]&pla[13])&(M1&T4);
ctl_mWrite = ctl_mWrite | (pla[8]&pla[13])&(M1&T4);
ctl_reg_gp_sel_pla8pla13M1T4_4 = (pla[8]&pla[13])&(M1&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla8pla13M1T4_4,ctl_reg_gp_sel_pla8pla13M1T4_4})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla8pla13M1T4_5 = (pla[8]&pla[13])&(M1&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla8pla13M1T4_5,ctl_reg_gp_hilo_pla8pla13M1T4_5})&(2'b10);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[8]&pla[13])&(M1&T4);
ctl_sw_2u = ctl_sw_2u | (pla[8]&pla[13])&(M1&T4);
ctl_sw_1u = ctl_sw_1u | (pla[8]&pla[13])&(M1&T4);
ctl_bus_db_we = ctl_bus_db_we | (pla[8]&pla[13])&(M1&T4);
fMWrite = fMWrite | (pla[8]&pla[13])&(M2&T1);
ctl_reg_gp_sel_pla8pla13M2T1_2 = (pla[8]&pla[13])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla8pla13M2T1_2,ctl_reg_gp_sel_pla8pla13M2T1_2})&(op54);
ctl_reg_gp_hilo_pla8pla13M2T1_3 = (pla[8]&pla[13])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla8pla13M2T1_3,ctl_reg_gp_hilo_pla8pla13M2T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[8]&pla[13])&(M2&T1);
ctl_al_we = ctl_al_we | (pla[8]&pla[13])&(M2&T1);
fMWrite = fMWrite | (pla[8]&pla[13])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[8]&pla[13])&(M2&T2);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[8]&pla[13])&(M2&T2);
ctl_reg_sys_hilo_pla8pla13M2T2_4 = (pla[8]&pla[13])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla8pla13M2T2_4,ctl_reg_sys_hilo_pla8pla13M2T2_4})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[8]&pla[13])&(M2&T2);
ctl_inc_cy = ctl_inc_cy | (pla[8]&pla[13])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[8]&pla[13])&(M2&T2);
fMWrite = fMWrite | (pla[8]&pla[13])&(M2&T3);
setM1 = setM1 | (pla[8]&pla[13])&(M2&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[8]&~pla[13])&(M1&T1);
ctl_reg_gp_sel_pla8npla13M1T1_2 = (pla[8]&~pla[13])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla8npla13M1T1_2,ctl_reg_gp_sel_pla8npla13M1T1_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla8npla13M1T1_3 = (pla[8]&~pla[13])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla8npla13M1T1_3,ctl_reg_gp_hilo_pla8npla13M1T1_3})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[8]&~pla[13])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[8]&~pla[13])&(M1&T1);
ctl_sw_2d = ctl_sw_2d | (pla[8]&~pla[13])&(M1&T1);
ctl_sw_1d = ctl_sw_1d | (pla[8]&~pla[13])&(M1&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[8]&~pla[13])&(M1&T1);
validPLA = validPLA | (pla[8]&~pla[13])&(M1&T4);
nextM = nextM | (pla[8]&~pla[13])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[8]&~pla[13])&(M1&T4);
fMRead = fMRead | (pla[8]&~pla[13])&(M2&T1);
ctl_reg_gp_sel_pla8npla13M2T1_2 = (pla[8]&~pla[13])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla8npla13M2T1_2,ctl_reg_gp_sel_pla8npla13M2T1_2})&(op54);
ctl_reg_gp_hilo_pla8npla13M2T1_3 = (pla[8]&~pla[13])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla8npla13M2T1_3,ctl_reg_gp_hilo_pla8npla13M2T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[8]&~pla[13])&(M2&T1);
ctl_al_we = ctl_al_we | (pla[8]&~pla[13])&(M2&T1);
fMRead = fMRead | (pla[8]&~pla[13])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[8]&~pla[13])&(M2&T2);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[8]&~pla[13])&(M2&T2);
ctl_reg_sys_hilo_pla8npla13M2T2_4 = (pla[8]&~pla[13])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla8npla13M2T2_4,ctl_reg_sys_hilo_pla8npla13M2T2_4})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[8]&~pla[13])&(M2&T2);
ctl_inc_cy = ctl_inc_cy | (pla[8]&~pla[13])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[8]&~pla[13])&(M2&T2);
fMRead = fMRead | (pla[8]&~pla[13])&(M2&T3);
setM1 = setM1 | (pla[8]&~pla[13])&(M2&T3);
validPLA = validPLA | (pla[38]&pla[13])&(M1&T4);
nextM = nextM | (pla[38]&pla[13])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[38]&pla[13])&(M1&T4);
fMRead = fMRead | (pla[38]&pla[13])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[38]&pla[13])&(M2&T1);
ctl_reg_sys_hilo_pla38pla13M2T1_3 = (pla[38]&pla[13])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38pla13M2T1_3,ctl_reg_sys_hilo_pla38pla13M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[38]&pla[13])&(M2&T1);
fMRead = fMRead | (pla[38]&pla[13])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[38]&pla[13])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[38]&pla[13])&(M2&T2);
ctl_reg_sys_hilo_pla38pla13M2T2_4 = (pla[38]&pla[13])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38pla13M2T2_4,ctl_reg_sys_hilo_pla38pla13M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[38]&pla[13])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[38]&pla[13])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[38]&pla[13])&(M2&T2);
fMRead = fMRead | (pla[38]&pla[13])&(M2&T3);
nextM = nextM | (pla[38]&pla[13])&(M2&T3);
ctl_mRead = ctl_mRead | (pla[38]&pla[13])&(M2&T3);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[38]&pla[13])&(M2&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[38]&pla[13])&(M2&T3);
ctl_reg_sys_hilo_pla38pla13M2T3_6 = (pla[38]&pla[13])&(M2&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38pla13M2T3_6,ctl_reg_sys_hilo_pla38pla13M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (pla[38]&pla[13])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[38]&pla[13])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (pla[38]&pla[13])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[38]&pla[13])&(M2&T3);
fMRead = fMRead | (pla[38]&pla[13])&(M3&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[38]&pla[13])&(M3&T1);
ctl_reg_sys_hilo_pla38pla13M3T1_3 = (pla[38]&pla[13])&(M3&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38pla13M3T1_3,ctl_reg_sys_hilo_pla38pla13M3T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[38]&pla[13])&(M3&T1);
fMRead = fMRead | (pla[38]&pla[13])&(M3&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[38]&pla[13])&(M3&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[38]&pla[13])&(M3&T2);
ctl_reg_sys_hilo_pla38pla13M3T2_4 = (pla[38]&pla[13])&(M3&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38pla13M3T2_4,ctl_reg_sys_hilo_pla38pla13M3T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[38]&pla[13])&(M3&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[38]&pla[13])&(M3&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[38]&pla[13])&(M3&T2);
fMRead = fMRead | (pla[38]&pla[13])&(M3&T3);
nextM = nextM | (pla[38]&pla[13])&(M3&T3);
ctl_mWrite = ctl_mWrite | (pla[38]&pla[13])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[38]&pla[13])&(M3&T3);
ctl_reg_sys_hilo_pla38pla13M3T3_5 = (pla[38]&pla[13])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38pla13M3T3_5,ctl_reg_sys_hilo_pla38pla13M3T3_5})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[38]&pla[13])&(M3&T3);
ctl_al_we = ctl_al_we | (pla[38]&pla[13])&(M3&T3);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[38]&pla[13])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[38]&pla[13])&(M3&T3);
ctl_reg_sys_hilo_pla38pla13M3T3_10 = (pla[38]&pla[13])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38pla13M3T3_10,ctl_reg_sys_hilo_pla38pla13M3T3_10})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[38]&pla[13])&(M3&T3);
ctl_sw_2d = ctl_sw_2d | (pla[38]&pla[13])&(M3&T3);
ctl_sw_1d = ctl_sw_1d | (pla[38]&pla[13])&(M3&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[38]&pla[13])&(M3&T3);
fMWrite = fMWrite | (pla[38]&pla[13])&(M4&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[38]&pla[13])&(M4&T1);
ctl_reg_gp_sel_pla38pla13M4T1_3 = (pla[38]&pla[13])&(M4&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla38pla13M4T1_3,ctl_reg_gp_sel_pla38pla13M4T1_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla38pla13M4T1_4 = (pla[38]&pla[13])&(M4&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla38pla13M4T1_4,ctl_reg_gp_hilo_pla38pla13M4T1_4})&(2'b10);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[38]&pla[13])&(M4&T1);
ctl_sw_2u = ctl_sw_2u | (pla[38]&pla[13])&(M4&T1);
ctl_sw_1u = ctl_sw_1u | (pla[38]&pla[13])&(M4&T1);
ctl_bus_db_we = ctl_bus_db_we | (pla[38]&pla[13])&(M4&T1);
fMWrite = fMWrite | (pla[38]&pla[13])&(M4&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[38]&pla[13])&(M4&T2);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[38]&pla[13])&(M4&T2);
ctl_reg_sys_hilo_pla38pla13M4T2_4 = (pla[38]&pla[13])&(M4&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38pla13M4T2_4,ctl_reg_sys_hilo_pla38pla13M4T2_4})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[38]&pla[13])&(M4&T2);
ctl_inc_cy = ctl_inc_cy | (pla[38]&pla[13])&(M4&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[38]&pla[13])&(M4&T2);
fMWrite = fMWrite | (pla[38]&pla[13])&(M4&T3);
setM1 = setM1 | (pla[38]&pla[13])&(M4&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[38]&~pla[13])&(M1&T1);
ctl_reg_gp_sel_pla38npla13M1T1_2 = (pla[38]&~pla[13])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla38npla13M1T1_2,ctl_reg_gp_sel_pla38npla13M1T1_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla38npla13M1T1_3 = (pla[38]&~pla[13])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla38npla13M1T1_3,ctl_reg_gp_hilo_pla38npla13M1T1_3})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[38]&~pla[13])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[38]&~pla[13])&(M1&T1);
ctl_sw_2d = ctl_sw_2d | (pla[38]&~pla[13])&(M1&T1);
ctl_sw_1d = ctl_sw_1d | (pla[38]&~pla[13])&(M1&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[38]&~pla[13])&(M1&T1);
validPLA = validPLA | (pla[38]&~pla[13])&(M1&T4);
nextM = nextM | (pla[38]&~pla[13])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[38]&~pla[13])&(M1&T4);
fMRead = fMRead | (pla[38]&~pla[13])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[38]&~pla[13])&(M2&T1);
ctl_reg_sys_hilo_pla38npla13M2T1_3 = (pla[38]&~pla[13])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38npla13M2T1_3,ctl_reg_sys_hilo_pla38npla13M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[38]&~pla[13])&(M2&T1);
fMRead = fMRead | (pla[38]&~pla[13])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[38]&~pla[13])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[38]&~pla[13])&(M2&T2);
ctl_reg_sys_hilo_pla38npla13M2T2_4 = (pla[38]&~pla[13])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38npla13M2T2_4,ctl_reg_sys_hilo_pla38npla13M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[38]&~pla[13])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[38]&~pla[13])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[38]&~pla[13])&(M2&T2);
fMRead = fMRead | (pla[38]&~pla[13])&(M2&T3);
nextM = nextM | (pla[38]&~pla[13])&(M2&T3);
ctl_mRead = ctl_mRead | (pla[38]&~pla[13])&(M2&T3);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[38]&~pla[13])&(M2&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[38]&~pla[13])&(M2&T3);
ctl_reg_sys_hilo_pla38npla13M2T3_6 = (pla[38]&~pla[13])&(M2&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38npla13M2T3_6,ctl_reg_sys_hilo_pla38npla13M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (pla[38]&~pla[13])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[38]&~pla[13])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (pla[38]&~pla[13])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[38]&~pla[13])&(M2&T3);
fMRead = fMRead | (pla[38]&~pla[13])&(M3&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[38]&~pla[13])&(M3&T1);
ctl_reg_sys_hilo_pla38npla13M3T1_3 = (pla[38]&~pla[13])&(M3&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38npla13M3T1_3,ctl_reg_sys_hilo_pla38npla13M3T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[38]&~pla[13])&(M3&T1);
fMRead = fMRead | (pla[38]&~pla[13])&(M3&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[38]&~pla[13])&(M3&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[38]&~pla[13])&(M3&T2);
ctl_reg_sys_hilo_pla38npla13M3T2_4 = (pla[38]&~pla[13])&(M3&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38npla13M3T2_4,ctl_reg_sys_hilo_pla38npla13M3T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[38]&~pla[13])&(M3&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[38]&~pla[13])&(M3&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[38]&~pla[13])&(M3&T2);
fMRead = fMRead | (pla[38]&~pla[13])&(M3&T3);
nextM = nextM | (pla[38]&~pla[13])&(M3&T3);
ctl_mRead = ctl_mRead | (pla[38]&~pla[13])&(M3&T3);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[38]&~pla[13])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[38]&~pla[13])&(M3&T3);
ctl_reg_sys_hilo_pla38npla13M3T3_6 = (pla[38]&~pla[13])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38npla13M3T3_6,ctl_reg_sys_hilo_pla38npla13M3T3_6})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[38]&~pla[13])&(M3&T3);
ctl_sw_2d = ctl_sw_2d | (pla[38]&~pla[13])&(M3&T3);
ctl_sw_1d = ctl_sw_1d | (pla[38]&~pla[13])&(M3&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[38]&~pla[13])&(M3&T3);
fMRead = fMRead | (pla[38]&~pla[13])&(M4&T1);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[38]&~pla[13])&(M4&T1);
ctl_reg_sys_hilo_pla38npla13M4T1_3 = (pla[38]&~pla[13])&(M4&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38npla13M4T1_3,ctl_reg_sys_hilo_pla38npla13M4T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[38]&~pla[13])&(M4&T1);
ctl_al_we = ctl_al_we | (pla[38]&~pla[13])&(M4&T1);
fMRead = fMRead | (pla[38]&~pla[13])&(M4&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[38]&~pla[13])&(M4&T2);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[38]&~pla[13])&(M4&T2);
ctl_reg_sys_hilo_pla38npla13M4T2_4 = (pla[38]&~pla[13])&(M4&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38npla13M4T2_4,ctl_reg_sys_hilo_pla38npla13M4T2_4})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[38]&~pla[13])&(M4&T2);
ctl_inc_cy = ctl_inc_cy | (pla[38]&~pla[13])&(M4&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[38]&~pla[13])&(M4&T2);
fMRead = fMRead | (pla[38]&~pla[13])&(M4&T3);
setM1 = setM1 | (pla[38]&~pla[13])&(M4&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[83])&(M1&T1);
ctl_reg_gp_sel_pla83M1T1_2 = (pla[83])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla83M1T1_2,ctl_reg_gp_sel_pla83M1T1_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla83M1T1_3 = (pla[83])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla83M1T1_3,ctl_reg_gp_hilo_pla83M1T1_3})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[83])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[83])&(M1&T1);
ctl_flags_alu = ctl_flags_alu | (pla[83])&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (pla[83])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[83])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[83])&(M1&T1);
ctl_alu_core_R = ctl_alu_core_R | (pla[83])&(M1&T1);
ctl_alu_core_V = ctl_alu_core_V | (pla[83])&(M1&T1);
ctl_alu_core_S = ctl_alu_core_S | (pla[83])&(M1&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[83])&(M1&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[83])&(M1&T1);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[83])&(M1&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[83])&(M1&T1);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[83])&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[83])&(M1&T1);
ctl_pf_sel_pla83M1T1_19 = (pla[83])&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla83M1T1_19,ctl_pf_sel_pla83M1T1_19})&(`PFSEL_IFF2);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[83])&(M1&T1);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[83])&(M1&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[83])&(M1&T2);
ctl_reg_gp_sel_pla83M1T2_2 = (pla[83])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla83M1T2_2,ctl_reg_gp_sel_pla83M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla83M1T2_3 = (pla[83])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla83M1T2_3,ctl_reg_gp_hilo_pla83M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[83])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[83])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (pla[83])&(M1&T2);
ctl_reg_gp_sel_pla83M1T3_1 = (pla[83])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla83M1T3_1,ctl_reg_gp_sel_pla83M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla83M1T3_2 = (pla[83])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla83M1T3_2,ctl_reg_gp_hilo_pla83M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[83])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[83])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[83])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[83])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[83])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[83])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[83])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[83])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[83])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[83])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[83])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[83])&(M1&T3);
validPLA = validPLA | (pla[83])&(M1&T4);
ctl_reg_sel_ir = ctl_reg_sel_ir | (pla[83])&(M1&T4);
ctl_reg_sys_hilo_pla83M1T4_3 = (pla[83])&(M1&T4);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla83M1T4_3,ctl_reg_sys_hilo_pla83M1T4_3})&({~op3,op3});
ctl_sw_4u = ctl_sw_4u | (pla[83])&(M1&T4);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[83])&(M1&T4)&(~rsel3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[83])&(M1&T4)&(rsel3);
ctl_sw_2u = ctl_sw_2u | (pla[83])&(M1&T4)&(~rsel3);
ctl_sw_2d = ctl_sw_2d | (pla[83])&(M1&T4)&(rsel3);
ctl_flags_alu = ctl_flags_alu | (pla[83])&(M1&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[83])&(M1&T4)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[83])&(M1&T4);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[83])&(M1&T4);
ctl_alu_op_low = ctl_alu_op_low | (pla[83])&(M1&T4);
ctl_alu_core_R = ctl_alu_core_R | (pla[83])&(M1&T4);
ctl_alu_core_V = ctl_alu_core_V | (pla[83])&(M1&T4);
ctl_alu_core_S = ctl_alu_core_S | (pla[83])&(M1&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[83])&(M1&T4);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[83])&(M1&T4);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[83])&(M1&T4);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[83])&(M1&T4);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[83])&(M1&T4);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[83])&(M1&T4);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[83])&(M1&T4);
setM1 = setM1 | (pla[83])&(M1&T5);
ctl_reg_gp_sel_pla57M1T3_1 = (pla[57])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla57M1T3_1,ctl_reg_gp_sel_pla57M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla57M1T3_2 = (pla[57])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla57M1T3_2,ctl_reg_gp_hilo_pla57M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[57])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[57])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[57])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[57])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[57])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[57])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[57])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[57])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[57])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[57])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[57])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[57])&(M1&T3);
validPLA = validPLA | (pla[57])&(M1&T4);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[57])&(M1&T4);
ctl_reg_sel_ir = ctl_reg_sel_ir | (pla[57])&(M1&T4);
ctl_reg_sys_hilo_pla57M1T4_4 = (pla[57])&(M1&T4);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla57M1T4_4,ctl_reg_sys_hilo_pla57M1T4_4})&({~op3,op3});
ctl_sw_4d = ctl_sw_4d | (pla[57])&(M1&T4);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[57])&(M1&T4);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[57])&(M1&T4);
ctl_sw_2u = ctl_sw_2u | (pla[57])&(M1&T4);
ctl_alu_oe = ctl_alu_oe | (pla[57])&(M1&T4);
ctl_alu_op1_oe = ctl_alu_op1_oe | (pla[57])&(M1&T4);
setM1 = setM1 | (pla[57])&(M1&T5);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[7])&(M1&T1);
ctl_reg_gp_sel_pla7M1T1_2 = (pla[7])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla7M1T1_2,ctl_reg_gp_sel_pla7M1T1_2})&(op54);
ctl_reg_gp_hilo_pla7M1T1_3 = (pla[7])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla7M1T1_3,ctl_reg_gp_hilo_pla7M1T1_3})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[7])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[7])&(M1&T1);
ctl_sw_2d = ctl_sw_2d | (pla[7])&(M1&T1);
ctl_sw_1d = ctl_sw_1d | (pla[7])&(M1&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[7])&(M1&T1);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[7])&(M1&T1);
validPLA = validPLA | (pla[7])&(M1&T4);
nextM = nextM | (pla[7])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[7])&(M1&T4);
fMRead = fMRead | (pla[7])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[7])&(M2&T1);
ctl_reg_sys_hilo_pla7M2T1_3 = (pla[7])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla7M2T1_3,ctl_reg_sys_hilo_pla7M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[7])&(M2&T1);
fMRead = fMRead | (pla[7])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[7])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[7])&(M2&T2);
ctl_reg_sys_hilo_pla7M2T2_4 = (pla[7])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla7M2T2_4,ctl_reg_sys_hilo_pla7M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[7])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[7])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[7])&(M2&T2);
fMRead = fMRead | (pla[7])&(M2&T3);
nextM = nextM | (pla[7])&(M2&T3);
ctl_mRead = ctl_mRead | (pla[7])&(M2&T3);
fMRead = fMRead | (pla[7])&(M3&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[7])&(M3&T1);
ctl_reg_sys_hilo_pla7M3T1_3 = (pla[7])&(M3&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla7M3T1_3,ctl_reg_sys_hilo_pla7M3T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[7])&(M3&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[7])&(M3&T1);
ctl_reg_gp_sel_pla7M3T1_6 = (pla[7])&(M3&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla7M3T1_6,ctl_reg_gp_sel_pla7M3T1_6})&(op54);
ctl_reg_gp_hilo_pla7M3T1_7 = (pla[7])&(M3&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla7M3T1_7,ctl_reg_gp_hilo_pla7M3T1_7})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[7])&(M3&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[7])&(M3&T1);
ctl_sw_2d = ctl_sw_2d | (pla[7])&(M3&T1);
ctl_sw_1d = ctl_sw_1d | (pla[7])&(M3&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[7])&(M3&T1);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[7])&(M3&T1);
fMRead = fMRead | (pla[7])&(M3&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[7])&(M3&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[7])&(M3&T2);
ctl_reg_sys_hilo_pla7M3T2_4 = (pla[7])&(M3&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla7M3T2_4,ctl_reg_sys_hilo_pla7M3T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[7])&(M3&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[7])&(M3&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[7])&(M3&T2);
fMRead = fMRead | (pla[7])&(M3&T3);
setM1 = setM1 | (pla[7])&(M3&T3);
validPLA = validPLA | (pla[30]&pla[13])&(M1&T4);
nextM = nextM | (pla[30]&pla[13])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[30]&pla[13])&(M1&T4);
fMRead = fMRead | (pla[30]&pla[13])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[30]&pla[13])&(M2&T1);
ctl_reg_sys_hilo_pla30pla13M2T1_3 = (pla[30]&pla[13])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30pla13M2T1_3,ctl_reg_sys_hilo_pla30pla13M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[30]&pla[13])&(M2&T1);
fMRead = fMRead | (pla[30]&pla[13])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[30]&pla[13])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[30]&pla[13])&(M2&T2);
ctl_reg_sys_hilo_pla30pla13M2T2_4 = (pla[30]&pla[13])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30pla13M2T2_4,ctl_reg_sys_hilo_pla30pla13M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[30]&pla[13])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[30]&pla[13])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[30]&pla[13])&(M2&T2);
fMRead = fMRead | (pla[30]&pla[13])&(M2&T3);
nextM = nextM | (pla[30]&pla[13])&(M2&T3);
ctl_mRead = ctl_mRead | (pla[30]&pla[13])&(M2&T3);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[30]&pla[13])&(M2&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&pla[13])&(M2&T3);
ctl_reg_sys_hilo_pla30pla13M2T3_6 = (pla[30]&pla[13])&(M2&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30pla13M2T3_6,ctl_reg_sys_hilo_pla30pla13M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (pla[30]&pla[13])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[30]&pla[13])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (pla[30]&pla[13])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[30]&pla[13])&(M2&T3);
fMRead = fMRead | (pla[30]&pla[13])&(M3&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[30]&pla[13])&(M3&T1);
ctl_reg_sys_hilo_pla30pla13M3T1_3 = (pla[30]&pla[13])&(M3&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30pla13M3T1_3,ctl_reg_sys_hilo_pla30pla13M3T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[30]&pla[13])&(M3&T1);
fMRead = fMRead | (pla[30]&pla[13])&(M3&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[30]&pla[13])&(M3&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[30]&pla[13])&(M3&T2);
ctl_reg_sys_hilo_pla30pla13M3T2_4 = (pla[30]&pla[13])&(M3&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30pla13M3T2_4,ctl_reg_sys_hilo_pla30pla13M3T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[30]&pla[13])&(M3&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[30]&pla[13])&(M3&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[30]&pla[13])&(M3&T2);
fMRead = fMRead | (pla[30]&pla[13])&(M3&T3);
nextM = nextM | (pla[30]&pla[13])&(M3&T3);
ctl_mWrite = ctl_mWrite | (pla[30]&pla[13])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&pla[13])&(M3&T3);
ctl_reg_sys_hilo_pla30pla13M3T3_5 = (pla[30]&pla[13])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30pla13M3T3_5,ctl_reg_sys_hilo_pla30pla13M3T3_5})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[30]&pla[13])&(M3&T3);
ctl_al_we = ctl_al_we | (pla[30]&pla[13])&(M3&T3);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[30]&pla[13])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&pla[13])&(M3&T3);
ctl_reg_sys_hilo_pla30pla13M3T3_10 = (pla[30]&pla[13])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30pla13M3T3_10,ctl_reg_sys_hilo_pla30pla13M3T3_10})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[30]&pla[13])&(M3&T3);
ctl_sw_2d = ctl_sw_2d | (pla[30]&pla[13])&(M3&T3);
ctl_sw_1d = ctl_sw_1d | (pla[30]&pla[13])&(M3&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[30]&pla[13])&(M3&T3);
fMWrite = fMWrite | (pla[30]&pla[13])&(M4&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[30]&pla[13])&(M4&T1);
ctl_reg_gp_sel_pla30pla13M4T1_3 = (pla[30]&pla[13])&(M4&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla30pla13M4T1_3,ctl_reg_gp_sel_pla30pla13M4T1_3})&(op54);
ctl_reg_gp_hilo_pla30pla13M4T1_4 = (pla[30]&pla[13])&(M4&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla30pla13M4T1_4,ctl_reg_gp_hilo_pla30pla13M4T1_4})&(2'b01);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[30]&pla[13])&(M4&T1);
ctl_sw_1u = ctl_sw_1u | (pla[30]&pla[13])&(M4&T1);
ctl_bus_db_we = ctl_bus_db_we | (pla[30]&pla[13])&(M4&T1);
fMWrite = fMWrite | (pla[30]&pla[13])&(M4&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[30]&pla[13])&(M4&T2);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&pla[13])&(M4&T2);
ctl_reg_sys_hilo_pla30pla13M4T2_4 = (pla[30]&pla[13])&(M4&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30pla13M4T2_4,ctl_reg_sys_hilo_pla30pla13M4T2_4})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[30]&pla[13])&(M4&T2);
ctl_inc_cy = ctl_inc_cy | (pla[30]&pla[13])&(M4&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[30]&pla[13])&(M4&T2);
fMWrite = fMWrite | (pla[30]&pla[13])&(M4&T3);
nextM = nextM | (pla[30]&pla[13])&(M4&T3);
ctl_mWrite = ctl_mWrite | (pla[30]&pla[13])&(M4&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&pla[13])&(M4&T3);
ctl_reg_sys_hilo_pla30pla13M4T3_5 = (pla[30]&pla[13])&(M4&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30pla13M4T3_5,ctl_reg_sys_hilo_pla30pla13M4T3_5})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[30]&pla[13])&(M4&T3);
ctl_al_we = ctl_al_we | (pla[30]&pla[13])&(M4&T3);
fMWrite = fMWrite | (pla[30]&pla[13])&(M5&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[30]&pla[13])&(M5&T1);
ctl_reg_gp_sel_pla30pla13M5T1_3 = (pla[30]&pla[13])&(M5&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla30pla13M5T1_3,ctl_reg_gp_sel_pla30pla13M5T1_3})&(op54);
ctl_reg_gp_hilo_pla30pla13M5T1_4 = (pla[30]&pla[13])&(M5&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla30pla13M5T1_4,ctl_reg_gp_hilo_pla30pla13M5T1_4})&(2'b10);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[30]&pla[13])&(M5&T1);
ctl_sw_2u = ctl_sw_2u | (pla[30]&pla[13])&(M5&T1);
ctl_sw_1u = ctl_sw_1u | (pla[30]&pla[13])&(M5&T1);
ctl_bus_db_we = ctl_bus_db_we | (pla[30]&pla[13])&(M5&T1);
fMWrite = fMWrite | (pla[30]&pla[13])&(M5&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[30]&pla[13])&(M5&T2);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&pla[13])&(M5&T2);
ctl_reg_sys_hilo_pla30pla13M5T2_4 = (pla[30]&pla[13])&(M5&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30pla13M5T2_4,ctl_reg_sys_hilo_pla30pla13M5T2_4})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[30]&pla[13])&(M5&T2);
ctl_inc_cy = ctl_inc_cy | (pla[30]&pla[13])&(M5&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[30]&pla[13])&(M5&T2);
fMWrite = fMWrite | (pla[30]&pla[13])&(M5&T3);
setM1 = setM1 | (pla[30]&pla[13])&(M5&T3);
validPLA = validPLA | (pla[30]&~pla[13])&(M1&T4);
nextM = nextM | (pla[30]&~pla[13])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[30]&~pla[13])&(M1&T4);
fMRead = fMRead | (pla[30]&~pla[13])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[30]&~pla[13])&(M2&T1);
ctl_reg_sys_hilo_pla30npla13M2T1_3 = (pla[30]&~pla[13])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30npla13M2T1_3,ctl_reg_sys_hilo_pla30npla13M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[30]&~pla[13])&(M2&T1);
fMRead = fMRead | (pla[30]&~pla[13])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[30]&~pla[13])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[30]&~pla[13])&(M2&T2);
ctl_reg_sys_hilo_pla30npla13M2T2_4 = (pla[30]&~pla[13])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30npla13M2T2_4,ctl_reg_sys_hilo_pla30npla13M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[30]&~pla[13])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[30]&~pla[13])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[30]&~pla[13])&(M2&T2);
fMRead = fMRead | (pla[30]&~pla[13])&(M2&T3);
nextM = nextM | (pla[30]&~pla[13])&(M2&T3);
ctl_mRead = ctl_mRead | (pla[30]&~pla[13])&(M2&T3);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[30]&~pla[13])&(M2&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&~pla[13])&(M2&T3);
ctl_reg_sys_hilo_pla30npla13M2T3_6 = (pla[30]&~pla[13])&(M2&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30npla13M2T3_6,ctl_reg_sys_hilo_pla30npla13M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (pla[30]&~pla[13])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[30]&~pla[13])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (pla[30]&~pla[13])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[30]&~pla[13])&(M2&T3);
fMRead = fMRead | (pla[30]&~pla[13])&(M3&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[30]&~pla[13])&(M3&T1);
ctl_reg_sys_hilo_pla30npla13M3T1_3 = (pla[30]&~pla[13])&(M3&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30npla13M3T1_3,ctl_reg_sys_hilo_pla30npla13M3T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[30]&~pla[13])&(M3&T1);
fMRead = fMRead | (pla[30]&~pla[13])&(M3&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[30]&~pla[13])&(M3&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[30]&~pla[13])&(M3&T2);
ctl_reg_sys_hilo_pla30npla13M3T2_4 = (pla[30]&~pla[13])&(M3&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30npla13M3T2_4,ctl_reg_sys_hilo_pla30npla13M3T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[30]&~pla[13])&(M3&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[30]&~pla[13])&(M3&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[30]&~pla[13])&(M3&T2);
fMRead = fMRead | (pla[30]&~pla[13])&(M3&T3);
nextM = nextM | (pla[30]&~pla[13])&(M3&T3);
ctl_mRead = ctl_mRead | (pla[30]&~pla[13])&(M3&T3);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[30]&~pla[13])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&~pla[13])&(M3&T3);
ctl_reg_sys_hilo_pla30npla13M3T3_6 = (pla[30]&~pla[13])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30npla13M3T3_6,ctl_reg_sys_hilo_pla30npla13M3T3_6})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[30]&~pla[13])&(M3&T3);
ctl_sw_2d = ctl_sw_2d | (pla[30]&~pla[13])&(M3&T3);
ctl_sw_1d = ctl_sw_1d | (pla[30]&~pla[13])&(M3&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[30]&~pla[13])&(M3&T3);
fMRead = fMRead | (pla[30]&~pla[13])&(M4&T1);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&~pla[13])&(M4&T1);
ctl_reg_sys_hilo_pla30npla13M4T1_3 = (pla[30]&~pla[13])&(M4&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30npla13M4T1_3,ctl_reg_sys_hilo_pla30npla13M4T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[30]&~pla[13])&(M4&T1);
ctl_al_we = ctl_al_we | (pla[30]&~pla[13])&(M4&T1);
fMRead = fMRead | (pla[30]&~pla[13])&(M4&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[30]&~pla[13])&(M4&T2);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&~pla[13])&(M4&T2);
ctl_reg_sys_hilo_pla30npla13M4T2_4 = (pla[30]&~pla[13])&(M4&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30npla13M4T2_4,ctl_reg_sys_hilo_pla30npla13M4T2_4})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[30]&~pla[13])&(M4&T2);
ctl_inc_cy = ctl_inc_cy | (pla[30]&~pla[13])&(M4&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[30]&~pla[13])&(M4&T2);
fMRead = fMRead | (pla[30]&~pla[13])&(M4&T3);
nextM = nextM | (pla[30]&~pla[13])&(M4&T3);
ctl_mRead = ctl_mRead | (pla[30]&~pla[13])&(M4&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[30]&~pla[13])&(M4&T3);
ctl_reg_gp_sel_pla30npla13M4T3_5 = (pla[30]&~pla[13])&(M4&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla30npla13M4T3_5,ctl_reg_gp_sel_pla30npla13M4T3_5})&(op54);
ctl_reg_gp_hilo_pla30npla13M4T3_6 = (pla[30]&~pla[13])&(M4&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla30npla13M4T3_6,ctl_reg_gp_hilo_pla30npla13M4T3_6})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[30]&~pla[13])&(M4&T3);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[30]&~pla[13])&(M4&T3);
ctl_sw_2d = ctl_sw_2d | (pla[30]&~pla[13])&(M4&T3);
ctl_sw_1d = ctl_sw_1d | (pla[30]&~pla[13])&(M4&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[30]&~pla[13])&(M4&T3);
fMRead = fMRead | (pla[30]&~pla[13])&(M5&T1);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&~pla[13])&(M5&T1);
ctl_reg_sys_hilo_pla30npla13M5T1_3 = (pla[30]&~pla[13])&(M5&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30npla13M5T1_3,ctl_reg_sys_hilo_pla30npla13M5T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[30]&~pla[13])&(M5&T1);
ctl_al_we = ctl_al_we | (pla[30]&~pla[13])&(M5&T1);
fMRead = fMRead | (pla[30]&~pla[13])&(M5&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[30]&~pla[13])&(M5&T2);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&~pla[13])&(M5&T2);
ctl_reg_sys_hilo_pla30npla13M5T2_4 = (pla[30]&~pla[13])&(M5&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30npla13M5T2_4,ctl_reg_sys_hilo_pla30npla13M5T2_4})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[30]&~pla[13])&(M5&T2);
ctl_inc_cy = ctl_inc_cy | (pla[30]&~pla[13])&(M5&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[30]&~pla[13])&(M5&T2);
fMRead = fMRead | (pla[30]&~pla[13])&(M5&T3);
setM1 = setM1 | (pla[30]&~pla[13])&(M5&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[30]&~pla[13])&(M5&T3);
ctl_reg_gp_sel_pla30npla13M5T3_4 = (pla[30]&~pla[13])&(M5&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla30npla13M5T3_4,ctl_reg_gp_sel_pla30npla13M5T3_4})&(op54);
ctl_reg_gp_hilo_pla30npla13M5T3_5 = (pla[30]&~pla[13])&(M5&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla30npla13M5T3_5,ctl_reg_gp_hilo_pla30npla13M5T3_5})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[30]&~pla[13])&(M5&T3);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[30]&~pla[13])&(M5&T3);
ctl_sw_2d = ctl_sw_2d | (pla[30]&~pla[13])&(M5&T3);
ctl_sw_1d = ctl_sw_1d | (pla[30]&~pla[13])&(M5&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[30]&~pla[13])&(M5&T3);
validPLA = validPLA | (pla[31]&pla[33])&(M1&T4);
nextM = nextM | (pla[31]&pla[33])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[31]&pla[33])&(M1&T4);
fMRead = fMRead | (pla[31]&pla[33])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[31]&pla[33])&(M2&T1);
ctl_reg_sys_hilo_pla31pla33M2T1_3 = (pla[31]&pla[33])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31pla33M2T1_3,ctl_reg_sys_hilo_pla31pla33M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[31]&pla[33])&(M2&T1);
fMRead = fMRead | (pla[31]&pla[33])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[31]&pla[33])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[31]&pla[33])&(M2&T2);
ctl_reg_sys_hilo_pla31pla33M2T2_4 = (pla[31]&pla[33])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31pla33M2T2_4,ctl_reg_sys_hilo_pla31pla33M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[31]&pla[33])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[31]&pla[33])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[31]&pla[33])&(M2&T2);
fMRead = fMRead | (pla[31]&pla[33])&(M2&T3);
nextM = nextM | (pla[31]&pla[33])&(M2&T3);
ctl_mRead = ctl_mRead | (pla[31]&pla[33])&(M2&T3);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[31]&pla[33])&(M2&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&pla[33])&(M2&T3);
ctl_reg_sys_hilo_pla31pla33M2T3_6 = (pla[31]&pla[33])&(M2&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31pla33M2T3_6,ctl_reg_sys_hilo_pla31pla33M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (pla[31]&pla[33])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[31]&pla[33])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (pla[31]&pla[33])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[31]&pla[33])&(M2&T3);
fMRead = fMRead | (pla[31]&pla[33])&(M3&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[31]&pla[33])&(M3&T1);
ctl_reg_sys_hilo_pla31pla33M3T1_3 = (pla[31]&pla[33])&(M3&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31pla33M3T1_3,ctl_reg_sys_hilo_pla31pla33M3T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[31]&pla[33])&(M3&T1);
fMRead = fMRead | (pla[31]&pla[33])&(M3&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[31]&pla[33])&(M3&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[31]&pla[33])&(M3&T2);
ctl_reg_sys_hilo_pla31pla33M3T2_4 = (pla[31]&pla[33])&(M3&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31pla33M3T2_4,ctl_reg_sys_hilo_pla31pla33M3T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[31]&pla[33])&(M3&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[31]&pla[33])&(M3&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[31]&pla[33])&(M3&T2);
fMRead = fMRead | (pla[31]&pla[33])&(M3&T3);
nextM = nextM | (pla[31]&pla[33])&(M3&T3);
ctl_mWrite = ctl_mWrite | (pla[31]&pla[33])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&pla[33])&(M3&T3);
ctl_reg_sys_hilo_pla31pla33M3T3_5 = (pla[31]&pla[33])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31pla33M3T3_5,ctl_reg_sys_hilo_pla31pla33M3T3_5})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[31]&pla[33])&(M3&T3);
ctl_al_we = ctl_al_we | (pla[31]&pla[33])&(M3&T3);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[31]&pla[33])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&pla[33])&(M3&T3);
ctl_reg_sys_hilo_pla31pla33M3T3_10 = (pla[31]&pla[33])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31pla33M3T3_10,ctl_reg_sys_hilo_pla31pla33M3T3_10})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[31]&pla[33])&(M3&T3);
ctl_sw_2d = ctl_sw_2d | (pla[31]&pla[33])&(M3&T3);
ctl_sw_1d = ctl_sw_1d | (pla[31]&pla[33])&(M3&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[31]&pla[33])&(M3&T3);
fMWrite = fMWrite | (pla[31]&pla[33])&(M4&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[31]&pla[33])&(M4&T1);
ctl_reg_gp_sel_pla31pla33M4T1_3 = (pla[31]&pla[33])&(M4&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla31pla33M4T1_3,ctl_reg_gp_sel_pla31pla33M4T1_3})&(op54);
ctl_reg_gp_hilo_pla31pla33M4T1_4 = (pla[31]&pla[33])&(M4&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla31pla33M4T1_4,ctl_reg_gp_hilo_pla31pla33M4T1_4})&(2'b01);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[31]&pla[33])&(M4&T1);
ctl_sw_1u = ctl_sw_1u | (pla[31]&pla[33])&(M4&T1);
ctl_bus_db_we = ctl_bus_db_we | (pla[31]&pla[33])&(M4&T1);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[31]&pla[33])&(M4&T1);
fMWrite = fMWrite | (pla[31]&pla[33])&(M4&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[31]&pla[33])&(M4&T2);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&pla[33])&(M4&T2);
ctl_reg_sys_hilo_pla31pla33M4T2_4 = (pla[31]&pla[33])&(M4&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31pla33M4T2_4,ctl_reg_sys_hilo_pla31pla33M4T2_4})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[31]&pla[33])&(M4&T2);
ctl_inc_cy = ctl_inc_cy | (pla[31]&pla[33])&(M4&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[31]&pla[33])&(M4&T2);
fMWrite = fMWrite | (pla[31]&pla[33])&(M4&T3);
nextM = nextM | (pla[31]&pla[33])&(M4&T3);
ctl_mWrite = ctl_mWrite | (pla[31]&pla[33])&(M4&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&pla[33])&(M4&T3);
ctl_reg_sys_hilo_pla31pla33M4T3_5 = (pla[31]&pla[33])&(M4&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31pla33M4T3_5,ctl_reg_sys_hilo_pla31pla33M4T3_5})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[31]&pla[33])&(M4&T3);
ctl_al_we = ctl_al_we | (pla[31]&pla[33])&(M4&T3);
fMWrite = fMWrite | (pla[31]&pla[33])&(M5&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[31]&pla[33])&(M5&T1);
ctl_reg_gp_sel_pla31pla33M5T1_3 = (pla[31]&pla[33])&(M5&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla31pla33M5T1_3,ctl_reg_gp_sel_pla31pla33M5T1_3})&(op54);
ctl_reg_gp_hilo_pla31pla33M5T1_4 = (pla[31]&pla[33])&(M5&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla31pla33M5T1_4,ctl_reg_gp_hilo_pla31pla33M5T1_4})&(2'b10);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[31]&pla[33])&(M5&T1);
ctl_sw_2u = ctl_sw_2u | (pla[31]&pla[33])&(M5&T1);
ctl_sw_1u = ctl_sw_1u | (pla[31]&pla[33])&(M5&T1);
ctl_bus_db_we = ctl_bus_db_we | (pla[31]&pla[33])&(M5&T1);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[31]&pla[33])&(M5&T1);
fMWrite = fMWrite | (pla[31]&pla[33])&(M5&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[31]&pla[33])&(M5&T2);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&pla[33])&(M5&T2);
ctl_reg_sys_hilo_pla31pla33M5T2_4 = (pla[31]&pla[33])&(M5&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31pla33M5T2_4,ctl_reg_sys_hilo_pla31pla33M5T2_4})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[31]&pla[33])&(M5&T2);
ctl_inc_cy = ctl_inc_cy | (pla[31]&pla[33])&(M5&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[31]&pla[33])&(M5&T2);
fMWrite = fMWrite | (pla[31]&pla[33])&(M5&T3);
setM1 = setM1 | (pla[31]&pla[33])&(M5&T3);
validPLA = validPLA | (pla[31]&~pla[33])&(M1&T4);
nextM = nextM | (pla[31]&~pla[33])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[31]&~pla[33])&(M1&T4);
fMRead = fMRead | (pla[31]&~pla[33])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[31]&~pla[33])&(M2&T1);
ctl_reg_sys_hilo_pla31npla33M2T1_3 = (pla[31]&~pla[33])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31npla33M2T1_3,ctl_reg_sys_hilo_pla31npla33M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[31]&~pla[33])&(M2&T1);
fMRead = fMRead | (pla[31]&~pla[33])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[31]&~pla[33])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[31]&~pla[33])&(M2&T2);
ctl_reg_sys_hilo_pla31npla33M2T2_4 = (pla[31]&~pla[33])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31npla33M2T2_4,ctl_reg_sys_hilo_pla31npla33M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[31]&~pla[33])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[31]&~pla[33])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[31]&~pla[33])&(M2&T2);
fMRead = fMRead | (pla[31]&~pla[33])&(M2&T3);
nextM = nextM | (pla[31]&~pla[33])&(M2&T3);
ctl_mRead = ctl_mRead | (pla[31]&~pla[33])&(M2&T3);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[31]&~pla[33])&(M2&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&~pla[33])&(M2&T3);
ctl_reg_sys_hilo_pla31npla33M2T3_6 = (pla[31]&~pla[33])&(M2&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31npla33M2T3_6,ctl_reg_sys_hilo_pla31npla33M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (pla[31]&~pla[33])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[31]&~pla[33])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (pla[31]&~pla[33])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[31]&~pla[33])&(M2&T3);
fMRead = fMRead | (pla[31]&~pla[33])&(M3&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[31]&~pla[33])&(M3&T1);
ctl_reg_sys_hilo_pla31npla33M3T1_3 = (pla[31]&~pla[33])&(M3&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31npla33M3T1_3,ctl_reg_sys_hilo_pla31npla33M3T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[31]&~pla[33])&(M3&T1);
fMRead = fMRead | (pla[31]&~pla[33])&(M3&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[31]&~pla[33])&(M3&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[31]&~pla[33])&(M3&T2);
ctl_reg_sys_hilo_pla31npla33M3T2_4 = (pla[31]&~pla[33])&(M3&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31npla33M3T2_4,ctl_reg_sys_hilo_pla31npla33M3T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[31]&~pla[33])&(M3&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[31]&~pla[33])&(M3&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[31]&~pla[33])&(M3&T2);
fMRead = fMRead | (pla[31]&~pla[33])&(M3&T3);
nextM = nextM | (pla[31]&~pla[33])&(M3&T3);
ctl_mRead = ctl_mRead | (pla[31]&~pla[33])&(M3&T3);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[31]&~pla[33])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&~pla[33])&(M3&T3);
ctl_reg_sys_hilo_pla31npla33M3T3_6 = (pla[31]&~pla[33])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31npla33M3T3_6,ctl_reg_sys_hilo_pla31npla33M3T3_6})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[31]&~pla[33])&(M3&T3);
ctl_sw_2d = ctl_sw_2d | (pla[31]&~pla[33])&(M3&T3);
ctl_sw_1d = ctl_sw_1d | (pla[31]&~pla[33])&(M3&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[31]&~pla[33])&(M3&T3);
fMRead = fMRead | (pla[31]&~pla[33])&(M4&T1);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&~pla[33])&(M4&T1);
ctl_reg_sys_hilo_pla31npla33M4T1_3 = (pla[31]&~pla[33])&(M4&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31npla33M4T1_3,ctl_reg_sys_hilo_pla31npla33M4T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[31]&~pla[33])&(M4&T1);
ctl_al_we = ctl_al_we | (pla[31]&~pla[33])&(M4&T1);
fMRead = fMRead | (pla[31]&~pla[33])&(M4&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[31]&~pla[33])&(M4&T2);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&~pla[33])&(M4&T2);
ctl_reg_sys_hilo_pla31npla33M4T2_4 = (pla[31]&~pla[33])&(M4&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31npla33M4T2_4,ctl_reg_sys_hilo_pla31npla33M4T2_4})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[31]&~pla[33])&(M4&T2);
ctl_inc_cy = ctl_inc_cy | (pla[31]&~pla[33])&(M4&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[31]&~pla[33])&(M4&T2);
fMRead = fMRead | (pla[31]&~pla[33])&(M4&T3);
nextM = nextM | (pla[31]&~pla[33])&(M4&T3);
ctl_mRead = ctl_mRead | (pla[31]&~pla[33])&(M4&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[31]&~pla[33])&(M4&T3);
ctl_reg_gp_sel_pla31npla33M4T3_5 = (pla[31]&~pla[33])&(M4&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla31npla33M4T3_5,ctl_reg_gp_sel_pla31npla33M4T3_5})&(op54);
ctl_reg_gp_hilo_pla31npla33M4T3_6 = (pla[31]&~pla[33])&(M4&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla31npla33M4T3_6,ctl_reg_gp_hilo_pla31npla33M4T3_6})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[31]&~pla[33])&(M4&T3);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[31]&~pla[33])&(M4&T3);
ctl_sw_2d = ctl_sw_2d | (pla[31]&~pla[33])&(M4&T3);
ctl_sw_1d = ctl_sw_1d | (pla[31]&~pla[33])&(M4&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[31]&~pla[33])&(M4&T3);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[31]&~pla[33])&(M4&T3);
fMRead = fMRead | (pla[31]&~pla[33])&(M5&T1);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&~pla[33])&(M5&T1);
ctl_reg_sys_hilo_pla31npla33M5T1_3 = (pla[31]&~pla[33])&(M5&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31npla33M5T1_3,ctl_reg_sys_hilo_pla31npla33M5T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[31]&~pla[33])&(M5&T1);
ctl_al_we = ctl_al_we | (pla[31]&~pla[33])&(M5&T1);
fMRead = fMRead | (pla[31]&~pla[33])&(M5&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[31]&~pla[33])&(M5&T2);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&~pla[33])&(M5&T2);
ctl_reg_sys_hilo_pla31npla33M5T2_4 = (pla[31]&~pla[33])&(M5&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31npla33M5T2_4,ctl_reg_sys_hilo_pla31npla33M5T2_4})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[31]&~pla[33])&(M5&T2);
ctl_inc_cy = ctl_inc_cy | (pla[31]&~pla[33])&(M5&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[31]&~pla[33])&(M5&T2);
fMRead = fMRead | (pla[31]&~pla[33])&(M5&T3);
setM1 = setM1 | (pla[31]&~pla[33])&(M5&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[31]&~pla[33])&(M5&T3);
ctl_reg_gp_sel_pla31npla33M5T3_4 = (pla[31]&~pla[33])&(M5&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla31npla33M5T3_4,ctl_reg_gp_sel_pla31npla33M5T3_4})&(op54);
ctl_reg_gp_hilo_pla31npla33M5T3_5 = (pla[31]&~pla[33])&(M5&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla31npla33M5T3_5,ctl_reg_gp_hilo_pla31npla33M5T3_5})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[31]&~pla[33])&(M5&T3);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[31]&~pla[33])&(M5&T3);
ctl_sw_2d = ctl_sw_2d | (pla[31]&~pla[33])&(M5&T3);
ctl_sw_1d = ctl_sw_1d | (pla[31]&~pla[33])&(M5&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[31]&~pla[33])&(M5&T3);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[31]&~pla[33])&(M5&T3);
validPLA = validPLA | (pla[5])&(M1&T4);
ctl_reg_gp_sel_pla5M1T4_2 = (pla[5])&(M1&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla5M1T4_2,ctl_reg_gp_sel_pla5M1T4_2})&(`GP_REG_HL);
ctl_reg_gp_hilo_pla5M1T4_3 = (pla[5])&(M1&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla5M1T4_3,ctl_reg_gp_hilo_pla5M1T4_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[5])&(M1&T4);
ctl_al_we = ctl_al_we | (pla[5])&(M1&T4);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[5])&(M1&T5);
ctl_reg_gp_sel_pla5M1T5_2 = (pla[5])&(M1&T5);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla5M1T5_2,ctl_reg_gp_sel_pla5M1T5_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla5M1T5_3 = (pla[5])&(M1&T5);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla5M1T5_3,ctl_reg_gp_hilo_pla5M1T5_3})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[5])&(M1&T5);
ctl_sw_4u = ctl_sw_4u | (pla[5])&(M1&T5);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[5])&(M1&T5);
setM1 = setM1 | (pla[5])&(M1&T6);
validPLA = validPLA | (pla[23]&pla[16])&(M1&T4);
nextM = nextM | (pla[23]&pla[16])&(M1&T5);
ctl_mWrite = ctl_mWrite | (pla[23]&pla[16])&(M1&T5);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[23]&pla[16])&(M1&T5);
ctl_reg_gp_sel_pla23pla16M1T5_4 = (pla[23]&pla[16])&(M1&T5);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23pla16M1T5_4,ctl_reg_gp_sel_pla23pla16M1T5_4})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla23pla16M1T5_5 = (pla[23]&pla[16])&(M1&T5);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23pla16M1T5_5,ctl_reg_gp_hilo_pla23pla16M1T5_5})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[23]&pla[16])&(M1&T5);
ctl_inc_cy = ctl_inc_cy | (pla[23]&pla[16])&(M1&T5)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[23]&pla[16])&(M1&T5);
ctl_al_we = ctl_al_we | (pla[23]&pla[16])&(M1&T5);
fMWrite = fMWrite | (pla[23]&pla[16])&(M2&T1);
ctl_inc_cy = ctl_inc_cy | (pla[23]&pla[16])&(M2&T1)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[23]&pla[16])&(M2&T1);
ctl_apin_mux = ctl_apin_mux | (pla[23]&pla[16])&(M2&T1);
ctl_reg_gp_sel_pla23pla16M2T1_5 = (pla[23]&pla[16])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23pla16M2T1_5,ctl_reg_gp_sel_pla23pla16M2T1_5})&(op54);
ctl_reg_gp_hilo_pla23pla16M2T1_6 = (pla[23]&pla[16])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23pla16M2T1_6,ctl_reg_gp_hilo_pla23pla16M2T1_6})&(2'b10);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[23]&pla[16])&(M2&T1);
ctl_sw_2u = ctl_sw_2u | (pla[23]&pla[16])&(M2&T1);
ctl_sw_1u = ctl_sw_1u | (pla[23]&pla[16])&(M2&T1);
ctl_bus_db_we = ctl_bus_db_we | (pla[23]&pla[16])&(M2&T1);
fMWrite = fMWrite | (pla[23]&pla[16])&(M2&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[23]&pla[16])&(M2&T2);
ctl_reg_gp_sel_pla23pla16M2T2_3 = (pla[23]&pla[16])&(M2&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23pla16M2T2_3,ctl_reg_gp_sel_pla23pla16M2T2_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla23pla16M2T2_4 = (pla[23]&pla[16])&(M2&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23pla16M2T2_4,ctl_reg_gp_hilo_pla23pla16M2T2_4})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[23]&pla[16])&(M2&T2);
ctl_sw_4u = ctl_sw_4u | (pla[23]&pla[16])&(M2&T2);
ctl_inc_cy = ctl_inc_cy | (pla[23]&pla[16])&(M2&T2)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[23]&pla[16])&(M2&T2);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[23]&pla[16])&(M2&T2);
fMWrite = fMWrite | (pla[23]&pla[16])&(M2&T3);
nextM = nextM | (pla[23]&pla[16])&(M2&T3);
ctl_mWrite = ctl_mWrite | (pla[23]&pla[16])&(M2&T3);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[23]&pla[16])&(M2&T3);
ctl_reg_gp_sel_pla23pla16M2T3_5 = (pla[23]&pla[16])&(M2&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23pla16M2T3_5,ctl_reg_gp_sel_pla23pla16M2T3_5})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla23pla16M2T3_6 = (pla[23]&pla[16])&(M2&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23pla16M2T3_6,ctl_reg_gp_hilo_pla23pla16M2T3_6})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[23]&pla[16])&(M2&T3);
ctl_inc_cy = ctl_inc_cy | (pla[23]&pla[16])&(M2&T3)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[23]&pla[16])&(M2&T3);
ctl_al_we = ctl_al_we | (pla[23]&pla[16])&(M2&T3);
fMWrite = fMWrite | (pla[23]&pla[16])&(M3&T1);
ctl_inc_cy = ctl_inc_cy | (pla[23]&pla[16])&(M3&T1)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[23]&pla[16])&(M3&T1);
ctl_apin_mux = ctl_apin_mux | (pla[23]&pla[16])&(M3&T1);
ctl_reg_gp_sel_pla23pla16M3T1_5 = (pla[23]&pla[16])&(M3&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23pla16M3T1_5,ctl_reg_gp_sel_pla23pla16M3T1_5})&(op54);
ctl_reg_gp_hilo_pla23pla16M3T1_6 = (pla[23]&pla[16])&(M3&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23pla16M3T1_6,ctl_reg_gp_hilo_pla23pla16M3T1_6})&(2'b01);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[23]&pla[16])&(M3&T1);
ctl_sw_1u = ctl_sw_1u | (pla[23]&pla[16])&(M3&T1);
ctl_bus_db_we = ctl_bus_db_we | (pla[23]&pla[16])&(M3&T1);
fMWrite = fMWrite | (pla[23]&pla[16])&(M3&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[23]&pla[16])&(M3&T2);
ctl_reg_gp_sel_pla23pla16M3T2_3 = (pla[23]&pla[16])&(M3&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23pla16M3T2_3,ctl_reg_gp_sel_pla23pla16M3T2_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla23pla16M3T2_4 = (pla[23]&pla[16])&(M3&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23pla16M3T2_4,ctl_reg_gp_hilo_pla23pla16M3T2_4})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[23]&pla[16])&(M3&T2);
ctl_sw_4u = ctl_sw_4u | (pla[23]&pla[16])&(M3&T2);
ctl_inc_cy = ctl_inc_cy | (pla[23]&pla[16])&(M3&T2)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[23]&pla[16])&(M3&T2);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[23]&pla[16])&(M3&T2);
fMWrite = fMWrite | (pla[23]&pla[16])&(M3&T3);
setM1 = setM1 | (pla[23]&pla[16])&(M3&T3);
validPLA = validPLA | (pla[23]&~pla[16])&(M1&T4);
nextM = nextM | (pla[23]&~pla[16])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[23]&~pla[16])&(M1&T4);
fMRead = fMRead | (pla[23]&~pla[16])&(M2&T1);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[23]&~pla[16])&(M2&T1);
ctl_reg_gp_sel_pla23npla16M2T1_3 = (pla[23]&~pla[16])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23npla16M2T1_3,ctl_reg_gp_sel_pla23npla16M2T1_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla23npla16M2T1_4 = (pla[23]&~pla[16])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23npla16M2T1_4,ctl_reg_gp_hilo_pla23npla16M2T1_4})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[23]&~pla[16])&(M2&T1);
ctl_al_we = ctl_al_we | (pla[23]&~pla[16])&(M2&T1);
fMRead = fMRead | (pla[23]&~pla[16])&(M2&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[23]&~pla[16])&(M2&T2);
ctl_reg_gp_sel_pla23npla16M2T2_3 = (pla[23]&~pla[16])&(M2&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23npla16M2T2_3,ctl_reg_gp_sel_pla23npla16M2T2_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla23npla16M2T2_4 = (pla[23]&~pla[16])&(M2&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23npla16M2T2_4,ctl_reg_gp_hilo_pla23npla16M2T2_4})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[23]&~pla[16])&(M2&T2);
ctl_sw_4u = ctl_sw_4u | (pla[23]&~pla[16])&(M2&T2);
ctl_inc_cy = ctl_inc_cy | (pla[23]&~pla[16])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[23]&~pla[16])&(M2&T2);
fMRead = fMRead | (pla[23]&~pla[16])&(M2&T3);
nextM = nextM | (pla[23]&~pla[16])&(M2&T3);
ctl_mRead = ctl_mRead | (pla[23]&~pla[16])&(M2&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[23]&~pla[16])&(M2&T3);
ctl_reg_gp_sel_pla23npla16M2T3_5 = (pla[23]&~pla[16])&(M2&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23npla16M2T3_5,ctl_reg_gp_sel_pla23npla16M2T3_5})&(op54);
ctl_reg_gp_hilo_pla23npla16M2T3_6 = (pla[23]&~pla[16])&(M2&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23npla16M2T3_6,ctl_reg_gp_hilo_pla23npla16M2T3_6})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[23]&~pla[16])&(M2&T3);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[23]&~pla[16])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[23]&~pla[16])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (pla[23]&~pla[16])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[23]&~pla[16])&(M2&T3);
fMRead = fMRead | (pla[23]&~pla[16])&(M3&T1);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[23]&~pla[16])&(M3&T1);
ctl_reg_gp_sel_pla23npla16M3T1_3 = (pla[23]&~pla[16])&(M3&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23npla16M3T1_3,ctl_reg_gp_sel_pla23npla16M3T1_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla23npla16M3T1_4 = (pla[23]&~pla[16])&(M3&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23npla16M3T1_4,ctl_reg_gp_hilo_pla23npla16M3T1_4})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[23]&~pla[16])&(M3&T1);
ctl_al_we = ctl_al_we | (pla[23]&~pla[16])&(M3&T1);
fMRead = fMRead | (pla[23]&~pla[16])&(M3&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[23]&~pla[16])&(M3&T2);
ctl_reg_gp_sel_pla23npla16M3T2_3 = (pla[23]&~pla[16])&(M3&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23npla16M3T2_3,ctl_reg_gp_sel_pla23npla16M3T2_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla23npla16M3T2_4 = (pla[23]&~pla[16])&(M3&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23npla16M3T2_4,ctl_reg_gp_hilo_pla23npla16M3T2_4})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[23]&~pla[16])&(M3&T2);
ctl_sw_4u = ctl_sw_4u | (pla[23]&~pla[16])&(M3&T2);
ctl_inc_cy = ctl_inc_cy | (pla[23]&~pla[16])&(M3&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[23]&~pla[16])&(M3&T2);
fMRead = fMRead | (pla[23]&~pla[16])&(M3&T3);
setM1 = setM1 | (pla[23]&~pla[16])&(M3&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[23]&~pla[16])&(M3&T3);
ctl_reg_gp_sel_pla23npla16M3T3_4 = (pla[23]&~pla[16])&(M3&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23npla16M3T3_4,ctl_reg_gp_sel_pla23npla16M3T3_4})&(op54);
ctl_reg_gp_hilo_pla23npla16M3T3_5 = (pla[23]&~pla[16])&(M3&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23npla16M3T3_5,ctl_reg_gp_hilo_pla23npla16M3T3_5})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[23]&~pla[16])&(M3&T3);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[23]&~pla[16])&(M3&T3);
ctl_sw_2d = ctl_sw_2d | (pla[23]&~pla[16])&(M3&T3);
ctl_sw_1d = ctl_sw_1d | (pla[23]&~pla[16])&(M3&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[23]&~pla[16])&(M3&T3);
ctl_reg_ex_de_hl = ctl_reg_ex_de_hl | (pla[2])&(M1&T2);
validPLA = validPLA | (pla[2])&(M1&T4);
setM1 = setM1 | (pla[2])&(M1&T4);
ctl_reg_ex_af = ctl_reg_ex_af | (pla[39])&(M1&T2);
validPLA = validPLA | (pla[39])&(M1&T4);
setM1 = setM1 | (pla[39])&(M1&T4);
ctl_reg_exx = ctl_reg_exx | (pla[1])&(M1&T2);
validPLA = validPLA | (pla[1])&(M1&T4);
setM1 = setM1 | (pla[1])&(M1&T4);
validPLA = validPLA | (pla[10])&(M1&T4);
nextM = nextM | (pla[10])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[10])&(M1&T4);
fMRead = fMRead | (pla[10])&(M2&T1);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[10])&(M2&T1);
ctl_reg_gp_sel_pla10M2T1_3 = (pla[10])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M2T1_3,ctl_reg_gp_sel_pla10M2T1_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla10M2T1_4 = (pla[10])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M2T1_4,ctl_reg_gp_hilo_pla10M2T1_4})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[10])&(M2&T1);
ctl_al_we = ctl_al_we | (pla[10])&(M2&T1);
fMRead = fMRead | (pla[10])&(M2&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[10])&(M2&T2);
ctl_reg_gp_sel_pla10M2T2_3 = (pla[10])&(M2&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M2T2_3,ctl_reg_gp_sel_pla10M2T2_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla10M2T2_4 = (pla[10])&(M2&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M2T2_4,ctl_reg_gp_hilo_pla10M2T2_4})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[10])&(M2&T2);
ctl_sw_4u = ctl_sw_4u | (pla[10])&(M2&T2);
ctl_inc_cy = ctl_inc_cy | (pla[10])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[10])&(M2&T2);
fMRead = fMRead | (pla[10])&(M2&T3);
nextM = nextM | (pla[10])&(M2&T3);
ctl_mRead = ctl_mRead | (pla[10])&(M2&T3);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[10])&(M2&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[10])&(M2&T3);
ctl_reg_sys_hilo_pla10M2T3_6 = (pla[10])&(M2&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla10M2T3_6,ctl_reg_sys_hilo_pla10M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (pla[10])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[10])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (pla[10])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[10])&(M2&T3);
fMRead = fMRead | (pla[10])&(M3&T1);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[10])&(M3&T1);
ctl_reg_gp_sel_pla10M3T1_3 = (pla[10])&(M3&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M3T1_3,ctl_reg_gp_sel_pla10M3T1_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla10M3T1_4 = (pla[10])&(M3&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M3T1_4,ctl_reg_gp_hilo_pla10M3T1_4})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[10])&(M3&T1);
ctl_al_we = ctl_al_we | (pla[10])&(M3&T1);
fMRead = fMRead | (pla[10])&(M3&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[10])&(M3&T2);
ctl_reg_gp_sel_pla10M3T2_3 = (pla[10])&(M3&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M3T2_3,ctl_reg_gp_sel_pla10M3T2_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla10M3T2_4 = (pla[10])&(M3&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M3T2_4,ctl_reg_gp_hilo_pla10M3T2_4})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[10])&(M3&T2);
ctl_sw_4u = ctl_sw_4u | (pla[10])&(M3&T2);
ctl_inc_cy = ctl_inc_cy | (pla[10])&(M3&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[10])&(M3&T2);
fMRead = fMRead | (pla[10])&(M3&T3);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[10])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[10])&(M3&T3);
ctl_reg_sys_hilo_pla10M3T3_4 = (pla[10])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla10M3T3_4,ctl_reg_sys_hilo_pla10M3T3_4})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[10])&(M3&T3);
ctl_sw_2d = ctl_sw_2d | (pla[10])&(M3&T3);
ctl_sw_1d = ctl_sw_1d | (pla[10])&(M3&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[10])&(M3&T3);
nextM = nextM | (pla[10])&(M3&T4);
ctl_mWrite = ctl_mWrite | (pla[10])&(M3&T4);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[10])&(M3&T4);
ctl_reg_gp_sel_pla10M3T4_4 = (pla[10])&(M3&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M3T4_4,ctl_reg_gp_sel_pla10M3T4_4})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla10M3T4_5 = (pla[10])&(M3&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M3T4_5,ctl_reg_gp_hilo_pla10M3T4_5})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[10])&(M3&T4);
ctl_inc_cy = ctl_inc_cy | (pla[10])&(M3&T4)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[10])&(M3&T4);
ctl_al_we = ctl_al_we | (pla[10])&(M3&T4);
fMWrite = fMWrite | (pla[10])&(M4&T1);
ctl_inc_cy = ctl_inc_cy | (pla[10])&(M4&T1)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[10])&(M4&T1);
ctl_apin_mux = ctl_apin_mux | (pla[10])&(M4&T1);
ctl_reg_gp_sel_pla10M4T1_5 = (pla[10])&(M4&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M4T1_5,ctl_reg_gp_sel_pla10M4T1_5})&(op54);
ctl_reg_gp_hilo_pla10M4T1_6 = (pla[10])&(M4&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M4T1_6,ctl_reg_gp_hilo_pla10M4T1_6})&(2'b10);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[10])&(M4&T1);
ctl_sw_2u = ctl_sw_2u | (pla[10])&(M4&T1);
ctl_sw_1u = ctl_sw_1u | (pla[10])&(M4&T1);
ctl_bus_db_we = ctl_bus_db_we | (pla[10])&(M4&T1);
fMWrite = fMWrite | (pla[10])&(M4&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[10])&(M4&T2);
ctl_reg_gp_sel_pla10M4T2_3 = (pla[10])&(M4&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M4T2_3,ctl_reg_gp_sel_pla10M4T2_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla10M4T2_4 = (pla[10])&(M4&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M4T2_4,ctl_reg_gp_hilo_pla10M4T2_4})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[10])&(M4&T2);
ctl_sw_4u = ctl_sw_4u | (pla[10])&(M4&T2);
ctl_inc_cy = ctl_inc_cy | (pla[10])&(M4&T2)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[10])&(M4&T2);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[10])&(M4&T2);
fMWrite = fMWrite | (pla[10])&(M4&T3);
nextM = nextM | (pla[10])&(M4&T3);
ctl_mWrite = ctl_mWrite | (pla[10])&(M4&T3);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[10])&(M4&T3);
ctl_reg_gp_sel_pla10M4T3_5 = (pla[10])&(M4&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M4T3_5,ctl_reg_gp_sel_pla10M4T3_5})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla10M4T3_6 = (pla[10])&(M4&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M4T3_6,ctl_reg_gp_hilo_pla10M4T3_6})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[10])&(M4&T3);
ctl_inc_cy = ctl_inc_cy | (pla[10])&(M4&T3)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[10])&(M4&T3);
ctl_al_we = ctl_al_we | (pla[10])&(M4&T3);
fMWrite = fMWrite | (pla[10])&(M5&T1);
ctl_inc_cy = ctl_inc_cy | (pla[10])&(M5&T1)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[10])&(M5&T1);
ctl_apin_mux = ctl_apin_mux | (pla[10])&(M5&T1);
ctl_reg_gp_sel_pla10M5T1_5 = (pla[10])&(M5&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M5T1_5,ctl_reg_gp_sel_pla10M5T1_5})&(op54);
ctl_reg_gp_hilo_pla10M5T1_6 = (pla[10])&(M5&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M5T1_6,ctl_reg_gp_hilo_pla10M5T1_6})&(2'b01);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[10])&(M5&T1);
ctl_sw_1u = ctl_sw_1u | (pla[10])&(M5&T1);
ctl_bus_db_we = ctl_bus_db_we | (pla[10])&(M5&T1);
fMWrite = fMWrite | (pla[10])&(M5&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[10])&(M5&T2);
ctl_reg_gp_sel_pla10M5T2_3 = (pla[10])&(M5&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M5T2_3,ctl_reg_gp_sel_pla10M5T2_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla10M5T2_4 = (pla[10])&(M5&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M5T2_4,ctl_reg_gp_hilo_pla10M5T2_4})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[10])&(M5&T2);
ctl_sw_4u = ctl_sw_4u | (pla[10])&(M5&T2);
ctl_inc_cy = ctl_inc_cy | (pla[10])&(M5&T2)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[10])&(M5&T2);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[10])&(M5&T2);
fMWrite = fMWrite | (pla[10])&(M5&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[10])&(M5&T3);
ctl_reg_sys_hilo_pla10M5T3_3 = (pla[10])&(M5&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla10M5T3_3,ctl_reg_sys_hilo_pla10M5T3_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[10])&(M5&T3);
ctl_al_we = ctl_al_we | (pla[10])&(M5&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[10])&(M5&T4);
ctl_reg_gp_sel_pla10M5T4_2 = (pla[10])&(M5&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M5T4_2,ctl_reg_gp_sel_pla10M5T4_2})&(`GP_REG_HL);
ctl_reg_gp_hilo_pla10M5T4_3 = (pla[10])&(M5&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M5T4_3,ctl_reg_gp_hilo_pla10M5T4_3})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[10])&(M5&T4);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[10])&(M5&T4);
setM1 = setM1 | (pla[10])&(M5&T5);
nonRep = nonRep | (pla[0]);
ctl_flags_alu = ctl_flags_alu | (pla[12])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[12])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[12])&(M1&T1);
ctl_alu_core_R = ctl_alu_core_R | (pla[12])&(M1&T1);
ctl_alu_core_V = ctl_alu_core_V | (pla[12])&(M1&T1);
ctl_alu_core_S = ctl_alu_core_S | (pla[12])&(M1&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[12])&(M1&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[12])&(M1&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[12])&(M1&T1);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[12])&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[12])&(M1&T1);
ctl_pf_sel_pla12M1T1_12 = (pla[12])&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla12M1T1_12,ctl_pf_sel_pla12M1T1_12})&(`PFSEL_REP);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[12])&(M1&T1);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[12])&(M1&T1);
ctl_flags_use_cf2 = ctl_flags_use_cf2 | (pla[12])&(M1&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[12])&(M1&T2);
ctl_reg_gp_sel_pla12M1T2_2 = (pla[12])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla12M1T2_2,ctl_reg_gp_sel_pla12M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla12M1T2_3 = (pla[12])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla12M1T2_3,ctl_reg_gp_hilo_pla12M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[12])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[12])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (pla[12])&(M1&T2);
ctl_reg_gp_sel_pla12M1T3_1 = (pla[12])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla12M1T3_1,ctl_reg_gp_sel_pla12M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla12M1T3_2 = (pla[12])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla12M1T3_2,ctl_reg_gp_hilo_pla12M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[12])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[12])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[12])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[12])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[12])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[12])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[12])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[12])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[12])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[12])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[12])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[12])&(M1&T3);
validPLA = validPLA | (pla[12])&(M1&T4);
nextM = nextM | (pla[12])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[12])&(M1&T4);
fMRead = fMRead | (pla[12])&(M2&T1);
ctl_reg_gp_sel_pla12M2T1_2 = (pla[12])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla12M2T1_2,ctl_reg_gp_sel_pla12M2T1_2})&(`GP_REG_HL);
ctl_reg_gp_hilo_pla12M2T1_3 = (pla[12])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla12M2T1_3,ctl_reg_gp_hilo_pla12M2T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[12])&(M2&T1);
ctl_al_we = ctl_al_we | (pla[12])&(M2&T1);
fMRead = fMRead | (pla[12])&(M2&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[12])&(M2&T2);
ctl_reg_gp_sel_pla12M2T2_3 = (pla[12])&(M2&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla12M2T2_3,ctl_reg_gp_sel_pla12M2T2_3})&(`GP_REG_HL);
ctl_reg_gp_hilo_pla12M2T2_4 = (pla[12])&(M2&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla12M2T2_4,ctl_reg_gp_hilo_pla12M2T2_4})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[12])&(M2&T2);
ctl_inc_cy = ctl_inc_cy | (pla[12])&(M2&T2)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[12])&(M2&T2)&(op3);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[12])&(M2&T2);
fMRead = fMRead | (pla[12])&(M2&T3);
nextM = nextM | (pla[12])&(M2&T3);
ctl_mWrite = ctl_mWrite | (pla[12])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[12])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (pla[12])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[12])&(M2&T3);
ctl_flags_alu = ctl_flags_alu | (pla[12])&(M2&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[12])&(M2&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[12])&(M2&T3);
ctl_alu_op_low = ctl_alu_op_low | (pla[12])&(M2&T3);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[12])&(M2&T3)&(ctl_alu_op_low);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[12])&(M2&T3)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[12])&(M2&T3)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[12])&(M2&T3);
ctl_flags_cf2_we = ctl_flags_cf2_we | (pla[12])&(M2&T3);
fMWrite = fMWrite | (pla[12])&(M3&T1);
ctl_reg_gp_sel_pla12M3T1_2 = (pla[12])&(M3&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla12M3T1_2,ctl_reg_gp_sel_pla12M3T1_2})&(`GP_REG_DE);
ctl_reg_gp_hilo_pla12M3T1_3 = (pla[12])&(M3&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla12M3T1_3,ctl_reg_gp_hilo_pla12M3T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[12])&(M3&T1);
ctl_al_we = ctl_al_we | (pla[12])&(M3&T1);
ctl_flags_alu = ctl_flags_alu | (pla[12])&(M3&T1);
ctl_alu_oe = ctl_alu_oe | (pla[12])&(M3&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[12])&(M3&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[12])&(M3&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[12])&(M3&T1)&(ctl_alu_op_low);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[12])&(M3&T1)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[12])&(M3&T1)&(~ctl_alu_op_low);
ctl_flags_use_cf2 = ctl_flags_use_cf2 | (pla[12])&(M3&T1);
fMWrite = fMWrite | (pla[12])&(M3&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[12])&(M3&T2);
ctl_reg_gp_sel_pla12M3T2_3 = (pla[12])&(M3&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla12M3T2_3,ctl_reg_gp_sel_pla12M3T2_3})&(`GP_REG_DE);
ctl_reg_gp_hilo_pla12M3T2_4 = (pla[12])&(M3&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla12M3T2_4,ctl_reg_gp_hilo_pla12M3T2_4})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[12])&(M3&T2);
ctl_inc_cy = ctl_inc_cy | (pla[12])&(M3&T2)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[12])&(M3&T2)&(op3);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[12])&(M3&T2);
fMWrite = fMWrite | (pla[12])&(M3&T3);
ctl_reg_gp_sel_pla12M3T3_2 = (pla[12])&(M3&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla12M3T3_2,ctl_reg_gp_sel_pla12M3T3_2})&(`GP_REG_BC);
ctl_reg_gp_hilo_pla12M3T3_3 = (pla[12])&(M3&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla12M3T3_3,ctl_reg_gp_hilo_pla12M3T3_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[12])&(M3&T3);
ctl_al_we = ctl_al_we | (pla[12])&(M3&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[12])&(M3&T4);
ctl_reg_gp_sel_pla12M3T4_2 = (pla[12])&(M3&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla12M3T4_2,ctl_reg_gp_sel_pla12M3T4_2})&(`GP_REG_BC);
ctl_reg_gp_hilo_pla12M3T4_3 = (pla[12])&(M3&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla12M3T4_3,ctl_reg_gp_hilo_pla12M3T4_3})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[12])&(M3&T4);
ctl_inc_cy = ctl_inc_cy | (pla[12])&(M3&T4)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[12])&(M3&T4);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[12])&(M3&T4);
ctl_repeat_we = ctl_repeat_we | (pla[12])&(M3&T4);
nextM = nextM | (pla[12])&(M3&T5);
setM1 = setM1 | (pla[12])&(M3&T5)&(nonRep|~repeat_en);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[12])&(M4&T1);
ctl_reg_sys_hilo_pla12M4T1_2 = (pla[12])&(M4&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla12M4T1_2,ctl_reg_sys_hilo_pla12M4T1_2})&(2'b11);
ctl_al_we = ctl_al_we | (pla[12])&(M4&T1);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[12])&(M4&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[12])&(M4&T2);
ctl_reg_sys_hilo_pla12M4T2_3 = (pla[12])&(M4&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla12M4T2_3,ctl_reg_sys_hilo_pla12M4T2_3})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[12])&(M4&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[12])&(M4&T2)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[12])&(M4&T2);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[12])&(M4&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[12])&(M4&T3);
ctl_reg_sys_hilo_pla12M4T3_2 = (pla[12])&(M4&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla12M4T3_2,ctl_reg_sys_hilo_pla12M4T3_2})&(2'b11);
ctl_al_we = ctl_al_we | (pla[12])&(M4&T3);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[12])&(M4&T4);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[12])&(M4&T4);
ctl_reg_sys_hilo_pla12M4T4_3 = (pla[12])&(M4&T4);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla12M4T4_3,ctl_reg_sys_hilo_pla12M4T4_3})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[12])&(M4&T4)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[12])&(M4&T4)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[12])&(M4&T4);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[12])&(M4&T4);
setM1 = setM1 | (pla[12])&(M4&T5);
ctl_flags_alu = ctl_flags_alu | (pla[11])&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (pla[11])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[11])&(M1&T1);
ctl_alu_op1_sel_zero = ctl_alu_op1_sel_zero | (pla[11])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[11])&(M1&T1);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[11])&(M1&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[11])&(M1&T1)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[11])&(M1&T1)&(~ctl_alu_op_low);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[11])&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[11])&(M1&T1);
ctl_pf_sel_pla11M1T1_11 = (pla[11])&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla11M1T1_11,ctl_pf_sel_pla11M1T1_11})&(`PFSEL_REP);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[11])&(M1&T1);
ctl_flags_nf_set = ctl_flags_nf_set | (pla[11])&(M1&T1);
ctl_flags_use_cf2 = ctl_flags_use_cf2 | (pla[11])&(M1&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[11])&(M1&T2);
ctl_reg_gp_sel_pla11M1T2_2 = (pla[11])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla11M1T2_2,ctl_reg_gp_sel_pla11M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla11M1T2_3 = (pla[11])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla11M1T2_3,ctl_reg_gp_hilo_pla11M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[11])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[11])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (pla[11])&(M1&T2);
ctl_flags_hf_cpl = ctl_flags_hf_cpl | (pla[11])&(M1&T2)&(flags_nf);
ctl_reg_gp_sel_pla11M1T3_1 = (pla[11])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla11M1T3_1,ctl_reg_gp_sel_pla11M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla11M1T3_2 = (pla[11])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla11M1T3_2,ctl_reg_gp_hilo_pla11M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[11])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[11])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[11])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[11])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[11])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[11])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[11])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[11])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[11])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[11])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[11])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[11])&(M1&T3);
validPLA = validPLA | (pla[11])&(M1&T4);
nextM = nextM | (pla[11])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[11])&(M1&T4);
fMRead = fMRead | (pla[11])&(M2&T1);
ctl_reg_gp_sel_pla11M2T1_2 = (pla[11])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla11M2T1_2,ctl_reg_gp_sel_pla11M2T1_2})&(`GP_REG_HL);
ctl_reg_gp_hilo_pla11M2T1_3 = (pla[11])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla11M2T1_3,ctl_reg_gp_hilo_pla11M2T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[11])&(M2&T1);
ctl_al_we = ctl_al_we | (pla[11])&(M2&T1);
fMRead = fMRead | (pla[11])&(M2&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[11])&(M2&T2);
ctl_reg_gp_sel_pla11M2T2_3 = (pla[11])&(M2&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla11M2T2_3,ctl_reg_gp_sel_pla11M2T2_3})&(`GP_REG_HL);
ctl_reg_gp_hilo_pla11M2T2_4 = (pla[11])&(M2&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla11M2T2_4,ctl_reg_gp_hilo_pla11M2T2_4})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[11])&(M2&T2);
ctl_inc_cy = ctl_inc_cy | (pla[11])&(M2&T2)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[11])&(M2&T2)&(op3);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[11])&(M2&T2);
fMRead = fMRead | (pla[11])&(M2&T3);
nextM = nextM | (pla[11])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[11])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (pla[11])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[11])&(M2&T3);
ctl_flags_alu = ctl_flags_alu | (pla[11])&(M2&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[11])&(M2&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[11])&(M2&T3);
ctl_alu_op_low = ctl_alu_op_low | (pla[11])&(M2&T3);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[11])&(M2&T3);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[11])&(M2&T3)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[11])&(M2&T3)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[11])&(M2&T3);
ctl_flags_cf2_we = ctl_flags_cf2_we | (pla[11])&(M2&T3);
ctl_flags_alu = ctl_flags_alu | (pla[11])&(M3&T1);
ctl_alu_oe = ctl_alu_oe | (pla[11])&(M3&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[11])&(M3&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[11])&(M3&T1);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[11])&(M3&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[11])&(M3&T1)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[11])&(M3&T1)&(~ctl_alu_op_low);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[11])&(M3&T1);
ctl_flags_use_cf2 = ctl_flags_use_cf2 | (pla[11])&(M3&T1);
ctl_reg_gp_sel_pla11M3T3_1 = (pla[11])&(M3&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla11M3T3_1,ctl_reg_gp_sel_pla11M3T3_1})&(`GP_REG_BC);
ctl_reg_gp_hilo_pla11M3T3_2 = (pla[11])&(M3&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla11M3T3_2,ctl_reg_gp_hilo_pla11M3T3_2})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[11])&(M3&T3);
ctl_al_we = ctl_al_we | (pla[11])&(M3&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[11])&(M3&T4);
ctl_reg_gp_sel_pla11M3T4_2 = (pla[11])&(M3&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla11M3T4_2,ctl_reg_gp_sel_pla11M3T4_2})&(`GP_REG_BC);
ctl_reg_gp_hilo_pla11M3T4_3 = (pla[11])&(M3&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla11M3T4_3,ctl_reg_gp_hilo_pla11M3T4_3})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[11])&(M3&T4);
ctl_inc_cy = ctl_inc_cy | (pla[11])&(M3&T4)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[11])&(M3&T4);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[11])&(M3&T4);
ctl_repeat_we = ctl_repeat_we | (pla[11])&(M3&T4);
nextM = nextM | (pla[11])&(M3&T5);
setM1 = setM1 | (pla[11])&(M3&T5)&(nonRep|~repeat_en|flags_zf);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[11])&(M4&T1);
ctl_reg_sys_hilo_pla11M4T1_2 = (pla[11])&(M4&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla11M4T1_2,ctl_reg_sys_hilo_pla11M4T1_2})&(2'b11);
ctl_al_we = ctl_al_we | (pla[11])&(M4&T1);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[11])&(M4&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[11])&(M4&T2);
ctl_reg_sys_hilo_pla11M4T2_3 = (pla[11])&(M4&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla11M4T2_3,ctl_reg_sys_hilo_pla11M4T2_3})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[11])&(M4&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[11])&(M4&T2)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[11])&(M4&T2);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[11])&(M4&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[11])&(M4&T3);
ctl_reg_sys_hilo_pla11M4T3_2 = (pla[11])&(M4&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla11M4T3_2,ctl_reg_sys_hilo_pla11M4T3_2})&(2'b11);
ctl_al_we = ctl_al_we | (pla[11])&(M4&T3);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[11])&(M4&T4);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[11])&(M4&T4);
ctl_reg_sys_hilo_pla11M4T4_3 = (pla[11])&(M4&T4);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla11M4T4_3,ctl_reg_sys_hilo_pla11M4T4_3})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[11])&(M4&T4)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[11])&(M4&T4)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[11])&(M4&T4);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[11])&(M4&T4);
setM1 = setM1 | (pla[11])&(M4&T5);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[65]&~pla[52])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[65]&~pla[52])&(M1&T1);
ctl_sw_2u = ctl_sw_2u | (pla[65]&~pla[52])&(M1&T1);
ctl_flags_alu = ctl_flags_alu | (pla[65]&~pla[52])&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (pla[65]&~pla[52])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[65]&~pla[52])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[65]&~pla[52])&(M1&T1);
ctl_state_alu = ctl_state_alu | (pla[65]&~pla[52])&(M1&T1);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[65]&~pla[52])&(M1&T1);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[65]&~pla[52])&(M1&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[65]&~pla[52])&(M1&T2);
ctl_reg_gp_sel_pla65npla52M1T2_2 = (pla[65]&~pla[52])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla65npla52M1T2_2,ctl_reg_gp_sel_pla65npla52M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla65npla52M1T2_3 = (pla[65]&~pla[52])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla65npla52M1T2_3,ctl_reg_gp_hilo_pla65npla52M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[65]&~pla[52])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[65]&~pla[52])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (pla[65]&~pla[52])&(M1&T2);
ctl_state_alu = ctl_state_alu | (pla[65]&~pla[52])&(M1&T2);
ctl_flags_hf_cpl = ctl_flags_hf_cpl | (pla[65]&~pla[52])&(M1&T2)&(flags_nf);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[65]&~pla[52])&(M1&T2)&(flags_nf);
ctl_reg_gp_sel_pla65npla52M1T3_1 = (pla[65]&~pla[52])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla65npla52M1T3_1,ctl_reg_gp_sel_pla65npla52M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla65npla52M1T3_2 = (pla[65]&~pla[52])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla65npla52M1T3_2,ctl_reg_gp_hilo_pla65npla52M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[65]&~pla[52])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[65]&~pla[52])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[65]&~pla[52])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[65]&~pla[52])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[65]&~pla[52])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[65]&~pla[52])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[65]&~pla[52])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[65]&~pla[52])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[65]&~pla[52])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[65]&~pla[52])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[65]&~pla[52])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[65]&~pla[52])&(M1&T3);
validPLA = validPLA | (pla[65]&~pla[52])&(M1&T4);
setM1 = setM1 | (pla[65]&~pla[52])&(M1&T4);
ctl_reg_gp_sel_pla65npla52M1T4_3 = (pla[65]&~pla[52])&(M1&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla65npla52M1T4_3,ctl_reg_gp_sel_pla65npla52M1T4_3})&(op21);
ctl_reg_gp_hilo_pla65npla52M1T4_4 = (pla[65]&~pla[52])&(M1&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla65npla52M1T4_4,ctl_reg_gp_hilo_pla65npla52M1T4_4})&({~rsel0,rsel0});
ctl_reg_out_hi = ctl_reg_out_hi | (pla[65]&~pla[52])&(M1&T4)&(~rsel0);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[65]&~pla[52])&(M1&T4)&(rsel0);
ctl_sw_2u = ctl_sw_2u | (pla[65]&~pla[52])&(M1&T4)&(~rsel0);
ctl_sw_2d = ctl_sw_2d | (pla[65]&~pla[52])&(M1&T4)&(rsel0);
ctl_flags_alu = ctl_flags_alu | (pla[65]&~pla[52])&(M1&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[65]&~pla[52])&(M1&T4)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[65]&~pla[52])&(M1&T4);
ctl_alu_op_low = ctl_alu_op_low | (pla[65]&~pla[52])&(M1&T4);
ctl_state_alu = ctl_state_alu | (pla[65]&~pla[52])&(M1&T4);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[65]&~pla[52])&(M1&T4);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[65]&~pla[52])&(M1&T4);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[65]&~pla[52])&(M1&T4);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[64])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[64])&(M1&T1);
ctl_sw_2u = ctl_sw_2u | (pla[64])&(M1&T1);
ctl_flags_alu = ctl_flags_alu | (pla[64])&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (pla[64])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[64])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[64])&(M1&T1);
ctl_state_alu = ctl_state_alu | (pla[64])&(M1&T1);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[64])&(M1&T1);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[64])&(M1&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[64])&(M1&T2);
ctl_reg_gp_sel_pla64M1T2_2 = (pla[64])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla64M1T2_2,ctl_reg_gp_sel_pla64M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla64M1T2_3 = (pla[64])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla64M1T2_3,ctl_reg_gp_hilo_pla64M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[64])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[64])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (pla[64])&(M1&T2);
ctl_state_alu = ctl_state_alu | (pla[64])&(M1&T2);
ctl_flags_hf_cpl = ctl_flags_hf_cpl | (pla[64])&(M1&T2)&(flags_nf);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[64])&(M1&T2)&(flags_nf);
ctl_reg_gp_sel_pla64M1T3_1 = (pla[64])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla64M1T3_1,ctl_reg_gp_sel_pla64M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla64M1T3_2 = (pla[64])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla64M1T3_2,ctl_reg_gp_hilo_pla64M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[64])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[64])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[64])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[64])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[64])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[64])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[64])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[64])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[64])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[64])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[64])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[64])&(M1&T3);
validPLA = validPLA | (pla[64])&(M1&T4);
nextM = nextM | (pla[64])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[64])&(M1&T4);
ctl_reg_gp_sel_pla64M1T4_4 = (pla[64])&(M1&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla64M1T4_4,ctl_reg_gp_sel_pla64M1T4_4})&(op21);
ctl_reg_gp_hilo_pla64M1T4_5 = (pla[64])&(M1&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla64M1T4_5,ctl_reg_gp_hilo_pla64M1T4_5})&({~rsel0,rsel0});
ctl_reg_out_hi = ctl_reg_out_hi | (pla[64])&(M1&T4)&(~rsel0);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[64])&(M1&T4)&(rsel0);
ctl_sw_2u = ctl_sw_2u | (pla[64])&(M1&T4)&(~rsel0);
ctl_sw_2d = ctl_sw_2d | (pla[64])&(M1&T4)&(rsel0);
ctl_flags_alu = ctl_flags_alu | (pla[64])&(M1&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[64])&(M1&T4)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[64])&(M1&T4);
ctl_alu_op_low = ctl_alu_op_low | (pla[64])&(M1&T4);
ctl_state_alu = ctl_state_alu | (pla[64])&(M1&T4);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[64])&(M1&T4);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[64])&(M1&T4);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[64])&(M1&T4);
fMRead = fMRead | (pla[64])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[64])&(M2&T1);
ctl_reg_sys_hilo_pla64M2T1_3 = (pla[64])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla64M2T1_3,ctl_reg_sys_hilo_pla64M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[64])&(M2&T1);
ctl_state_alu = ctl_state_alu | (pla[64])&(M2&T1);
fMRead = fMRead | (pla[64])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[64])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[64])&(M2&T2);
ctl_reg_sys_hilo_pla64M2T2_4 = (pla[64])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla64M2T2_4,ctl_reg_sys_hilo_pla64M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[64])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[64])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[64])&(M2&T2);
fMRead = fMRead | (pla[64])&(M2&T3);
setM1 = setM1 | (pla[64])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[64])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (pla[64])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[64])&(M2&T3);
ctl_flags_alu = ctl_flags_alu | (pla[64])&(M2&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[64])&(M2&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[64])&(M2&T3);
ctl_alu_op_low = ctl_alu_op_low | (pla[64])&(M2&T3);
ctl_state_alu = ctl_state_alu | (pla[64])&(M2&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[64])&(M2&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[64])&(M2&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[64])&(M2&T3);
ctl_reg_gp_sel_use_ixiypla52M1T3_1 = (use_ixiy&pla[52])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_use_ixiypla52M1T3_1,ctl_reg_gp_sel_use_ixiypla52M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_use_ixiypla52M1T3_2 = (use_ixiy&pla[52])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_use_ixiypla52M1T3_2,ctl_reg_gp_hilo_use_ixiypla52M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (use_ixiy&pla[52])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (use_ixiy&pla[52])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (use_ixiy&pla[52])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (use_ixiy&pla[52])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (use_ixiy&pla[52])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (use_ixiy&pla[52])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (use_ixiy&pla[52])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (use_ixiy&pla[52])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (use_ixiy&pla[52])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (use_ixiy&pla[52])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (use_ixiy&pla[52])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (use_ixiy&pla[52])&(M1&T3);
validPLA = validPLA | (use_ixiy&pla[52])&(M1&T4);
nextM = nextM | (use_ixiy&pla[52])&(M1&T4);
ctl_mRead = ctl_mRead | (use_ixiy&pla[52])&(M1&T4);
fMRead = fMRead | (use_ixiy&pla[52])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (use_ixiy&pla[52])&(M2&T1);
ctl_reg_sys_hilo_use_ixiypla52M2T1_3 = (use_ixiy&pla[52])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_use_ixiypla52M2T1_3,ctl_reg_sys_hilo_use_ixiypla52M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (use_ixiy&pla[52])&(M2&T1);
fMRead = fMRead | (use_ixiy&pla[52])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (use_ixiy&pla[52])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (use_ixiy&pla[52])&(M2&T2);
ctl_reg_sys_hilo_use_ixiypla52M2T2_4 = (use_ixiy&pla[52])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_use_ixiypla52M2T2_4,ctl_reg_sys_hilo_use_ixiypla52M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (use_ixiy&pla[52])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (use_ixiy&pla[52])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (use_ixiy&pla[52])&(M2&T2);
fMRead = fMRead | (use_ixiy&pla[52])&(M2&T3);
nextM = nextM | (use_ixiy&pla[52])&(M2&T3);
ixy_d = ixy_d | (use_ixiy&pla[52])&(M3&T1);
ixy_d = ixy_d | (use_ixiy&pla[52])&(M3&T2);
ixy_d = ixy_d | (use_ixiy&pla[52])&(M3&T3);
ixy_d = ixy_d | (use_ixiy&pla[52])&(M3&T4);
nextM = nextM | (use_ixiy&pla[52])&(M3&T5);
ctl_mRead = ctl_mRead | (use_ixiy&pla[52])&(M3&T5);
ixy_d = ixy_d | (use_ixiy&pla[52])&(M3&T5);
ctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[52])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[52])&(M1&T1);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[52])&(M1&T1);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[52])&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[52])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[52])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[52])&(M1&T1);
ctl_state_alu = ctl_state_alu | (~use_ixiy&pla[52])&(M1&T1);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[52])&(M1&T1);
ctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[52])&(M1&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (~use_ixiy&pla[52])&(M1&T2);
ctl_reg_gp_sel_nuse_ixiypla52M1T2_2 = (~use_ixiy&pla[52])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla52M1T2_2,ctl_reg_gp_sel_nuse_ixiypla52M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_nuse_ixiypla52M1T2_3 = (~use_ixiy&pla[52])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla52M1T2_3,ctl_reg_gp_hilo_nuse_ixiypla52M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[52])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[52])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (~use_ixiy&pla[52])&(M1&T2);
ctl_state_alu = ctl_state_alu | (~use_ixiy&pla[52])&(M1&T2);
ctl_flags_hf_cpl = ctl_flags_hf_cpl | (~use_ixiy&pla[52])&(M1&T2)&(flags_nf);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[52])&(M1&T2)&(flags_nf);
ctl_reg_gp_sel_nuse_ixiypla52M1T3_1 = (~use_ixiy&pla[52])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla52M1T3_1,ctl_reg_gp_sel_nuse_ixiypla52M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_nuse_ixiypla52M1T3_2 = (~use_ixiy&pla[52])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla52M1T3_2,ctl_reg_gp_hilo_nuse_ixiypla52M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[52])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[52])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[52])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[52])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[52])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[52])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[52])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[52])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[52])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[52])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[52])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[52])&(M1&T3);
validPLA = validPLA | (~use_ixiy&pla[52])&(M1&T4);
nextM = nextM | (~use_ixiy&pla[52])&(M1&T4);
ctl_mRead = ctl_mRead | (~use_ixiy&pla[52])&(M1&T4);
fMRead = fMRead | (~use_ixiy&pla[52])&(M2&T1);
ctl_reg_gp_sel_nuse_ixiypla52M2T1_2 = (~use_ixiy&pla[52])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla52M2T1_2,ctl_reg_gp_sel_nuse_ixiypla52M2T1_2})&(`GP_REG_HL);
ctl_reg_gp_hilo_nuse_ixiypla52M2T1_3 = (~use_ixiy&pla[52])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla52M2T1_3,ctl_reg_gp_hilo_nuse_ixiypla52M2T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[52])&(M2&T1);
ctl_al_we = ctl_al_we | (~use_ixiy&pla[52])&(M2&T1);
fMRead = fMRead | (~use_ixiy&pla[52])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (~use_ixiy&pla[52])&(M2&T2);
ctl_reg_sel_wz = ctl_reg_sel_wz | (~use_ixiy&pla[52])&(M2&T2);
ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 = (~use_ixiy&pla[52])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4,ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (~use_ixiy&pla[52])&(M2&T2);
ctl_inc_cy = ctl_inc_cy | (~use_ixiy&pla[52])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[52])&(M2&T2);
fMRead = fMRead | (~use_ixiy&pla[52])&(M2&T3);
setM1 = setM1 | (~use_ixiy&pla[52])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[52])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[52])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[52])&(M2&T3);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[52])&(M2&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[52])&(M2&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[52])&(M2&T3);
ctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[52])&(M2&T3);
ctl_state_alu = ctl_state_alu | (~use_ixiy&pla[52])&(M2&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[52])&(M2&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[52])&(M2&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[52])&(M2&T3);
fMRead = fMRead | (~use_ixiy&pla[52])&(M4&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[52])&(M4&T1);
fMRead = fMRead | (~use_ixiy&pla[52])&(M4&T2);
ctl_reg_gp_sel_nuse_ixiypla52M4T2_2 = (~use_ixiy&pla[52])&(M4&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla52M4T2_2,ctl_reg_gp_sel_nuse_ixiypla52M4T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_nuse_ixiypla52M4T2_3 = (~use_ixiy&pla[52])&(M4&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla52M4T2_3,ctl_reg_gp_hilo_nuse_ixiypla52M4T2_3})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[52])&(M4&T2);
ctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[52])&(M4&T2);
ctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[52])&(M4&T2);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[52])&(M4&T2)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[52])&(M4&T2);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[52])&(M4&T2);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[52])&(M4&T2);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[52])&(M4&T2);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[52])&(M4&T2);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[52])&(M4&T2);
ctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[52])&(M4&T2);
fMRead = fMRead | (~use_ixiy&pla[52])&(M4&T3);
setM1 = setM1 | (~use_ixiy&pla[52])&(M4&T3);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[52])&(M4&T3);
ctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[52])&(M4&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[52])&(M4&T3);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[52])&(M4&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[52])&(M4&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[52])&(M4&T3);
ctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[52])&(M4&T3);
ctl_state_alu = ctl_state_alu | (~use_ixiy&pla[52])&(M4&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[52])&(M4&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[52])&(M4&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[52])&(M4&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[66]&~pla[53])&(M1&T1);
ctl_reg_gp_sel_pla66npla53M1T1_2 = (pla[66]&~pla[53])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla66npla53M1T1_2,ctl_reg_gp_sel_pla66npla53M1T1_2})&(op54);
ctl_reg_gp_hilo_pla66npla53M1T1_3 = (pla[66]&~pla[53])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla66npla53M1T1_3,ctl_reg_gp_hilo_pla66npla53M1T1_3})&({~rsel3,rsel3});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[66]&~pla[53])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[66]&~pla[53])&(M1&T1);
ctl_sw_2u = ctl_sw_2u | (pla[66]&~pla[53])&(M1&T1);
ctl_flags_alu = ctl_flags_alu | (pla[66]&~pla[53])&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (pla[66]&~pla[53])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[66]&~pla[53])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[66]&~pla[53])&(M1&T1);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[66]&~pla[53])&(M1&T1)&(~ctl_alu_op_low);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[66]&~pla[53])&(M1&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[66]&~pla[53])&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[66]&~pla[53])&(M1&T1);
ctl_pf_sel_pla66npla53M1T1_15 = (pla[66]&~pla[53])&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla66npla53M1T1_15,ctl_pf_sel_pla66npla53M1T1_15})&(`PFSEL_V);
ctl_flags_use_cf2 = ctl_flags_use_cf2 | (pla[66]&~pla[53])&(M1&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[66]&~pla[53])&(M1&T2);
ctl_reg_gp_sel_pla66npla53M1T2_2 = (pla[66]&~pla[53])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla66npla53M1T2_2,ctl_reg_gp_sel_pla66npla53M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla66npla53M1T2_3 = (pla[66]&~pla[53])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla66npla53M1T2_3,ctl_reg_gp_hilo_pla66npla53M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[66]&~pla[53])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[66]&~pla[53])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (pla[66]&~pla[53])&(M1&T2);
ctl_flags_hf_cpl = ctl_flags_hf_cpl | (pla[66]&~pla[53])&(M1&T2)&(flags_nf);
ctl_reg_gp_sel_pla66npla53M1T3_1 = (pla[66]&~pla[53])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla66npla53M1T3_1,ctl_reg_gp_sel_pla66npla53M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla66npla53M1T3_2 = (pla[66]&~pla[53])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla66npla53M1T3_2,ctl_reg_gp_hilo_pla66npla53M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[66]&~pla[53])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[66]&~pla[53])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[66]&~pla[53])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[66]&~pla[53])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[66]&~pla[53])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[66]&~pla[53])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[66]&~pla[53])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[66]&~pla[53])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[66]&~pla[53])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[66]&~pla[53])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[66]&~pla[53])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[66]&~pla[53])&(M1&T3);
validPLA = validPLA | (pla[66]&~pla[53])&(M1&T4);
setM1 = setM1 | (pla[66]&~pla[53])&(M1&T4);
ctl_bus_zero_oe = ctl_bus_zero_oe | (pla[66]&~pla[53])&(M1&T4)&(op4&op5&~op3);
ctl_reg_gp_sel_pla66npla53M1T4nop4op5nop3_1 = (pla[66]&~pla[53])&(M1&T4)&(~(op4&op5&~op3));
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla66npla53M1T4nop4op5nop3_1,ctl_reg_gp_sel_pla66npla53M1T4nop4op5nop3_1})&(op54);
ctl_reg_gp_hilo_pla66npla53M1T4nop4op5nop3_2 = (pla[66]&~pla[53])&(M1&T4)&(~(op4&op5&~op3));
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla66npla53M1T4nop4op5nop3_2,ctl_reg_gp_hilo_pla66npla53M1T4nop4op5nop3_2})&({~rsel3,rsel3});
ctl_reg_out_hi = ctl_reg_out_hi | (pla[66]&~pla[53])&(M1&T4)&(~rsel3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[66]&~pla[53])&(M1&T4)&(rsel3);
ctl_sw_2u = ctl_sw_2u | (pla[66]&~pla[53])&(M1&T4)&(~rsel3);
ctl_sw_2d = ctl_sw_2d | (pla[66]&~pla[53])&(M1&T4)&(rsel3);
ctl_flags_alu = ctl_flags_alu | (pla[66]&~pla[53])&(M1&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[66]&~pla[53])&(M1&T4)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_zero = ctl_alu_op2_sel_zero | (pla[66]&~pla[53])&(M1&T4);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[66]&~pla[53])&(M1&T4);
ctl_alu_op_low = ctl_alu_op_low | (pla[66]&~pla[53])&(M1&T4);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[66]&~pla[53])&(M1&T4)&(~ctl_alu_op_low);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[66]&~pla[53])&(M1&T4);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[66]&~pla[53])&(M1&T4);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[66]&~pla[53])&(M1&T4);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[66]&~pla[53])&(M1&T4);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[66]&~pla[53])&(M1&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[66]&~pla[53])&(M1&T4);
ctl_flags_cf2_we = ctl_flags_cf2_we | (pla[66]&~pla[53])&(M1&T4);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[75])&(M1&T1);
ctl_flags_nf_set = ctl_flags_nf_set | (pla[75])&(M1&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[75])&(M1&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[75])&(M1&T1);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[75])&(M1&T1);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[75])&(M1&T4);
ctl_flags_nf_set = ctl_flags_nf_set | (pla[75])&(M1&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[75])&(M1&T4);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[75])&(M1&T4);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[75])&(M1&T4);
ctl_flags_nf_we = ctl_flags_nf_we | ((M2|M4)&pla[75]);
ctl_flags_nf_set = ctl_flags_nf_set | ((M2|M4)&pla[75]);
ctl_flags_cf_set = ctl_flags_cf_set | ((M2|M4)&pla[75]);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | ((M2|M4)&pla[75]);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | ((M2|M4)&pla[75]);
ctl_reg_gp_sel_use_ixiypla53M1T3_1 = (use_ixiy&pla[53])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_use_ixiypla53M1T3_1,ctl_reg_gp_sel_use_ixiypla53M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_use_ixiypla53M1T3_2 = (use_ixiy&pla[53])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_use_ixiypla53M1T3_2,ctl_reg_gp_hilo_use_ixiypla53M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (use_ixiy&pla[53])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (use_ixiy&pla[53])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (use_ixiy&pla[53])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (use_ixiy&pla[53])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (use_ixiy&pla[53])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (use_ixiy&pla[53])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (use_ixiy&pla[53])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (use_ixiy&pla[53])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (use_ixiy&pla[53])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (use_ixiy&pla[53])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (use_ixiy&pla[53])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (use_ixiy&pla[53])&(M1&T3);
validPLA = validPLA | (use_ixiy&pla[53])&(M1&T4);
nextM = nextM | (use_ixiy&pla[53])&(M1&T4);
ctl_mRead = ctl_mRead | (use_ixiy&pla[53])&(M1&T4);
fMRead = fMRead | (use_ixiy&pla[53])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (use_ixiy&pla[53])&(M2&T1);
ctl_reg_sys_hilo_use_ixiypla53M2T1_3 = (use_ixiy&pla[53])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_use_ixiypla53M2T1_3,ctl_reg_sys_hilo_use_ixiypla53M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (use_ixiy&pla[53])&(M2&T1);
fMRead = fMRead | (use_ixiy&pla[53])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (use_ixiy&pla[53])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (use_ixiy&pla[53])&(M2&T2);
ctl_reg_sys_hilo_use_ixiypla53M2T2_4 = (use_ixiy&pla[53])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_use_ixiypla53M2T2_4,ctl_reg_sys_hilo_use_ixiypla53M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (use_ixiy&pla[53])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (use_ixiy&pla[53])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (use_ixiy&pla[53])&(M2&T2);
fMRead = fMRead | (use_ixiy&pla[53])&(M2&T3);
nextM = nextM | (use_ixiy&pla[53])&(M2&T3);
ixy_d = ixy_d | (use_ixiy&pla[53])&(M3&T1);
ixy_d = ixy_d | (use_ixiy&pla[53])&(M3&T2);
ixy_d = ixy_d | (use_ixiy&pla[53])&(M3&T3);
ixy_d = ixy_d | (use_ixiy&pla[53])&(M3&T4);
nextM = nextM | (use_ixiy&pla[53])&(M3&T5);
ctl_mRead = ctl_mRead | (use_ixiy&pla[53])&(M3&T5);
ixy_d = ixy_d | (use_ixiy&pla[53])&(M3&T5);
ctl_reg_gp_we = ctl_reg_gp_we | (~use_ixiy&pla[53])&(M1&T2);
ctl_reg_gp_sel_nuse_ixiypla53M1T2_2 = (~use_ixiy&pla[53])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla53M1T2_2,ctl_reg_gp_sel_nuse_ixiypla53M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_nuse_ixiypla53M1T2_3 = (~use_ixiy&pla[53])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla53M1T2_3,ctl_reg_gp_hilo_nuse_ixiypla53M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[53])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[53])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (~use_ixiy&pla[53])&(M1&T2);
ctl_flags_hf_cpl = ctl_flags_hf_cpl | (~use_ixiy&pla[53])&(M1&T2)&(flags_nf);
ctl_reg_gp_sel_nuse_ixiypla53M1T3_1 = (~use_ixiy&pla[53])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla53M1T3_1,ctl_reg_gp_sel_nuse_ixiypla53M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_nuse_ixiypla53M1T3_2 = (~use_ixiy&pla[53])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla53M1T3_2,ctl_reg_gp_hilo_nuse_ixiypla53M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[53])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[53])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[53])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[53])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[53])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[53])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[53])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[53])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[53])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[53])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[53])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[53])&(M1&T3);
validPLA = validPLA | (~use_ixiy&pla[53])&(M1&T4);
nextM = nextM | (~use_ixiy&pla[53])&(M1&T4);
ctl_mRead = ctl_mRead | (~use_ixiy&pla[53])&(M1&T4);
fMRead = fMRead | (~use_ixiy&pla[53])&(M2&T1);
ctl_reg_gp_sel_nuse_ixiypla53M2T1_2 = (~use_ixiy&pla[53])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla53M2T1_2,ctl_reg_gp_sel_nuse_ixiypla53M2T1_2})&(`GP_REG_HL);
ctl_reg_gp_hilo_nuse_ixiypla53M2T1_3 = (~use_ixiy&pla[53])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla53M2T1_3,ctl_reg_gp_hilo_nuse_ixiypla53M2T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[53])&(M2&T1);
ctl_al_we = ctl_al_we | (~use_ixiy&pla[53])&(M2&T1);
fMRead = fMRead | (~use_ixiy&pla[53])&(M2&T2);
fMRead = fMRead | (~use_ixiy&pla[53])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[53])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[53])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[53])&(M2&T3);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[53])&(M2&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[53])&(M2&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_zero = ctl_alu_op2_sel_zero | (~use_ixiy&pla[53])&(M2&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[53])&(M2&T3);
ctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[53])&(M2&T3);
ctl_alu_core_hf = ctl_alu_core_hf | (~use_ixiy&pla[53])&(M2&T3)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[53])&(M2&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[53])&(M2&T3);
ctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[53])&(M2&T3);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[53])&(M2&T3);
ctl_flags_cf2_we = ctl_flags_cf2_we | (~use_ixiy&pla[53])&(M2&T3);
nextM = nextM | (~use_ixiy&pla[53])&(M2&T4);
ctl_mWrite = ctl_mWrite | (~use_ixiy&pla[53])&(M2&T4);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[53])&(M2&T4);
ctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[53])&(M2&T4);
ctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[53])&(M2&T4);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[53])&(M2&T4);
ctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[53])&(M2&T4);
ctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[53])&(M2&T4);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[53])&(M2&T4);
ctl_alu_core_hf = ctl_alu_core_hf | (~use_ixiy&pla[53])&(M2&T4)&(~ctl_alu_op_low);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[53])&(M2&T4);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[53])&(M2&T4);
ctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[53])&(M2&T4);
ctl_pf_sel_nuse_ixiypla53M2T4_14 = (~use_ixiy&pla[53])&(M2&T4);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_nuse_ixiypla53M2T4_14,ctl_pf_sel_nuse_ixiypla53M2T4_14})&(`PFSEL_V);
ctl_flags_use_cf2 = ctl_flags_use_cf2 | (~use_ixiy&pla[53])&(M2&T4);
fMWrite = fMWrite | (~use_ixiy&pla[53])&(M3&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[53])&(M3&T1);
fMWrite = fMWrite | (~use_ixiy&pla[53])&(M3&T2);
fMWrite = fMWrite | (~use_ixiy&pla[53])&(M3&T3);
setM1 = setM1 | (~use_ixiy&pla[53])&(M3&T3);
fMRead = fMRead | (~use_ixiy&pla[53])&(M4&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[53])&(M4&T1);
fMRead = fMRead | (~use_ixiy&pla[53])&(M4&T2);
fMRead = fMRead | (~use_ixiy&pla[53])&(M4&T3);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[53])&(M4&T3);
ctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[53])&(M4&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[53])&(M4&T3);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[53])&(M4&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[53])&(M4&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_zero = ctl_alu_op2_sel_zero | (~use_ixiy&pla[53])&(M4&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[53])&(M4&T3);
ctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[53])&(M4&T3);
ctl_alu_core_hf = ctl_alu_core_hf | (~use_ixiy&pla[53])&(M4&T3)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[53])&(M4&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[53])&(M4&T3);
ctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[53])&(M4&T3);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[53])&(M4&T3);
ctl_flags_cf2_we = ctl_flags_cf2_we | (~use_ixiy&pla[53])&(M4&T3);
nextM = nextM | (~use_ixiy&pla[53])&(M4&T4);
ctl_mWrite = ctl_mWrite | (~use_ixiy&pla[53])&(M4&T4);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[53])&(M4&T4);
ctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[53])&(M4&T4);
ctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[53])&(M4&T4);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[53])&(M4&T4);
ctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[53])&(M4&T4);
ctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[53])&(M4&T4);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[53])&(M4&T4);
ctl_alu_core_hf = ctl_alu_core_hf | (~use_ixiy&pla[53])&(M4&T4)&(~ctl_alu_op_low);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[53])&(M4&T4);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[53])&(M4&T4);
ctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[53])&(M4&T4);
ctl_pf_sel_nuse_ixiypla53M4T4_14 = (~use_ixiy&pla[53])&(M4&T4);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_nuse_ixiypla53M4T4_14,ctl_pf_sel_nuse_ixiypla53M4T4_14})&(`PFSEL_V);
ctl_flags_use_cf2 = ctl_flags_use_cf2 | (~use_ixiy&pla[53])&(M4&T4);
fMWrite = fMWrite | (~use_ixiy&pla[53])&(M5&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[53])&(M5&T1);
fMWrite = fMWrite | (~use_ixiy&pla[53])&(M5&T2);
fMWrite = fMWrite | (~use_ixiy&pla[53])&(M5&T3);
setM1 = setM1 | (~use_ixiy&pla[53])&(M5&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[69])&(M1&T2);
ctl_reg_gp_sel_pla69M1T2_2 = (pla[69])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla69M1T2_2,ctl_reg_gp_sel_pla69M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla69M1T2_3 = (pla[69])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla69M1T2_3,ctl_reg_gp_hilo_pla69M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[69])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[69])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (pla[69])&(M1&T2);
ctl_reg_gp_sel_pla69M1T3_1 = (pla[69])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla69M1T3_1,ctl_reg_gp_sel_pla69M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla69M1T3_2 = (pla[69])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla69M1T3_2,ctl_reg_gp_hilo_pla69M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[69])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[69])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[69])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[69])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[69])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[69])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[69])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[69])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[69])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[69])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[69])&(M1&T3);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[69])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[69])&(M1&T3);
validPLA = validPLA | (pla[69])&(M1&T4);
nextM = nextM | (pla[69])&(M1&T4);
ctl_reg_gp_sel_pla69M1T4_3 = (pla[69])&(M1&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla69M1T4_3,ctl_reg_gp_sel_pla69M1T4_3})&(`GP_REG_HL);
ctl_reg_gp_hilo_pla69M1T4_4 = (pla[69])&(M1&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla69M1T4_4,ctl_reg_gp_hilo_pla69M1T4_4})&(2'b01);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[69])&(M1&T4);
ctl_sw_2d = ctl_sw_2d | (pla[69])&(M1&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[69])&(M1&T4)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[69])&(M1&T4);
ctl_reg_gp_sel_pla69M2T1_1 = (pla[69])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla69M2T1_1,ctl_reg_gp_sel_pla69M2T1_1})&(op54);
ctl_reg_gp_hilo_pla69M2T1_2 = (pla[69])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla69M2T1_2,ctl_reg_gp_hilo_pla69M2T1_2})&(2'b01);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[69])&(M2&T1);
ctl_sw_2d = ctl_sw_2d | (pla[69])&(M2&T1);
ctl_flags_alu = ctl_flags_alu | (pla[69])&(M2&T1);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[69])&(M2&T1)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[69])&(M2&T1);
ctl_alu_op_low = ctl_alu_op_low | (pla[69])&(M2&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[69])&(M2&T1)&(ctl_alu_op_low);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[69])&(M2&T1)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[69])&(M2&T1)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[69])&(M2&T1);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[69])&(M2&T1);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[69])&(M2&T2);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[69])&(M2&T2);
ctl_reg_sys_hilo_pla69M2T2_3 = (pla[69])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla69M2T2_3,ctl_reg_sys_hilo_pla69M2T2_3})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (pla[69])&(M2&T2);
ctl_sw_2u = ctl_sw_2u | (pla[69])&(M2&T2);
ctl_flags_alu = ctl_flags_alu | (pla[69])&(M2&T2);
ctl_alu_oe = ctl_alu_oe | (pla[69])&(M2&T2);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[69])&(M2&T2);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[69])&(M2&T2);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[69])&(M2&T2)&(~ctl_alu_op_low);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[69])&(M2&T2);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[69])&(M2&T2);
ctl_reg_gp_sel_pla69M2T3_1 = (pla[69])&(M2&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla69M2T3_1,ctl_reg_gp_sel_pla69M2T3_1})&(`GP_REG_HL);
ctl_reg_gp_hilo_pla69M2T3_2 = (pla[69])&(M2&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla69M2T3_2,ctl_reg_gp_hilo_pla69M2T3_2})&(2'b10);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[69])&(M2&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[69])&(M2&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[69])&(M2&T3)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[69])&(M2&T3);
nextM = nextM | (pla[69])&(M2&T4);
ctl_reg_gp_sel_pla69M2T4_2 = (pla[69])&(M2&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla69M2T4_2,ctl_reg_gp_sel_pla69M2T4_2})&(op54);
ctl_reg_gp_hilo_pla69M2T4_3 = (pla[69])&(M2&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla69M2T4_3,ctl_reg_gp_hilo_pla69M2T4_3})&(2'b10);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[69])&(M2&T4);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[69])&(M2&T4);
ctl_flags_alu = ctl_flags_alu | (pla[69])&(M2&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[69])&(M2&T4)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[69])&(M2&T4);
ctl_alu_op_low = ctl_alu_op_low | (pla[69])&(M2&T4);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[69])&(M2&T4)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[69])&(M2&T4);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[69])&(M2&T4);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[69])&(M3&T1);
ctl_reg_sys_hilo_pla69M3T1_2 = (pla[69])&(M3&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla69M3T1_2,ctl_reg_sys_hilo_pla69M3T1_2})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[69])&(M3&T1);
ctl_al_we = ctl_al_we | (pla[69])&(M3&T1);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[69])&(M3&T1);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[69])&(M3&T1);
ctl_reg_sys_hilo_pla69M3T1_7 = (pla[69])&(M3&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla69M3T1_7,ctl_reg_sys_hilo_pla69M3T1_7})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[69])&(M3&T1);
ctl_sw_2u = ctl_sw_2u | (pla[69])&(M3&T1);
ctl_flags_alu = ctl_flags_alu | (pla[69])&(M3&T1);
ctl_alu_oe = ctl_alu_oe | (pla[69])&(M3&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[69])&(M3&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[69])&(M3&T1);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[69])&(M3&T1)&(~ctl_alu_op_low);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[69])&(M3&T1);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[69])&(M3&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[69])&(M3&T2);
ctl_reg_gp_sel_pla69M3T2_2 = (pla[69])&(M3&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla69M3T2_2,ctl_reg_gp_sel_pla69M3T2_2})&(`GP_REG_HL);
ctl_reg_gp_hilo_pla69M3T2_3 = (pla[69])&(M3&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla69M3T2_3,ctl_reg_gp_hilo_pla69M3T2_3})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[69])&(M3&T2);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[69])&(M3&T2);
setM1 = setM1 | (pla[69])&(M3&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (op3&pla[68])&(M1&T2);
ctl_reg_gp_sel_op3pla68M1T2_2 = (op3&pla[68])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_op3pla68M1T2_2,ctl_reg_gp_sel_op3pla68M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_op3pla68M1T2_3 = (op3&pla[68])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_op3pla68M1T2_3,ctl_reg_gp_hilo_op3pla68M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (op3&pla[68])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (op3&pla[68])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (op3&pla[68])&(M1&T2);
ctl_reg_gp_sel_op3pla68M1T3_1 = (op3&pla[68])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_op3pla68M1T3_1,ctl_reg_gp_sel_op3pla68M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_op3pla68M1T3_2 = (op3&pla[68])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_op3pla68M1T3_2,ctl_reg_gp_hilo_op3pla68M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (op3&pla[68])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (op3&pla[68])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (op3&pla[68])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (op3&pla[68])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (op3&pla[68])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (op3&pla[68])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (op3&pla[68])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (op3&pla[68])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (op3&pla[68])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (op3&pla[68])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (op3&pla[68])&(M1&T3);
ctl_flags_nf_clr = ctl_flags_nf_clr | (op3&pla[68])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (op3&pla[68])&(M1&T3);
validPLA = validPLA | (op3&pla[68])&(M1&T4);
nextM = nextM | (op3&pla[68])&(M1&T4);
ctl_reg_gp_sel_op3pla68M1T4_3 = (op3&pla[68])&(M1&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_op3pla68M1T4_3,ctl_reg_gp_sel_op3pla68M1T4_3})&(`GP_REG_HL);
ctl_reg_gp_hilo_op3pla68M1T4_4 = (op3&pla[68])&(M1&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_op3pla68M1T4_4,ctl_reg_gp_hilo_op3pla68M1T4_4})&(2'b01);
ctl_reg_out_lo = ctl_reg_out_lo | (op3&pla[68])&(M1&T4);
ctl_sw_2d = ctl_sw_2d | (op3&pla[68])&(M1&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (op3&pla[68])&(M1&T4)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (op3&pla[68])&(M1&T4);
ctl_reg_gp_sel_op3pla68M2T1_1 = (op3&pla[68])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_op3pla68M2T1_1,ctl_reg_gp_sel_op3pla68M2T1_1})&(op54);
ctl_reg_gp_hilo_op3pla68M2T1_2 = (op3&pla[68])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_op3pla68M2T1_2,ctl_reg_gp_hilo_op3pla68M2T1_2})&(2'b01);
ctl_reg_out_lo = ctl_reg_out_lo | (op3&pla[68])&(M2&T1);
ctl_sw_2d = ctl_sw_2d | (op3&pla[68])&(M2&T1);
ctl_flags_alu = ctl_flags_alu | (op3&pla[68])&(M2&T1);
ctl_alu_shift_oe = ctl_alu_shift_oe | (op3&pla[68])&(M2&T1)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (op3&pla[68])&(M2&T1);
ctl_alu_op_low = ctl_alu_op_low | (op3&pla[68])&(M2&T1);
ctl_alu_core_hf = ctl_alu_core_hf | (op3&pla[68])&(M2&T1)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (op3&pla[68])&(M2&T1);
ctl_reg_use_sp = ctl_reg_use_sp | (op3&pla[68])&(M2&T1);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (op3&pla[68])&(M2&T2);
ctl_reg_sel_wz = ctl_reg_sel_wz | (op3&pla[68])&(M2&T2);
ctl_reg_sys_hilo_op3pla68M2T2_3 = (op3&pla[68])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_op3pla68M2T2_3,ctl_reg_sys_hilo_op3pla68M2T2_3})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (op3&pla[68])&(M2&T2);
ctl_sw_2u = ctl_sw_2u | (op3&pla[68])&(M2&T2);
ctl_flags_alu = ctl_flags_alu | (op3&pla[68])&(M2&T2);
ctl_alu_oe = ctl_alu_oe | (op3&pla[68])&(M2&T2);
ctl_alu_res_oe = ctl_alu_res_oe | (op3&pla[68])&(M2&T2);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (op3&pla[68])&(M2&T2);
ctl_alu_core_hf = ctl_alu_core_hf | (op3&pla[68])&(M2&T2)&(~ctl_alu_op_low);
ctl_flags_sz_we = ctl_flags_sz_we | (op3&pla[68])&(M2&T2);
ctl_flags_xy_we = ctl_flags_xy_we | (op3&pla[68])&(M2&T2);
ctl_flags_cf_we = ctl_flags_cf_we | (op3&pla[68])&(M2&T2);
ctl_reg_gp_sel_op3pla68M2T3_1 = (op3&pla[68])&(M2&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_op3pla68M2T3_1,ctl_reg_gp_sel_op3pla68M2T3_1})&(`GP_REG_HL);
ctl_reg_gp_hilo_op3pla68M2T3_2 = (op3&pla[68])&(M2&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_op3pla68M2T3_2,ctl_reg_gp_hilo_op3pla68M2T3_2})&(2'b10);
ctl_reg_out_hi = ctl_reg_out_hi | (op3&pla[68])&(M2&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (op3&pla[68])&(M2&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (op3&pla[68])&(M2&T3)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (op3&pla[68])&(M2&T3);
nextM = nextM | (op3&pla[68])&(M2&T4);
ctl_reg_gp_sel_op3pla68M2T4_2 = (op3&pla[68])&(M2&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_op3pla68M2T4_2,ctl_reg_gp_sel_op3pla68M2T4_2})&(op54);
ctl_reg_gp_hilo_op3pla68M2T4_3 = (op3&pla[68])&(M2&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_op3pla68M2T4_3,ctl_reg_gp_hilo_op3pla68M2T4_3})&(2'b10);
ctl_reg_out_hi = ctl_reg_out_hi | (op3&pla[68])&(M2&T4);
ctl_reg_out_lo = ctl_reg_out_lo | (op3&pla[68])&(M2&T4);
ctl_flags_alu = ctl_flags_alu | (op3&pla[68])&(M2&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (op3&pla[68])&(M2&T4)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (op3&pla[68])&(M2&T4);
ctl_alu_op_low = ctl_alu_op_low | (op3&pla[68])&(M2&T4);
ctl_alu_core_hf = ctl_alu_core_hf | (op3&pla[68])&(M2&T4)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (op3&pla[68])&(M2&T4);
ctl_reg_use_sp = ctl_reg_use_sp | (op3&pla[68])&(M2&T4);
ctl_reg_sel_wz = ctl_reg_sel_wz | (op3&pla[68])&(M3&T1);
ctl_reg_sys_hilo_op3pla68M3T1_2 = (op3&pla[68])&(M3&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_op3pla68M3T1_2,ctl_reg_sys_hilo_op3pla68M3T1_2})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (op3&pla[68])&(M3&T1);
ctl_al_we = ctl_al_we | (op3&pla[68])&(M3&T1);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (op3&pla[68])&(M3&T1);
ctl_reg_sel_wz = ctl_reg_sel_wz | (op3&pla[68])&(M3&T1);
ctl_reg_sys_hilo_op3pla68M3T1_7 = (op3&pla[68])&(M3&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_op3pla68M3T1_7,ctl_reg_sys_hilo_op3pla68M3T1_7})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (op3&pla[68])&(M3&T1);
ctl_sw_2u = ctl_sw_2u | (op3&pla[68])&(M3&T1);
ctl_flags_alu = ctl_flags_alu | (op3&pla[68])&(M3&T1);
ctl_alu_oe = ctl_alu_oe | (op3&pla[68])&(M3&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (op3&pla[68])&(M3&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (op3&pla[68])&(M3&T1);
ctl_alu_core_hf = ctl_alu_core_hf | (op3&pla[68])&(M3&T1)&(~ctl_alu_op_low);
ctl_flags_sz_we = ctl_flags_sz_we | (op3&pla[68])&(M3&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (op3&pla[68])&(M3&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (op3&pla[68])&(M3&T1);
ctl_pf_sel_op3pla68M3T1_18 = (op3&pla[68])&(M3&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_op3pla68M3T1_18,ctl_pf_sel_op3pla68M3T1_18})&(`PFSEL_V);
ctl_flags_cf_we = ctl_flags_cf_we | (op3&pla[68])&(M3&T1);
ctl_alu_zero_16bit = ctl_alu_zero_16bit | (op3&pla[68])&(M3&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (op3&pla[68])&(M3&T2);
ctl_reg_gp_sel_op3pla68M3T2_2 = (op3&pla[68])&(M3&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_op3pla68M3T2_2,ctl_reg_gp_sel_op3pla68M3T2_2})&(`GP_REG_HL);
ctl_reg_gp_hilo_op3pla68M3T2_3 = (op3&pla[68])&(M3&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_op3pla68M3T2_3,ctl_reg_gp_hilo_op3pla68M3T2_3})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (op3&pla[68])&(M3&T2);
ctl_bus_inc_oe = ctl_bus_inc_oe | (op3&pla[68])&(M3&T2);
setM1 = setM1 | (op3&pla[68])&(M3&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (~op3&pla[68])&(M1&T2);
ctl_reg_gp_sel_nop3pla68M1T2_2 = (~op3&pla[68])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nop3pla68M1T2_2,ctl_reg_gp_sel_nop3pla68M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_nop3pla68M1T2_3 = (~op3&pla[68])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nop3pla68M1T2_3,ctl_reg_gp_hilo_nop3pla68M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (~op3&pla[68])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (~op3&pla[68])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (~op3&pla[68])&(M1&T2);
ctl_flags_hf_cpl = ctl_flags_hf_cpl | (~op3&pla[68])&(M1&T2)&(flags_nf);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~op3&pla[68])&(M1&T2)&(flags_nf);
ctl_reg_gp_sel_nop3pla68M1T3_1 = (~op3&pla[68])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nop3pla68M1T3_1,ctl_reg_gp_sel_nop3pla68M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_nop3pla68M1T3_2 = (~op3&pla[68])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nop3pla68M1T3_2,ctl_reg_gp_hilo_nop3pla68M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (~op3&pla[68])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (~op3&pla[68])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (~op3&pla[68])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~op3&pla[68])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~op3&pla[68])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~op3&pla[68])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (~op3&pla[68])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (~op3&pla[68])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (~op3&pla[68])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (~op3&pla[68])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (~op3&pla[68])&(M1&T3);
ctl_flags_nf_set = ctl_flags_nf_set | (~op3&pla[68])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (~op3&pla[68])&(M1&T3);
validPLA = validPLA | (~op3&pla[68])&(M1&T4);
nextM = nextM | (~op3&pla[68])&(M1&T4);
ctl_reg_gp_sel_nop3pla68M1T4_3 = (~op3&pla[68])&(M1&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nop3pla68M1T4_3,ctl_reg_gp_sel_nop3pla68M1T4_3})&(`GP_REG_HL);
ctl_reg_gp_hilo_nop3pla68M1T4_4 = (~op3&pla[68])&(M1&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nop3pla68M1T4_4,ctl_reg_gp_hilo_nop3pla68M1T4_4})&(2'b01);
ctl_reg_out_lo = ctl_reg_out_lo | (~op3&pla[68])&(M1&T4);
ctl_sw_2d = ctl_sw_2d | (~op3&pla[68])&(M1&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~op3&pla[68])&(M1&T4)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~op3&pla[68])&(M1&T4);
ctl_reg_gp_sel_nop3pla68M2T1_1 = (~op3&pla[68])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nop3pla68M2T1_1,ctl_reg_gp_sel_nop3pla68M2T1_1})&(op54);
ctl_reg_gp_hilo_nop3pla68M2T1_2 = (~op3&pla[68])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nop3pla68M2T1_2,ctl_reg_gp_hilo_nop3pla68M2T1_2})&(2'b01);
ctl_reg_out_lo = ctl_reg_out_lo | (~op3&pla[68])&(M2&T1);
ctl_sw_2d = ctl_sw_2d | (~op3&pla[68])&(M2&T1);
ctl_flags_alu = ctl_flags_alu | (~op3&pla[68])&(M2&T1);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~op3&pla[68])&(M2&T1)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~op3&pla[68])&(M2&T1);
ctl_alu_op_low = ctl_alu_op_low | (~op3&pla[68])&(M2&T1);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~op3&pla[68])&(M2&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~op3&pla[68])&(M2&T1)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (~op3&pla[68])&(M2&T1)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (~op3&pla[68])&(M2&T1);
ctl_reg_use_sp = ctl_reg_use_sp | (~op3&pla[68])&(M2&T1);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (~op3&pla[68])&(M2&T2);
ctl_reg_sel_wz = ctl_reg_sel_wz | (~op3&pla[68])&(M2&T2);
ctl_reg_sys_hilo_nop3pla68M2T2_3 = (~op3&pla[68])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nop3pla68M2T2_3,ctl_reg_sys_hilo_nop3pla68M2T2_3})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (~op3&pla[68])&(M2&T2);
ctl_sw_2u = ctl_sw_2u | (~op3&pla[68])&(M2&T2);
ctl_flags_alu = ctl_flags_alu | (~op3&pla[68])&(M2&T2);
ctl_alu_oe = ctl_alu_oe | (~op3&pla[68])&(M2&T2);
ctl_alu_res_oe = ctl_alu_res_oe | (~op3&pla[68])&(M2&T2);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~op3&pla[68])&(M2&T2);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~op3&pla[68])&(M2&T2);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~op3&pla[68])&(M2&T2)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (~op3&pla[68])&(M2&T2)&(~ctl_alu_op_low);
ctl_flags_sz_we = ctl_flags_sz_we | (~op3&pla[68])&(M2&T2);
ctl_flags_xy_we = ctl_flags_xy_we | (~op3&pla[68])&(M2&T2);
ctl_flags_cf_we = ctl_flags_cf_we | (~op3&pla[68])&(M2&T2);
ctl_reg_gp_sel_nop3pla68M2T3_1 = (~op3&pla[68])&(M2&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nop3pla68M2T3_1,ctl_reg_gp_sel_nop3pla68M2T3_1})&(`GP_REG_HL);
ctl_reg_gp_hilo_nop3pla68M2T3_2 = (~op3&pla[68])&(M2&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nop3pla68M2T3_2,ctl_reg_gp_hilo_nop3pla68M2T3_2})&(2'b10);
ctl_reg_out_hi = ctl_reg_out_hi | (~op3&pla[68])&(M2&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (~op3&pla[68])&(M2&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~op3&pla[68])&(M2&T3)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~op3&pla[68])&(M2&T3);
nextM = nextM | (~op3&pla[68])&(M2&T4);
ctl_reg_gp_sel_nop3pla68M2T4_2 = (~op3&pla[68])&(M2&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nop3pla68M2T4_2,ctl_reg_gp_sel_nop3pla68M2T4_2})&(op54);
ctl_reg_gp_hilo_nop3pla68M2T4_3 = (~op3&pla[68])&(M2&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nop3pla68M2T4_3,ctl_reg_gp_hilo_nop3pla68M2T4_3})&(2'b10);
ctl_reg_out_hi = ctl_reg_out_hi | (~op3&pla[68])&(M2&T4);
ctl_reg_out_lo = ctl_reg_out_lo | (~op3&pla[68])&(M2&T4);
ctl_flags_alu = ctl_flags_alu | (~op3&pla[68])&(M2&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~op3&pla[68])&(M2&T4)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~op3&pla[68])&(M2&T4);
ctl_alu_op_low = ctl_alu_op_low | (~op3&pla[68])&(M2&T4);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~op3&pla[68])&(M2&T4);
ctl_alu_core_hf = ctl_alu_core_hf | (~op3&pla[68])&(M2&T4)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (~op3&pla[68])&(M2&T4);
ctl_reg_use_sp = ctl_reg_use_sp | (~op3&pla[68])&(M2&T4);
ctl_reg_sel_wz = ctl_reg_sel_wz | (~op3&pla[68])&(M3&T1);
ctl_reg_sys_hilo_nop3pla68M3T1_2 = (~op3&pla[68])&(M3&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nop3pla68M3T1_2,ctl_reg_sys_hilo_nop3pla68M3T1_2})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (~op3&pla[68])&(M3&T1);
ctl_al_we = ctl_al_we | (~op3&pla[68])&(M3&T1);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (~op3&pla[68])&(M3&T1);
ctl_reg_sel_wz = ctl_reg_sel_wz | (~op3&pla[68])&(M3&T1);
ctl_reg_sys_hilo_nop3pla68M3T1_7 = (~op3&pla[68])&(M3&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nop3pla68M3T1_7,ctl_reg_sys_hilo_nop3pla68M3T1_7})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (~op3&pla[68])&(M3&T1);
ctl_sw_2u = ctl_sw_2u | (~op3&pla[68])&(M3&T1);
ctl_flags_alu = ctl_flags_alu | (~op3&pla[68])&(M3&T1);
ctl_alu_oe = ctl_alu_oe | (~op3&pla[68])&(M3&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (~op3&pla[68])&(M3&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~op3&pla[68])&(M3&T1);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~op3&pla[68])&(M3&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~op3&pla[68])&(M3&T1)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (~op3&pla[68])&(M3&T1)&(~ctl_alu_op_low);
ctl_flags_sz_we = ctl_flags_sz_we | (~op3&pla[68])&(M3&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (~op3&pla[68])&(M3&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (~op3&pla[68])&(M3&T1);
ctl_pf_sel_nop3pla68M3T1_20 = (~op3&pla[68])&(M3&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_nop3pla68M3T1_20,ctl_pf_sel_nop3pla68M3T1_20})&(`PFSEL_V);
ctl_flags_cf_we = ctl_flags_cf_we | (~op3&pla[68])&(M3&T1);
ctl_alu_zero_16bit = ctl_alu_zero_16bit | (~op3&pla[68])&(M3&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (~op3&pla[68])&(M3&T2);
ctl_reg_gp_sel_nop3pla68M3T2_2 = (~op3&pla[68])&(M3&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nop3pla68M3T2_2,ctl_reg_gp_sel_nop3pla68M3T2_2})&(`GP_REG_HL);
ctl_reg_gp_hilo_nop3pla68M3T2_3 = (~op3&pla[68])&(M3&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nop3pla68M3T2_3,ctl_reg_gp_hilo_nop3pla68M3T2_3})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (~op3&pla[68])&(M3&T2);
ctl_bus_inc_oe = ctl_bus_inc_oe | (~op3&pla[68])&(M3&T2);
setM1 = setM1 | (~op3&pla[68])&(M3&T3);
validPLA = validPLA | (pla[9])&(M1&T4);
ctl_reg_gp_sel_pla9M1T4_2 = (pla[9])&(M1&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla9M1T4_2,ctl_reg_gp_sel_pla9M1T4_2})&(op54);
ctl_reg_gp_hilo_pla9M1T4_3 = (pla[9])&(M1&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla9M1T4_3,ctl_reg_gp_hilo_pla9M1T4_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[9])&(M1&T4);
ctl_al_we = ctl_al_we | (pla[9])&(M1&T4);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[9])&(M1&T4);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[9])&(M1&T5);
ctl_reg_gp_sel_pla9M1T5_2 = (pla[9])&(M1&T5);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla9M1T5_2,ctl_reg_gp_sel_pla9M1T5_2})&(op54);
ctl_reg_gp_hilo_pla9M1T5_3 = (pla[9])&(M1&T5);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla9M1T5_3,ctl_reg_gp_hilo_pla9M1T5_3})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[9])&(M1&T5);
ctl_inc_cy = ctl_inc_cy | (pla[9])&(M1&T5)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[9])&(M1&T5)&(op3);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[9])&(M1&T5);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[9])&(M1&T5);
setM1 = setM1 | (pla[9])&(M1&T6);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[77])&(M1&T1);
ctl_reg_gp_sel_pla77M1T1_2 = (pla[77])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla77M1T1_2,ctl_reg_gp_sel_pla77M1T1_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla77M1T1_3 = (pla[77])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla77M1T1_3,ctl_reg_gp_hilo_pla77M1T1_3})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[77])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[77])&(M1&T1);
ctl_flags_alu = ctl_flags_alu | (pla[77])&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (pla[77])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[77])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[77])&(M1&T1);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[77])&(M1&T1)&(~ctl_alu_op_low);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[77])&(M1&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[77])&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[77])&(M1&T1);
ctl_pf_sel_pla77M1T1_14 = (pla[77])&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla77M1T1_14,ctl_pf_sel_pla77M1T1_14})&(`PFSEL_P);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[77])&(M1&T1);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[77])&(M1&T1)&(flags_nf);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[77])&(M1&T1)&(~flags_nf);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[77])&(M1&T2);
ctl_reg_gp_sel_pla77M1T2_2 = (pla[77])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla77M1T2_2,ctl_reg_gp_sel_pla77M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla77M1T2_3 = (pla[77])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla77M1T2_3,ctl_reg_gp_hilo_pla77M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[77])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[77])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (pla[77])&(M1&T2);
ctl_flags_use_cf2 = ctl_flags_use_cf2 | (pla[77])&(M1&T2);
ctl_flags_hf_cpl = ctl_flags_hf_cpl | (pla[77])&(M1&T2)&(flags_nf);
ctl_reg_gp_sel_pla77M1T3_1 = (pla[77])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla77M1T3_1,ctl_reg_gp_sel_pla77M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla77M1T3_2 = (pla[77])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla77M1T3_2,ctl_reg_gp_hilo_pla77M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[77])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[77])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[77])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[77])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[77])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[77])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[77])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[77])&(M1&T3);
ctl_flags_hf2_we = ctl_flags_hf2_we | (pla[77])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[77])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[77])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[77])&(M1&T3);
validPLA = validPLA | (pla[77])&(M1&T4);
setM1 = setM1 | (pla[77])&(M1&T4);
ctl_sw_2d = ctl_sw_2d | (pla[77])&(M1&T4);
ctl_flags_alu = ctl_flags_alu | (pla[77])&(M1&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[77])&(M1&T4)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[77])&(M1&T4);
ctl_alu_op_low = ctl_alu_op_low | (pla[77])&(M1&T4);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[77])&(M1&T4)&(~ctl_alu_op_low);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[77])&(M1&T4);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[77])&(M1&T4);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[77])&(M1&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[77])&(M1&T4);
ctl_flags_cf2_we = ctl_flags_cf2_we | (pla[77])&(M1&T4);
ctl_flags_cf2_sel_daa = ctl_flags_cf2_sel_daa | (pla[77])&(M1&T4);
ctl_daa_oe = ctl_daa_oe | (pla[77])&(M1&T4);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[77])&(M1&T4)&(flags_nf);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[77])&(M1&T4)&(~flags_nf);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[81])&(M1&T1);
ctl_reg_gp_sel_pla81M1T1_2 = (pla[81])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla81M1T1_2,ctl_reg_gp_sel_pla81M1T1_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla81M1T1_3 = (pla[81])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla81M1T1_3,ctl_reg_gp_hilo_pla81M1T1_3})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[81])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[81])&(M1&T1);
ctl_flags_alu = ctl_flags_alu | (pla[81])&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (pla[81])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[81])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[81])&(M1&T1);
ctl_alu_core_R = ctl_alu_core_R | (pla[81])&(M1&T1);
ctl_alu_core_V = ctl_alu_core_V | (pla[81])&(M1&T1);
ctl_alu_core_S = ctl_alu_core_S | (pla[81])&(M1&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[81])&(M1&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[81])&(M1&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[81])&(M1&T1);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[81])&(M1&T1);
ctl_flags_nf_set = ctl_flags_nf_set | (pla[81])&(M1&T1);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[81])&(M1&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[81])&(M1&T2);
ctl_reg_gp_sel_pla81M1T2_2 = (pla[81])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla81M1T2_2,ctl_reg_gp_sel_pla81M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla81M1T2_3 = (pla[81])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla81M1T2_3,ctl_reg_gp_hilo_pla81M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[81])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[81])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (pla[81])&(M1&T2);
ctl_flags_hf_cpl = ctl_flags_hf_cpl | (pla[81])&(M1&T2)&(flags_nf);
ctl_reg_gp_sel_pla81M1T3_1 = (pla[81])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla81M1T3_1,ctl_reg_gp_sel_pla81M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla81M1T3_2 = (pla[81])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla81M1T3_2,ctl_reg_gp_hilo_pla81M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[81])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[81])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[81])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[81])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[81])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[81])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[81])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[81])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[81])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[81])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[81])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[81])&(M1&T3);
validPLA = validPLA | (pla[81])&(M1&T4);
setM1 = setM1 | (pla[81])&(M1&T4);
ctl_flags_alu = ctl_flags_alu | (pla[81])&(M1&T4);
ctl_alu_op1_sel_zero = ctl_alu_op1_sel_zero | (pla[81])&(M1&T4);
ctl_alu_op_low = ctl_alu_op_low | (pla[81])&(M1&T4);
ctl_alu_core_R = ctl_alu_core_R | (pla[81])&(M1&T4);
ctl_alu_core_V = ctl_alu_core_V | (pla[81])&(M1&T4);
ctl_alu_core_S = ctl_alu_core_S | (pla[81])&(M1&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[81])&(M1&T4);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[81])&(M1&T4);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[81])&(M1&T4);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[81])&(M1&T4);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[81])&(M1&T4);
ctl_flags_nf_set = ctl_flags_nf_set | (pla[81])&(M1&T4);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[81])&(M1&T4);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[82])&(M1&T1);
ctl_reg_gp_sel_pla82M1T1_2 = (pla[82])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla82M1T1_2,ctl_reg_gp_sel_pla82M1T1_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla82M1T1_3 = (pla[82])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla82M1T1_3,ctl_reg_gp_hilo_pla82M1T1_3})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[82])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[82])&(M1&T1);
ctl_flags_alu = ctl_flags_alu | (pla[82])&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (pla[82])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[82])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[82])&(M1&T1);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[82])&(M1&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[82])&(M1&T1)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[82])&(M1&T1)&(~ctl_alu_op_low);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[82])&(M1&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[82])&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[82])&(M1&T1);
ctl_pf_sel_pla82M1T1_16 = (pla[82])&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla82M1T1_16,ctl_pf_sel_pla82M1T1_16})&(`PFSEL_V);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[82])&(M1&T1);
ctl_flags_nf_set = ctl_flags_nf_set | (pla[82])&(M1&T1);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[82])&(M1&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[82])&(M1&T2);
ctl_reg_gp_sel_pla82M1T2_2 = (pla[82])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla82M1T2_2,ctl_reg_gp_sel_pla82M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla82M1T2_3 = (pla[82])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla82M1T2_3,ctl_reg_gp_hilo_pla82M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[82])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[82])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (pla[82])&(M1&T2);
ctl_flags_hf_cpl = ctl_flags_hf_cpl | (pla[82])&(M1&T2)&(flags_nf);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[82])&(M1&T2)&(flags_nf);
ctl_reg_gp_sel_pla82M1T3_1 = (pla[82])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla82M1T3_1,ctl_reg_gp_sel_pla82M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla82M1T3_2 = (pla[82])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla82M1T3_2,ctl_reg_gp_hilo_pla82M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[82])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[82])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[82])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[82])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[82])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[82])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[82])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[82])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[82])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[82])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[82])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[82])&(M1&T3);
validPLA = validPLA | (pla[82])&(M1&T4);
setM1 = setM1 | (pla[82])&(M1&T4);
ctl_flags_alu = ctl_flags_alu | (pla[82])&(M1&T4);
ctl_alu_op1_sel_zero = ctl_alu_op1_sel_zero | (pla[82])&(M1&T4);
ctl_alu_op_low = ctl_alu_op_low | (pla[82])&(M1&T4);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[82])&(M1&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[82])&(M1&T4)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[82])&(M1&T4)&(~ctl_alu_op_low);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[82])&(M1&T4);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[82])&(M1&T4);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[82])&(M1&T4);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[82])&(M1&T4);
ctl_flags_nf_set = ctl_flags_nf_set | (pla[82])&(M1&T4);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[82])&(M1&T4);
ctl_flags_alu = ctl_flags_alu | (pla[89])&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (pla[89])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[89])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[89])&(M1&T1);
ctl_alu_core_R = ctl_alu_core_R | (pla[89])&(M1&T1);
ctl_alu_core_V = ctl_alu_core_V | (pla[89])&(M1&T1);
ctl_alu_core_S = ctl_alu_core_S | (pla[89])&(M1&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[89])&(M1&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[89])&(M1&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[89])&(M1&T1);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[89])&(M1&T1);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[89])&(M1&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[89])&(M1&T2);
ctl_reg_gp_sel_pla89M1T2_2 = (pla[89])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla89M1T2_2,ctl_reg_gp_sel_pla89M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla89M1T2_3 = (pla[89])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla89M1T2_3,ctl_reg_gp_hilo_pla89M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[89])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[89])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (pla[89])&(M1&T2);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[89])&(M1&T2);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[89])&(M1&T2);
ctl_flags_hf_cpl = ctl_flags_hf_cpl | (pla[89])&(M1&T2)&(~flags_cf);
ctl_reg_gp_sel_pla89M1T3_1 = (pla[89])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla89M1T3_1,ctl_reg_gp_sel_pla89M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla89M1T3_2 = (pla[89])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla89M1T3_2,ctl_reg_gp_hilo_pla89M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[89])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[89])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[89])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[89])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[89])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[89])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[89])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[89])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[89])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[89])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[89])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[89])&(M1&T3);
validPLA = validPLA | (pla[89])&(M1&T4);
setM1 = setM1 | (pla[89])&(M1&T4);
ctl_flags_alu = ctl_flags_alu | (pla[89])&(M1&T4);
ctl_alu_op_low = ctl_alu_op_low | (pla[89])&(M1&T4);
ctl_alu_core_R = ctl_alu_core_R | (pla[89])&(M1&T4);
ctl_alu_core_V = ctl_alu_core_V | (pla[89])&(M1&T4);
ctl_alu_core_S = ctl_alu_core_S | (pla[89])&(M1&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[89])&(M1&T4);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[89])&(M1&T4);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[89])&(M1&T4);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[89])&(M1&T4);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[89])&(M1&T4);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[89])&(M1&T4);
ctl_flags_alu = ctl_flags_alu | (pla[92])&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (pla[92])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[92])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[92])&(M1&T1);
ctl_alu_core_R = ctl_alu_core_R | (pla[92])&(M1&T1);
ctl_alu_core_V = ctl_alu_core_V | (pla[92])&(M1&T1);
ctl_alu_core_S = ctl_alu_core_S | (pla[92])&(M1&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[92])&(M1&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[92])&(M1&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[92])&(M1&T1);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[92])&(M1&T1);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[92])&(M1&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[92])&(M1&T2);
ctl_reg_gp_sel_pla92M1T2_2 = (pla[92])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla92M1T2_2,ctl_reg_gp_sel_pla92M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla92M1T2_3 = (pla[92])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla92M1T2_3,ctl_reg_gp_hilo_pla92M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[92])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[92])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (pla[92])&(M1&T2);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[92])&(M1&T2);
ctl_reg_gp_sel_pla92M1T3_1 = (pla[92])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla92M1T3_1,ctl_reg_gp_sel_pla92M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla92M1T3_2 = (pla[92])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla92M1T3_2,ctl_reg_gp_hilo_pla92M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[92])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[92])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[92])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[92])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[92])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[92])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[92])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[92])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[92])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[92])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[92])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[92])&(M1&T3);
validPLA = validPLA | (pla[92])&(M1&T4);
setM1 = setM1 | (pla[92])&(M1&T4);
ctl_flags_alu = ctl_flags_alu | (pla[92])&(M1&T4);
ctl_alu_op_low = ctl_alu_op_low | (pla[92])&(M1&T4);
ctl_alu_core_R = ctl_alu_core_R | (pla[92])&(M1&T4);
ctl_alu_core_V = ctl_alu_core_V | (pla[92])&(M1&T4);
ctl_alu_core_S = ctl_alu_core_S | (pla[92])&(M1&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[92])&(M1&T4);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[92])&(M1&T4);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[92])&(M1&T4);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[92])&(M1&T4);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[92])&(M1&T4);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[92])&(M1&T4);
ctl_state_halt_set = ctl_state_halt_set | (pla[95])&(M1&T3);
validPLA = validPLA | (pla[95])&(M1&T4);
setM1 = setM1 | (pla[95])&(M1&T4);
ctl_iffx_bit = ctl_iffx_bit | (pla[97])&(M1&T3)&(op3);
ctl_iffx_we = ctl_iffx_we | (pla[97])&(M1&T3);
validPLA = validPLA | (pla[97])&(M1&T4);
setM1 = setM1 | (pla[97])&(M1&T4);
ctl_no_ints = ctl_no_ints | (pla[97])&(M1&T4);
ctl_sw_1d = ctl_sw_1d | (pla[96])&(M1&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[96])&(M1&T3);
ctl_im_we = ctl_im_we | (pla[96])&(M1&T3);
validPLA = validPLA | (pla[96])&(M1&T4);
setM1 = setM1 | (pla[96])&(M1&T4);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[25])&(M1&T1);
ctl_reg_gp_sel_pla25M1T1_2 = (pla[25])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla25M1T1_2,ctl_reg_gp_sel_pla25M1T1_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla25M1T1_3 = (pla[25])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla25M1T1_3,ctl_reg_gp_hilo_pla25M1T1_3})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[25])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[25])&(M1&T1);
ctl_flags_alu = ctl_flags_alu | (pla[25])&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (pla[25])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[25])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[25])&(M1&T1);
ctl_alu_core_R = ctl_alu_core_R | (pla[25])&(M1&T1);
ctl_alu_core_V = ctl_alu_core_V | (pla[25])&(M1&T1);
ctl_alu_core_S = ctl_alu_core_S | (pla[25])&(M1&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[25])&(M1&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[25])&(M1&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[25])&(M1&T1);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[25])&(M1&T1);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[25])&(M1&T1);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[25])&(M1&T1);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[25])&(M1&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[25])&(M1&T2);
ctl_reg_gp_sel_pla25M1T2_2 = (pla[25])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla25M1T2_2,ctl_reg_gp_sel_pla25M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla25M1T2_3 = (pla[25])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla25M1T2_3,ctl_reg_gp_hilo_pla25M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[25])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[25])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (pla[25])&(M1&T2);
ctl_flags_use_cf2 = ctl_flags_use_cf2 | (pla[25])&(M1&T2);
ctl_reg_gp_sel_pla25M1T3_1 = (pla[25])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla25M1T3_1,ctl_reg_gp_sel_pla25M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla25M1T3_2 = (pla[25])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla25M1T3_2,ctl_reg_gp_hilo_pla25M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[25])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[25])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[25])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[25])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[25])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[25])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[25])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[25])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[25])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[25])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[25])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[25])&(M1&T3);
validPLA = validPLA | (pla[25])&(M1&T4);
setM1 = setM1 | (pla[25])&(M1&T4);
ctl_reg_gp_sel_pla25M1T4_3 = (pla[25])&(M1&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla25M1T4_3,ctl_reg_gp_sel_pla25M1T4_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla25M1T4_4 = (pla[25])&(M1&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla25M1T4_4,ctl_reg_gp_hilo_pla25M1T4_4})&(2'b10);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[25])&(M1&T4);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[25])&(M1&T4);
ctl_flags_alu = ctl_flags_alu | (pla[25])&(M1&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[25])&(M1&T4);
ctl_shift_en = ctl_shift_en | (pla[25])&(M1&T4);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[25])&(M1&T4);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[25])&(M1&T4);
ctl_alu_op_low = ctl_alu_op_low | (pla[25])&(M1&T4);
ctl_alu_core_R = ctl_alu_core_R | (pla[25])&(M1&T4);
ctl_alu_core_V = ctl_alu_core_V | (pla[25])&(M1&T4);
ctl_alu_core_S = ctl_alu_core_S | (pla[25])&(M1&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[25])&(M1&T4);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[25])&(M1&T4);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[25])&(M1&T4);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[25])&(M1&T4);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[25])&(M1&T4);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[25])&(M1&T4);
ctl_flags_cf2_we = ctl_flags_cf2_we | (pla[25])&(M1&T4);
ctl_flags_cf2_sel_shift = ctl_flags_cf2_sel_shift | (pla[25])&(M1&T4);
ctl_reg_gp_we = ctl_reg_gp_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_reg_gp_sel_nuse_ixiypla70npla55M1T1_2 = (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla70npla55M1T1_2,ctl_reg_gp_sel_nuse_ixiypla70npla55M1T1_2})&(op21);
ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T1_3 = (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T1_3,ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T1_3})&({~rsel0,rsel0});
ctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_pf_sel_nuse_ixiypla70npla55M1T1_20 = (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_nuse_ixiypla70npla55M1T1_20,ctl_pf_sel_nuse_ixiypla70npla55M1T1_20})&(`PFSEL_P);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T2);
ctl_reg_gp_sel_nuse_ixiypla70npla55M1T2_2 = (~use_ixiy&pla[70]&~pla[55])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla70npla55M1T2_2,ctl_reg_gp_sel_nuse_ixiypla70npla55M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T2_3 = (~use_ixiy&pla[70]&~pla[55])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T2_3,ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[70]&~pla[55])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[70]&~pla[55])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (~use_ixiy&pla[70]&~pla[55])&(M1&T2);
ctl_flags_use_cf2 = ctl_flags_use_cf2 | (~use_ixiy&pla[70]&~pla[55])&(M1&T2);
ctl_reg_gp_sel_nuse_ixiypla70npla55M1T3_1 = (~use_ixiy&pla[70]&~pla[55])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla70npla55M1T3_1,ctl_reg_gp_sel_nuse_ixiypla70npla55M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T3_2 = (~use_ixiy&pla[70]&~pla[55])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T3_2,ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[70]&~pla[55])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);
validPLA = validPLA | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
setM1 = setM1 | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
ctl_reg_gp_sel_nuse_ixiypla70npla55M1T4_3 = (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla70npla55M1T4_3,ctl_reg_gp_sel_nuse_ixiypla70npla55M1T4_3})&(op21);
ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T4_4 = (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T4_4,ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T4_4})&({~rsel0,rsel0});
ctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[70]&~pla[55])&(M1&T4)&(~rsel0);
ctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[70]&~pla[55])&(M1&T4)&(rsel0);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[70]&~pla[55])&(M1&T4)&(~rsel0);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[70]&~pla[55])&(M1&T4)&(rsel0);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
ctl_shift_en = ctl_shift_en | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
ctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
ctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
ctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
ctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
ctl_flags_cf2_we = ctl_flags_cf2_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
ctl_flags_cf2_sel_shift = ctl_flags_cf2_sel_shift | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);
fMRead = fMRead | (~use_ixiy&pla[70]&~pla[55])&(M4&T1);
ctl_reg_sel_wz = ctl_reg_sel_wz | (~use_ixiy&pla[70]&~pla[55])&(M4&T1);
ctl_reg_sys_hilo_nuse_ixiypla70npla55M4T1_3 = (~use_ixiy&pla[70]&~pla[55])&(M4&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nuse_ixiypla70npla55M4T1_3,ctl_reg_sys_hilo_nuse_ixiypla70npla55M4T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[70]&~pla[55])&(M4&T1);
ctl_al_we = ctl_al_we | (~use_ixiy&pla[70]&~pla[55])&(M4&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[70]&~pla[55])&(M4&T1);
ctl_ir_we = ctl_ir_we | (~use_ixiy&pla[70]&~pla[55])&(M4&T1);
fMRead = fMRead | (~use_ixiy&pla[70]&~pla[55])&(M4&T2);
fMRead = fMRead | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
nextM = nextM | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
ctl_mWrite = ctl_mWrite | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
ctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
ctl_shift_en = ctl_shift_en | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
ctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
ctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
ctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
ctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
ctl_flags_cf2_we = ctl_flags_cf2_we | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
ctl_flags_cf2_sel_shift = ctl_flags_cf2_sel_shift | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);
fMWrite = fMWrite | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_pf_sel_nuse_ixiypla70npla55M5T1_19 = (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_nuse_ixiypla70npla55M5T1_19,ctl_pf_sel_nuse_ixiypla70npla55M5T1_19})&(`PFSEL_P);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
ctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);
fMWrite = fMWrite | (~use_ixiy&pla[70]&~pla[55])&(M5&T2);
fMWrite = fMWrite | (~use_ixiy&pla[70]&~pla[55])&(M5&T3);
setM1 = setM1 | (~use_ixiy&pla[70]&~pla[55])&(M5&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (~use_ixiy&pla[70]&pla[55])&(M1&T2);
ctl_reg_gp_sel_nuse_ixiypla70pla55M1T2_2 = (~use_ixiy&pla[70]&pla[55])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla70pla55M1T2_2,ctl_reg_gp_sel_nuse_ixiypla70pla55M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_nuse_ixiypla70pla55M1T2_3 = (~use_ixiy&pla[70]&pla[55])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla70pla55M1T2_3,ctl_reg_gp_hilo_nuse_ixiypla70pla55M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[70]&pla[55])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[70]&pla[55])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (~use_ixiy&pla[70]&pla[55])&(M1&T2);
ctl_flags_use_cf2 = ctl_flags_use_cf2 | (~use_ixiy&pla[70]&pla[55])&(M1&T2);
ctl_reg_gp_sel_nuse_ixiypla70pla55M1T3_1 = (~use_ixiy&pla[70]&pla[55])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla70pla55M1T3_1,ctl_reg_gp_sel_nuse_ixiypla70pla55M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_nuse_ixiypla70pla55M1T3_2 = (~use_ixiy&pla[70]&pla[55])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla70pla55M1T3_2,ctl_reg_gp_hilo_nuse_ixiypla70pla55M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[70]&pla[55])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[70]&pla[55])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[70]&pla[55])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[70]&pla[55])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[70]&pla[55])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[70]&pla[55])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[70]&pla[55])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[70]&pla[55])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[70]&pla[55])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[70]&pla[55])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[70]&pla[55])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[70]&pla[55])&(M1&T3);
validPLA = validPLA | (~use_ixiy&pla[70]&pla[55])&(M1&T4);
nextM = nextM | (~use_ixiy&pla[70]&pla[55])&(M1&T4);
ctl_mRead = ctl_mRead | (~use_ixiy&pla[70]&pla[55])&(M1&T4);
fMRead = fMRead | (~use_ixiy&pla[70]&pla[55])&(M2&T1);
ctl_reg_gp_sel_nuse_ixiypla70pla55M2T1_2 = (~use_ixiy&pla[70]&pla[55])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla70pla55M2T1_2,ctl_reg_gp_sel_nuse_ixiypla70pla55M2T1_2})&(`GP_REG_HL);
ctl_reg_gp_hilo_nuse_ixiypla70pla55M2T1_3 = (~use_ixiy&pla[70]&pla[55])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla70pla55M2T1_3,ctl_reg_gp_hilo_nuse_ixiypla70pla55M2T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[70]&pla[55])&(M2&T1);
ctl_al_we = ctl_al_we | (~use_ixiy&pla[70]&pla[55])&(M2&T1);
fMRead = fMRead | (~use_ixiy&pla[70]&pla[55])&(M2&T2);
fMRead = fMRead | (~use_ixiy&pla[70]&pla[55])&(M2&T3);
nextM = nextM | (~use_ixiy&pla[70]&pla[55])&(M2&T4);
ctl_mWrite = ctl_mWrite | (~use_ixiy&pla[70]&pla[55])&(M2&T4);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[70]&pla[55])&(M2&T4);
ctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[70]&pla[55])&(M2&T4);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[70]&pla[55])&(M2&T4);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[70]&pla[55])&(M2&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[70]&pla[55])&(M2&T4);
ctl_shift_en = ctl_shift_en | (~use_ixiy&pla[70]&pla[55])&(M2&T4);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[70]&pla[55])&(M2&T4);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[70]&pla[55])&(M2&T4);
ctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[70]&pla[55])&(M2&T4);
ctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[70]&pla[55])&(M2&T4);
ctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[70]&pla[55])&(M2&T4);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[70]&pla[55])&(M2&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[70]&pla[55])&(M2&T4);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[70]&pla[55])&(M2&T4);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[70]&pla[55])&(M2&T4);
ctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[70]&pla[55])&(M2&T4);
ctl_flags_cf2_we = ctl_flags_cf2_we | (~use_ixiy&pla[70]&pla[55])&(M2&T4);
ctl_flags_cf2_sel_shift = ctl_flags_cf2_sel_shift | (~use_ixiy&pla[70]&pla[55])&(M2&T4);
fMWrite = fMWrite | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_pf_sel_nuse_ixiypla70pla55M3T1_19 = (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_nuse_ixiypla70pla55M3T1_19,ctl_pf_sel_nuse_ixiypla70pla55M3T1_19})&(`PFSEL_P);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
ctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[70]&pla[55])&(M3&T1);
fMWrite = fMWrite | (~use_ixiy&pla[70]&pla[55])&(M3&T2);
fMWrite = fMWrite | (~use_ixiy&pla[70]&pla[55])&(M3&T3);
setM1 = setM1 | (~use_ixiy&pla[70]&pla[55])&(M3&T3);
fMRead = fMRead | (~use_ixiy&pla[70]&pla[55])&(M4&T1);
ctl_reg_sel_wz = ctl_reg_sel_wz | (~use_ixiy&pla[70]&pla[55])&(M4&T1);
ctl_reg_sys_hilo_nuse_ixiypla70pla55M4T1_3 = (~use_ixiy&pla[70]&pla[55])&(M4&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nuse_ixiypla70pla55M4T1_3,ctl_reg_sys_hilo_nuse_ixiypla70pla55M4T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[70]&pla[55])&(M4&T1);
ctl_al_we = ctl_al_we | (~use_ixiy&pla[70]&pla[55])&(M4&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[70]&pla[55])&(M4&T1);
ctl_ir_we = ctl_ir_we | (~use_ixiy&pla[70]&pla[55])&(M4&T1);
fMRead = fMRead | (~use_ixiy&pla[70]&pla[55])&(M4&T2);
fMRead = fMRead | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
nextM = nextM | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
ctl_mWrite = ctl_mWrite | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
ctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
ctl_shift_en = ctl_shift_en | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
ctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
ctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
ctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
ctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
ctl_flags_cf2_we = ctl_flags_cf2_we | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
ctl_flags_cf2_sel_shift = ctl_flags_cf2_sel_shift | (~use_ixiy&pla[70]&pla[55])&(M4&T3);
fMWrite = fMWrite | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_pf_sel_nuse_ixiypla70pla55M5T1_19 = (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_nuse_ixiypla70pla55M5T1_19,ctl_pf_sel_nuse_ixiypla70pla55M5T1_19})&(`PFSEL_P);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
ctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[70]&pla[55])&(M5&T1);
fMWrite = fMWrite | (~use_ixiy&pla[70]&pla[55])&(M5&T2);
fMWrite = fMWrite | (~use_ixiy&pla[70]&pla[55])&(M5&T3);
setM1 = setM1 | (~use_ixiy&pla[70]&pla[55])&(M5&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[15]&op3)&(M1&T1);
ctl_reg_gp_sel_pla15op3M1T1_2 = (pla[15]&op3)&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla15op3M1T1_2,ctl_reg_gp_sel_pla15op3M1T1_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla15op3M1T1_3 = (pla[15]&op3)&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla15op3M1T1_3,ctl_reg_gp_hilo_pla15op3M1T1_3})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[15]&op3)&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[15]&op3)&(M1&T1);
ctl_flags_alu = ctl_flags_alu | (pla[15]&op3)&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (pla[15]&op3)&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[15]&op3)&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[15]&op3)&(M1&T1);
ctl_alu_core_R = ctl_alu_core_R | (pla[15]&op3)&(M1&T1);
ctl_alu_core_V = ctl_alu_core_V | (pla[15]&op3)&(M1&T1);
ctl_alu_core_S = ctl_alu_core_S | (pla[15]&op3)&(M1&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[15]&op3)&(M1&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[15]&op3)&(M1&T1);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[15]&op3)&(M1&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[15]&op3)&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[15]&op3)&(M1&T1);
ctl_pf_sel_pla15op3M1T1_18 = (pla[15]&op3)&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla15op3M1T1_18,ctl_pf_sel_pla15op3M1T1_18})&(`PFSEL_P);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[15]&op3)&(M1&T1);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[15]&op3)&(M1&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[15]&op3)&(M1&T2);
ctl_reg_gp_sel_pla15op3M1T2_2 = (pla[15]&op3)&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla15op3M1T2_2,ctl_reg_gp_sel_pla15op3M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla15op3M1T2_3 = (pla[15]&op3)&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla15op3M1T2_3,ctl_reg_gp_hilo_pla15op3M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[15]&op3)&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[15]&op3)&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (pla[15]&op3)&(M1&T2);
ctl_reg_gp_sel_pla15op3M1T3_1 = (pla[15]&op3)&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla15op3M1T3_1,ctl_reg_gp_sel_pla15op3M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla15op3M1T3_2 = (pla[15]&op3)&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla15op3M1T3_2,ctl_reg_gp_hilo_pla15op3M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[15]&op3)&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[15]&op3)&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[15]&op3)&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[15]&op3)&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[15]&op3)&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[15]&op3)&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[15]&op3)&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[15]&op3)&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[15]&op3)&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[15]&op3)&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[15]&op3)&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[15]&op3)&(M1&T3);
validPLA = validPLA | (pla[15]&op3)&(M1&T4);
nextM = nextM | (pla[15]&op3)&(M1&T4);
ctl_mRead = ctl_mRead | (pla[15]&op3)&(M1&T4);
fMRead = fMRead | (pla[15]&op3)&(M2&T1);
ctl_reg_gp_sel_pla15op3M2T1_2 = (pla[15]&op3)&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla15op3M2T1_2,ctl_reg_gp_sel_pla15op3M2T1_2})&(`GP_REG_HL);
ctl_reg_gp_hilo_pla15op3M2T1_3 = (pla[15]&op3)&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla15op3M2T1_3,ctl_reg_gp_hilo_pla15op3M2T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[15]&op3)&(M2&T1);
ctl_al_we = ctl_al_we | (pla[15]&op3)&(M2&T1);
fMRead = fMRead | (pla[15]&op3)&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[15]&op3)&(M2&T2);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[15]&op3)&(M2&T2);
ctl_reg_sys_hilo_pla15op3M2T2_4 = (pla[15]&op3)&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla15op3M2T2_4,ctl_reg_sys_hilo_pla15op3M2T2_4})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[15]&op3)&(M2&T2);
ctl_inc_cy = ctl_inc_cy | (pla[15]&op3)&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[15]&op3)&(M2&T2);
fMRead = fMRead | (pla[15]&op3)&(M2&T3);
nextM = nextM | (pla[15]&op3)&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[15]&op3)&(M3&T1);
ctl_sw_1d = ctl_sw_1d | (pla[15]&op3)&(M3&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[15]&op3)&(M3&T1);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[15]&op3)&(M3&T1)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_lq = ctl_alu_op2_sel_lq | (pla[15]&op3)&(M3&T1);
ctl_alu_op_low = ctl_alu_op_low | (pla[15]&op3)&(M3&T1);
nextM = nextM | (pla[15]&op3)&(M3&T4);
ctl_mWrite = ctl_mWrite | (pla[15]&op3)&(M3&T4);
ctl_sw_2d = ctl_sw_2d | (pla[15]&op3)&(M3&T4);
ctl_sw_1d = ctl_sw_1d | (pla[15]&op3)&(M3&T4);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[15]&op3)&(M3&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[15]&op3)&(M3&T4)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_low = ctl_alu_op1_sel_low | (pla[15]&op3)&(M3&T4);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[15]&op3)&(M3&T4);
fMWrite = fMWrite | (pla[15]&op3)&(M4&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[15]&op3)&(M4&T1);
ctl_sw_2u = ctl_sw_2u | (pla[15]&op3)&(M4&T1);
ctl_sw_1u = ctl_sw_1u | (pla[15]&op3)&(M4&T1);
ctl_bus_db_we = ctl_bus_db_we | (pla[15]&op3)&(M4&T1);
ctl_alu_oe = ctl_alu_oe | (pla[15]&op3)&(M4&T1);
ctl_alu_op2_oe = ctl_alu_op2_oe | (pla[15]&op3)&(M4&T1);
fMWrite = fMWrite | (pla[15]&op3)&(M4&T2);
ctl_alu_op1_oe = ctl_alu_op1_oe | (pla[15]&op3)&(M4&T2);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[15]&op3)&(M4&T2);
fMWrite = fMWrite | (pla[15]&op3)&(M4&T3);
setM1 = setM1 | (pla[15]&op3)&(M4&T3);
ctl_flags_alu = ctl_flags_alu | (pla[15]&op3)&(M4&T3);
ctl_alu_op_low = ctl_alu_op_low | (pla[15]&op3)&(M4&T3);
ctl_alu_core_R = ctl_alu_core_R | (pla[15]&op3)&(M4&T3);
ctl_alu_core_V = ctl_alu_core_V | (pla[15]&op3)&(M4&T3);
ctl_alu_core_S = ctl_alu_core_S | (pla[15]&op3)&(M4&T3);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[15]&op3)&(M4&T3);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[15]&op3)&(M4&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[15]&op3)&(M4&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[15]&op3)&(M4&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[15]&op3)&(M4&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[15]&op3)&(M4&T3);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[15]&op3)&(M4&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[15]&~op3)&(M1&T1);
ctl_reg_gp_sel_pla15nop3M1T1_2 = (pla[15]&~op3)&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla15nop3M1T1_2,ctl_reg_gp_sel_pla15nop3M1T1_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla15nop3M1T1_3 = (pla[15]&~op3)&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla15nop3M1T1_3,ctl_reg_gp_hilo_pla15nop3M1T1_3})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[15]&~op3)&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[15]&~op3)&(M1&T1);
ctl_flags_alu = ctl_flags_alu | (pla[15]&~op3)&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (pla[15]&~op3)&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[15]&~op3)&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[15]&~op3)&(M1&T1);
ctl_alu_core_R = ctl_alu_core_R | (pla[15]&~op3)&(M1&T1);
ctl_alu_core_V = ctl_alu_core_V | (pla[15]&~op3)&(M1&T1);
ctl_alu_core_S = ctl_alu_core_S | (pla[15]&~op3)&(M1&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[15]&~op3)&(M1&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[15]&~op3)&(M1&T1);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[15]&~op3)&(M1&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[15]&~op3)&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[15]&~op3)&(M1&T1);
ctl_pf_sel_pla15nop3M1T1_18 = (pla[15]&~op3)&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla15nop3M1T1_18,ctl_pf_sel_pla15nop3M1T1_18})&(`PFSEL_P);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[15]&~op3)&(M1&T1);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[15]&~op3)&(M1&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[15]&~op3)&(M1&T2);
ctl_reg_gp_sel_pla15nop3M1T2_2 = (pla[15]&~op3)&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla15nop3M1T2_2,ctl_reg_gp_sel_pla15nop3M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla15nop3M1T2_3 = (pla[15]&~op3)&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla15nop3M1T2_3,ctl_reg_gp_hilo_pla15nop3M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[15]&~op3)&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[15]&~op3)&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (pla[15]&~op3)&(M1&T2);
ctl_reg_gp_sel_pla15nop3M1T3_1 = (pla[15]&~op3)&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla15nop3M1T3_1,ctl_reg_gp_sel_pla15nop3M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla15nop3M1T3_2 = (pla[15]&~op3)&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla15nop3M1T3_2,ctl_reg_gp_hilo_pla15nop3M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[15]&~op3)&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[15]&~op3)&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[15]&~op3)&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[15]&~op3)&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[15]&~op3)&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[15]&~op3)&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[15]&~op3)&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[15]&~op3)&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[15]&~op3)&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[15]&~op3)&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[15]&~op3)&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[15]&~op3)&(M1&T3);
validPLA = validPLA | (pla[15]&~op3)&(M1&T4);
nextM = nextM | (pla[15]&~op3)&(M1&T4);
ctl_mRead = ctl_mRead | (pla[15]&~op3)&(M1&T4);
fMRead = fMRead | (pla[15]&~op3)&(M2&T1);
ctl_reg_gp_sel_pla15nop3M2T1_2 = (pla[15]&~op3)&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla15nop3M2T1_2,ctl_reg_gp_sel_pla15nop3M2T1_2})&(`GP_REG_HL);
ctl_reg_gp_hilo_pla15nop3M2T1_3 = (pla[15]&~op3)&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla15nop3M2T1_3,ctl_reg_gp_hilo_pla15nop3M2T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[15]&~op3)&(M2&T1);
ctl_al_we = ctl_al_we | (pla[15]&~op3)&(M2&T1);
fMRead = fMRead | (pla[15]&~op3)&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[15]&~op3)&(M2&T2);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[15]&~op3)&(M2&T2);
ctl_reg_sys_hilo_pla15nop3M2T2_4 = (pla[15]&~op3)&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla15nop3M2T2_4,ctl_reg_sys_hilo_pla15nop3M2T2_4})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[15]&~op3)&(M2&T2);
ctl_inc_cy = ctl_inc_cy | (pla[15]&~op3)&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[15]&~op3)&(M2&T2);
fMRead = fMRead | (pla[15]&~op3)&(M2&T3);
nextM = nextM | (pla[15]&~op3)&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[15]&~op3)&(M3&T1);
ctl_sw_1d = ctl_sw_1d | (pla[15]&~op3)&(M3&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[15]&~op3)&(M3&T1);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[15]&~op3)&(M3&T1)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_lq = ctl_alu_op2_sel_lq | (pla[15]&~op3)&(M3&T1);
ctl_alu_op1_sel_low = ctl_alu_op1_sel_low | (pla[15]&~op3)&(M3&T1);
ctl_alu_op_low = ctl_alu_op_low | (pla[15]&~op3)&(M3&T1);
ctl_sw_2u = ctl_sw_2u | (pla[15]&~op3)&(M3&T2);
ctl_sw_1u = ctl_sw_1u | (pla[15]&~op3)&(M3&T2);
ctl_bus_db_we = ctl_bus_db_we | (pla[15]&~op3)&(M3&T2);
ctl_alu_oe = ctl_alu_oe | (pla[15]&~op3)&(M3&T2);
ctl_alu_op2_oe = ctl_alu_op2_oe | (pla[15]&~op3)&(M3&T2);
ctl_reg_gp_sel_pla15nop3M3T3_1 = (pla[15]&~op3)&(M3&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla15nop3M3T3_1,ctl_reg_gp_sel_pla15nop3M3T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla15nop3M3T3_2 = (pla[15]&~op3)&(M3&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla15nop3M3T3_2,ctl_reg_gp_hilo_pla15nop3M3T3_2})&(2'b10);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[15]&~op3)&(M3&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[15]&~op3)&(M3&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[15]&~op3)&(M3&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_lq = ctl_alu_op2_sel_lq | (pla[15]&~op3)&(M3&T3);
ctl_alu_op_low = ctl_alu_op_low | (pla[15]&~op3)&(M3&T3);
nextM = nextM | (pla[15]&~op3)&(M3&T4);
ctl_mWrite = ctl_mWrite | (pla[15]&~op3)&(M3&T4);
ctl_sw_2d = ctl_sw_2d | (pla[15]&~op3)&(M3&T4);
ctl_sw_1d = ctl_sw_1d | (pla[15]&~op3)&(M3&T4);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[15]&~op3)&(M3&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[15]&~op3)&(M3&T4)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_low = ctl_alu_op1_sel_low | (pla[15]&~op3)&(M3&T4);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[15]&~op3)&(M3&T4);
fMWrite = fMWrite | (pla[15]&~op3)&(M4&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[15]&~op3)&(M4&T1);
ctl_sw_2u = ctl_sw_2u | (pla[15]&~op3)&(M4&T1);
ctl_sw_1u = ctl_sw_1u | (pla[15]&~op3)&(M4&T1);
ctl_bus_db_we = ctl_bus_db_we | (pla[15]&~op3)&(M4&T1);
ctl_alu_oe = ctl_alu_oe | (pla[15]&~op3)&(M4&T1);
ctl_alu_op2_oe = ctl_alu_op2_oe | (pla[15]&~op3)&(M4&T1);
fMWrite = fMWrite | (pla[15]&~op3)&(M4&T2);
ctl_alu_op1_oe = ctl_alu_op1_oe | (pla[15]&~op3)&(M4&T2);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[15]&~op3)&(M4&T2);
fMWrite = fMWrite | (pla[15]&~op3)&(M4&T3);
setM1 = setM1 | (pla[15]&~op3)&(M4&T3);
ctl_flags_alu = ctl_flags_alu | (pla[15]&~op3)&(M4&T3);
ctl_alu_op_low = ctl_alu_op_low | (pla[15]&~op3)&(M4&T3);
ctl_alu_core_R = ctl_alu_core_R | (pla[15]&~op3)&(M4&T3);
ctl_alu_core_V = ctl_alu_core_V | (pla[15]&~op3)&(M4&T3);
ctl_alu_core_S = ctl_alu_core_S | (pla[15]&~op3)&(M4&T3);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[15]&~op3)&(M4&T3);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[15]&~op3)&(M4&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[15]&~op3)&(M4&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[15]&~op3)&(M4&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[15]&~op3)&(M4&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[15]&~op3)&(M4&T3);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[15]&~op3)&(M4&T3);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);
ctl_pf_sel_nuse_ixiypla72npla55M1T1_10 = (~use_ixiy&pla[72]&~pla[55])&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_nuse_ixiypla72npla55M1T1_10,ctl_pf_sel_nuse_ixiypla72npla55M1T1_10})&(`PFSEL_P);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);
ctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T2);
ctl_reg_gp_sel_nuse_ixiypla72npla55M1T2_2 = (~use_ixiy&pla[72]&~pla[55])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla72npla55M1T2_2,ctl_reg_gp_sel_nuse_ixiypla72npla55M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T2_3 = (~use_ixiy&pla[72]&~pla[55])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T2_3,ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[72]&~pla[55])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[72]&~pla[55])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (~use_ixiy&pla[72]&~pla[55])&(M1&T2);
ctl_reg_gp_sel_nuse_ixiypla72npla55M1T3_1 = (~use_ixiy&pla[72]&~pla[55])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla72npla55M1T3_1,ctl_reg_gp_sel_nuse_ixiypla72npla55M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T3_2 = (~use_ixiy&pla[72]&~pla[55])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T3_2,ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);
ctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);
validPLA = validPLA | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);
setM1 = setM1 | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);
ctl_reg_gp_sel_nuse_ixiypla72npla55M1T4_3 = (~use_ixiy&pla[72]&~pla[55])&(M1&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla72npla55M1T4_3,ctl_reg_gp_sel_nuse_ixiypla72npla55M1T4_3})&(op21);
ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 = (~use_ixiy&pla[72]&~pla[55])&(M1&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4,ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4})&({~rsel0,rsel0});
ctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[72]&~pla[55])&(M1&T4)&(~rsel0);
ctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[72]&~pla[55])&(M1&T4)&(rsel0);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[72]&~pla[55])&(M1&T4)&(~rsel0);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[72]&~pla[55])&(M1&T4)&(rsel0);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[72]&~pla[55])&(M1&T4)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);
ctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);
ctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);
fMRead = fMRead | (~use_ixiy&pla[72]&~pla[55])&(M4&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[72]&~pla[55])&(M4&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[72]&~pla[55])&(M4&T1);
ctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[72]&~pla[55])&(M4&T1);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[72]&~pla[55])&(M4&T1);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[72]&~pla[55])&(M4&T1);
ctl_ir_we = ctl_ir_we | (~use_ixiy&pla[72]&~pla[55])&(M4&T1);
fMRead = fMRead | (~use_ixiy&pla[72]&~pla[55])&(M4&T2);
fMRead = fMRead | (~use_ixiy&pla[72]&~pla[55])&(M4&T3);
setM1 = setM1 | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);
ctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[72]&~pla[55])&(M4&T4)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);
ctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);
ctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[72]&pla[55])&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[72]&pla[55])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[72]&pla[55])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[72]&pla[55])&(M1&T1);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[72]&pla[55])&(M1&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[72]&pla[55])&(M1&T1);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[72]&pla[55])&(M1&T1);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[72]&pla[55])&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[72]&pla[55])&(M1&T1);
ctl_pf_sel_nuse_ixiypla72pla55M1T1_10 = (~use_ixiy&pla[72]&pla[55])&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_nuse_ixiypla72pla55M1T1_10,ctl_pf_sel_nuse_ixiypla72pla55M1T1_10})&(`PFSEL_P);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[72]&pla[55])&(M1&T1);
ctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[72]&pla[55])&(M1&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (~use_ixiy&pla[72]&pla[55])&(M1&T2);
ctl_reg_gp_sel_nuse_ixiypla72pla55M1T2_2 = (~use_ixiy&pla[72]&pla[55])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla72pla55M1T2_2,ctl_reg_gp_sel_nuse_ixiypla72pla55M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_nuse_ixiypla72pla55M1T2_3 = (~use_ixiy&pla[72]&pla[55])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla72pla55M1T2_3,ctl_reg_gp_hilo_nuse_ixiypla72pla55M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[72]&pla[55])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[72]&pla[55])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (~use_ixiy&pla[72]&pla[55])&(M1&T2);
ctl_reg_gp_sel_nuse_ixiypla72pla55M1T3_1 = (~use_ixiy&pla[72]&pla[55])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla72pla55M1T3_1,ctl_reg_gp_sel_nuse_ixiypla72pla55M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_nuse_ixiypla72pla55M1T3_2 = (~use_ixiy&pla[72]&pla[55])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla72pla55M1T3_2,ctl_reg_gp_hilo_nuse_ixiypla72pla55M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[72]&pla[55])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[72]&pla[55])&(M1&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[72]&pla[55])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[72]&pla[55])&(M1&T3);
ctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[72]&pla[55])&(M1&T3);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[72]&pla[55])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[72]&pla[55])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[72]&pla[55])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[72]&pla[55])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[72]&pla[55])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[72]&pla[55])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[72]&pla[55])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[72]&pla[55])&(M1&T3);
validPLA = validPLA | (~use_ixiy&pla[72]&pla[55])&(M1&T4);
nextM = nextM | (~use_ixiy&pla[72]&pla[55])&(M1&T4);
ctl_mRead = ctl_mRead | (~use_ixiy&pla[72]&pla[55])&(M1&T4);
fMRead = fMRead | (~use_ixiy&pla[72]&pla[55])&(M2&T1);
ctl_reg_gp_sel_nuse_ixiypla72pla55M2T1_2 = (~use_ixiy&pla[72]&pla[55])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla72pla55M2T1_2,ctl_reg_gp_sel_nuse_ixiypla72pla55M2T1_2})&(`GP_REG_HL);
ctl_reg_gp_hilo_nuse_ixiypla72pla55M2T1_3 = (~use_ixiy&pla[72]&pla[55])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla72pla55M2T1_3,ctl_reg_gp_hilo_nuse_ixiypla72pla55M2T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[72]&pla[55])&(M2&T1);
ctl_al_we = ctl_al_we | (~use_ixiy&pla[72]&pla[55])&(M2&T1);
fMRead = fMRead | (~use_ixiy&pla[72]&pla[55])&(M2&T2);
fMRead = fMRead | (~use_ixiy&pla[72]&pla[55])&(M2&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (~use_ixiy&pla[72]&pla[55])&(M2&T3);
ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 = (~use_ixiy&pla[72]&pla[55])&(M2&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3,ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (~use_ixiy&pla[72]&pla[55])&(M2&T3);
ctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[72]&pla[55])&(M2&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[72]&pla[55])&(M2&T3);
ctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[72]&pla[55])&(M2&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[72]&pla[55])&(M2&T3);
setM1 = setM1 | (~use_ixiy&pla[72]&pla[55])&(M2&T4);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[72]&pla[55])&(M2&T4);
ctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[72]&pla[55])&(M2&T4);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[72]&pla[55])&(M2&T4);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[72]&pla[55])&(M2&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[72]&pla[55])&(M2&T4)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[72]&pla[55])&(M2&T4);
ctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[72]&pla[55])&(M2&T4);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[72]&pla[55])&(M2&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[72]&pla[55])&(M2&T4);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[72]&pla[55])&(M2&T4);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[72]&pla[55])&(M2&T4);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[72]&pla[55])&(M2&T4);
ctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[72]&pla[55])&(M2&T4);
fMRead = fMRead | (~use_ixiy&pla[72]&pla[55])&(M4&T1);
ctl_reg_sel_wz = ctl_reg_sel_wz | (~use_ixiy&pla[72]&pla[55])&(M4&T1);
ctl_reg_sys_hilo_nuse_ixiypla72pla55M4T1_3 = (~use_ixiy&pla[72]&pla[55])&(M4&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nuse_ixiypla72pla55M4T1_3,ctl_reg_sys_hilo_nuse_ixiypla72pla55M4T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[72]&pla[55])&(M4&T1);
ctl_al_we = ctl_al_we | (~use_ixiy&pla[72]&pla[55])&(M4&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[72]&pla[55])&(M4&T1);
ctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[72]&pla[55])&(M4&T1);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[72]&pla[55])&(M4&T1);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[72]&pla[55])&(M4&T1);
ctl_ir_we = ctl_ir_we | (~use_ixiy&pla[72]&pla[55])&(M4&T1);
fMRead = fMRead | (~use_ixiy&pla[72]&pla[55])&(M4&T2);
fMRead = fMRead | (~use_ixiy&pla[72]&pla[55])&(M4&T3);
setM1 = setM1 | (~use_ixiy&pla[72]&pla[55])&(M4&T4);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[72]&pla[55])&(M4&T4);
ctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[72]&pla[55])&(M4&T4);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[72]&pla[55])&(M4&T4);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[72]&pla[55])&(M4&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[72]&pla[55])&(M4&T4)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[72]&pla[55])&(M4&T4);
ctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[72]&pla[55])&(M4&T4);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[72]&pla[55])&(M4&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[72]&pla[55])&(M4&T4);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[72]&pla[55])&(M4&T4);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[72]&pla[55])&(M4&T4);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[72]&pla[55])&(M4&T4);
ctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[72]&pla[55])&(M4&T4);
ctl_reg_gp_we = ctl_reg_gp_we | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);
ctl_reg_gp_sel_nuse_ixiypla74npla55M1T1_2 = (~use_ixiy&pla[74]&~pla[55])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla74npla55M1T1_2,ctl_reg_gp_sel_nuse_ixiypla74npla55M1T1_2})&(op21);
ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T1_3 = (~use_ixiy&pla[74]&~pla[55])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T1_3,ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T1_3})&({~rsel0,rsel0});
ctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);
ctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);
ctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);
ctl_reg_gp_sel_nuse_ixiypla74npla55M1T3_1 = (~use_ixiy&pla[74]&~pla[55])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla74npla55M1T3_1,ctl_reg_gp_sel_nuse_ixiypla74npla55M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T3_2 = (~use_ixiy&pla[74]&~pla[55])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T3_2,ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);
ctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);
validPLA = validPLA | (~use_ixiy&pla[74]&~pla[55])&(M1&T4);
setM1 = setM1 | (~use_ixiy&pla[74]&~pla[55])&(M1&T4);
ctl_reg_gp_sel_nuse_ixiypla74npla55M1T4_3 = (~use_ixiy&pla[74]&~pla[55])&(M1&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla74npla55M1T4_3,ctl_reg_gp_sel_nuse_ixiypla74npla55M1T4_3})&(op21);
ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T4_4 = (~use_ixiy&pla[74]&~pla[55])&(M1&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T4_4,ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T4_4})&({~rsel0,rsel0});
ctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[74]&~pla[55])&(M1&T4)&(~rsel0);
ctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[74]&~pla[55])&(M1&T4)&(rsel0);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[74]&~pla[55])&(M1&T4)&(~rsel0);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[74]&~pla[55])&(M1&T4)&(rsel0);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[74]&~pla[55])&(M1&T4)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[74]&~pla[55])&(M1&T4);
ctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[74]&~pla[55])&(M1&T4);
ctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[74]&~pla[55])&(M1&T4);
ctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[74]&~pla[55])&(M1&T4);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[74]&~pla[55])&(M1&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[74]&~pla[55])&(M1&T4);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[74]&~pla[55])&(M1&T4);
fMRead = fMRead | (~use_ixiy&pla[74]&~pla[55])&(M4&T1);
ctl_reg_sel_wz = ctl_reg_sel_wz | (~use_ixiy&pla[74]&~pla[55])&(M4&T1);
ctl_reg_sys_hilo_nuse_ixiypla74npla55M4T1_3 = (~use_ixiy&pla[74]&~pla[55])&(M4&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nuse_ixiypla74npla55M4T1_3,ctl_reg_sys_hilo_nuse_ixiypla74npla55M4T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[74]&~pla[55])&(M4&T1);
ctl_al_we = ctl_al_we | (~use_ixiy&pla[74]&~pla[55])&(M4&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[74]&~pla[55])&(M4&T1);
ctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[74]&~pla[55])&(M4&T1);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[74]&~pla[55])&(M4&T1);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[74]&~pla[55])&(M4&T1);
ctl_ir_we = ctl_ir_we | (~use_ixiy&pla[74]&~pla[55])&(M4&T1);
fMRead = fMRead | (~use_ixiy&pla[74]&~pla[55])&(M4&T2);
fMRead = fMRead | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);
nextM = nextM | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);
ctl_mWrite = ctl_mWrite | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);
ctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[74]&~pla[55])&(M4&T3)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);
ctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);
ctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);
ctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);
fMWrite = fMWrite | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);
ctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);
ctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);
ctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);
ctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);
ctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);
fMWrite = fMWrite | (~use_ixiy&pla[74]&~pla[55])&(M5&T2);
fMWrite = fMWrite | (~use_ixiy&pla[74]&~pla[55])&(M5&T3);
setM1 = setM1 | (~use_ixiy&pla[74]&~pla[55])&(M5&T3);
ctl_reg_gp_sel_nuse_ixiypla74pla55M1T3_1 = (~use_ixiy&pla[74]&pla[55])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla74pla55M1T3_1,ctl_reg_gp_sel_nuse_ixiypla74pla55M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_nuse_ixiypla74pla55M1T3_2 = (~use_ixiy&pla[74]&pla[55])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla74pla55M1T3_2,ctl_reg_gp_hilo_nuse_ixiypla74pla55M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[74]&pla[55])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[74]&pla[55])&(M1&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[74]&pla[55])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[74]&pla[55])&(M1&T3);
ctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[74]&pla[55])&(M1&T3);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[74]&pla[55])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[74]&pla[55])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[74]&pla[55])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[74]&pla[55])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[74]&pla[55])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[74]&pla[55])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[74]&pla[55])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[74]&pla[55])&(M1&T3);
validPLA = validPLA | (~use_ixiy&pla[74]&pla[55])&(M1&T4);
nextM = nextM | (~use_ixiy&pla[74]&pla[55])&(M1&T4);
ctl_mRead = ctl_mRead | (~use_ixiy&pla[74]&pla[55])&(M1&T4);
fMRead = fMRead | (~use_ixiy&pla[74]&pla[55])&(M2&T1);
ctl_reg_gp_sel_nuse_ixiypla74pla55M2T1_2 = (~use_ixiy&pla[74]&pla[55])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla74pla55M2T1_2,ctl_reg_gp_sel_nuse_ixiypla74pla55M2T1_2})&(`GP_REG_HL);
ctl_reg_gp_hilo_nuse_ixiypla74pla55M2T1_3 = (~use_ixiy&pla[74]&pla[55])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla74pla55M2T1_3,ctl_reg_gp_hilo_nuse_ixiypla74pla55M2T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[74]&pla[55])&(M2&T1);
ctl_al_we = ctl_al_we | (~use_ixiy&pla[74]&pla[55])&(M2&T1);
fMRead = fMRead | (~use_ixiy&pla[74]&pla[55])&(M2&T2);
fMRead = fMRead | (~use_ixiy&pla[74]&pla[55])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[74]&pla[55])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[74]&pla[55])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[74]&pla[55])&(M2&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[74]&pla[55])&(M2&T3)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[74]&pla[55])&(M2&T3);
ctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[74]&pla[55])&(M2&T3);
ctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[74]&pla[55])&(M2&T3);
ctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[74]&pla[55])&(M2&T3);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[74]&pla[55])&(M2&T3);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[74]&pla[55])&(M2&T3);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[74]&pla[55])&(M2&T3);
nextM = nextM | (~use_ixiy&pla[74]&pla[55])&(M2&T4);
ctl_mWrite = ctl_mWrite | (~use_ixiy&pla[74]&pla[55])&(M2&T4);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[74]&pla[55])&(M2&T4);
ctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[74]&pla[55])&(M2&T4);
ctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[74]&pla[55])&(M2&T4);
ctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[74]&pla[55])&(M2&T4);
ctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[74]&pla[55])&(M2&T4);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[74]&pla[55])&(M2&T4);
ctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[74]&pla[55])&(M2&T4);
ctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[74]&pla[55])&(M2&T4);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[74]&pla[55])&(M2&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[74]&pla[55])&(M2&T4);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[74]&pla[55])&(M2&T4);
fMWrite = fMWrite | (~use_ixiy&pla[74]&pla[55])&(M3&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[74]&pla[55])&(M3&T1);
fMWrite = fMWrite | (~use_ixiy&pla[74]&pla[55])&(M3&T2);
fMWrite = fMWrite | (~use_ixiy&pla[74]&pla[55])&(M3&T3);
setM1 = setM1 | (~use_ixiy&pla[74]&pla[55])&(M3&T3);
fMRead = fMRead | (~use_ixiy&pla[74]&pla[55])&(M4&T1);
ctl_reg_sel_wz = ctl_reg_sel_wz | (~use_ixiy&pla[74]&pla[55])&(M4&T1);
ctl_reg_sys_hilo_nuse_ixiypla74pla55M4T1_3 = (~use_ixiy&pla[74]&pla[55])&(M4&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nuse_ixiypla74pla55M4T1_3,ctl_reg_sys_hilo_nuse_ixiypla74pla55M4T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[74]&pla[55])&(M4&T1);
ctl_al_we = ctl_al_we | (~use_ixiy&pla[74]&pla[55])&(M4&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[74]&pla[55])&(M4&T1);
ctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[74]&pla[55])&(M4&T1);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[74]&pla[55])&(M4&T1);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[74]&pla[55])&(M4&T1);
ctl_ir_we = ctl_ir_we | (~use_ixiy&pla[74]&pla[55])&(M4&T1);
fMRead = fMRead | (~use_ixiy&pla[74]&pla[55])&(M4&T2);
fMRead = fMRead | (~use_ixiy&pla[74]&pla[55])&(M4&T3);
nextM = nextM | (~use_ixiy&pla[74]&pla[55])&(M4&T3);
ctl_mWrite = ctl_mWrite | (~use_ixiy&pla[74]&pla[55])&(M4&T3);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[74]&pla[55])&(M4&T3);
ctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[74]&pla[55])&(M4&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[74]&pla[55])&(M4&T3);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[74]&pla[55])&(M4&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[74]&pla[55])&(M4&T3)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[74]&pla[55])&(M4&T3);
ctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[74]&pla[55])&(M4&T3);
ctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[74]&pla[55])&(M4&T3);
ctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[74]&pla[55])&(M4&T3);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[74]&pla[55])&(M4&T3);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[74]&pla[55])&(M4&T3);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[74]&pla[55])&(M4&T3);
fMWrite = fMWrite | (~use_ixiy&pla[74]&pla[55])&(M5&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[74]&pla[55])&(M5&T1);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[74]&pla[55])&(M5&T1);
ctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[74]&pla[55])&(M5&T1);
ctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[74]&pla[55])&(M5&T1);
ctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[74]&pla[55])&(M5&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[74]&pla[55])&(M5&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[74]&pla[55])&(M5&T1);
ctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[74]&pla[55])&(M5&T1);
ctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[74]&pla[55])&(M5&T1);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[74]&pla[55])&(M5&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[74]&pla[55])&(M5&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[74]&pla[55])&(M5&T1);
fMWrite = fMWrite | (~use_ixiy&pla[74]&pla[55])&(M5&T2);
fMWrite = fMWrite | (~use_ixiy&pla[74]&pla[55])&(M5&T3);
setM1 = setM1 | (~use_ixiy&pla[74]&pla[55])&(M5&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (~use_ixiy&pla[73]&~pla[55])&(M1&T1);
ctl_reg_gp_sel_nuse_ixiypla73npla55M1T1_2 = (~use_ixiy&pla[73]&~pla[55])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla73npla55M1T1_2,ctl_reg_gp_sel_nuse_ixiypla73npla55M1T1_2})&(op21);
ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T1_3 = (~use_ixiy&pla[73]&~pla[55])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T1_3,ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T1_3})&({~rsel0,rsel0});
ctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[73]&~pla[55])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[73]&~pla[55])&(M1&T1);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[73]&~pla[55])&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[73]&~pla[55])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[73]&~pla[55])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[73]&~pla[55])&(M1&T1);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[73]&~pla[55])&(M1&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[73]&~pla[55])&(M1&T1);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~use_ixiy&pla[73]&~pla[55])&(M1&T1);
ctl_reg_gp_sel_nuse_ixiypla73npla55M1T3_1 = (~use_ixiy&pla[73]&~pla[55])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla73npla55M1T3_1,ctl_reg_gp_sel_nuse_ixiypla73npla55M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T3_2 = (~use_ixiy&pla[73]&~pla[55])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T3_2,ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);
ctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);
validPLA = validPLA | (~use_ixiy&pla[73]&~pla[55])&(M1&T4);
setM1 = setM1 | (~use_ixiy&pla[73]&~pla[55])&(M1&T4);
ctl_reg_gp_sel_nuse_ixiypla73npla55M1T4_3 = (~use_ixiy&pla[73]&~pla[55])&(M1&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla73npla55M1T4_3,ctl_reg_gp_sel_nuse_ixiypla73npla55M1T4_3})&(op21);
ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T4_4 = (~use_ixiy&pla[73]&~pla[55])&(M1&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T4_4,ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T4_4})&({~rsel0,rsel0});
ctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[73]&~pla[55])&(M1&T4)&(~rsel0);
ctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[73]&~pla[55])&(M1&T4)&(rsel0);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[73]&~pla[55])&(M1&T4)&(~rsel0);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[73]&~pla[55])&(M1&T4)&(rsel0);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[73]&~pla[55])&(M1&T4)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[73]&~pla[55])&(M1&T4);
ctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[73]&~pla[55])&(M1&T4);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[73]&~pla[55])&(M1&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[73]&~pla[55])&(M1&T4);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~use_ixiy&pla[73]&~pla[55])&(M1&T4);
fMRead = fMRead | (~use_ixiy&pla[73]&~pla[55])&(M4&T1);
ctl_reg_sel_wz = ctl_reg_sel_wz | (~use_ixiy&pla[73]&~pla[55])&(M4&T1);
ctl_reg_sys_hilo_nuse_ixiypla73npla55M4T1_3 = (~use_ixiy&pla[73]&~pla[55])&(M4&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nuse_ixiypla73npla55M4T1_3,ctl_reg_sys_hilo_nuse_ixiypla73npla55M4T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[73]&~pla[55])&(M4&T1);
ctl_al_we = ctl_al_we | (~use_ixiy&pla[73]&~pla[55])&(M4&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[73]&~pla[55])&(M4&T1);
ctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[73]&~pla[55])&(M4&T1);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[73]&~pla[55])&(M4&T1);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[73]&~pla[55])&(M4&T1);
ctl_ir_we = ctl_ir_we | (~use_ixiy&pla[73]&~pla[55])&(M4&T1);
fMRead = fMRead | (~use_ixiy&pla[73]&~pla[55])&(M4&T2);
fMRead = fMRead | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);
nextM = nextM | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);
ctl_mWrite = ctl_mWrite | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);
ctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[73]&~pla[55])&(M4&T3)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);
ctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);
fMWrite = fMWrite | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);
ctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);
ctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);
ctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);
fMWrite = fMWrite | (~use_ixiy&pla[73]&~pla[55])&(M5&T2);
fMWrite = fMWrite | (~use_ixiy&pla[73]&~pla[55])&(M5&T3);
setM1 = setM1 | (~use_ixiy&pla[73]&~pla[55])&(M5&T3);
ctl_reg_gp_sel_nuse_ixiypla73pla55M1T3_1 = (~use_ixiy&pla[73]&pla[55])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla73pla55M1T3_1,ctl_reg_gp_sel_nuse_ixiypla73pla55M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_nuse_ixiypla73pla55M1T3_2 = (~use_ixiy&pla[73]&pla[55])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla73pla55M1T3_2,ctl_reg_gp_hilo_nuse_ixiypla73pla55M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[73]&pla[55])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[73]&pla[55])&(M1&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[73]&pla[55])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[73]&pla[55])&(M1&T3);
ctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[73]&pla[55])&(M1&T3);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[73]&pla[55])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[73]&pla[55])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[73]&pla[55])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[73]&pla[55])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[73]&pla[55])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[73]&pla[55])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[73]&pla[55])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[73]&pla[55])&(M1&T3);
validPLA = validPLA | (~use_ixiy&pla[73]&pla[55])&(M1&T4);
nextM = nextM | (~use_ixiy&pla[73]&pla[55])&(M1&T4);
ctl_mRead = ctl_mRead | (~use_ixiy&pla[73]&pla[55])&(M1&T4);
fMRead = fMRead | (~use_ixiy&pla[73]&pla[55])&(M2&T1);
ctl_reg_gp_sel_nuse_ixiypla73pla55M2T1_2 = (~use_ixiy&pla[73]&pla[55])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla73pla55M2T1_2,ctl_reg_gp_sel_nuse_ixiypla73pla55M2T1_2})&(`GP_REG_HL);
ctl_reg_gp_hilo_nuse_ixiypla73pla55M2T1_3 = (~use_ixiy&pla[73]&pla[55])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla73pla55M2T1_3,ctl_reg_gp_hilo_nuse_ixiypla73pla55M2T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[73]&pla[55])&(M2&T1);
ctl_al_we = ctl_al_we | (~use_ixiy&pla[73]&pla[55])&(M2&T1);
fMRead = fMRead | (~use_ixiy&pla[73]&pla[55])&(M2&T2);
fMRead = fMRead | (~use_ixiy&pla[73]&pla[55])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[73]&pla[55])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[73]&pla[55])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[73]&pla[55])&(M2&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[73]&pla[55])&(M2&T3)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[73]&pla[55])&(M2&T3);
ctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[73]&pla[55])&(M2&T3);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[73]&pla[55])&(M2&T3);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[73]&pla[55])&(M2&T3);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~use_ixiy&pla[73]&pla[55])&(M2&T3);
nextM = nextM | (~use_ixiy&pla[73]&pla[55])&(M2&T4);
ctl_mWrite = ctl_mWrite | (~use_ixiy&pla[73]&pla[55])&(M2&T4);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[73]&pla[55])&(M2&T4);
ctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[73]&pla[55])&(M2&T4);
ctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[73]&pla[55])&(M2&T4);
ctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[73]&pla[55])&(M2&T4);
ctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[73]&pla[55])&(M2&T4);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[73]&pla[55])&(M2&T4);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[73]&pla[55])&(M2&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[73]&pla[55])&(M2&T4);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~use_ixiy&pla[73]&pla[55])&(M2&T4);
fMWrite = fMWrite | (~use_ixiy&pla[73]&pla[55])&(M3&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[73]&pla[55])&(M3&T1);
fMWrite = fMWrite | (~use_ixiy&pla[73]&pla[55])&(M3&T2);
fMWrite = fMWrite | (~use_ixiy&pla[73]&pla[55])&(M3&T3);
setM1 = setM1 | (~use_ixiy&pla[73]&pla[55])&(M3&T3);
fMRead = fMRead | (~use_ixiy&pla[73]&pla[55])&(M4&T1);
ctl_reg_sel_wz = ctl_reg_sel_wz | (~use_ixiy&pla[73]&pla[55])&(M4&T1);
ctl_reg_sys_hilo_nuse_ixiypla73pla55M4T1_3 = (~use_ixiy&pla[73]&pla[55])&(M4&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nuse_ixiypla73pla55M4T1_3,ctl_reg_sys_hilo_nuse_ixiypla73pla55M4T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[73]&pla[55])&(M4&T1);
ctl_al_we = ctl_al_we | (~use_ixiy&pla[73]&pla[55])&(M4&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[73]&pla[55])&(M4&T1);
ctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[73]&pla[55])&(M4&T1);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[73]&pla[55])&(M4&T1);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[73]&pla[55])&(M4&T1);
ctl_ir_we = ctl_ir_we | (~use_ixiy&pla[73]&pla[55])&(M4&T1);
fMRead = fMRead | (~use_ixiy&pla[73]&pla[55])&(M4&T2);
fMRead = fMRead | (~use_ixiy&pla[73]&pla[55])&(M4&T3);
nextM = nextM | (~use_ixiy&pla[73]&pla[55])&(M4&T3);
ctl_mWrite = ctl_mWrite | (~use_ixiy&pla[73]&pla[55])&(M4&T3);
ctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[73]&pla[55])&(M4&T3);
ctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[73]&pla[55])&(M4&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[73]&pla[55])&(M4&T3);
ctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[73]&pla[55])&(M4&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[73]&pla[55])&(M4&T3)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[73]&pla[55])&(M4&T3);
ctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[73]&pla[55])&(M4&T3);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[73]&pla[55])&(M4&T3);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[73]&pla[55])&(M4&T3);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~use_ixiy&pla[73]&pla[55])&(M4&T3);
fMWrite = fMWrite | (~use_ixiy&pla[73]&pla[55])&(M5&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[73]&pla[55])&(M5&T1);
ctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[73]&pla[55])&(M5&T1);
ctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[73]&pla[55])&(M5&T1);
ctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[73]&pla[55])&(M5&T1);
ctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[73]&pla[55])&(M5&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[73]&pla[55])&(M5&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[73]&pla[55])&(M5&T1);
ctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[73]&pla[55])&(M5&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[73]&pla[55])&(M5&T1);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~use_ixiy&pla[73]&pla[55])&(M5&T1);
fMWrite = fMWrite | (~use_ixiy&pla[73]&pla[55])&(M5&T2);
fMWrite = fMWrite | (~use_ixiy&pla[73]&pla[55])&(M5&T3);
setM1 = setM1 | (~use_ixiy&pla[73]&pla[55])&(M5&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[37]&~pla[28])&(M1&T1);
ctl_reg_gp_sel_pla37npla28M1T1_2 = (pla[37]&~pla[28])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla37npla28M1T1_2,ctl_reg_gp_sel_pla37npla28M1T1_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla37npla28M1T1_3 = (pla[37]&~pla[28])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla37npla28M1T1_3,ctl_reg_gp_hilo_pla37npla28M1T1_3})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[37]&~pla[28])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[37]&~pla[28])&(M1&T1);
ctl_sw_2d = ctl_sw_2d | (pla[37]&~pla[28])&(M1&T1);
ctl_sw_1d = ctl_sw_1d | (pla[37]&~pla[28])&(M1&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[37]&~pla[28])&(M1&T1);
validPLA = validPLA | (pla[37]&~pla[28])&(M1&T4);
nextM = nextM | (pla[37]&~pla[28])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[37]&~pla[28])&(M1&T4);
fMRead = fMRead | (pla[37]&~pla[28])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[37]&~pla[28])&(M2&T1);
ctl_reg_sys_hilo_pla37npla28M2T1_3 = (pla[37]&~pla[28])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla37npla28M2T1_3,ctl_reg_sys_hilo_pla37npla28M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[37]&~pla[28])&(M2&T1);
fMRead = fMRead | (pla[37]&~pla[28])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[37]&~pla[28])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[37]&~pla[28])&(M2&T2);
ctl_reg_sys_hilo_pla37npla28M2T2_4 = (pla[37]&~pla[28])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla37npla28M2T2_4,ctl_reg_sys_hilo_pla37npla28M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[37]&~pla[28])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[37]&~pla[28])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[37]&~pla[28])&(M2&T2);
fMRead = fMRead | (pla[37]&~pla[28])&(M2&T3);
nextM = nextM | (pla[37]&~pla[28])&(M2&T3);
ctl_iorw = ctl_iorw | (pla[37]&~pla[28])&(M2&T3);
fIORead = fIORead | (pla[37]&~pla[28])&(M3&T1);
ctl_reg_gp_sel_pla37npla28M3T1_2 = (pla[37]&~pla[28])&(M3&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla37npla28M3T1_2,ctl_reg_gp_sel_pla37npla28M3T1_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla37npla28M3T1_3 = (pla[37]&~pla[28])&(M3&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla37npla28M3T1_3,ctl_reg_gp_hilo_pla37npla28M3T1_3})&(2'b10);
ctl_sw_4d = ctl_sw_4d | (pla[37]&~pla[28])&(M3&T1);
ctl_al_we = ctl_al_we | (pla[37]&~pla[28])&(M3&T1);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[37]&~pla[28])&(M3&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[37]&~pla[28])&(M3&T1);
ctl_sw_1d = ctl_sw_1d | (pla[37]&~pla[28])&(M3&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[37]&~pla[28])&(M3&T1);
fIORead = fIORead | (pla[37]&~pla[28])&(M3&T2);
fIORead = fIORead | (pla[37]&~pla[28])&(M3&T3);
fIORead = fIORead | (pla[37]&~pla[28])&(M3&T4);
setM1 = setM1 | (pla[37]&~pla[28])&(M3&T4);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[27]&~pla[34])&(M1&T1);
ctl_reg_gp_sel_pla27npla34M1T1_2 = (pla[27]&~pla[34])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla27npla34M1T1_2,ctl_reg_gp_sel_pla27npla34M1T1_2})&(op54);
ctl_reg_gp_hilo_pla27npla34M1T1_3 = (pla[27]&~pla[34])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla27npla34M1T1_3,ctl_reg_gp_hilo_pla27npla34M1T1_3})&({~rsel3,rsel3});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[27]&~pla[34])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[27]&~pla[34])&(M1&T1);
ctl_sw_2d = ctl_sw_2d | (pla[27]&~pla[34])&(M1&T1);
ctl_sw_1d = ctl_sw_1d | (pla[27]&~pla[34])&(M1&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[27]&~pla[34])&(M1&T1);
ctl_flags_alu = ctl_flags_alu | (pla[27]&~pla[34])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[27]&~pla[34])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[27]&~pla[34])&(M1&T1);
ctl_alu_core_R = ctl_alu_core_R | (pla[27]&~pla[34])&(M1&T1);
ctl_alu_core_V = ctl_alu_core_V | (pla[27]&~pla[34])&(M1&T1);
ctl_alu_core_S = ctl_alu_core_S | (pla[27]&~pla[34])&(M1&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[27]&~pla[34])&(M1&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[27]&~pla[34])&(M1&T1);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[27]&~pla[34])&(M1&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[27]&~pla[34])&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[27]&~pla[34])&(M1&T1);
ctl_pf_sel_pla27npla34M1T1_20 = (pla[27]&~pla[34])&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla27npla34M1T1_20,ctl_pf_sel_pla27npla34M1T1_20})&(`PFSEL_P);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[27]&~pla[34])&(M1&T1);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[27]&~pla[34])&(M1&T1);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[27]&~pla[34])&(M1&T2);
ctl_reg_gp_sel_pla27npla34M1T2_2 = (pla[27]&~pla[34])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla27npla34M1T2_2,ctl_reg_gp_sel_pla27npla34M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla27npla34M1T2_3 = (pla[27]&~pla[34])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla27npla34M1T2_3,ctl_reg_gp_hilo_pla27npla34M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[27]&~pla[34])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[27]&~pla[34])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (pla[27]&~pla[34])&(M1&T2);
ctl_reg_gp_sel_pla27npla34M1T3_1 = (pla[27]&~pla[34])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla27npla34M1T3_1,ctl_reg_gp_sel_pla27npla34M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla27npla34M1T3_2 = (pla[27]&~pla[34])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla27npla34M1T3_2,ctl_reg_gp_hilo_pla27npla34M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[27]&~pla[34])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[27]&~pla[34])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[27]&~pla[34])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[27]&~pla[34])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[27]&~pla[34])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[27]&~pla[34])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[27]&~pla[34])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[27]&~pla[34])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[27]&~pla[34])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[27]&~pla[34])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[27]&~pla[34])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[27]&~pla[34])&(M1&T3);
validPLA = validPLA | (pla[27]&~pla[34])&(M1&T4);
nextM = nextM | (pla[27]&~pla[34])&(M1&T4);
ctl_iorw = ctl_iorw | (pla[27]&~pla[34])&(M1&T4);
fIORead = fIORead | (pla[27]&~pla[34])&(M2&T1);
ctl_reg_gp_sel_pla27npla34M2T1_2 = (pla[27]&~pla[34])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla27npla34M2T1_2,ctl_reg_gp_sel_pla27npla34M2T1_2})&(`GP_REG_BC);
ctl_reg_gp_hilo_pla27npla34M2T1_3 = (pla[27]&~pla[34])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla27npla34M2T1_3,ctl_reg_gp_hilo_pla27npla34M2T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[27]&~pla[34])&(M2&T1);
ctl_al_we = ctl_al_we | (pla[27]&~pla[34])&(M2&T1);
fIORead = fIORead | (pla[27]&~pla[34])&(M2&T2);
fIORead = fIORead | (pla[27]&~pla[34])&(M2&T3);
fIORead = fIORead | (pla[27]&~pla[34])&(M2&T4);
setM1 = setM1 | (pla[27]&~pla[34])&(M2&T4);
ctl_sw_2d = ctl_sw_2d | (pla[27]&~pla[34])&(M2&T4);
ctl_sw_1d = ctl_sw_1d | (pla[27]&~pla[34])&(M2&T4);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[27]&~pla[34])&(M2&T4);
ctl_flags_alu = ctl_flags_alu | (pla[27]&~pla[34])&(M2&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[27]&~pla[34])&(M2&T4)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[27]&~pla[34])&(M2&T4);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[27]&~pla[34])&(M2&T4);
ctl_alu_op_low = ctl_alu_op_low | (pla[27]&~pla[34])&(M2&T4);
ctl_alu_core_R = ctl_alu_core_R | (pla[27]&~pla[34])&(M2&T4);
ctl_alu_core_V = ctl_alu_core_V | (pla[27]&~pla[34])&(M2&T4);
ctl_alu_core_S = ctl_alu_core_S | (pla[27]&~pla[34])&(M2&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[27]&~pla[34])&(M2&T4);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[27]&~pla[34])&(M2&T4);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[27]&~pla[34])&(M2&T4);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[27]&~pla[34])&(M2&T4);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[27]&~pla[34])&(M2&T4);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[27]&~pla[34])&(M2&T4);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[27]&~pla[34])&(M2&T4);
validPLA = validPLA | (pla[37]&pla[28])&(M1&T4);
nextM = nextM | (pla[37]&pla[28])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[37]&pla[28])&(M1&T4);
fMRead = fMRead | (pla[37]&pla[28])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[37]&pla[28])&(M2&T1);
ctl_reg_sys_hilo_pla37pla28M2T1_3 = (pla[37]&pla[28])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla37pla28M2T1_3,ctl_reg_sys_hilo_pla37pla28M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[37]&pla[28])&(M2&T1);
fMRead = fMRead | (pla[37]&pla[28])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[37]&pla[28])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[37]&pla[28])&(M2&T2);
ctl_reg_sys_hilo_pla37pla28M2T2_4 = (pla[37]&pla[28])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla37pla28M2T2_4,ctl_reg_sys_hilo_pla37pla28M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[37]&pla[28])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[37]&pla[28])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[37]&pla[28])&(M2&T2);
fMRead = fMRead | (pla[37]&pla[28])&(M2&T3);
nextM = nextM | (pla[37]&pla[28])&(M2&T3);
ctl_iorw = ctl_iorw | (pla[37]&pla[28])&(M2&T3);
ctl_reg_gp_sel_pla37pla28M2T3_4 = (pla[37]&pla[28])&(M2&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla37pla28M2T3_4,ctl_reg_gp_sel_pla37pla28M2T3_4})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla37pla28M2T3_5 = (pla[37]&pla[28])&(M2&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla37pla28M2T3_5,ctl_reg_gp_hilo_pla37pla28M2T3_5})&(2'b10);
ctl_sw_4d = ctl_sw_4d | (pla[37]&pla[28])&(M2&T3);
ctl_al_we = ctl_al_we | (pla[37]&pla[28])&(M2&T3);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[37]&pla[28])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (pla[37]&pla[28])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[37]&pla[28])&(M2&T3);
fIOWrite = fIOWrite | (pla[37]&pla[28])&(M3&T1);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[37]&pla[28])&(M3&T1);
ctl_reg_gp_sel_pla37pla28M3T1_3 = (pla[37]&pla[28])&(M3&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla37pla28M3T1_3,ctl_reg_gp_sel_pla37pla28M3T1_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla37pla28M3T1_4 = (pla[37]&pla[28])&(M3&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla37pla28M3T1_4,ctl_reg_gp_hilo_pla37pla28M3T1_4})&(2'b10);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[37]&pla[28])&(M3&T1);
ctl_sw_2u = ctl_sw_2u | (pla[37]&pla[28])&(M3&T1);
ctl_sw_1u = ctl_sw_1u | (pla[37]&pla[28])&(M3&T1);
ctl_bus_db_we = ctl_bus_db_we | (pla[37]&pla[28])&(M3&T1);
fIOWrite = fIOWrite | (pla[37]&pla[28])&(M3&T2);
fIOWrite = fIOWrite | (pla[37]&pla[28])&(M3&T3);
fIOWrite = fIOWrite | (pla[37]&pla[28])&(M3&T4);
setM1 = setM1 | (pla[37]&pla[28])&(M3&T4);
validPLA = validPLA | (pla[27]&pla[34])&(M1&T4);
nextM = nextM | (pla[27]&pla[34])&(M1&T4);
ctl_iorw = ctl_iorw | (pla[27]&pla[34])&(M1&T4);
ctl_bus_zero_oe = ctl_bus_zero_oe | (pla[27]&pla[34])&(M1&T4)&(op4&op5&~op3);
ctl_reg_gp_sel_pla27pla34M1T4nop4op5nop3_1 = (pla[27]&pla[34])&(M1&T4)&(~(op4&op5&~op3));
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla27pla34M1T4nop4op5nop3_1,ctl_reg_gp_sel_pla27pla34M1T4nop4op5nop3_1})&(op54);
ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2 = (pla[27]&pla[34])&(M1&T4)&(~(op4&op5&~op3));
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2,ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2})&({~rsel3,rsel3});
ctl_reg_out_hi = ctl_reg_out_hi | (pla[27]&pla[34])&(M1&T4)&(~rsel3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[27]&pla[34])&(M1&T4)&(rsel3);
ctl_sw_2u = ctl_sw_2u | (pla[27]&pla[34])&(M1&T4)&(~rsel3);
ctl_sw_2d = ctl_sw_2d | (pla[27]&pla[34])&(M1&T4)&(rsel3);
ctl_sw_1u = ctl_sw_1u | (pla[27]&pla[34])&(M1&T4);
ctl_bus_db_we = ctl_bus_db_we | (pla[27]&pla[34])&(M1&T4);
fIOWrite = fIOWrite | (pla[27]&pla[34])&(M2&T1);
ctl_reg_gp_sel_pla27pla34M2T1_2 = (pla[27]&pla[34])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla27pla34M2T1_2,ctl_reg_gp_sel_pla27pla34M2T1_2})&(`GP_REG_BC);
ctl_reg_gp_hilo_pla27pla34M2T1_3 = (pla[27]&pla[34])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla27pla34M2T1_3,ctl_reg_gp_hilo_pla27pla34M2T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[27]&pla[34])&(M2&T1);
ctl_al_we = ctl_al_we | (pla[27]&pla[34])&(M2&T1);
fIOWrite = fIOWrite | (pla[27]&pla[34])&(M2&T2);
fIOWrite = fIOWrite | (pla[27]&pla[34])&(M2&T3);
fIOWrite = fIOWrite | (pla[27]&pla[34])&(M2&T4);
setM1 = setM1 | (pla[27]&pla[34])&(M2&T4);
ctl_alu_oe = ctl_alu_oe | (pla[91]&pla[21])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[91]&pla[21])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[91]&pla[21])&(M1&T1);
ctl_alu_core_R = ctl_alu_core_R | (pla[91]&pla[21])&(M1&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[91]&pla[21])&(M1&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[91]&pla[21])&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[91]&pla[21])&(M1&T1);
ctl_pf_sel_pla91pla21M1T1_8 = (pla[91]&pla[21])&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla91pla21M1T1_8,ctl_pf_sel_pla91pla21M1T1_8})&(`PFSEL_P);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[91]&pla[21])&(M1&T2);
ctl_reg_gp_sel_pla91pla21M1T2_2 = (pla[91]&pla[21])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla21M1T2_2,ctl_reg_gp_sel_pla91pla21M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla91pla21M1T2_3 = (pla[91]&pla[21])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla21M1T2_3,ctl_reg_gp_hilo_pla91pla21M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[91]&pla[21])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[91]&pla[21])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (pla[91]&pla[21])&(M1&T2);
ctl_reg_gp_sel_pla91pla21M1T3_1 = (pla[91]&pla[21])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla21M1T3_1,ctl_reg_gp_sel_pla91pla21M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla91pla21M1T3_2 = (pla[91]&pla[21])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla21M1T3_2,ctl_reg_gp_hilo_pla91pla21M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[91]&pla[21])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[91]&pla[21])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[91]&pla[21])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[91]&pla[21])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[91]&pla[21])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[91]&pla[21])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[91]&pla[21])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[91]&pla[21])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[91]&pla[21])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[91]&pla[21])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[91]&pla[21])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[91]&pla[21])&(M1&T3);
validPLA = validPLA | (pla[91]&pla[21])&(M1&T4);
nextM = nextM | (pla[91]&pla[21])&(M1&T5);
ctl_iorw = ctl_iorw | (pla[91]&pla[21])&(M1&T5);
fIORead = fIORead | (pla[91]&pla[21])&(M2&T1);
ctl_reg_gp_sel_pla91pla21M2T1_2 = (pla[91]&pla[21])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla21M2T1_2,ctl_reg_gp_sel_pla91pla21M2T1_2})&(`GP_REG_BC);
ctl_reg_gp_hilo_pla91pla21M2T1_3 = (pla[91]&pla[21])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla21M2T1_3,ctl_reg_gp_hilo_pla91pla21M2T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[91]&pla[21])&(M2&T1);
ctl_al_we = ctl_al_we | (pla[91]&pla[21])&(M2&T1);
fIORead = fIORead | (pla[91]&pla[21])&(M2&T2);
ctl_reg_gp_sel_pla91pla21M2T2_2 = (pla[91]&pla[21])&(M2&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla21M2T2_2,ctl_reg_gp_sel_pla91pla21M2T2_2})&(`GP_REG_BC);
ctl_reg_gp_hilo_pla91pla21M2T2_3 = (pla[91]&pla[21])&(M2&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla21M2T2_3,ctl_reg_gp_hilo_pla91pla21M2T2_3})&(2'b10);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[91]&pla[21])&(M2&T2);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[91]&pla[21])&(M2&T2);
ctl_flags_alu = ctl_flags_alu | (pla[91]&pla[21])&(M2&T2);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[91]&pla[21])&(M2&T2)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_zero = ctl_alu_op2_sel_zero | (pla[91]&pla[21])&(M2&T2);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[91]&pla[21])&(M2&T2);
ctl_alu_op_low = ctl_alu_op_low | (pla[91]&pla[21])&(M2&T2);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[91]&pla[21])&(M2&T2)&(ctl_alu_op_low);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[91]&pla[21])&(M2&T2)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[91]&pla[21])&(M2&T2)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[91]&pla[21])&(M2&T2);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[91]&pla[21])&(M2&T2);
fIORead = fIORead | (pla[91]&pla[21])&(M2&T3);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[91]&pla[21])&(M2&T3);
ctl_reg_gp_sel_pla91pla21M2T3_3 = (pla[91]&pla[21])&(M2&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla21M2T3_3,ctl_reg_gp_sel_pla91pla21M2T3_3})&(`GP_REG_BC);
ctl_reg_gp_hilo_pla91pla21M2T3_4 = (pla[91]&pla[21])&(M2&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla21M2T3_4,ctl_reg_gp_hilo_pla91pla21M2T3_4})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[91]&pla[21])&(M2&T3);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[91]&pla[21])&(M2&T3);
ctl_flags_alu = ctl_flags_alu | (pla[91]&pla[21])&(M2&T3);
ctl_alu_oe = ctl_alu_oe | (pla[91]&pla[21])&(M2&T3);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[91]&pla[21])&(M2&T3);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[91]&pla[21])&(M2&T3);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[91]&pla[21])&(M2&T3)&(ctl_alu_op_low);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[91]&pla[21])&(M2&T3)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[91]&pla[21])&(M2&T3)&(~ctl_alu_op_low);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[91]&pla[21])&(M2&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[91]&pla[21])&(M2&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[91]&pla[21])&(M2&T3);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[91]&pla[21])&(M2&T3);
fIORead = fIORead | (pla[91]&pla[21])&(M2&T4);
nextM = nextM | (pla[91]&pla[21])&(M2&T4);
ctl_mWrite = ctl_mWrite | (pla[91]&pla[21])&(M2&T4);
ctl_sw_2d = ctl_sw_2d | (pla[91]&pla[21])&(M2&T4);
ctl_sw_1d = ctl_sw_1d | (pla[91]&pla[21])&(M2&T4);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[91]&pla[21])&(M2&T4);
ctl_flags_alu = ctl_flags_alu | (pla[91]&pla[21])&(M2&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[91]&pla[21])&(M2&T4)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[91]&pla[21])&(M2&T4);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[91]&pla[21])&(M2&T4);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[91]&pla[21])&(M2&T4);
fMWrite = fMWrite | (pla[91]&pla[21])&(M3&T1);
ctl_reg_gp_sel_pla91pla21M3T1_2 = (pla[91]&pla[21])&(M3&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla21M3T1_2,ctl_reg_gp_sel_pla91pla21M3T1_2})&(`GP_REG_HL);
ctl_reg_gp_hilo_pla91pla21M3T1_3 = (pla[91]&pla[21])&(M3&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla21M3T1_3,ctl_reg_gp_hilo_pla91pla21M3T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[91]&pla[21])&(M3&T1);
ctl_al_we = ctl_al_we | (pla[91]&pla[21])&(M3&T1);
fMWrite = fMWrite | (pla[91]&pla[21])&(M3&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[91]&pla[21])&(M3&T2);
ctl_reg_gp_sel_pla91pla21M3T2_3 = (pla[91]&pla[21])&(M3&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla21M3T2_3,ctl_reg_gp_sel_pla91pla21M3T2_3})&(`GP_REG_HL);
ctl_reg_gp_hilo_pla91pla21M3T2_4 = (pla[91]&pla[21])&(M3&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla21M3T2_4,ctl_reg_gp_hilo_pla91pla21M3T2_4})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[91]&pla[21])&(M3&T2);
ctl_inc_cy = ctl_inc_cy | (pla[91]&pla[21])&(M3&T2)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[91]&pla[21])&(M3&T2)&(op3);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[91]&pla[21])&(M3&T2);
fMWrite = fMWrite | (pla[91]&pla[21])&(M3&T3);
nextM = nextM | (pla[91]&pla[21])&(M3&T3);
setM1 = setM1 | (pla[91]&pla[21])&(M3&T3)&(nonRep|flags_zf);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[91]&pla[21])&(M4&T1);
ctl_reg_sys_hilo_pla91pla21M4T1_2 = (pla[91]&pla[21])&(M4&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla91pla21M4T1_2,ctl_reg_sys_hilo_pla91pla21M4T1_2})&(2'b11);
ctl_al_we = ctl_al_we | (pla[91]&pla[21])&(M4&T1);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[91]&pla[21])&(M4&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[91]&pla[21])&(M4&T2);
ctl_reg_sys_hilo_pla91pla21M4T2_3 = (pla[91]&pla[21])&(M4&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla91pla21M4T2_3,ctl_reg_sys_hilo_pla91pla21M4T2_3})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[91]&pla[21])&(M4&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[91]&pla[21])&(M4&T2)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[91]&pla[21])&(M4&T2);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[91]&pla[21])&(M4&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[91]&pla[21])&(M4&T3);
ctl_reg_sys_hilo_pla91pla21M4T3_2 = (pla[91]&pla[21])&(M4&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla91pla21M4T3_2,ctl_reg_sys_hilo_pla91pla21M4T3_2})&(2'b11);
ctl_al_we = ctl_al_we | (pla[91]&pla[21])&(M4&T3);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[91]&pla[21])&(M4&T4);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[91]&pla[21])&(M4&T4);
ctl_reg_sys_hilo_pla91pla21M4T4_3 = (pla[91]&pla[21])&(M4&T4);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla91pla21M4T4_3,ctl_reg_sys_hilo_pla91pla21M4T4_3})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[91]&pla[21])&(M4&T4)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[91]&pla[21])&(M4&T4)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[91]&pla[21])&(M4&T4);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[91]&pla[21])&(M4&T4);
setM1 = setM1 | (pla[91]&pla[21])&(M4&T5);
ctl_flags_alu = ctl_flags_alu | (pla[91]&pla[20])&(M1&T1);
ctl_alu_oe = ctl_alu_oe | (pla[91]&pla[20])&(M1&T1);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[91]&pla[20])&(M1&T1);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[91]&pla[20])&(M1&T1);
ctl_alu_core_R = ctl_alu_core_R | (pla[91]&pla[20])&(M1&T1);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[91]&pla[20])&(M1&T1);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[91]&pla[20])&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[91]&pla[20])&(M1&T1);
ctl_pf_sel_pla91pla20M1T1_9 = (pla[91]&pla[20])&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla91pla20M1T1_9,ctl_pf_sel_pla91pla20M1T1_9})&(`PFSEL_P);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[91]&pla[20])&(M1&T2);
ctl_reg_gp_sel_pla91pla20M1T2_2 = (pla[91]&pla[20])&(M1&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla20M1T2_2,ctl_reg_gp_sel_pla91pla20M1T2_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla91pla20M1T2_3 = (pla[91]&pla[20])&(M1&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla20M1T2_3,ctl_reg_gp_hilo_pla91pla20M1T2_3})&(2'b01);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[91]&pla[20])&(M1&T2);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[91]&pla[20])&(M1&T2);
ctl_flags_oe = ctl_flags_oe | (pla[91]&pla[20])&(M1&T2);
ctl_reg_gp_sel_pla91pla20M1T3_1 = (pla[91]&pla[20])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla20M1T3_1,ctl_reg_gp_sel_pla91pla20M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla91pla20M1T3_2 = (pla[91]&pla[20])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla20M1T3_2,ctl_reg_gp_hilo_pla91pla20M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[91]&pla[20])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[91]&pla[20])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[91]&pla[20])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[91]&pla[20])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[91]&pla[20])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[91]&pla[20])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[91]&pla[20])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[91]&pla[20])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[91]&pla[20])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[91]&pla[20])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[91]&pla[20])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[91]&pla[20])&(M1&T3);
validPLA = validPLA | (pla[91]&pla[20])&(M1&T4);
ctl_reg_gp_sel_pla91pla20M1T4_2 = (pla[91]&pla[20])&(M1&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla20M1T4_2,ctl_reg_gp_sel_pla91pla20M1T4_2})&(`GP_REG_BC);
ctl_reg_gp_hilo_pla91pla20M1T4_3 = (pla[91]&pla[20])&(M1&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla20M1T4_3,ctl_reg_gp_hilo_pla91pla20M1T4_3})&(2'b10);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[91]&pla[20])&(M1&T4);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[91]&pla[20])&(M1&T4);
ctl_flags_alu = ctl_flags_alu | (pla[91]&pla[20])&(M1&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[91]&pla[20])&(M1&T4)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_zero = ctl_alu_op2_sel_zero | (pla[91]&pla[20])&(M1&T4);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[91]&pla[20])&(M1&T4);
ctl_alu_op_low = ctl_alu_op_low | (pla[91]&pla[20])&(M1&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[91]&pla[20])&(M1&T4)&(ctl_alu_op_low);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[91]&pla[20])&(M1&T4)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[91]&pla[20])&(M1&T4)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[91]&pla[20])&(M1&T4);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[91]&pla[20])&(M1&T4);
nextM = nextM | (pla[91]&pla[20])&(M1&T5);
ctl_mRead = ctl_mRead | (pla[91]&pla[20])&(M1&T5);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[91]&pla[20])&(M1&T5);
ctl_reg_gp_sel_pla91pla20M1T5_4 = (pla[91]&pla[20])&(M1&T5);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla20M1T5_4,ctl_reg_gp_sel_pla91pla20M1T5_4})&(`GP_REG_BC);
ctl_reg_gp_hilo_pla91pla20M1T5_5 = (pla[91]&pla[20])&(M1&T5);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla20M1T5_5,ctl_reg_gp_hilo_pla91pla20M1T5_5})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[91]&pla[20])&(M1&T5);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[91]&pla[20])&(M1&T5);
ctl_flags_alu = ctl_flags_alu | (pla[91]&pla[20])&(M1&T5);
ctl_alu_oe = ctl_alu_oe | (pla[91]&pla[20])&(M1&T5);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[91]&pla[20])&(M1&T5);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[91]&pla[20])&(M1&T5);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[91]&pla[20])&(M1&T5)&(ctl_alu_op_low);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[91]&pla[20])&(M1&T5)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[91]&pla[20])&(M1&T5)&(~ctl_alu_op_low);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[91]&pla[20])&(M1&T5);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[91]&pla[20])&(M1&T5);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[91]&pla[20])&(M1&T5);
fMRead = fMRead | (pla[91]&pla[20])&(M2&T1);
ctl_reg_gp_sel_pla91pla20M2T1_2 = (pla[91]&pla[20])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla20M2T1_2,ctl_reg_gp_sel_pla91pla20M2T1_2})&(`GP_REG_HL);
ctl_reg_gp_hilo_pla91pla20M2T1_3 = (pla[91]&pla[20])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla20M2T1_3,ctl_reg_gp_hilo_pla91pla20M2T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[91]&pla[20])&(M2&T1);
ctl_al_we = ctl_al_we | (pla[91]&pla[20])&(M2&T1);
fMRead = fMRead | (pla[91]&pla[20])&(M2&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[91]&pla[20])&(M2&T2);
ctl_reg_gp_sel_pla91pla20M2T2_3 = (pla[91]&pla[20])&(M2&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla20M2T2_3,ctl_reg_gp_sel_pla91pla20M2T2_3})&(`GP_REG_HL);
ctl_reg_gp_hilo_pla91pla20M2T2_4 = (pla[91]&pla[20])&(M2&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla20M2T2_4,ctl_reg_gp_hilo_pla91pla20M2T2_4})&(2'b11);
ctl_sw_4u = ctl_sw_4u | (pla[91]&pla[20])&(M2&T2);
ctl_inc_cy = ctl_inc_cy | (pla[91]&pla[20])&(M2&T2)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[91]&pla[20])&(M2&T2)&(op3);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[91]&pla[20])&(M2&T2);
fMRead = fMRead | (pla[91]&pla[20])&(M2&T3);
nextM = nextM | (pla[91]&pla[20])&(M2&T3);
ctl_iorw = ctl_iorw | (pla[91]&pla[20])&(M2&T3);
ctl_reg_gp_sel_pla91pla20M2T3_4 = (pla[91]&pla[20])&(M2&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla20M2T3_4,ctl_reg_gp_sel_pla91pla20M2T3_4})&(`GP_REG_HL);
ctl_reg_gp_hilo_pla91pla20M2T3_5 = (pla[91]&pla[20])&(M2&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla20M2T3_5,ctl_reg_gp_hilo_pla91pla20M2T3_5})&(2'b01);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[91]&pla[20])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[91]&pla[20])&(M2&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[91]&pla[20])&(M2&T3)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[91]&pla[20])&(M2&T3);
fIOWrite = fIOWrite | (pla[91]&pla[20])&(M3&T1);
ctl_reg_gp_sel_pla91pla20M3T1_2 = (pla[91]&pla[20])&(M3&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla20M3T1_2,ctl_reg_gp_sel_pla91pla20M3T1_2})&(`GP_REG_BC);
ctl_reg_gp_hilo_pla91pla20M3T1_3 = (pla[91]&pla[20])&(M3&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla20M3T1_3,ctl_reg_gp_hilo_pla91pla20M3T1_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[91]&pla[20])&(M3&T1);
ctl_al_we = ctl_al_we | (pla[91]&pla[20])&(M3&T1);
fIOWrite = fIOWrite | (pla[91]&pla[20])&(M3&T2);
ctl_sw_2d = ctl_sw_2d | (pla[91]&pla[20])&(M3&T2);
ctl_sw_1d = ctl_sw_1d | (pla[91]&pla[20])&(M3&T2);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[91]&pla[20])&(M3&T2);
ctl_flags_alu = ctl_flags_alu | (pla[91]&pla[20])&(M3&T2);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[91]&pla[20])&(M3&T2)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[91]&pla[20])&(M3&T2);
ctl_alu_op_low = ctl_alu_op_low | (pla[91]&pla[20])&(M3&T2);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[91]&pla[20])&(M3&T2)&(ctl_alu_op_low);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[91]&pla[20])&(M3&T2)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[91]&pla[20])&(M3&T2)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[91]&pla[20])&(M3&T2);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[91]&pla[20])&(M3&T2);
fIOWrite = fIOWrite | (pla[91]&pla[20])&(M3&T3);
ctl_flags_alu = ctl_flags_alu | (pla[91]&pla[20])&(M3&T3);
ctl_alu_oe = ctl_alu_oe | (pla[91]&pla[20])&(M3&T3);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[91]&pla[20])&(M3&T3);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[91]&pla[20])&(M3&T3);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[91]&pla[20])&(M3&T3)&(ctl_alu_op_low);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[91]&pla[20])&(M3&T3)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[91]&pla[20])&(M3&T3)&(~ctl_alu_op_low);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[91]&pla[20])&(M3&T3);
fIOWrite = fIOWrite | (pla[91]&pla[20])&(M3&T4);
nextM = nextM | (pla[91]&pla[20])&(M3&T4);
setM1 = setM1 | (pla[91]&pla[20])&(M3&T4)&(nonRep|flags_zf);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[91]&pla[20])&(M4&T1);
ctl_reg_sys_hilo_pla91pla20M4T1_2 = (pla[91]&pla[20])&(M4&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla91pla20M4T1_2,ctl_reg_sys_hilo_pla91pla20M4T1_2})&(2'b11);
ctl_al_we = ctl_al_we | (pla[91]&pla[20])&(M4&T1);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[91]&pla[20])&(M4&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[91]&pla[20])&(M4&T2);
ctl_reg_sys_hilo_pla91pla20M4T2_3 = (pla[91]&pla[20])&(M4&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla91pla20M4T2_3,ctl_reg_sys_hilo_pla91pla20M4T2_3})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[91]&pla[20])&(M4&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[91]&pla[20])&(M4&T2)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[91]&pla[20])&(M4&T2);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[91]&pla[20])&(M4&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[91]&pla[20])&(M4&T3);
ctl_reg_sys_hilo_pla91pla20M4T3_2 = (pla[91]&pla[20])&(M4&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla91pla20M4T3_2,ctl_reg_sys_hilo_pla91pla20M4T3_2})&(2'b11);
ctl_al_we = ctl_al_we | (pla[91]&pla[20])&(M4&T3);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[91]&pla[20])&(M4&T4);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[91]&pla[20])&(M4&T4);
ctl_reg_sys_hilo_pla91pla20M4T4_3 = (pla[91]&pla[20])&(M4&T4);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla91pla20M4T4_3,ctl_reg_sys_hilo_pla91pla20M4T4_3})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[91]&pla[20])&(M4&T4)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[91]&pla[20])&(M4&T4)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[91]&pla[20])&(M4&T4);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[91]&pla[20])&(M4&T4);
setM1 = setM1 | (pla[91]&pla[20])&(M4&T5);
validPLA = validPLA | (pla[29])&(M1&T4);
nextM = nextM | (pla[29])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[29])&(M1&T4);
fMRead = fMRead | (pla[29])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[29])&(M2&T1);
ctl_reg_sys_hilo_pla29M2T1_3 = (pla[29])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla29M2T1_3,ctl_reg_sys_hilo_pla29M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[29])&(M2&T1);
fMRead = fMRead | (pla[29])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[29])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[29])&(M2&T2);
ctl_reg_sys_hilo_pla29M2T2_4 = (pla[29])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla29M2T2_4,ctl_reg_sys_hilo_pla29M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[29])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[29])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[29])&(M2&T2);
fMRead = fMRead | (pla[29])&(M2&T3);
nextM = nextM | (pla[29])&(M2&T3);
ctl_mRead = ctl_mRead | (pla[29])&(M2&T3);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[29])&(M2&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[29])&(M2&T3);
ctl_reg_sys_hilo_pla29M2T3_6 = (pla[29])&(M2&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla29M2T3_6,ctl_reg_sys_hilo_pla29M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (pla[29])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[29])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (pla[29])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[29])&(M2&T3);
fMRead = fMRead | (pla[29])&(M3&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[29])&(M3&T1);
ctl_reg_sys_hilo_pla29M3T1_3 = (pla[29])&(M3&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla29M3T1_3,ctl_reg_sys_hilo_pla29M3T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[29])&(M3&T1);
fMRead = fMRead | (pla[29])&(M3&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[29])&(M3&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[29])&(M3&T2);
ctl_reg_sys_hilo_pla29M3T2_4 = (pla[29])&(M3&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla29M3T2_4,ctl_reg_sys_hilo_pla29M3T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[29])&(M3&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[29])&(M3&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[29])&(M3&T2);
fMRead = fMRead | (pla[29])&(M3&T3);
setM1 = setM1 | (pla[29])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[29])&(M3&T3);
ctl_reg_sys_hilo_pla29M3T3_4 = (pla[29])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla29M3T3_4,ctl_reg_sys_hilo_pla29M3T3_4})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[29])&(M3&T3);
ctl_al_we = ctl_al_we | (pla[29])&(M3&T3);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[29])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[29])&(M3&T3);
ctl_reg_sys_hilo_pla29M3T3_9 = (pla[29])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla29M3T3_9,ctl_reg_sys_hilo_pla29M3T3_9})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[29])&(M3&T3);
ctl_sw_2d = ctl_sw_2d | (pla[29])&(M3&T3);
ctl_sw_1d = ctl_sw_1d | (pla[29])&(M3&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[29])&(M3&T3);
ctl_reg_not_pc = ctl_reg_not_pc | (pla[29])&(M3&T3);
ctl_reg_gp_sel_pla43M1T3_1 = (pla[43])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla43M1T3_1,ctl_reg_gp_sel_pla43M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla43M1T3_2 = (pla[43])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla43M1T3_2,ctl_reg_gp_hilo_pla43M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[43])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[43])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[43])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[43])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[43])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[43])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[43])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[43])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[43])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[43])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[43])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[43])&(M1&T3);
validPLA = validPLA | (pla[43])&(M1&T4);
nextM = nextM | (pla[43])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[43])&(M1&T4);
fMRead = fMRead | (pla[43])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[43])&(M2&T1);
ctl_reg_sys_hilo_pla43M2T1_3 = (pla[43])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla43M2T1_3,ctl_reg_sys_hilo_pla43M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[43])&(M2&T1);
fMRead = fMRead | (pla[43])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[43])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[43])&(M2&T2);
ctl_reg_sys_hilo_pla43M2T2_4 = (pla[43])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla43M2T2_4,ctl_reg_sys_hilo_pla43M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[43])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[43])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[43])&(M2&T2);
fMRead = fMRead | (pla[43])&(M2&T3);
nextM = nextM | (pla[43])&(M2&T3);
ctl_mRead = ctl_mRead | (pla[43])&(M2&T3);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[43])&(M2&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[43])&(M2&T3);
ctl_reg_sys_hilo_pla43M2T3_6 = (pla[43])&(M2&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla43M2T3_6,ctl_reg_sys_hilo_pla43M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (pla[43])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[43])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (pla[43])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[43])&(M2&T3);
fMRead = fMRead | (pla[43])&(M3&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[43])&(M3&T1);
ctl_reg_sys_hilo_pla43M3T1_3 = (pla[43])&(M3&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla43M3T1_3,ctl_reg_sys_hilo_pla43M3T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[43])&(M3&T1);
fMRead = fMRead | (pla[43])&(M3&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[43])&(M3&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[43])&(M3&T2);
ctl_reg_sys_hilo_pla43M3T2_4 = (pla[43])&(M3&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla43M3T2_4,ctl_reg_sys_hilo_pla43M3T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[43])&(M3&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[43])&(M3&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[43])&(M3&T2);
fMRead = fMRead | (pla[43])&(M3&T3);
setM1 = setM1 | (pla[43])&(M3&T3);
ctl_reg_not_pc = ctl_reg_not_pc | (pla[43])&(M3&T3)&(flags_cond_true);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[43])&(M3&T3)&(flags_cond_true);
ctl_reg_sys_hilo_pla43M3T3_5 = (pla[43])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla43M3T3_5,ctl_reg_sys_hilo_pla43M3T3_5})&({flags_cond_true,flags_cond_true});
ctl_sw_4d = ctl_sw_4d | (pla[43])&(M3&T3)&(flags_cond_true);
ctl_al_we = ctl_al_we | (pla[43])&(M3&T3);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[43])&(M3&T3)&(flags_cond_true);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[43])&(M3&T3)&(flags_cond_true);
ctl_reg_sys_hilo_pla43M3T3_10 = (pla[43])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla43M3T3_10,ctl_reg_sys_hilo_pla43M3T3_10})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[43])&(M3&T3);
ctl_sw_2d = ctl_sw_2d | (pla[43])&(M3&T3);
ctl_sw_1d = ctl_sw_1d | (pla[43])&(M3&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[43])&(M3&T3);
ctl_reg_gp_sel_pla47M1T3_1 = (pla[47])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla47M1T3_1,ctl_reg_gp_sel_pla47M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla47M1T3_2 = (pla[47])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla47M1T3_2,ctl_reg_gp_hilo_pla47M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[47])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[47])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[47])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[47])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[47])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[47])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[47])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[47])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[47])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[47])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[47])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[47])&(M1&T3);
validPLA = validPLA | (pla[47])&(M1&T4);
nextM = nextM | (pla[47])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[47])&(M1&T4);
fMRead = fMRead | (pla[47])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[47])&(M2&T1);
ctl_reg_sys_hilo_pla47M2T1_3 = (pla[47])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla47M2T1_3,ctl_reg_sys_hilo_pla47M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[47])&(M2&T1);
fMRead = fMRead | (pla[47])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[47])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[47])&(M2&T2);
ctl_reg_sys_hilo_pla47M2T2_4 = (pla[47])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla47M2T2_4,ctl_reg_sys_hilo_pla47M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[47])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[47])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[47])&(M2&T2);
fMRead = fMRead | (pla[47])&(M2&T3);
nextM = nextM | (pla[47])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[47])&(M3&T1);
ctl_sw_1d = ctl_sw_1d | (pla[47])&(M3&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[47])&(M3&T1);
ctl_flags_alu = ctl_flags_alu | (pla[47])&(M3&T1);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[47])&(M3&T1)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[47])&(M3&T1);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[47])&(M3&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[47])&(M3&T2);
ctl_reg_sys_hilo_pla47M3T2_2 = (pla[47])&(M3&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla47M3T2_2,ctl_reg_sys_hilo_pla47M3T2_2})&(2'b01);
ctl_sw_4u = ctl_sw_4u | (pla[47])&(M3&T2);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[47])&(M3&T2);
ctl_sw_2d = ctl_sw_2d | (pla[47])&(M3&T2);
ctl_flags_alu = ctl_flags_alu | (pla[47])&(M3&T2);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[47])&(M3&T2)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[47])&(M3&T2);
ctl_alu_op_low = ctl_alu_op_low | (pla[47])&(M3&T2);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[47])&(M3&T2)&(ctl_alu_op_low);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[47])&(M3&T2)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[47])&(M3&T2)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[47])&(M3&T2);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[47])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[47])&(M3&T3);
ctl_reg_sys_hilo_pla47M3T3_3 = (pla[47])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla47M3T3_3,ctl_reg_sys_hilo_pla47M3T3_3})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (pla[47])&(M3&T3);
ctl_sw_2u = ctl_sw_2u | (pla[47])&(M3&T3);
ctl_flags_alu = ctl_flags_alu | (pla[47])&(M3&T3);
ctl_alu_oe = ctl_alu_oe | (pla[47])&(M3&T3);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[47])&(M3&T3);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[47])&(M3&T3);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[47])&(M3&T3)&(ctl_alu_op_low);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[47])&(M3&T3)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[47])&(M3&T3)&(~ctl_alu_op_low);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[47])&(M3&T3);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[47])&(M3&T4);
ctl_reg_sys_hilo_pla47M3T4_2 = (pla[47])&(M3&T4);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla47M3T4_2,ctl_reg_sys_hilo_pla47M3T4_2})&(2'b10);
ctl_sw_4u = ctl_sw_4u | (pla[47])&(M3&T4);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[47])&(M3&T4);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[47])&(M3&T4);
ctl_flags_alu = ctl_flags_alu | (pla[47])&(M3&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[47])&(M3&T4)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_zero = ctl_alu_op2_sel_zero | (pla[47])&(M3&T4);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[47])&(M3&T4);
ctl_alu_op_low = ctl_alu_op_low | (pla[47])&(M3&T4);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[47])&(M3&T4)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[47])&(M3&T4);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[47])&(M3&T4)&(flags_sf);
setM1 = setM1 | (pla[47])&(M3&T5);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[47])&(M3&T5);
ctl_reg_sys_hilo_pla47M3T5_3 = (pla[47])&(M3&T5);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla47M3T5_3,ctl_reg_sys_hilo_pla47M3T5_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[47])&(M3&T5);
ctl_al_we = ctl_al_we | (pla[47])&(M3&T5);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[47])&(M3&T5);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[47])&(M3&T5);
ctl_reg_sys_hilo_pla47M3T5_8 = (pla[47])&(M3&T5);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla47M3T5_8,ctl_reg_sys_hilo_pla47M3T5_8})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[47])&(M3&T5);
ctl_flags_alu = ctl_flags_alu | (pla[47])&(M3&T5);
ctl_alu_oe = ctl_alu_oe | (pla[47])&(M3&T5);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[47])&(M3&T5);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[47])&(M3&T5);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[47])&(M3&T5)&(~ctl_alu_op_low);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[47])&(M3&T5)&(flags_sf);
ctl_reg_not_pc = ctl_reg_not_pc | (pla[47])&(M3&T5);
ctl_reg_gp_sel_pla48M1T3_1 = (pla[48])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla48M1T3_1,ctl_reg_gp_sel_pla48M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla48M1T3_2 = (pla[48])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla48M1T3_2,ctl_reg_gp_hilo_pla48M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[48])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[48])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[48])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[48])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[48])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[48])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[48])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[48])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[48])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[48])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[48])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[48])&(M1&T3);
validPLA = validPLA | (pla[48])&(M1&T4);
nextM = nextM | (pla[48])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[48])&(M1&T4);
ctl_cond_short = ctl_cond_short | (pla[48])&(M1&T4);
fMRead = fMRead | (pla[48])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[48])&(M2&T1);
ctl_reg_sys_hilo_pla48M2T1_3 = (pla[48])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla48M2T1_3,ctl_reg_sys_hilo_pla48M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[48])&(M2&T1);
fMRead = fMRead | (pla[48])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[48])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[48])&(M2&T2);
ctl_reg_sys_hilo_pla48M2T2_4 = (pla[48])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla48M2T2_4,ctl_reg_sys_hilo_pla48M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[48])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[48])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[48])&(M2&T2);
fMRead = fMRead | (pla[48])&(M2&T3);
nextM = nextM | (pla[48])&(M2&T3);
setM1 = setM1 | (pla[48])&(M2&T3)&(~flags_cond_true);
ctl_sw_2d = ctl_sw_2d | (pla[48])&(M3&T1);
ctl_sw_1d = ctl_sw_1d | (pla[48])&(M3&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[48])&(M3&T1);
ctl_flags_alu = ctl_flags_alu | (pla[48])&(M3&T1);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[48])&(M3&T1)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[48])&(M3&T1);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[48])&(M3&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[48])&(M3&T2);
ctl_reg_sys_hilo_pla48M3T2_2 = (pla[48])&(M3&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla48M3T2_2,ctl_reg_sys_hilo_pla48M3T2_2})&(2'b01);
ctl_sw_4u = ctl_sw_4u | (pla[48])&(M3&T2);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[48])&(M3&T2);
ctl_sw_2d = ctl_sw_2d | (pla[48])&(M3&T2);
ctl_flags_alu = ctl_flags_alu | (pla[48])&(M3&T2);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[48])&(M3&T2)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[48])&(M3&T2);
ctl_alu_op_low = ctl_alu_op_low | (pla[48])&(M3&T2);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[48])&(M3&T2)&(ctl_alu_op_low);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[48])&(M3&T2)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[48])&(M3&T2)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[48])&(M3&T2);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[48])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[48])&(M3&T3);
ctl_reg_sys_hilo_pla48M3T3_3 = (pla[48])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla48M3T3_3,ctl_reg_sys_hilo_pla48M3T3_3})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (pla[48])&(M3&T3);
ctl_sw_2u = ctl_sw_2u | (pla[48])&(M3&T3);
ctl_flags_alu = ctl_flags_alu | (pla[48])&(M3&T3);
ctl_alu_oe = ctl_alu_oe | (pla[48])&(M3&T3);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[48])&(M3&T3);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[48])&(M3&T3);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[48])&(M3&T3)&(ctl_alu_op_low);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[48])&(M3&T3)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[48])&(M3&T3)&(~ctl_alu_op_low);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[48])&(M3&T3);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[48])&(M3&T4);
ctl_reg_sys_hilo_pla48M3T4_2 = (pla[48])&(M3&T4);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla48M3T4_2,ctl_reg_sys_hilo_pla48M3T4_2})&(2'b10);
ctl_sw_4u = ctl_sw_4u | (pla[48])&(M3&T4);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[48])&(M3&T4);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[48])&(M3&T4);
ctl_flags_alu = ctl_flags_alu | (pla[48])&(M3&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[48])&(M3&T4)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_zero = ctl_alu_op2_sel_zero | (pla[48])&(M3&T4);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[48])&(M3&T4);
ctl_alu_op_low = ctl_alu_op_low | (pla[48])&(M3&T4);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[48])&(M3&T4)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[48])&(M3&T4);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[48])&(M3&T4)&(flags_sf);
setM1 = setM1 | (pla[48])&(M3&T5);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[48])&(M3&T5);
ctl_reg_sys_hilo_pla48M3T5_3 = (pla[48])&(M3&T5);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla48M3T5_3,ctl_reg_sys_hilo_pla48M3T5_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[48])&(M3&T5);
ctl_al_we = ctl_al_we | (pla[48])&(M3&T5);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[48])&(M3&T5);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[48])&(M3&T5);
ctl_reg_sys_hilo_pla48M3T5_8 = (pla[48])&(M3&T5);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla48M3T5_8,ctl_reg_sys_hilo_pla48M3T5_8})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[48])&(M3&T5);
ctl_flags_alu = ctl_flags_alu | (pla[48])&(M3&T5);
ctl_alu_oe = ctl_alu_oe | (pla[48])&(M3&T5);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[48])&(M3&T5);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[48])&(M3&T5);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[48])&(M3&T5)&(~ctl_alu_op_low);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[48])&(M3&T5)&(flags_sf);
ctl_reg_not_pc = ctl_reg_not_pc | (pla[48])&(M3&T5);
validPLA = validPLA | (pla[6])&(M1&T4);
setM1 = setM1 | (pla[6])&(M1&T4);
ctl_reg_gp_sel_pla6M1T4_3 = (pla[6])&(M1&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla6M1T4_3,ctl_reg_gp_sel_pla6M1T4_3})&(`GP_REG_HL);
ctl_reg_gp_hilo_pla6M1T4_4 = (pla[6])&(M1&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla6M1T4_4,ctl_reg_gp_hilo_pla6M1T4_4})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[6])&(M1&T4);
ctl_al_we = ctl_al_we | (pla[6])&(M1&T4);
ctl_reg_not_pc = ctl_reg_not_pc | (pla[6])&(M1&T4);
ctl_reg_gp_sel_pla26M1T3_1 = (pla[26])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla26M1T3_1,ctl_reg_gp_sel_pla26M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla26M1T3_2 = (pla[26])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla26M1T3_2,ctl_reg_gp_hilo_pla26M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[26])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[26])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[26])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[26])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[26])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[26])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[26])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[26])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[26])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[26])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[26])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[26])&(M1&T3);
validPLA = validPLA | (pla[26])&(M1&T4);
ctl_reg_gp_sel_pla26M1T4_2 = (pla[26])&(M1&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla26M1T4_2,ctl_reg_gp_sel_pla26M1T4_2})&(`GP_REG_BC);
ctl_reg_gp_hilo_pla26M1T4_3 = (pla[26])&(M1&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla26M1T4_3,ctl_reg_gp_hilo_pla26M1T4_3})&(2'b10);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[26])&(M1&T4);
ctl_flags_alu = ctl_flags_alu | (pla[26])&(M1&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[26])&(M1&T4)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_zero = ctl_alu_op2_sel_zero | (pla[26])&(M1&T4);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[26])&(M1&T4);
ctl_alu_op_low = ctl_alu_op_low | (pla[26])&(M1&T4);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[26])&(M1&T4)&(ctl_alu_op_low);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[26])&(M1&T4)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[26])&(M1&T4)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[26])&(M1&T4);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[26])&(M1&T4);
nextM = nextM | (pla[26])&(M1&T5);
ctl_mRead = ctl_mRead | (pla[26])&(M1&T5);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[26])&(M1&T5);
ctl_reg_gp_sel_pla26M1T5_4 = (pla[26])&(M1&T5);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla26M1T5_4,ctl_reg_gp_sel_pla26M1T5_4})&(`GP_REG_BC);
ctl_reg_gp_hilo_pla26M1T5_5 = (pla[26])&(M1&T5);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla26M1T5_5,ctl_reg_gp_hilo_pla26M1T5_5})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[26])&(M1&T5);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[26])&(M1&T5);
ctl_flags_alu = ctl_flags_alu | (pla[26])&(M1&T5);
ctl_alu_oe = ctl_alu_oe | (pla[26])&(M1&T5);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[26])&(M1&T5);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[26])&(M1&T5);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[26])&(M1&T5)&(ctl_alu_op_low);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[26])&(M1&T5)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[26])&(M1&T5)&(~ctl_alu_op_low);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[26])&(M1&T5);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[26])&(M1&T5);
fMRead = fMRead | (pla[26])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[26])&(M2&T1);
ctl_reg_sys_hilo_pla26M2T1_3 = (pla[26])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla26M2T1_3,ctl_reg_sys_hilo_pla26M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[26])&(M2&T1);
fMRead = fMRead | (pla[26])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[26])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[26])&(M2&T2);
ctl_reg_sys_hilo_pla26M2T2_4 = (pla[26])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla26M2T2_4,ctl_reg_sys_hilo_pla26M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[26])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[26])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[26])&(M2&T2);
fMRead = fMRead | (pla[26])&(M2&T3);
nextM = nextM | (pla[26])&(M2&T3);
setM1 = setM1 | (pla[26])&(M2&T3)&(flags_zf);
ctl_sw_2d = ctl_sw_2d | (pla[26])&(M3&T1);
ctl_sw_1d = ctl_sw_1d | (pla[26])&(M3&T1);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[26])&(M3&T1);
ctl_flags_alu = ctl_flags_alu | (pla[26])&(M3&T1);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[26])&(M3&T1)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[26])&(M3&T1);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[26])&(M3&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[26])&(M3&T2);
ctl_reg_sys_hilo_pla26M3T2_2 = (pla[26])&(M3&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla26M3T2_2,ctl_reg_sys_hilo_pla26M3T2_2})&(2'b01);
ctl_sw_4u = ctl_sw_4u | (pla[26])&(M3&T2);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[26])&(M3&T2);
ctl_sw_2d = ctl_sw_2d | (pla[26])&(M3&T2);
ctl_flags_alu = ctl_flags_alu | (pla[26])&(M3&T2);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[26])&(M3&T2)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[26])&(M3&T2);
ctl_alu_op_low = ctl_alu_op_low | (pla[26])&(M3&T2);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[26])&(M3&T2)&(ctl_alu_op_low);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[26])&(M3&T2)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[26])&(M3&T2)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[26])&(M3&T2);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[26])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[26])&(M3&T3);
ctl_reg_sys_hilo_pla26M3T3_3 = (pla[26])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla26M3T3_3,ctl_reg_sys_hilo_pla26M3T3_3})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (pla[26])&(M3&T3);
ctl_sw_2u = ctl_sw_2u | (pla[26])&(M3&T3);
ctl_flags_alu = ctl_flags_alu | (pla[26])&(M3&T3);
ctl_alu_oe = ctl_alu_oe | (pla[26])&(M3&T3);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[26])&(M3&T3);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[26])&(M3&T3);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[26])&(M3&T3)&(ctl_alu_op_low);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[26])&(M3&T3)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[26])&(M3&T3)&(~ctl_alu_op_low);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[26])&(M3&T3);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[26])&(M3&T4);
ctl_reg_sys_hilo_pla26M3T4_2 = (pla[26])&(M3&T4);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla26M3T4_2,ctl_reg_sys_hilo_pla26M3T4_2})&(2'b10);
ctl_sw_4u = ctl_sw_4u | (pla[26])&(M3&T4);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[26])&(M3&T4);
ctl_flags_alu = ctl_flags_alu | (pla[26])&(M3&T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[26])&(M3&T4)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_zero = ctl_alu_op2_sel_zero | (pla[26])&(M3&T4);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[26])&(M3&T4);
ctl_alu_op_low = ctl_alu_op_low | (pla[26])&(M3&T4);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[26])&(M3&T4)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[26])&(M3&T4);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[26])&(M3&T4)&(flags_sf);
setM1 = setM1 | (pla[26])&(M3&T5);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[26])&(M3&T5);
ctl_reg_sys_hilo_pla26M3T5_3 = (pla[26])&(M3&T5);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla26M3T5_3,ctl_reg_sys_hilo_pla26M3T5_3})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[26])&(M3&T5);
ctl_al_we = ctl_al_we | (pla[26])&(M3&T5);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[26])&(M3&T5);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[26])&(M3&T5);
ctl_reg_sys_hilo_pla26M3T5_8 = (pla[26])&(M3&T5);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla26M3T5_8,ctl_reg_sys_hilo_pla26M3T5_8})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[26])&(M3&T5);
ctl_flags_alu = ctl_flags_alu | (pla[26])&(M3&T5);
ctl_alu_oe = ctl_alu_oe | (pla[26])&(M3&T5);
ctl_alu_res_oe = ctl_alu_res_oe | (pla[26])&(M3&T5);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[26])&(M3&T5);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[26])&(M3&T5)&(~ctl_alu_op_low);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[26])&(M3&T5)&(flags_sf);
ctl_reg_not_pc = ctl_reg_not_pc | (pla[26])&(M3&T5);
validPLA = validPLA | (pla[24])&(M1&T4);
nextM = nextM | (pla[24])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[24])&(M1&T4);
fMRead = fMRead | (pla[24])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[24])&(M2&T1);
ctl_reg_sys_hilo_pla24M2T1_3 = (pla[24])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla24M2T1_3,ctl_reg_sys_hilo_pla24M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[24])&(M2&T1);
fMRead = fMRead | (pla[24])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[24])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[24])&(M2&T2);
ctl_reg_sys_hilo_pla24M2T2_4 = (pla[24])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla24M2T2_4,ctl_reg_sys_hilo_pla24M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[24])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[24])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[24])&(M2&T2);
fMRead = fMRead | (pla[24])&(M2&T3);
nextM = nextM | (pla[24])&(M2&T3);
ctl_mRead = ctl_mRead | (pla[24])&(M2&T3);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[24])&(M2&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[24])&(M2&T3);
ctl_reg_sys_hilo_pla24M2T3_6 = (pla[24])&(M2&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla24M2T3_6,ctl_reg_sys_hilo_pla24M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (pla[24])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[24])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (pla[24])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[24])&(M2&T3);
fMRead = fMRead | (pla[24])&(M3&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[24])&(M3&T1);
ctl_reg_sys_hilo_pla24M3T1_3 = (pla[24])&(M3&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla24M3T1_3,ctl_reg_sys_hilo_pla24M3T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[24])&(M3&T1);
fMRead = fMRead | (pla[24])&(M3&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[24])&(M3&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[24])&(M3&T2);
ctl_reg_sys_hilo_pla24M3T2_4 = (pla[24])&(M3&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla24M3T2_4,ctl_reg_sys_hilo_pla24M3T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[24])&(M3&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[24])&(M3&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[24])&(M3&T2);
fMRead = fMRead | (pla[24])&(M3&T3);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[24])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[24])&(M3&T3);
ctl_reg_sys_hilo_pla24M3T3_4 = (pla[24])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla24M3T3_4,ctl_reg_sys_hilo_pla24M3T3_4})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[24])&(M3&T3);
ctl_sw_2d = ctl_sw_2d | (pla[24])&(M3&T3);
ctl_sw_1d = ctl_sw_1d | (pla[24])&(M3&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[24])&(M3&T3);
nextM = nextM | (pla[24])&(M3&T4);
ctl_mWrite = ctl_mWrite | (pla[24])&(M3&T4);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[24])&(M3&T4);
ctl_reg_gp_sel_pla24M3T4_4 = (pla[24])&(M3&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla24M3T4_4,ctl_reg_gp_sel_pla24M3T4_4})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla24M3T4_5 = (pla[24])&(M3&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla24M3T4_5,ctl_reg_gp_hilo_pla24M3T4_5})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[24])&(M3&T4);
ctl_inc_cy = ctl_inc_cy | (pla[24])&(M3&T4)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[24])&(M3&T4);
ctl_al_we = ctl_al_we | (pla[24])&(M3&T4);
fMWrite = fMWrite | (pla[24])&(M4&T1);
ctl_inc_cy = ctl_inc_cy | (pla[24])&(M4&T1)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[24])&(M4&T1);
ctl_apin_mux = ctl_apin_mux | (pla[24])&(M4&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[24])&(M4&T1);
ctl_reg_sys_hilo_pla24M4T1_6 = (pla[24])&(M4&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla24M4T1_6,ctl_reg_sys_hilo_pla24M4T1_6})&(2'b10);
ctl_sw_4u = ctl_sw_4u | (pla[24])&(M4&T1);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[24])&(M4&T1);
ctl_sw_2u = ctl_sw_2u | (pla[24])&(M4&T1);
ctl_sw_1u = ctl_sw_1u | (pla[24])&(M4&T1);
ctl_bus_db_we = ctl_bus_db_we | (pla[24])&(M4&T1);
fMWrite = fMWrite | (pla[24])&(M4&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[24])&(M4&T2);
ctl_reg_gp_sel_pla24M4T2_3 = (pla[24])&(M4&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla24M4T2_3,ctl_reg_gp_sel_pla24M4T2_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla24M4T2_4 = (pla[24])&(M4&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla24M4T2_4,ctl_reg_gp_hilo_pla24M4T2_4})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[24])&(M4&T2);
ctl_sw_4u = ctl_sw_4u | (pla[24])&(M4&T2);
ctl_inc_cy = ctl_inc_cy | (pla[24])&(M4&T2)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[24])&(M4&T2);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[24])&(M4&T2);
fMWrite = fMWrite | (pla[24])&(M4&T3);
nextM = nextM | (pla[24])&(M4&T3);
ctl_mWrite = ctl_mWrite | (pla[24])&(M4&T3);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[24])&(M4&T3);
ctl_reg_gp_sel_pla24M4T3_5 = (pla[24])&(M4&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla24M4T3_5,ctl_reg_gp_sel_pla24M4T3_5})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla24M4T3_6 = (pla[24])&(M4&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla24M4T3_6,ctl_reg_gp_hilo_pla24M4T3_6})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[24])&(M4&T3);
ctl_inc_cy = ctl_inc_cy | (pla[24])&(M4&T3)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[24])&(M4&T3);
ctl_al_we = ctl_al_we | (pla[24])&(M4&T3);
fMWrite = fMWrite | (pla[24])&(M5&T1);
ctl_inc_cy = ctl_inc_cy | (pla[24])&(M5&T1)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[24])&(M5&T1);
ctl_apin_mux = ctl_apin_mux | (pla[24])&(M5&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[24])&(M5&T1);
ctl_reg_sys_hilo_pla24M5T1_6 = (pla[24])&(M5&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla24M5T1_6,ctl_reg_sys_hilo_pla24M5T1_6})&(2'b01);
ctl_sw_4u = ctl_sw_4u | (pla[24])&(M5&T1);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[24])&(M5&T1);
ctl_sw_1u = ctl_sw_1u | (pla[24])&(M5&T1);
ctl_bus_db_we = ctl_bus_db_we | (pla[24])&(M5&T1);
fMWrite = fMWrite | (pla[24])&(M5&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[24])&(M5&T2);
ctl_reg_gp_sel_pla24M5T2_3 = (pla[24])&(M5&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla24M5T2_3,ctl_reg_gp_sel_pla24M5T2_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla24M5T2_4 = (pla[24])&(M5&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla24M5T2_4,ctl_reg_gp_hilo_pla24M5T2_4})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[24])&(M5&T2);
ctl_sw_4u = ctl_sw_4u | (pla[24])&(M5&T2);
ctl_inc_cy = ctl_inc_cy | (pla[24])&(M5&T2)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[24])&(M5&T2);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[24])&(M5&T2);
fMWrite = fMWrite | (pla[24])&(M5&T3);
setM1 = setM1 | (pla[24])&(M5&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[24])&(M5&T3);
ctl_reg_sys_hilo_pla24M5T3_4 = (pla[24])&(M5&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla24M5T3_4,ctl_reg_sys_hilo_pla24M5T3_4})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[24])&(M5&T3);
ctl_al_we = ctl_al_we | (pla[24])&(M5&T3);
ctl_reg_not_pc = ctl_reg_not_pc | (pla[24])&(M5&T3);
ctl_reg_gp_sel_pla42M1T3_1 = (pla[42])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla42M1T3_1,ctl_reg_gp_sel_pla42M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla42M1T3_2 = (pla[42])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla42M1T3_2,ctl_reg_gp_hilo_pla42M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[42])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[42])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[42])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[42])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[42])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[42])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[42])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[42])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[42])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[42])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[42])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[42])&(M1&T3);
validPLA = validPLA | (pla[42])&(M1&T4);
nextM = nextM | (pla[42])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[42])&(M1&T4);
fMRead = fMRead | (pla[42])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[42])&(M2&T1);
ctl_reg_sys_hilo_pla42M2T1_3 = (pla[42])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla42M2T1_3,ctl_reg_sys_hilo_pla42M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[42])&(M2&T1);
fMRead = fMRead | (pla[42])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[42])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[42])&(M2&T2);
ctl_reg_sys_hilo_pla42M2T2_4 = (pla[42])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla42M2T2_4,ctl_reg_sys_hilo_pla42M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[42])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[42])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[42])&(M2&T2);
fMRead = fMRead | (pla[42])&(M2&T3);
nextM = nextM | (pla[42])&(M2&T3);
ctl_mRead = ctl_mRead | (pla[42])&(M2&T3);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[42])&(M2&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[42])&(M2&T3);
ctl_reg_sys_hilo_pla42M2T3_6 = (pla[42])&(M2&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla42M2T3_6,ctl_reg_sys_hilo_pla42M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (pla[42])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[42])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (pla[42])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[42])&(M2&T3);
fMRead = fMRead | (pla[42])&(M3&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[42])&(M3&T1);
ctl_reg_sys_hilo_pla42M3T1_3 = (pla[42])&(M3&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla42M3T1_3,ctl_reg_sys_hilo_pla42M3T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[42])&(M3&T1);
fMRead = fMRead | (pla[42])&(M3&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[42])&(M3&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[42])&(M3&T2);
ctl_reg_sys_hilo_pla42M3T2_4 = (pla[42])&(M3&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla42M3T2_4,ctl_reg_sys_hilo_pla42M3T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[42])&(M3&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[42])&(M3&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[42])&(M3&T2);
fMRead = fMRead | (pla[42])&(M3&T3);
nextM = nextM | (pla[42])&(M3&T3)&(~flags_cond_true);
setM1 = setM1 | (pla[42])&(M3&T3)&(~flags_cond_true);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[42])&(M3&T3)&(flags_cond_true);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[42])&(M3&T3)&(flags_cond_true);
ctl_reg_sys_hilo_pla42M3T3_6 = (pla[42])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla42M3T3_6,ctl_reg_sys_hilo_pla42M3T3_6})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[42])&(M3&T3);
ctl_sw_2d = ctl_sw_2d | (pla[42])&(M3&T3);
ctl_sw_1d = ctl_sw_1d | (pla[42])&(M3&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[42])&(M3&T3);
nextM = nextM | (pla[42])&(M3&T4);
ctl_mWrite = ctl_mWrite | (pla[42])&(M3&T4);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[42])&(M3&T4);
ctl_reg_gp_sel_pla42M3T4_4 = (pla[42])&(M3&T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla42M3T4_4,ctl_reg_gp_sel_pla42M3T4_4})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla42M3T4_5 = (pla[42])&(M3&T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla42M3T4_5,ctl_reg_gp_hilo_pla42M3T4_5})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[42])&(M3&T4);
ctl_inc_cy = ctl_inc_cy | (pla[42])&(M3&T4)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[42])&(M3&T4);
ctl_al_we = ctl_al_we | (pla[42])&(M3&T4);
fMWrite = fMWrite | (pla[42])&(M4&T1);
ctl_inc_cy = ctl_inc_cy | (pla[42])&(M4&T1)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[42])&(M4&T1);
ctl_apin_mux = ctl_apin_mux | (pla[42])&(M4&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[42])&(M4&T1);
ctl_reg_sys_hilo_pla42M4T1_6 = (pla[42])&(M4&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla42M4T1_6,ctl_reg_sys_hilo_pla42M4T1_6})&(2'b10);
ctl_sw_4u = ctl_sw_4u | (pla[42])&(M4&T1);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[42])&(M4&T1);
ctl_sw_2u = ctl_sw_2u | (pla[42])&(M4&T1);
ctl_sw_1u = ctl_sw_1u | (pla[42])&(M4&T1);
ctl_bus_db_we = ctl_bus_db_we | (pla[42])&(M4&T1);
fMWrite = fMWrite | (pla[42])&(M4&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[42])&(M4&T2);
ctl_reg_gp_sel_pla42M4T2_3 = (pla[42])&(M4&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla42M4T2_3,ctl_reg_gp_sel_pla42M4T2_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla42M4T2_4 = (pla[42])&(M4&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla42M4T2_4,ctl_reg_gp_hilo_pla42M4T2_4})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[42])&(M4&T2);
ctl_sw_4u = ctl_sw_4u | (pla[42])&(M4&T2);
ctl_inc_cy = ctl_inc_cy | (pla[42])&(M4&T2)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[42])&(M4&T2);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[42])&(M4&T2);
fMWrite = fMWrite | (pla[42])&(M4&T3);
nextM = nextM | (pla[42])&(M4&T3);
ctl_mWrite = ctl_mWrite | (pla[42])&(M4&T3);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[42])&(M4&T3);
ctl_reg_gp_sel_pla42M4T3_5 = (pla[42])&(M4&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla42M4T3_5,ctl_reg_gp_sel_pla42M4T3_5})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla42M4T3_6 = (pla[42])&(M4&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla42M4T3_6,ctl_reg_gp_hilo_pla42M4T3_6})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[42])&(M4&T3);
ctl_inc_cy = ctl_inc_cy | (pla[42])&(M4&T3)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[42])&(M4&T3);
ctl_al_we = ctl_al_we | (pla[42])&(M4&T3);
fMWrite = fMWrite | (pla[42])&(M5&T1);
ctl_inc_cy = ctl_inc_cy | (pla[42])&(M5&T1)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[42])&(M5&T1);
ctl_apin_mux = ctl_apin_mux | (pla[42])&(M5&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[42])&(M5&T1);
ctl_reg_sys_hilo_pla42M5T1_6 = (pla[42])&(M5&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla42M5T1_6,ctl_reg_sys_hilo_pla42M5T1_6})&(2'b01);
ctl_sw_4u = ctl_sw_4u | (pla[42])&(M5&T1);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[42])&(M5&T1);
ctl_sw_1u = ctl_sw_1u | (pla[42])&(M5&T1);
ctl_bus_db_we = ctl_bus_db_we | (pla[42])&(M5&T1);
fMWrite = fMWrite | (pla[42])&(M5&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[42])&(M5&T2);
ctl_reg_gp_sel_pla42M5T2_3 = (pla[42])&(M5&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla42M5T2_3,ctl_reg_gp_sel_pla42M5T2_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla42M5T2_4 = (pla[42])&(M5&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla42M5T2_4,ctl_reg_gp_hilo_pla42M5T2_4})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[42])&(M5&T2);
ctl_sw_4u = ctl_sw_4u | (pla[42])&(M5&T2);
ctl_inc_cy = ctl_inc_cy | (pla[42])&(M5&T2)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[42])&(M5&T2);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[42])&(M5&T2);
fMWrite = fMWrite | (pla[42])&(M5&T3);
setM1 = setM1 | (pla[42])&(M5&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[42])&(M5&T3);
ctl_reg_sys_hilo_pla42M5T3_4 = (pla[42])&(M5&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla42M5T3_4,ctl_reg_sys_hilo_pla42M5T3_4})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[42])&(M5&T3);
ctl_al_we = ctl_al_we | (pla[42])&(M5&T3);
ctl_reg_not_pc = ctl_reg_not_pc | (pla[42])&(M5&T3);
validPLA = validPLA | (pla[35])&(M1&T4);
nextM = nextM | (pla[35])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[35])&(M1&T4);
fMRead = fMRead | (pla[35])&(M2&T1);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[35])&(M2&T1);
ctl_reg_gp_sel_pla35M2T1_3 = (pla[35])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla35M2T1_3,ctl_reg_gp_sel_pla35M2T1_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla35M2T1_4 = (pla[35])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla35M2T1_4,ctl_reg_gp_hilo_pla35M2T1_4})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[35])&(M2&T1);
ctl_al_we = ctl_al_we | (pla[35])&(M2&T1);
fMRead = fMRead | (pla[35])&(M2&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[35])&(M2&T2);
ctl_reg_gp_sel_pla35M2T2_3 = (pla[35])&(M2&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla35M2T2_3,ctl_reg_gp_sel_pla35M2T2_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla35M2T2_4 = (pla[35])&(M2&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla35M2T2_4,ctl_reg_gp_hilo_pla35M2T2_4})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[35])&(M2&T2);
ctl_sw_4u = ctl_sw_4u | (pla[35])&(M2&T2);
ctl_inc_cy = ctl_inc_cy | (pla[35])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[35])&(M2&T2);
fMRead = fMRead | (pla[35])&(M2&T3);
nextM = nextM | (pla[35])&(M2&T3);
ctl_mRead = ctl_mRead | (pla[35])&(M2&T3);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[35])&(M2&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[35])&(M2&T3);
ctl_reg_sys_hilo_pla35M2T3_6 = (pla[35])&(M2&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla35M2T3_6,ctl_reg_sys_hilo_pla35M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (pla[35])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[35])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (pla[35])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[35])&(M2&T3);
fMRead = fMRead | (pla[35])&(M3&T1);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[35])&(M3&T1);
ctl_reg_gp_sel_pla35M3T1_3 = (pla[35])&(M3&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla35M3T1_3,ctl_reg_gp_sel_pla35M3T1_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla35M3T1_4 = (pla[35])&(M3&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla35M3T1_4,ctl_reg_gp_hilo_pla35M3T1_4})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[35])&(M3&T1);
ctl_al_we = ctl_al_we | (pla[35])&(M3&T1);
fMRead = fMRead | (pla[35])&(M3&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[35])&(M3&T2);
ctl_reg_gp_sel_pla35M3T2_3 = (pla[35])&(M3&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla35M3T2_3,ctl_reg_gp_sel_pla35M3T2_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla35M3T2_4 = (pla[35])&(M3&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla35M3T2_4,ctl_reg_gp_hilo_pla35M3T2_4})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[35])&(M3&T2);
ctl_sw_4u = ctl_sw_4u | (pla[35])&(M3&T2);
ctl_inc_cy = ctl_inc_cy | (pla[35])&(M3&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[35])&(M3&T2);
fMRead = fMRead | (pla[35])&(M3&T3);
setM1 = setM1 | (pla[35])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[35])&(M3&T3);
ctl_reg_sys_hilo_pla35M3T3_4 = (pla[35])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla35M3T3_4,ctl_reg_sys_hilo_pla35M3T3_4})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[35])&(M3&T3);
ctl_al_we = ctl_al_we | (pla[35])&(M3&T3);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[35])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[35])&(M3&T3);
ctl_reg_sys_hilo_pla35M3T3_9 = (pla[35])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla35M3T3_9,ctl_reg_sys_hilo_pla35M3T3_9})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[35])&(M3&T3);
ctl_sw_2d = ctl_sw_2d | (pla[35])&(M3&T3);
ctl_sw_1d = ctl_sw_1d | (pla[35])&(M3&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[35])&(M3&T3);
ctl_reg_not_pc = ctl_reg_not_pc | (pla[35])&(M3&T3);
ctl_reg_gp_sel_pla45M1T3_1 = (pla[45])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla45M1T3_1,ctl_reg_gp_sel_pla45M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla45M1T3_2 = (pla[45])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla45M1T3_2,ctl_reg_gp_hilo_pla45M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[45])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[45])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[45])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[45])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[45])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[45])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[45])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[45])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[45])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[45])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[45])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[45])&(M1&T3);
validPLA = validPLA | (pla[45])&(M1&T4);
nextM = nextM | (pla[45])&(M1&T5);
ctl_mRead = ctl_mRead | (pla[45])&(M1&T5);
setM1 = setM1 | (pla[45])&(M1&T5)&(~flags_cond_true);
fMRead = fMRead | (pla[45])&(M2&T1);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[45])&(M2&T1);
ctl_reg_gp_sel_pla45M2T1_3 = (pla[45])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla45M2T1_3,ctl_reg_gp_sel_pla45M2T1_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla45M2T1_4 = (pla[45])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla45M2T1_4,ctl_reg_gp_hilo_pla45M2T1_4})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[45])&(M2&T1);
ctl_al_we = ctl_al_we | (pla[45])&(M2&T1);
fMRead = fMRead | (pla[45])&(M2&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[45])&(M2&T2);
ctl_reg_gp_sel_pla45M2T2_3 = (pla[45])&(M2&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla45M2T2_3,ctl_reg_gp_sel_pla45M2T2_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla45M2T2_4 = (pla[45])&(M2&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla45M2T2_4,ctl_reg_gp_hilo_pla45M2T2_4})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[45])&(M2&T2);
ctl_sw_4u = ctl_sw_4u | (pla[45])&(M2&T2);
ctl_inc_cy = ctl_inc_cy | (pla[45])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[45])&(M2&T2);
fMRead = fMRead | (pla[45])&(M2&T3);
nextM = nextM | (pla[45])&(M2&T3);
ctl_mRead = ctl_mRead | (pla[45])&(M2&T3);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[45])&(M2&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[45])&(M2&T3);
ctl_reg_sys_hilo_pla45M2T3_6 = (pla[45])&(M2&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla45M2T3_6,ctl_reg_sys_hilo_pla45M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (pla[45])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[45])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (pla[45])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[45])&(M2&T3);
fMRead = fMRead | (pla[45])&(M3&T1);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[45])&(M3&T1);
ctl_reg_gp_sel_pla45M3T1_3 = (pla[45])&(M3&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla45M3T1_3,ctl_reg_gp_sel_pla45M3T1_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla45M3T1_4 = (pla[45])&(M3&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla45M3T1_4,ctl_reg_gp_hilo_pla45M3T1_4})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[45])&(M3&T1);
ctl_al_we = ctl_al_we | (pla[45])&(M3&T1);
fMRead = fMRead | (pla[45])&(M3&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[45])&(M3&T2);
ctl_reg_gp_sel_pla45M3T2_3 = (pla[45])&(M3&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla45M3T2_3,ctl_reg_gp_sel_pla45M3T2_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla45M3T2_4 = (pla[45])&(M3&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla45M3T2_4,ctl_reg_gp_hilo_pla45M3T2_4})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[45])&(M3&T2);
ctl_sw_4u = ctl_sw_4u | (pla[45])&(M3&T2);
ctl_inc_cy = ctl_inc_cy | (pla[45])&(M3&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[45])&(M3&T2);
fMRead = fMRead | (pla[45])&(M3&T3);
setM1 = setM1 | (pla[45])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[45])&(M3&T3);
ctl_reg_sys_hilo_pla45M3T3_4 = (pla[45])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla45M3T3_4,ctl_reg_sys_hilo_pla45M3T3_4})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[45])&(M3&T3);
ctl_al_we = ctl_al_we | (pla[45])&(M3&T3);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[45])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[45])&(M3&T3);
ctl_reg_sys_hilo_pla45M3T3_9 = (pla[45])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla45M3T3_9,ctl_reg_sys_hilo_pla45M3T3_9})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[45])&(M3&T3);
ctl_sw_2d = ctl_sw_2d | (pla[45])&(M3&T3);
ctl_sw_1d = ctl_sw_1d | (pla[45])&(M3&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[45])&(M3&T3);
ctl_reg_not_pc = ctl_reg_not_pc | (pla[45])&(M3&T3);
validPLA = validPLA | (pla[46])&(M1&T4);
nextM = nextM | (pla[46])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[46])&(M1&T4);
ctl_iff1_iff2 = ctl_iff1_iff2 | (pla[46])&(M1&T4);
fMRead = fMRead | (pla[46])&(M2&T1);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[46])&(M2&T1);
ctl_reg_gp_sel_pla46M2T1_3 = (pla[46])&(M2&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla46M2T1_3,ctl_reg_gp_sel_pla46M2T1_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla46M2T1_4 = (pla[46])&(M2&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla46M2T1_4,ctl_reg_gp_hilo_pla46M2T1_4})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[46])&(M2&T1);
ctl_al_we = ctl_al_we | (pla[46])&(M2&T1);
fMRead = fMRead | (pla[46])&(M2&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[46])&(M2&T2);
ctl_reg_gp_sel_pla46M2T2_3 = (pla[46])&(M2&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla46M2T2_3,ctl_reg_gp_sel_pla46M2T2_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla46M2T2_4 = (pla[46])&(M2&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla46M2T2_4,ctl_reg_gp_hilo_pla46M2T2_4})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[46])&(M2&T2);
ctl_sw_4u = ctl_sw_4u | (pla[46])&(M2&T2);
ctl_inc_cy = ctl_inc_cy | (pla[46])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[46])&(M2&T2);
fMRead = fMRead | (pla[46])&(M2&T3);
nextM = nextM | (pla[46])&(M2&T3);
ctl_mRead = ctl_mRead | (pla[46])&(M2&T3);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[46])&(M2&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[46])&(M2&T3);
ctl_reg_sys_hilo_pla46M2T3_6 = (pla[46])&(M2&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla46M2T3_6,ctl_reg_sys_hilo_pla46M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (pla[46])&(M2&T3);
ctl_sw_2d = ctl_sw_2d | (pla[46])&(M2&T3);
ctl_sw_1d = ctl_sw_1d | (pla[46])&(M2&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[46])&(M2&T3);
fMRead = fMRead | (pla[46])&(M3&T1);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[46])&(M3&T1);
ctl_reg_gp_sel_pla46M3T1_3 = (pla[46])&(M3&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla46M3T1_3,ctl_reg_gp_sel_pla46M3T1_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla46M3T1_4 = (pla[46])&(M3&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla46M3T1_4,ctl_reg_gp_hilo_pla46M3T1_4})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[46])&(M3&T1);
ctl_al_we = ctl_al_we | (pla[46])&(M3&T1);
fMRead = fMRead | (pla[46])&(M3&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[46])&(M3&T2);
ctl_reg_gp_sel_pla46M3T2_3 = (pla[46])&(M3&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla46M3T2_3,ctl_reg_gp_sel_pla46M3T2_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla46M3T2_4 = (pla[46])&(M3&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla46M3T2_4,ctl_reg_gp_hilo_pla46M3T2_4})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[46])&(M3&T2);
ctl_sw_4u = ctl_sw_4u | (pla[46])&(M3&T2);
ctl_inc_cy = ctl_inc_cy | (pla[46])&(M3&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[46])&(M3&T2);
fMRead = fMRead | (pla[46])&(M3&T3);
setM1 = setM1 | (pla[46])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[46])&(M3&T3);
ctl_reg_sys_hilo_pla46M3T3_4 = (pla[46])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla46M3T3_4,ctl_reg_sys_hilo_pla46M3T3_4})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[46])&(M3&T3);
ctl_al_we = ctl_al_we | (pla[46])&(M3&T3);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[46])&(M3&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[46])&(M3&T3);
ctl_reg_sys_hilo_pla46M3T3_9 = (pla[46])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla46M3T3_9,ctl_reg_sys_hilo_pla46M3T3_9})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[46])&(M3&T3);
ctl_sw_2d = ctl_sw_2d | (pla[46])&(M3&T3);
ctl_sw_1d = ctl_sw_1d | (pla[46])&(M3&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[46])&(M3&T3);
ctl_reg_not_pc = ctl_reg_not_pc | (pla[46])&(M3&T3);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[56])&(M1&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[56])&(M1&T3);
ctl_reg_sys_hilo_pla56M1T3_3 = (pla[56])&(M1&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla56M1T3_3,ctl_reg_sys_hilo_pla56M1T3_3})&(2'b11);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[56])&(M1&T3);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[56])&(M1&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[56])&(M1&T3);
ctl_alu_oe = ctl_alu_oe | (pla[56])&(M1&T3);
ctl_alu_op1_oe = ctl_alu_op1_oe | (pla[56])&(M1&T3);
ctl_alu_op1_sel_zero = ctl_alu_op1_sel_zero | (pla[56])&(M1&T3);
ctl_sw_mask543_en = ctl_sw_mask543_en | (pla[56])&(M1&T3)&(~((in_intr&im2)|in_nmi));
ctl_sw_1d = ctl_sw_1d | (pla[56])&(M1&T3)&(~in_nmi);
ctl_66_oe = ctl_66_oe | (pla[56])&(M1&T3)&(in_nmi);
ctl_bus_ff_oe = ctl_bus_ff_oe | (pla[56])&(M1&T3)&(in_intr&im1);
validPLA = validPLA | (pla[56])&(M1&T4);
nextM = nextM | (pla[56])&(M1&T5);
ctl_mWrite = ctl_mWrite | (pla[56])&(M1&T5);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[56])&(M1&T5);
ctl_reg_gp_sel_pla56M1T5_4 = (pla[56])&(M1&T5);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla56M1T5_4,ctl_reg_gp_sel_pla56M1T5_4})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla56M1T5_5 = (pla[56])&(M1&T5);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla56M1T5_5,ctl_reg_gp_hilo_pla56M1T5_5})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[56])&(M1&T5);
ctl_inc_cy = ctl_inc_cy | (pla[56])&(M1&T5)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[56])&(M1&T5);
ctl_al_we = ctl_al_we | (pla[56])&(M1&T5);
ctl_sw_2d = ctl_sw_2d | (pla[56])&(M1&T5);
ctl_sw_1d = ctl_sw_1d | (pla[56])&(M1&T5);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[56])&(M1&T5);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[56])&(M1&T5)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[56])&(M1&T5);
fMWrite = fMWrite | (pla[56])&(M2&T1);
ctl_inc_cy = ctl_inc_cy | (pla[56])&(M2&T1)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[56])&(M2&T1);
ctl_apin_mux = ctl_apin_mux | (pla[56])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[56])&(M2&T1);
ctl_reg_sys_hilo_pla56M2T1_6 = (pla[56])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla56M2T1_6,ctl_reg_sys_hilo_pla56M2T1_6})&(2'b10);
ctl_sw_4u = ctl_sw_4u | (pla[56])&(M2&T1);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[56])&(M2&T1);
ctl_sw_2u = ctl_sw_2u | (pla[56])&(M2&T1);
ctl_sw_1u = ctl_sw_1u | (pla[56])&(M2&T1);
ctl_bus_db_we = ctl_bus_db_we | (pla[56])&(M2&T1);
fMWrite = fMWrite | (pla[56])&(M2&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[56])&(M2&T2);
ctl_reg_gp_sel_pla56M2T2_3 = (pla[56])&(M2&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla56M2T2_3,ctl_reg_gp_sel_pla56M2T2_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla56M2T2_4 = (pla[56])&(M2&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla56M2T2_4,ctl_reg_gp_hilo_pla56M2T2_4})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[56])&(M2&T2);
ctl_sw_4u = ctl_sw_4u | (pla[56])&(M2&T2);
ctl_inc_cy = ctl_inc_cy | (pla[56])&(M2&T2)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[56])&(M2&T2);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[56])&(M2&T2);
fMWrite = fMWrite | (pla[56])&(M2&T3);
nextM = nextM | (pla[56])&(M2&T3);
ctl_mWrite = ctl_mWrite | (pla[56])&(M2&T3);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[56])&(M2&T3);
ctl_reg_gp_sel_pla56M2T3_5 = (pla[56])&(M2&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla56M2T3_5,ctl_reg_gp_sel_pla56M2T3_5})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla56M2T3_6 = (pla[56])&(M2&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla56M2T3_6,ctl_reg_gp_hilo_pla56M2T3_6})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[56])&(M2&T3);
ctl_inc_cy = ctl_inc_cy | (pla[56])&(M2&T3)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[56])&(M2&T3);
ctl_al_we = ctl_al_we | (pla[56])&(M2&T3);
fMWrite = fMWrite | (pla[56])&(M3&T1);
ctl_inc_cy = ctl_inc_cy | (pla[56])&(M3&T1)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[56])&(M3&T1);
ctl_apin_mux = ctl_apin_mux | (pla[56])&(M3&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[56])&(M3&T1);
ctl_reg_sys_hilo_pla56M3T1_6 = (pla[56])&(M3&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla56M3T1_6,ctl_reg_sys_hilo_pla56M3T1_6})&(2'b01);
ctl_sw_4u = ctl_sw_4u | (pla[56])&(M3&T1);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[56])&(M3&T1);
ctl_sw_1u = ctl_sw_1u | (pla[56])&(M3&T1);
ctl_bus_db_we = ctl_bus_db_we | (pla[56])&(M3&T1);
fMWrite = fMWrite | (pla[56])&(M3&T2);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[56])&(M3&T2);
ctl_reg_gp_sel_pla56M3T2_3 = (pla[56])&(M3&T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla56M3T2_3,ctl_reg_gp_sel_pla56M3T2_3})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla56M3T2_4 = (pla[56])&(M3&T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla56M3T2_4,ctl_reg_gp_hilo_pla56M3T2_4})&(2'b11);
ctl_reg_use_sp = ctl_reg_use_sp | (pla[56])&(M3&T2);
ctl_sw_4u = ctl_sw_4u | (pla[56])&(M3&T2);
ctl_inc_cy = ctl_inc_cy | (pla[56])&(M3&T2)&(~pc_inc_hold);
ctl_inc_dec = ctl_inc_dec | (pla[56])&(M3&T2);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[56])&(M3&T2);
fMWrite = fMWrite | (pla[56])&(M3&T3);
nextM = nextM | (pla[56])&(M3&T3);
ctl_mRead = ctl_mRead | (pla[56])&(M3&T3)&(in_intr&im2);
setM1 = setM1 | (pla[56])&(M3&T3)&(~(in_intr&im2));
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[56])&(M3&T3);
ctl_reg_sys_hilo_pla56M3T3_6 = (pla[56])&(M3&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla56M3T3_6,ctl_reg_sys_hilo_pla56M3T3_6})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[56])&(M3&T3);
ctl_al_we = ctl_al_we | (pla[56])&(M3&T3);
ctl_reg_not_pc = ctl_reg_not_pc | (pla[56])&(M3&T3);
fMRead = fMRead | (pla[56])&(M4&T1);
ctl_reg_sel_ir = ctl_reg_sel_ir | (pla[56])&(M4&T1);
ctl_reg_sys_hilo_pla56M4T1_3 = (pla[56])&(M4&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla56M4T1_3,ctl_reg_sys_hilo_pla56M4T1_3})&(2'b10);
ctl_sw_4d = ctl_sw_4d | (pla[56])&(M4&T1);
ctl_al_we = ctl_al_we | (pla[56])&(M4&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[56])&(M4&T1);
ctl_sw_2u = ctl_sw_2u | (pla[56])&(M4&T1);
ctl_alu_oe = ctl_alu_oe | (pla[56])&(M4&T1);
ctl_alu_op1_oe = ctl_alu_op1_oe | (pla[56])&(M4&T1);
fMRead = fMRead | (pla[56])&(M4&T2);
ctl_sw_4u = ctl_sw_4u | (pla[56])&(M4&T2);
ctl_inc_cy = ctl_inc_cy | (pla[56])&(M4&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[56])&(M4&T2);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[56])&(M4&T2);
ctl_sw_2d = ctl_sw_2d | (pla[56])&(M4&T2);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[56])&(M4&T2)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[56])&(M4&T2);
fMRead = fMRead | (pla[56])&(M4&T3);
nextM = nextM | (pla[56])&(M4&T3);
ctl_mRead = ctl_mRead | (pla[56])&(M4&T3);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[56])&(M4&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[56])&(M4&T3);
ctl_reg_sys_hilo_pla56M4T3_6 = (pla[56])&(M4&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla56M4T3_6,ctl_reg_sys_hilo_pla56M4T3_6})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (pla[56])&(M4&T3);
ctl_sw_2d = ctl_sw_2d | (pla[56])&(M4&T3);
ctl_sw_1d = ctl_sw_1d | (pla[56])&(M4&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[56])&(M4&T3);
fMRead = fMRead | (pla[56])&(M5&T1);
ctl_reg_sel_ir = ctl_reg_sel_ir | (pla[56])&(M5&T1);
ctl_reg_sys_hilo_pla56M5T1_3 = (pla[56])&(M5&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla56M5T1_3,ctl_reg_sys_hilo_pla56M5T1_3})&(2'b10);
ctl_sw_4d = ctl_sw_4d | (pla[56])&(M5&T1);
ctl_al_we = ctl_al_we | (pla[56])&(M5&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[56])&(M5&T1);
ctl_sw_2u = ctl_sw_2u | (pla[56])&(M5&T1);
ctl_alu_oe = ctl_alu_oe | (pla[56])&(M5&T1);
ctl_alu_op1_oe = ctl_alu_op1_oe | (pla[56])&(M5&T1);
fMRead = fMRead | (pla[56])&(M5&T2);
ctl_inc_cy = ctl_inc_cy | (pla[56])&(M5&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[56])&(M5&T2);
fMRead = fMRead | (pla[56])&(M5&T3);
setM1 = setM1 | (pla[56])&(M5&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[56])&(M5&T3);
ctl_reg_sys_hilo_pla56M5T3_4 = (pla[56])&(M5&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla56M5T3_4,ctl_reg_sys_hilo_pla56M5T3_4})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (pla[56])&(M5&T3);
ctl_al_we = ctl_al_we | (pla[56])&(M5&T3);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[56])&(M5&T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (pla[56])&(M5&T3);
ctl_reg_sys_hilo_pla56M5T3_9 = (pla[56])&(M5&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla56M5T3_9,ctl_reg_sys_hilo_pla56M5T3_9})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (pla[56])&(M5&T3);
ctl_sw_2d = ctl_sw_2d | (pla[56])&(M5&T3);
ctl_sw_1d = ctl_sw_1d | (pla[56])&(M5&T3);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[56])&(M5&T3);
ctl_reg_not_pc = ctl_reg_not_pc | (pla[56])&(M5&T3);
ctl_reg_gp_sel_pla49M1T3_1 = (pla[49])&(M1&T3);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla49M1T3_1,ctl_reg_gp_sel_pla49M1T3_1})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla49M1T3_2 = (pla[49])&(M1&T3);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla49M1T3_2,ctl_reg_gp_hilo_pla49M1T3_2})&(2'b11);
ctl_reg_out_hi = ctl_reg_out_hi | (pla[49])&(M1&T3);
ctl_reg_out_lo = ctl_reg_out_lo | (pla[49])&(M1&T3);
ctl_flags_bus = ctl_flags_bus | (pla[49])&(M1&T3);
ctl_alu_shift_oe = ctl_alu_shift_oe | (pla[49])&(M1&T3)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[49])&(M1&T3);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[49])&(M1&T3);
ctl_flags_sz_we = ctl_flags_sz_we | (pla[49])&(M1&T3);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[49])&(M1&T3);
ctl_flags_hf_we = ctl_flags_hf_we | (pla[49])&(M1&T3);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[49])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[49])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[49])&(M1&T3);
ctl_state_tbl_cb_set = ctl_state_tbl_cb_set | (pla[49])&(M1&T3);
setCBED = setCBED | (pla[49])&(M1&T3);
validPLA = validPLA | (pla[49])&(M1&T4);
nextM = nextM | (pla[49])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[49])&(M1&T4);
fMRead = fMRead | (pla[49])&(M2&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[49])&(M2&T1);
ctl_reg_sys_hilo_pla49M2T1_3 = (pla[49])&(M2&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla49M2T1_3,ctl_reg_sys_hilo_pla49M2T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[49])&(M2&T1);
fMRead = fMRead | (pla[49])&(M2&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[49])&(M2&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[49])&(M2&T2);
ctl_reg_sys_hilo_pla49M2T2_4 = (pla[49])&(M2&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla49M2T2_4,ctl_reg_sys_hilo_pla49M2T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[49])&(M2&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[49])&(M2&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[49])&(M2&T2);
fMRead = fMRead | (pla[49])&(M2&T3);
nextM = nextM | (pla[49])&(M2&T3);
ctl_mRead = ctl_mRead | (pla[49])&(M2&T3);
fMRead = fMRead | (pla[49])&(M3&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[49])&(M3&T1);
ctl_reg_sys_hilo_pla49M3T1_3 = (pla[49])&(M3&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla49M3T1_3,ctl_reg_sys_hilo_pla49M3T1_3})&(2'b11);
ctl_al_we = ctl_al_we | (pla[49])&(M3&T1);
ixy_d = ixy_d | (pla[49])&(M3&T1);
fMRead = fMRead | (pla[49])&(M3&T2);
ctl_reg_sys_we = ctl_reg_sys_we | (pla[49])&(M3&T2);
ctl_reg_sel_pc = ctl_reg_sel_pc | (pla[49])&(M3&T2);
ctl_reg_sys_hilo_pla49M3T2_4 = (pla[49])&(M3&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla49M3T2_4,ctl_reg_sys_hilo_pla49M3T2_4})&(2'b11);
pc_inc_hold = pc_inc_hold | (pla[49])&(M3&T2)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (pla[49])&(M3&T2)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (pla[49])&(M3&T2);
ixy_d = ixy_d | (pla[49])&(M3&T2);
fMRead = fMRead | (pla[49])&(M3&T3);
ixy_d = ixy_d | (pla[49])&(M3&T3);
ixy_d = ixy_d | (pla[49])&(M3&T4);
nextM = nextM | (pla[49])&(M3&T5);
ctl_mRead = ctl_mRead | (pla[49])&(M3&T5);
ixy_d = ixy_d | (pla[49])&(M3&T5);
ctl_bus_db_oe = ctl_bus_db_oe | (pla[49])&(M4&T1);
ctl_alu_bs_oe = ctl_alu_bs_oe | (pla[49])&(M4&T1);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[49])&(M4&T1);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[49])&(M4&T1);
ctl_ir_we = ctl_ir_we | (pla[49])&(M4&T1);
ctl_state_ixiy_we = ctl_state_ixiy_we | (pla[3])&(M1&T2);
ctl_state_iy_set = ctl_state_iy_set | (pla[3])&(M1&T2)&(op5);
setIXIY = setIXIY | (pla[3])&(M1&T2);
validPLA = validPLA | (pla[3])&(M1&T4);
setM1 = setM1 | (pla[3])&(M1&T4);
ctl_no_ints = ctl_no_ints | (pla[3])&(M1&T4);
ctl_state_tbl_cb_set = ctl_state_tbl_cb_set | (pla[44])&(M1&T2);
setCBED = setCBED | (pla[44])&(M1&T2);
validPLA = validPLA | (pla[44])&(M1&T4);
setM1 = setM1 | (pla[44])&(M1&T4);
ctl_no_ints = ctl_no_ints | (pla[44])&(M1&T4);
ctl_state_tbl_ed_set = ctl_state_tbl_ed_set | (pla[51])&(M1&T2);
setCBED = setCBED | (pla[51])&(M1&T2);
validPLA = validPLA | (pla[51])&(M1&T4);
setM1 = setM1 | (pla[51])&(M1&T4);
ctl_no_ints = ctl_no_ints | (pla[51])&(M1&T4);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[76]);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[76])&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[76])&(~ctl_alu_op_low);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[76]);
ctl_flags_nf_set = ctl_flags_nf_set | (pla[76]);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[76])&(M1&T1);
ctl_pf_sel_pla76M1T1_2 = (pla[76])&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla76M1T1_2,ctl_pf_sel_pla76M1T1_2})&(`PFSEL_V);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[78]);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[78])&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[78])&(~ctl_alu_op_low);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[78]);
ctl_flags_nf_set = ctl_flags_nf_set | (pla[78]);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[78])&(M1&T1);
ctl_reg_gp_sel_pla78M1T1_2 = (pla[78])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla78M1T1_2,ctl_reg_gp_sel_pla78M1T1_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla78M1T1_3 = (pla[78])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla78M1T1_3,ctl_reg_gp_hilo_pla78M1T1_3})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[78])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[78])&(M1&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[78])&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[78])&(M1&T1);
ctl_pf_sel_pla78M1T1_8 = (pla[78])&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla78M1T1_8,ctl_pf_sel_pla78M1T1_8})&(`PFSEL_V);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[79]);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[79])&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[79])&(~ctl_alu_op_low);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[79]);
ctl_flags_nf_set = ctl_flags_nf_set | (pla[79]);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[79])&(M1&T1);
ctl_reg_gp_sel_pla79M1T1_2 = (pla[79])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla79M1T1_2,ctl_reg_gp_sel_pla79M1T1_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla79M1T1_3 = (pla[79])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla79M1T1_3,ctl_reg_gp_hilo_pla79M1T1_3})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[79])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[79])&(M1&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[79])&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[79])&(M1&T1);
ctl_pf_sel_pla79M1T1_8 = (pla[79])&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla79M1T1_8,ctl_pf_sel_pla79M1T1_8})&(`PFSEL_V);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[80])&(~ctl_alu_op_low);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[80]);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[80]);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[80])&(M1&T1);
ctl_reg_gp_sel_pla80M1T1_2 = (pla[80])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla80M1T1_2,ctl_reg_gp_sel_pla80M1T1_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla80M1T1_3 = (pla[80])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla80M1T1_3,ctl_reg_gp_hilo_pla80M1T1_3})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[80])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[80])&(M1&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[80])&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[80])&(M1&T1);
ctl_pf_sel_pla80M1T1_8 = (pla[80])&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla80M1T1_8,ctl_pf_sel_pla80M1T1_8})&(`PFSEL_V);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[84])&(ctl_alu_op_low);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[84])&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (pla[84])&(~ctl_alu_op_low);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[84]);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[84]);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[84])&(M1&T1);
ctl_reg_gp_sel_pla84M1T1_2 = (pla[84])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla84M1T1_2,ctl_reg_gp_sel_pla84M1T1_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla84M1T1_3 = (pla[84])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla84M1T1_3,ctl_reg_gp_hilo_pla84M1T1_3})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[84])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[84])&(M1&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[84])&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[84])&(M1&T1);
ctl_pf_sel_pla84M1T1_8 = (pla[84])&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla84M1T1_8,ctl_pf_sel_pla84M1T1_8})&(`PFSEL_V);
ctl_alu_core_S = ctl_alu_core_S | (pla[85]);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[85]);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[85]);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[85]);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[85])&(M1&T1);
ctl_reg_gp_sel_pla85M1T1_2 = (pla[85])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla85M1T1_2,ctl_reg_gp_sel_pla85M1T1_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla85M1T1_3 = (pla[85])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla85M1T1_3,ctl_reg_gp_hilo_pla85M1T1_3})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[85])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[85])&(M1&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[85])&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[85])&(M1&T1);
ctl_pf_sel_pla85M1T1_8 = (pla[85])&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla85M1T1_8,ctl_pf_sel_pla85M1T1_8})&(`PFSEL_P);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[85])&(M1&T2);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[85])&(M1&T2);
ctl_alu_core_R = ctl_alu_core_R | (pla[86]);
ctl_alu_core_V = ctl_alu_core_V | (pla[86]);
ctl_alu_core_S = ctl_alu_core_S | (pla[86]);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[86]);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[86]);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[86]);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[86]);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[86])&(M1&T1);
ctl_reg_gp_sel_pla86M1T1_2 = (pla[86])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla86M1T1_2,ctl_reg_gp_sel_pla86M1T1_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla86M1T1_3 = (pla[86])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla86M1T1_3,ctl_reg_gp_hilo_pla86M1T1_3})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[86])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[86])&(M1&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[86])&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[86])&(M1&T1);
ctl_pf_sel_pla86M1T1_8 = (pla[86])&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla86M1T1_8,ctl_pf_sel_pla86M1T1_8})&(`PFSEL_P);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[86])&(M1&T2);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[86])&(M1&T2);
ctl_alu_core_R = ctl_alu_core_R | (pla[88]);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[88]);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[88]);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[88]);
ctl_flags_nf_clr = ctl_flags_nf_clr | (pla[88]);
ctl_reg_gp_we = ctl_reg_gp_we | (pla[88])&(M1&T1);
ctl_reg_gp_sel_pla88M1T1_2 = (pla[88])&(M1&T1);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla88M1T1_2,ctl_reg_gp_sel_pla88M1T1_2})&(`GP_REG_AF);
ctl_reg_gp_hilo_pla88M1T1_3 = (pla[88])&(M1&T1);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla88M1T1_3,ctl_reg_gp_hilo_pla88M1T1_3})&(2'b10);
ctl_reg_in_hi = ctl_reg_in_hi | (pla[88])&(M1&T1);
ctl_reg_in_lo = ctl_reg_in_lo | (pla[88])&(M1&T1);
ctl_flags_xy_we = ctl_flags_xy_we | (pla[88])&(M1&T1);
ctl_flags_pf_we = ctl_flags_pf_we | (pla[88])&(M1&T1);
ctl_pf_sel_pla88M1T1_8 = (pla[88])&(M1&T1);
ctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla88M1T1_8,ctl_pf_sel_pla88M1T1_8})&(`PFSEL_P);
ctl_flags_cf_set = ctl_flags_cf_set | (pla[88])&(M1&T2);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[88])&(M1&T2);
ctl_sw_2d = ctl_sw_2d | (ixy_d)&(T1);
ctl_sw_1d = ctl_sw_1d | (ixy_d)&(T1);
ctl_bus_db_oe = ctl_bus_db_oe | (ixy_d)&(T1);
ctl_flags_alu = ctl_flags_alu | (ixy_d)&(T1);
ctl_alu_shift_oe = ctl_alu_shift_oe | (ixy_d)&(T1)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (ixy_d)&(T1);
ctl_flags_sz_we = ctl_flags_sz_we | (ixy_d)&(T1);
ctl_reg_gp_sel_ixy_dT2_1 = (ixy_d)&(T2);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_ixy_dT2_1,ctl_reg_gp_sel_ixy_dT2_1})&(`GP_REG_HL);
ctl_reg_gp_hilo_ixy_dT2_2 = (ixy_d)&(T2);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_ixy_dT2_2,ctl_reg_gp_hilo_ixy_dT2_2})&(2'b01);
ctl_reg_out_lo = ctl_reg_out_lo | (ixy_d)&(T2);
ctl_sw_2d = ctl_sw_2d | (ixy_d)&(T2);
ctl_flags_alu = ctl_flags_alu | (ixy_d)&(T2);
ctl_alu_shift_oe = ctl_alu_shift_oe | (ixy_d)&(T2)&(~ctl_alu_bs_oe);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (ixy_d)&(T2);
ctl_alu_op_low = ctl_alu_op_low | (ixy_d)&(T2);
ctl_flags_cf_set = ctl_flags_cf_set | (ixy_d)&(T2)&(ctl_alu_op_low);
ctl_flags_cf_cpl = ctl_flags_cf_cpl | (ixy_d)&(T2)&(ctl_alu_op_low);
ctl_alu_core_hf = ctl_alu_core_hf | (ixy_d)&(T2)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (ixy_d)&(T2);
ctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (ixy_d)&(T3);
ctl_reg_sel_wz = ctl_reg_sel_wz | (ixy_d)&(T3);
ctl_reg_sys_hilo_ixy_dT3_3 = (ixy_d)&(T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_ixy_dT3_3,ctl_reg_sys_hilo_ixy_dT3_3})&({ctl_reg_sys_hilo[1],1'b1});
ctl_reg_in_lo = ctl_reg_in_lo | (ixy_d)&(T3);
ctl_sw_2u = ctl_sw_2u | (ixy_d)&(T3);
ctl_flags_alu = ctl_flags_alu | (ixy_d)&(T3);
ctl_alu_oe = ctl_alu_oe | (ixy_d)&(T3);
ctl_alu_res_oe = ctl_alu_res_oe | (ixy_d)&(T3);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (ixy_d)&(T3);
ctl_alu_core_hf = ctl_alu_core_hf | (ixy_d)&(T3)&(~ctl_alu_op_low);
ctl_flags_cf2_we = ctl_flags_cf2_we | (ixy_d)&(T3);
ctl_reg_gp_sel_ixy_dT4_1 = (ixy_d)&(T4);
ctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_ixy_dT4_1,ctl_reg_gp_sel_ixy_dT4_1})&(`GP_REG_HL);
ctl_reg_gp_hilo_ixy_dT4_2 = (ixy_d)&(T4);
ctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_ixy_dT4_2,ctl_reg_gp_hilo_ixy_dT4_2})&(2'b10);
ctl_reg_out_hi = ctl_reg_out_hi | (ixy_d)&(T4);
ctl_reg_out_lo = ctl_reg_out_lo | (ixy_d)&(T4);
ctl_flags_alu = ctl_flags_alu | (ixy_d)&(T4);
ctl_alu_shift_oe = ctl_alu_shift_oe | (ixy_d)&(T4)&(~ctl_alu_bs_oe);
ctl_alu_op2_sel_zero = ctl_alu_op2_sel_zero | (ixy_d)&(T4);
ctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (ixy_d)&(T4);
ctl_alu_op_low = ctl_alu_op_low | (ixy_d)&(T4);
ctl_alu_core_hf = ctl_alu_core_hf | (ixy_d)&(T4)&(~ctl_alu_op_low);
ctl_flags_hf_we = ctl_flags_hf_we | (ixy_d)&(T4);
ctl_flags_use_cf2 = ctl_flags_use_cf2 | (ixy_d)&(T4);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (ixy_d)&(T4)&(flags_sf);
ctl_reg_sel_wz = ctl_reg_sel_wz | (ixy_d)&(T5);
ctl_reg_sys_hilo_ixy_dT5_2 = (ixy_d)&(T5);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_ixy_dT5_2,ctl_reg_sys_hilo_ixy_dT5_2})&(2'b11);
ctl_sw_4d = ctl_sw_4d | (ixy_d)&(T5);
ctl_al_we = ctl_al_we | (ixy_d)&(T5);
ctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (ixy_d)&(T5);
ctl_reg_sel_wz = ctl_reg_sel_wz | (ixy_d)&(T5);
ctl_reg_sys_hilo_ixy_dT5_7 = (ixy_d)&(T5);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_ixy_dT5_7,ctl_reg_sys_hilo_ixy_dT5_7})&({1'b1,ctl_reg_sys_hilo[0]});
ctl_reg_in_hi = ctl_reg_in_hi | (ixy_d)&(T5);
ctl_flags_alu = ctl_flags_alu | (ixy_d)&(T5);
ctl_alu_oe = ctl_alu_oe | (ixy_d)&(T5);
ctl_alu_res_oe = ctl_alu_res_oe | (ixy_d)&(T5);
ctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (ixy_d)&(T5);
ctl_alu_core_hf = ctl_alu_core_hf | (ixy_d)&(T5)&(~ctl_alu_op_low);
ctl_flags_xy_we = ctl_flags_xy_we | (ixy_d)&(T5);
ctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (ixy_d)&(T5)&(flags_sf);
ctl_state_ixiy_we = ctl_state_ixiy_we | (ixy_d)&(T5);
ctl_state_ixiy_clr = ctl_state_ixiy_clr | (ixy_d)&(T5)&(~setIXIY);
ctl_reg_sys_we = ctl_reg_sys_we | (M1&T1);
ctl_reg_sel_pc = ctl_reg_sel_pc | (M1&T1);
ctl_reg_sys_hilo_1M1T1_3 = (M1&T1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_1M1T1_3,ctl_reg_sys_hilo_1M1T1_3})&(2'b11);
pc_inc_hold = pc_inc_hold | (M1&T1)&((in_halt|in_intr|in_nmi));
ctl_inc_cy = ctl_inc_cy | (M1&T1)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (M1&T1);
ctl_apin_mux2 = ctl_apin_mux2 | (M1&T1);
ctl_reg_sel_ir = ctl_reg_sel_ir | (M1&T2);
ctl_reg_sys_hilo_1M1T2_2 = (M1&T2);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_1M1T2_2,ctl_reg_sys_hilo_1M1T2_2})&(2'b11);
ctl_al_we = ctl_al_we | (M1&T2);
ctl_bus_db_oe = ctl_bus_db_oe | (M1&T2);
ctl_state_ixiy_we = ctl_state_ixiy_we | (M1&T2);
ctl_state_ixiy_clr = ctl_state_ixiy_clr | (M1&T2)&(~setIXIY);
ctl_state_tbl_clr = ctl_state_tbl_clr | (M1&T2)&(~setCBED);
ctl_ir_we = ctl_ir_we | (M1&T2);
ctl_bus_zero_oe = ctl_bus_zero_oe | (M1&T2)&(in_halt);
ctl_bus_ff_oe = ctl_bus_ff_oe | (M1&T2)&((in_intr&(im1|im2))|in_nmi);
ctl_reg_sys_we = ctl_reg_sys_we | (M1&T3);
ctl_reg_sel_ir = ctl_reg_sel_ir | (M1&T3);
ctl_reg_sys_hilo_1M1T3_3 = (M1&T3);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_1M1T3_3,ctl_reg_sys_hilo_1M1T3_3})&(2'b11);
ctl_inc_cy = ctl_inc_cy | (M1&T3)&(~pc_inc_hold);
ctl_bus_inc_oe = ctl_bus_inc_oe | (M1&T3);
ctl_apin_mux2 = ctl_apin_mux2 | (M1&T3);
ctl_inc_limit6 = ctl_inc_limit6 | (M1&T3);
ctl_eval_cond = ctl_eval_cond | (M1&T4);
setM1 = setM1 | (~validPLA)&(M1&T4);
ctl_reg_sel_pc = ctl_reg_sel_pc | (setM1);
ctl_reg_sys_hilo_setM1_2 = (setM1);
ctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_setM1_2,ctl_reg_sys_hilo_setM1_2})&(2'b11);
ctl_al_we = ctl_al_we | (setM1);
/sequencer.bsf
108,13 → 108,6
(line (pt 200 96)(pt 184 96))
)
(port
(pt 200 112)
(output)
(text "M6" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "M6" (rect 163 107 179 121)(font "Arial" (font_size 8)))
(line (pt 200 112)(pt 184 112))
)
(port
(pt 200 128)
(output)
(text "T1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
/test_interrupts.sv
27,6 → 27,7
 
// ----------------- STATES ----------------
wire iff1_sig;
assign iff1_sig = interrupts_inst.iff1;
wire iff2_sig;
wire im1_sig;
wire im2_sig;
82,7 → 83,6
.clk(clk) , // input clk
.ctl_no_ints(ctl_no_ints_sig) , // input ctl_no_ints_sig
.nreset(nreset) , // input nreset
.iff1(iff1_sig) , // output iff1_sig
.iff2(iff2_sig) , // output iff2_sig
.im1(im1_sig) , // output im1_sig
.im2(im2_sig) , // output im2_sig
/execute.v
0,0 → 1,160
//=============================================================================
// This module implements the instruction execute state logic.
//
// Copyright (C) 2014-2016 Goran Devic
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//=============================================================================
// Using a compiled format will include files generated by "gencompile.py" script
// These files are a processed version of "exec_matrix_compiled.vh"
// You would define this on Xilinx and undefine (comment out) on Altera
`define USE_COMPILED_FORMAT
 
module execute
(
//----------------------------------------------------------
// Control signals generated by the instruction execution
//----------------------------------------------------------
`include "exec_module.vh"
 
output reg nextM, // Last M cycle of any instruction
output reg setM1, // Last T clock of any instruction
output reg fFetch, // Function: opcode fetch cycle ("M1")
output reg fMRead, // Function: memory read cycle
output reg fMWrite, // Function: memory write cycle
output reg fIORead, // Function: IO Read cycle
output reg fIOWrite, // Function: IO Write cycle
 
//----------------------------------------------------------
// Inputs from the instruction decode PLA
//----------------------------------------------------------
input wire [104:0] pla, // Statically decoded instructions
 
//----------------------------------------------------------
// Inputs from various blocks
//----------------------------------------------------------
input wire in_intr, // Servicing maskable interrupt
input wire in_nmi, // Servicing non-maskable interrupt
input wire in_halt, // Currently in HALT mode
input wire im1, // Interrupt Mode 1
input wire im2, // Interrupt Mode 2
input wire use_ixiy, // Special decode signal
input wire flags_cond_true, // Flags condition is true
input wire repeat_en, // Enable repeat of a block instruction
input wire flags_zf, // ZF to test a condition
input wire flags_nf, // NF to test for subtraction
input wire flags_sf, // SF to test for 8-bit sign of a value
input wire flags_cf, // CF to set HF for CCF
 
//----------------------------------------------------------
// Machine and clock cycles
//----------------------------------------------------------
input wire M1, // Machine cycle #1
input wire M2, // Machine cycle #2
input wire M3, // Machine cycle #3
input wire M4, // Machine cycle #4
input wire M5, // Machine cycle #5
input wire T1, // T-cycle #1
input wire T2, // T-cycle #2
input wire T3, // T-cycle #3
input wire T4, // T-cycle #4
input wire T5, // T-cycle #5
input wire T6 // T-cycle #6
);
 
// Detects unknown instructions by signalling the known ones
reg validPLA; // Valid PLA asserts this reg
// Activates a state machine to compute WZ=IX+d; takes 5T cycles
reg ixy_d; // Compute WX=IX+d
// Signals the setting of IX/IY and CB/ED prefix flags; inhibits clearing them
reg setIXIY; // Set IX/IY flag at the next T cycle
reg setCBED; // Set CB or ED flag at the next T cycle
// Holds asserted by non-repeating versions of block instructions (LDI/CPI,...)
reg nonRep; // Non-repeating block instruction
// Suspends incrementing PC through address latch unless in HALT or interrupt mode
reg pc_inc_hold; // Normally 0 unless in one of those modes
 
//--------------------------------------------------------------
// Define various shortcuts to field naming
//--------------------------------------------------------------
`define GP_REG_BC 2'h0
`define GP_REG_DE 2'h1
`define GP_REG_HL 2'h2
`define GP_REG_AF 2'h3
 
`define PFSEL_P 2'h0
`define PFSEL_V 2'h1
`define PFSEL_IFF2 2'h2
`define PFSEL_REP 2'h3
 
//--------------------------------------------------------------
// Make available different bits and sections of the opcode byte
//--------------------------------------------------------------
wire op0 = pla[99];
wire op1 = pla[100];
wire op2 = pla[101];
wire op3 = pla[102];
wire op4 = pla[103];
wire op5 = pla[104];
 
wire [1:0] op21 = { pla[101], pla[100] };
wire [1:0] op54 = { pla[104], pla[103] };
 
//--------------------------------------------------------------
// 8-bit register selections needs to swizzle mux for A and F
//--------------------------------------------------------------
wire rsel0 = op0 ^ (op1 & op2);
wire rsel3 = op3 ^ (op4 & op5);
 
`ifdef USE_COMPILED_FORMAT
`include "temp_wires.vh" // Define all temp wires used with compiled equations
`endif
 
always @(*) // always_comb
begin
//-----------------------------------------------------------------------------
// Default assignment of all control outputs to 0 to prevent generating latches
//-----------------------------------------------------------------------------
`include "exec_zero.vh" // Initial assignment to all ctl wires to zero
 
// Reset internal control regs
validPLA = 0; // Will be set by every *valid* PLA entry
nextM = 0; // Will be set to advance to the next M cycle
setM1 = 0; // Will be set on a last M/T cycle of an instruction
 
// Reset global machine cycle functions
fFetch = M1; // Fetch is aliased to M1
fMRead = 0; fMWrite = 0; fIORead = 0; fIOWrite = 0;
ixy_d = 0;
setIXIY = 0;
setCBED = 0;
nonRep = 0;
pc_inc_hold = 0;
 
//-------------------------------------------------------------------------
// State-based signal assignment; code generated from Timings spreadsheet
//-------------------------------------------------------------------------
`ifdef USE_COMPILED_FORMAT
`include "exec_matrix_compiled.vh" // Compiled execution equations
`else
`include "exec_matrix.vh" // Execution statements in the original nested-if format
`endif
 
// Needed by data bus 0 override logic, make only one bus writer active at any time
ctl_bus_db_oe = ctl_bus_db_oe & ~(ctl_bus_zero_oe | ctl_bus_ff_oe);
 
end
 
endmodule
/test_control.qsf
1,17 → 1,17
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
61,8 → 61,8
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name SYSTEMVERILOG_FILE pla_decode.sv
set_global_assignment -name SYSTEMVERILOG_FILE execute.sv
set_global_assignment -name VERILOG_FILE pla_decode.v
set_global_assignment -name VERILOG_FILE execute.v
set_global_assignment -name BDF_FILE sequencer.bdf
set_global_assignment -name BDF_FILE resets.bdf
set_global_assignment -name BDF_FILE memory_ifc.bdf
/test_reset.sv
8,7 → 8,7
// ----------------- CLOCKS AND RESET -----------------
`define T #2
bit clk = 1;
initial repeat (30) #1 clk = ~clk;
initial repeat (40) #1 clk = ~clk;
 
// Specific to FPGA, some modules in the schematic need to be pre-initialized
reg fpga_reset = 1;
30,7 → 30,15
// Test normal reset sequence - 3 clocks long
`T reset_in = 1;
`T `T `T reset_in = 0;
`T assert(nreset==0 && clrpc==0);
`T assert(nreset==0);
// Out of the reset for several more cycles
// Check that the clrpc is set for the next 2 1/2 cycles (see waveform)
`T assert(nreset==1 && clrpc==1);
`T assert(nreset==1 && clrpc==1);
`T assert(nreset==1 && clrpc==0);
`T assert(nreset==1 && clrpc==0);
`T assert(nreset==1 && clrpc==0);
 
// Test special reset sequence: a reset pin is briefly
// asserted at M1/T1 and CLRPC should hold until the next
// M1/T2
/interrupts.bdf
197,22 → 197,6
)
(pin
(output)
(rect 728 104 904 120)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "iff1" (rect 90 0 107 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(pin
(output)
(rect 728 232 904 248)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "iff2" (rect 90 0 107 12)(font "Arial" ))
1499,10 → 1483,6
(pt 288 752)
)
(connector
(pt 688 112)
(pt 728 112)
)
(connector
(pt 368 240)
(pt 384 240)
)
1867,6 → 1847,11
(pt 520 760)
(pt 584 760)
)
(connector
(text "iff1" (rect 756 96 773 108)(font "Arial" ))
(pt 768 112)
(pt 688 112)
)
(junction (pt 240 160))
(junction (pt 240 176))
(junction (pt 296 128))
1890,11 → 1875,11
(title_block
(rect 24 1144 281 1196)
(name "title-custom-small")
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "July 19, 2014, 2016" (rect 56 3 166 17)(font "Arial" (font_size 8)))(border))
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "interrupts" (rect 43 2 109 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "interrupts" (rect 43 2 109 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "July 19, 2014" (rect 56 3 131 17)(font "Arial" (font_size 8)))(border))
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.3" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.4" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
(drawing
)
)

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