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URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

Subversion Repositories a-z80

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /a-z80/trunk/cpu/registers
    from Rev 13 to Rev 16
    ↔ Reverse comparison
  •

Rev 13 → Rev 16

/reg_control.bdf
343,7 → 343,7
(input)
(rect 32 848 208 864)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "hold_clk_wait" (rect 9 0 73 12)(font "Arial" ))
(text "nhold_clk_wait" (rect 9 0 79 12)(font "Arial" ))
(pt 176 8)
(drawing
(line (pt 92 12)(pt 117 12))
2498,31 → 2498,6
(circle (rect 28 4 36 12))
)
)
(symbol
(rect 328 840 376 872)
(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
(text "inst7" (rect 3 21 26 33)(font "Arial" ))
(port
(pt 0 16)
(input)
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 13 16))
)
(port
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
)
(drawing
(line (pt 13 25)(pt 13 7))
(line (pt 13 7)(pt 31 16))
(line (pt 13 25)(pt 31 16))
(circle (rect 31 12 39 20))
)
)
(connector
(pt 616 680)
(pt 600 680)
3575,10 → 3550,6
(pt 312 496)
)
(connector
(pt 208 856)
(pt 328 856)
)
(connector
(pt 312 496)
(pt 312 800)
)
3591,24 → 3562,23
(pt 528 856)
)
(connector
(pt 208 856)
(pt 528 856)
(pt 680 856)
)
(connector
(text "n_hold_clk_wait" (rect 400 840 476 852)(font "Arial" ))
(pt 376 856)
(pt 528 856)
(pt 680 856)
)
(connector
(text "n_hold_clk_wait" (rect 607 544 683 556)(font "Arial" ))
(text "nhold_clk_wait" (rect 608 432 678 444)(font "Arial" ))
(pt 680 432)
(pt 656 432)
)
(connector
(text "nhold_clk_wait" (rect 607 544 677 556)(font "Arial" ))
(pt 680 544)
(pt 656 544)
)
(connector
(text "n_hold_clk_wait" (rect 608 432 684 444)(font "Arial" ))
(pt 680 432)
(pt 656 432)
)
(junction (pt 600 624))
(junction (pt 264 312))
(junction (pt 264 632))
3690,7 → 3660,7
(section (rect 130 0 320 20)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "reg_control" (rect 43 2 146 21)(font "Arial" (font_size 12)(bold)))(border))
(section (rect 0 21 320 40)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 151 19)(font "Arial" (font_size 11)))(border))
(section (rect 0 41 240 60)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 17, 2014, 2016" (rect 56 3 191 19)(font "Arial" (font_size 10)))(border))
(section (rect 241 41 320 60)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.4" (rect 43 3 64 19)(font "Arial" (font_size 10)))(border))
(section (rect 241 41 320 60)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.5" (rect 43 3 64 19)(font "Arial" (font_size 10)))(border))
(drawing
)
)
/reg_control.bsf
96,8 → 96,8
(port
(pt 0 192)
(input)
(text "hold_clk_wait" (rect 0 0 77 14)(font "Arial" (font_size 8)))
(text "hold_clk_wait" (rect 21 187 98 201)(font "Arial" (font_size 8)))
(text "nhold_clk_wait" (rect 0 0 84 14)(font "Arial" (font_size 8)))
(text "nhold_clk_wait" (rect 21 187 105 201)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 16 192))
)
(port
/reg_control.v
14,7 → 14,7
 
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Thu Dec 08 22:19:25 2016"
// CREATED "Sat Dec 10 09:05:10 2016"
 
module reg_control(
ctl_reg_exx,
34,7 → 34,7
ctl_reg_sys_we,
clk,
ctl_sw_4d,
hold_clk_wait,
nhold_clk_wait,
ctl_reg_gp_hilo,
ctl_reg_gp_sel,
ctl_reg_sys_hilo,
81,7 → 81,7
input wire ctl_reg_sys_we;
input wire clk;
input wire ctl_sw_4d;
input wire hold_clk_wait;
input wire nhold_clk_wait;
input wire [1:0] ctl_reg_gp_hilo;
input wire [1:0] ctl_reg_gp_sel;
input wire [1:0] ctl_reg_sys_hilo;
113,7 → 113,6
reg bank_exx;
reg bank_hl_de1;
reg bank_hl_de2;
wire n_hold_clk_wait;
wire reg_sys_we_lo_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_52;
wire SYNTHESIZED_WIRE_53;
243,7 → 242,7
bank_af <= 0;
end
else
if (n_hold_clk_wait)
if (nhold_clk_wait)
begin
bank_af <= bank_af ^ ctl_reg_ex_af;
end
273,7 → 272,7
bank_hl_de2 <= 0;
end
else
if (n_hold_clk_wait)
if (nhold_clk_wait)
begin
bank_hl_de2 <= bank_hl_de2 ^ SYNTHESIZED_WIRE_43;
end
293,7 → 292,7
bank_hl_de1 <= 0;
end
else
if (n_hold_clk_wait)
if (nhold_clk_wait)
begin
bank_hl_de1 <= bank_hl_de1 ^ SYNTHESIZED_WIRE_50;
end
307,7 → 306,7
bank_exx <= 0;
end
else
if (n_hold_clk_wait)
if (nhold_clk_wait)
begin
bank_exx <= bank_exx ^ ctl_reg_exx;
end
319,8 → 318,6
 
assign SYNTHESIZED_WIRE_31 = ~ctl_reg_gp_sel[1];
 
assign n_hold_clk_wait = ~hold_clk_wait;
 
assign reg_sel_bc2 = SYNTHESIZED_WIRE_52 & bank_exx;
 
assign reg_sys_we_lo = reg_sys_we_lo_ALTERA_SYNTHESIZED;
/test_registers.sv
49,7 → 49,7
logic ctl_reg_sys_we_sig=0; // Write to system register
logic use_ixiy_sig=0; // Use IX or IY
logic use_ix_sig=0; // Use IX and not IY
logic hold_clk_wait_sig=0; // Hold all transitions
logic nhold_clk_wait_sig=1; // Enable transitions due to nWAIT
 
logic ctl_reg_exx_sig=0; // Exchange register banks
logic ctl_reg_ex_af_sig=0; // Exchange AF banks
183,7 → 183,7
.ctl_reg_sys_we(ctl_reg_sys_we_sig) , // input ctl_reg_sys_we_sig
.clk(clk) , // input clk
.ctl_sw_4d (ctl_sw_4d_sig) , // input ctl_sw_4d
.hold_clk_wait(hold_clk_wait_sig) , // input hold_clk_wait_sig
.nhold_clk_wait(nhold_clk_wait_sig) , // input nhold_clk_wait_sig
.reg_sel_bc(reg_sel_bc_sig) , // output reg_sel_bc_sig
.reg_sel_bc2(reg_sel_bc2_sig) , // output reg_sel_bc2_sig
.reg_sel_ix(reg_sel_ix_sig) , // output reg_sel_ix_sig

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