URL
https://opencores.org/ocsvn/a-z80/a-z80/trunk
Subversion Repositories a-z80
Compare Revisions
- This comparison shows the changes necessary to convert path
/a-z80/trunk/cpu/toplevel/simulation
- from Rev 3 to Rev 8
- ↔ Reverse comparison
Rev 3 → Rev 8
/modelsim/test_top.mpf
2,9 → 2,9
; |
; All Rights Reserved. |
; |
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF |
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF |
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. |
; |
; |
|
[Library] |
std = $MODEL_TECH/../std |
128,7 → 128,7
hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip |
|
[vcom] |
; VHDL93 variable selects language version as the default. |
; VHDL93 variable selects language version as the default. |
; Default is VHDL-2002. |
; Value of 0 or 1987 for VHDL-1987. |
; Value of 1 or 1993 for VHDL-1993. |
271,7 → 271,7
BreakOnAssertion = 3 |
|
; Assertion Message Format |
; %S - Severity Level |
; %S - Severity Level |
; %R - Report Message |
; %T - Time of assertion |
; %D - Delta |
422,10 → 422,10
; description of a message. |
|
; Control transcripting of elaboration/runtime messages. |
; The default is to have messages appear in the transcript and |
; The default is to have messages appear in the transcript and |
; recorded in the wlf file (messages that are recorded in the |
; wlf file can be viewed in the MsgViewer). The other settings |
; are to send messages only to the transcript or only to the |
; are to send messages only to the transcript or only to the |
; wlf file. The valid values are |
; both {default} |
; tran {transcript only} |
477,7 → 477,7
Project_File_P_16 = compile_order 13 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
Project_File_17 = $ROOT/cpu/bus/bus_control.v |
Project_File_P_17 = compile_order 32 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
Project_File_18 = $ROOT/cpu/bus/bus_switch.sv |
Project_File_18 = $ROOT/cpu/bus/bus_switch.v |
Project_File_P_18 = compile_order 30 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
Project_File_19 = $ROOT/cpu/bus/control_pins_n.v |
Project_File_P_19 = compile_order 42 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
495,7 → 495,7
Project_File_P_25 = compile_order 28 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
Project_File_26 = $ROOT/cpu/control/decode_state.v |
Project_File_P_26 = compile_order 29 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
Project_File_27 = $ROOT/cpu/control/execute.sv |
Project_File_27 = $ROOT/cpu/control/execute.v |
Project_File_P_27 = compile_order 18 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options +incdir+../../../control vlog_protect 0 vlog_showsource 1 vlog_upper 0 voptflow 1 |
Project_File_28 = $ROOT/cpu/control/interrupts.v |
Project_File_P_28 = compile_order 27 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
505,7 → 505,7
Project_File_P_30 = compile_order 41 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
Project_File_31 = $ROOT/cpu/control/pin_control.v |
Project_File_P_31 = compile_order 43 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
Project_File_32 = $ROOT/cpu/control/pla_decode.sv |
Project_File_32 = $ROOT/cpu/control/pla_decode.v |
Project_File_P_32 = compile_order 20 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
Project_File_33 = $ROOT/cpu/control/resets.v |
Project_File_P_33 = compile_order 37 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
553,42 → 553,42
ForceSoftPaths = 1 |
ProjectStatusDelay = 5000 |
VERILOG_DoubleClick = Edit |
VERILOG_CustomDoubleClick = |
VERILOG_CustomDoubleClick = |
SYSTEMVERILOG_DoubleClick = Compile |
SYSTEMVERILOG_CustomDoubleClick = |
SYSTEMVERILOG_CustomDoubleClick = |
VHDL_DoubleClick = Edit |
VHDL_CustomDoubleClick = |
VHDL_CustomDoubleClick = |
PSL_DoubleClick = Edit |
PSL_CustomDoubleClick = |
PSL_CustomDoubleClick = |
TEXT_DoubleClick = Edit |
TEXT_CustomDoubleClick = |
TEXT_CustomDoubleClick = |
SYSTEMC_DoubleClick = Edit |
SYSTEMC_CustomDoubleClick = |
SYSTEMC_CustomDoubleClick = |
TCL_DoubleClick = Edit |
TCL_CustomDoubleClick = |
TCL_CustomDoubleClick = |
MACRO_DoubleClick = Edit |
MACRO_CustomDoubleClick = |
MACRO_CustomDoubleClick = |
VCD_DoubleClick = Edit |
VCD_CustomDoubleClick = |
VCD_CustomDoubleClick = |
SDF_DoubleClick = Edit |
SDF_CustomDoubleClick = |
SDF_CustomDoubleClick = |
XML_DoubleClick = Edit |
XML_CustomDoubleClick = |
XML_CustomDoubleClick = |
LOGFILE_DoubleClick = Edit |
LOGFILE_CustomDoubleClick = |
LOGFILE_CustomDoubleClick = |
UCDB_DoubleClick = Edit |
UCDB_CustomDoubleClick = |
UCDB_CustomDoubleClick = |
UPF_DoubleClick = Edit |
UPF_CustomDoubleClick = |
UPF_CustomDoubleClick = |
PCF_DoubleClick = Edit |
PCF_CustomDoubleClick = |
PCF_CustomDoubleClick = |
PROJECT_DoubleClick = Edit |
PROJECT_CustomDoubleClick = |
PROJECT_CustomDoubleClick = |
VRM_DoubleClick = Edit |
VRM_CustomDoubleClick = |
VRM_CustomDoubleClick = |
DEBUGDATABASE_DoubleClick = Edit |
DEBUGDATABASE_CustomDoubleClick = |
DEBUGDATABASE_CustomDoubleClick = |
DEBUGARCHIVE_DoubleClick = Edit |
DEBUGARCHIVE_CustomDoubleClick = |
DEBUGARCHIVE_CustomDoubleClick = |
Project_Major_Version = 10 |
Project_Minor_Version = 1 |
/modelsim/wave_fuse.do
58,7 → 58,6
add wave -noupdate -group sequencer -expand -group M /test_fuse/dut/sequencer_/M3 |
add wave -noupdate -group sequencer -expand -group M /test_fuse/dut/sequencer_/M4 |
add wave -noupdate -group sequencer -expand -group M /test_fuse/dut/sequencer_/M5 |
add wave -noupdate -group sequencer -expand -group M /test_fuse/dut/sequencer_/M6 |
add wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T1 |
add wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T2 |
add wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T3 |
65,14 → 64,13
add wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T4 |
add wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T5 |
add wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T6 |
add wave -noupdate -group opcode /test_fuse/dut/instruction_reg_/ctl_ir_we |
add wave -noupdate -group opcode /test_fuse/dut/instruction_reg_/opcode |
add wave -noupdate -group opcode /test_fuse/dut/ir_/ctl_ir_we |
add wave -noupdate -group opcode /test_fuse/dut/ir_/opcode |
add wave -noupdate -group db -radix hexadecimal /test_fuse/dut/db0 |
add wave -noupdate -group db -radix hexadecimal /test_fuse/dut/db1 |
add wave -noupdate -group db -radix hexadecimal /test_fuse/dut/db2 |
add wave -noupdate -group {bus control} /test_fuse/dut/bus_control_/ctl_bus_ff_oe |
add wave -noupdate -group {bus control} /test_fuse/dut/bus_control_/ctl_bus_zero_oe |
add wave -noupdate -group {bus control} /test_fuse/dut/bus_control_/ctl_bus_db_oe |
add wave -noupdate -group {bus control} /test_fuse/dut/pin_control_/bus_ab_pin_we |
add wave -noupdate -group {bus control} /test_fuse/dut/pin_control_/bus_db_pin_oe |
add wave -noupdate -group {bus control} /test_fuse/dut/pin_control_/bus_db_pin_re |
154,6 → 152,8
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_wz |
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_ir |
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_pc |
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sw_4d_lo |
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sw_4d_hi |
add wave -noupdate -group regfile -radix hexadecimal /test_fuse/dut/reg_file_/db_hi_as |
add wave -noupdate -group regfile -radix hexadecimal -childformat {{{/test_fuse/dut/reg_file_/db_lo_as[7]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[6]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[5]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[4]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[3]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[2]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[1]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[0]} -radix hexadecimal}} -subitemconfig {{/test_fuse/dut/reg_file_/db_lo_as[7]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[6]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[5]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[4]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[3]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[2]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[1]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[0]} {-height 15 -radix hexadecimal}} /test_fuse/dut/reg_file_/db_lo_as |
add wave -noupdate -group switch /test_fuse/dut/bus_switch_/ctl_sw_mask543_en |
161,12 → 161,12
add wave -noupdate -group switch /test_fuse/dut/bus_switch_/ctl_sw_1d |
add wave -noupdate -group switch /test_fuse/dut/bus_switch_/ctl_sw_2u |
add wave -noupdate -group switch /test_fuse/dut/bus_switch_/ctl_sw_2d |
add wave -noupdate -group switch -color Aquamarine /test_fuse/dut/reg_file_/ctl_sw_4d |
add wave -noupdate -group switch /test_fuse/dut/reg_control_/ctl_sw_4d |
add wave -noupdate -group switch -color Aquamarine /test_fuse/dut/reg_file_/ctl_sw_4u |
add wave -noupdate -group {data pins} /test_fuse/dut/data_pins_/bus_db_pin_oe |
add wave -noupdate -group {data pins} /test_fuse/dut/data_pins_/bus_db_pin_re |
add wave -noupdate -group {data pins} /test_fuse/dut/data_pins_/ctl_bus_db_we |
add wave -noupdate -group {data pins} /test_fuse/dut/data_pins_/bus_db_oe |
add wave -noupdate -group {data pins} /test_fuse/dut/data_pins_/ctl_bus_db_oe |
add wave -noupdate -group {data pins} -radix hexadecimal /test_fuse/dut/data_pins_/D |
add wave -noupdate -group {data pins} -radix hexadecimal /test_fuse/dut/data_pins_/db |
add wave -noupdate -group {alu |
370,7 → 370,7
} -radix hexadecimal /test_fuse/dut/alu_/op2_low |
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_inc_cy |
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_inc_dec |
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_inc_zero |
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/clrpc |
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_al_we |
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_inc_limit6 |
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_bus_inc_oe |
/modelsim/wave_top.do
58,7 → 58,6
add wave -noupdate -group sequencer -expand -group M /test_top/dut/sequencer_/M3 |
add wave -noupdate -group sequencer -expand -group M /test_top/dut/sequencer_/M4 |
add wave -noupdate -group sequencer -expand -group M /test_top/dut/sequencer_/M5 |
add wave -noupdate -group sequencer -expand -group M /test_top/dut/sequencer_/M6 |
add wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T1 |
add wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T2 |
add wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T3 |
65,14 → 64,13
add wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T4 |
add wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T5 |
add wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T6 |
add wave -noupdate -group opcode /test_top/dut/instruction_reg_/ctl_ir_we |
add wave -noupdate -group opcode /test_top/dut/instruction_reg_/opcode |
add wave -noupdate -group opcode /test_top/dut/ir_/ctl_ir_we |
add wave -noupdate -group opcode /test_top/dut/ir_/opcode |
add wave -noupdate -group db -radix hexadecimal /test_top/dut/db0 |
add wave -noupdate -group db -radix hexadecimal /test_top/dut/db1 |
add wave -noupdate -group db -radix hexadecimal /test_top/dut/db2 |
add wave -noupdate -group {bus control} /test_top/dut/bus_control_/ctl_bus_ff_oe |
add wave -noupdate -group {bus control} /test_top/dut/bus_control_/ctl_bus_zero_oe |
add wave -noupdate -group {bus control} /test_top/dut/bus_control_/ctl_bus_db_oe |
add wave -noupdate -group {bus control} /test_top/dut/pin_control_/bus_ab_pin_we |
add wave -noupdate -group {bus control} /test_top/dut/pin_control_/bus_db_pin_oe |
add wave -noupdate -group {bus control} /test_top/dut/pin_control_/bus_db_pin_re |
154,6 → 152,8
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_wz |
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_ir |
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_pc |
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sw_4d_lo |
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sw_4d_hi |
add wave -noupdate -group regfile -radix hexadecimal /test_top/dut/reg_file_/db_hi_as |
add wave -noupdate -group regfile -radix hexadecimal -childformat {{{/test_top/dut/reg_file_/db_lo_as[7]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[6]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[5]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[4]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[3]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[2]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[1]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[0]} -radix hexadecimal}} -subitemconfig {{/test_top/dut/reg_file_/db_lo_as[7]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[6]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[5]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[4]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[3]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[2]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[1]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[0]} {-height 15 -radix hexadecimal}} /test_top/dut/reg_file_/db_lo_as |
add wave -noupdate -group switch /test_top/dut/bus_switch_/ctl_sw_mask543_en |
161,12 → 161,12
add wave -noupdate -group switch /test_top/dut/bus_switch_/ctl_sw_1d |
add wave -noupdate -group switch /test_top/dut/bus_switch_/ctl_sw_2u |
add wave -noupdate -group switch /test_top/dut/bus_switch_/ctl_sw_2d |
add wave -noupdate -group switch -color Aquamarine /test_top/dut/reg_file_/ctl_sw_4d |
add wave -noupdate -group switch /test_top/dut/reg_control_/ctl_sw_4d |
add wave -noupdate -group switch -color Aquamarine /test_top/dut/reg_file_/ctl_sw_4u |
add wave -noupdate -group {data pins} /test_top/dut/data_pins_/bus_db_pin_oe |
add wave -noupdate -group {data pins} /test_top/dut/data_pins_/bus_db_pin_re |
add wave -noupdate -group {data pins} /test_top/dut/data_pins_/ctl_bus_db_we |
add wave -noupdate -group {data pins} /test_top/dut/data_pins_/bus_db_oe |
add wave -noupdate -group {data pins} /test_top/dut/data_pins_/ctl_bus_db_oe |
add wave -noupdate -group {data pins} -radix hexadecimal /test_top/dut/data_pins_/D |
add wave -noupdate -group {data pins} -radix hexadecimal /test_top/dut/data_pins_/db |
add wave -noupdate -group {alu |
370,7 → 370,7
} -radix hexadecimal /test_top/dut/alu_/op2_low |
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_inc_cy |
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_inc_dec |
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_inc_zero |
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/clrpc |
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_al_we |
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_inc_limit6 |
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_bus_inc_oe |