OpenCores
URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

Subversion Repositories a-z80

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /a-z80/trunk/cpu/toplevel
    from Rev 6 to Rev 8
    Reverse comparison

Rev 6 → Rev 8

/z80_top_direct_n.sv File deleted
/genfuse.py
1,4 → 1,4
#!/usr/bin/env python
#!/usr/bin/env python3
#
# This script generates a test include file from a set of "Fuse" test vectors.
#
62,7 → 62,7
while t1[0].split(" ")[0]!=start_test:
while len(t1.pop(0))>0:
pass
t1 = filter(None, t1) # Filter out empty lines
t1 = list(filter(None, t1)) # Filter out empty lines
 
with open(tests_expected) as f2:
t2 = f2.read().splitlines()
96,6 → 96,7
ftest.write("// Automatically generated by genfuse.py\n\n")
 
# Initial pre-test state is reset and control signals asserted
ftest.write("force dut.resets_.clrpc=0;\n")
ftest.write("force dut.reg_file_.reg_gp_we=0;\n")
ftest.write("force dut.reg_control_.ctl_reg_sys_we=0;\n")
ftest.write("force dut.z80_top_ifc_n.fpga_reset=1;\n")
110,10 → 111,10
run_tests = run_tests-1
 
# Clear opcode register before starting a new instruction
ftest.write(" force dut.instruction_reg_.ctl_ir_we=1;\n")
ftest.write(" force dut.instruction_reg_.db=0;\n")
ftest.write("#2 release dut.instruction_reg_.ctl_ir_we;\n")
ftest.write(" release dut.instruction_reg_.db;\n")
ftest.write(" force dut.ir_.ctl_ir_we=1;\n")
ftest.write(" force dut.ir_.db=0;\n")
ftest.write("#2 release dut.ir_.ctl_ir_we;\n")
ftest.write(" release dut.ir_.db;\n")
total_clks = total_clks + 2
 
# Format of the test.in file:
124,7 → 125,7
ftest.write("$fdisplay(f,\"Testing opcode " + name + "\");\n")
name = name.split(" ")[0]
r = t1.pop(0).split(' ')
r = filter(None, r)
r = list(filter(None, r))
# 0 1 2 3 4 5 6 7 8 9 10 11 (index)
# AF BC DE HL AF' BC' DE' HL' IX IY SP PC
RegWrite("af", r[0])
142,7 → 143,7
RegWrite("pc", r[11])
 
s = t1.pop(0).split(' ')
s = filter(None, s)
s = list(filter(None, s))
# 0 1 2 3 4 5 6 (index)
# I R IFF1 IFF2 IM <halted> <tstates?>
RegWrite("ir", s[0]+s[1])
170,7 → 171,7
t2b = list(t2)
while True:
m = t2b.pop(0).split(' ')
m = filter(None, m)
m = list(filter(None, m))
if len(m)==0 or m[0]=="-1":
break
if len(m)==4 and m[1]=="PR":
186,12 → 187,12
# Similarly, we let the execution continues 2T into the next instruction but we prevent
# it from writing to system registers so it cannot update PC and IR.
ftest.write(" force dut.z80_top_ifc_n.fpga_reset=0;\n")
ftest.write(" force dut.address_latch_.abus=16'h" + r[11] +";\n")
ftest.write(" force dut.address_latch_.Q=16'h" + r[11] +";\n") # Force PC into the address latch
ftest.write(" release dut.reg_control_.ctl_reg_sys_we;\n")
ftest.write(" release dut.reg_file_.reg_gp_we;\n")
ftest.write("#3\n") # 1T (#2) overlaps the reset cycle
total_clks = total_clks + 3 # We borrow 1T (#2) to to force the PC to be what our test wants...
ftest.write(" release dut.address_latch_.abus;\n")
ftest.write(" release dut.address_latch_.Q;\n")
ftest.write("#1\n")
total_clks = total_clks + 1
 
207,10 → 208,10
if l[0]!=' ':
break
r = l.split(' ')
r = filter(None, r)
r = list(filter(None, r))
 
s = t2.pop(0).split(' ')
s = filter(None, s)
s = list(filter(None, s))
 
ticks = int(s[6]) * 2 - 2 # We return 1T (#2) that we borrowed to set PC
total_clks = total_clks + ticks
264,7 → 265,7
# Read memory configuration until an empty line or -1 at the end
while True:
m = t2.pop(0).split(' ')
m = filter(None, m)
m = list(filter(None, m))
if len(m)==0 or m[0]=="-1":
break
address = int(m.pop(0),16)
/simulation/modelsim/test_top.mpf
2,9 → 2,9
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
;
 
[Library]
std = $MODEL_TECH/../std
128,7 → 128,7
hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip
 
[vcom]
; VHDL93 variable selects language version as the default.
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
271,7 → 271,7
BreakOnAssertion = 3
 
; Assertion Message Format
; %S - Severity Level
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
422,10 → 422,10
; description of a message.
 
; Control transcripting of elaboration/runtime messages.
; The default is to have messages appear in the transcript and
; The default is to have messages appear in the transcript and
; recorded in the wlf file (messages that are recorded in the
; wlf file can be viewed in the MsgViewer). The other settings
; are to send messages only to the transcript or only to the
; are to send messages only to the transcript or only to the
; wlf file. The valid values are
; both {default}
; tran {transcript only}
477,7 → 477,7
Project_File_P_16 = compile_order 13 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_17 = $ROOT/cpu/bus/bus_control.v
Project_File_P_17 = compile_order 32 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_18 = $ROOT/cpu/bus/bus_switch.sv
Project_File_18 = $ROOT/cpu/bus/bus_switch.v
Project_File_P_18 = compile_order 30 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_19 = $ROOT/cpu/bus/control_pins_n.v
Project_File_P_19 = compile_order 42 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
495,7 → 495,7
Project_File_P_25 = compile_order 28 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_26 = $ROOT/cpu/control/decode_state.v
Project_File_P_26 = compile_order 29 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_27 = $ROOT/cpu/control/execute.sv
Project_File_27 = $ROOT/cpu/control/execute.v
Project_File_P_27 = compile_order 18 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options +incdir+../../../control vlog_protect 0 vlog_showsource 1 vlog_upper 0 voptflow 1
Project_File_28 = $ROOT/cpu/control/interrupts.v
Project_File_P_28 = compile_order 27 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
505,7 → 505,7
Project_File_P_30 = compile_order 41 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_31 = $ROOT/cpu/control/pin_control.v
Project_File_P_31 = compile_order 43 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_32 = $ROOT/cpu/control/pla_decode.sv
Project_File_32 = $ROOT/cpu/control/pla_decode.v
Project_File_P_32 = compile_order 20 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_33 = $ROOT/cpu/control/resets.v
Project_File_P_33 = compile_order 37 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
553,42 → 553,42
ForceSoftPaths = 1
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
VERILOG_CustomDoubleClick =
SYSTEMVERILOG_DoubleClick = Compile
SYSTEMVERILOG_CustomDoubleClick =
SYSTEMVERILOG_CustomDoubleClick =
VHDL_DoubleClick = Edit
VHDL_CustomDoubleClick =
VHDL_CustomDoubleClick =
PSL_DoubleClick = Edit
PSL_CustomDoubleClick =
PSL_CustomDoubleClick =
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick =
TEXT_CustomDoubleClick =
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick =
SYSTEMC_CustomDoubleClick =
TCL_DoubleClick = Edit
TCL_CustomDoubleClick =
TCL_CustomDoubleClick =
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick =
MACRO_CustomDoubleClick =
VCD_DoubleClick = Edit
VCD_CustomDoubleClick =
VCD_CustomDoubleClick =
SDF_DoubleClick = Edit
SDF_CustomDoubleClick =
SDF_CustomDoubleClick =
XML_DoubleClick = Edit
XML_CustomDoubleClick =
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
UCDB_CustomDoubleClick =
UPF_DoubleClick = Edit
UPF_CustomDoubleClick =
UPF_CustomDoubleClick =
PCF_DoubleClick = Edit
PCF_CustomDoubleClick =
PCF_CustomDoubleClick =
PROJECT_DoubleClick = Edit
PROJECT_CustomDoubleClick =
PROJECT_CustomDoubleClick =
VRM_DoubleClick = Edit
VRM_CustomDoubleClick =
VRM_CustomDoubleClick =
DEBUGDATABASE_DoubleClick = Edit
DEBUGDATABASE_CustomDoubleClick =
DEBUGDATABASE_CustomDoubleClick =
DEBUGARCHIVE_DoubleClick = Edit
DEBUGARCHIVE_CustomDoubleClick =
DEBUGARCHIVE_CustomDoubleClick =
Project_Major_Version = 10
Project_Minor_Version = 1
/simulation/modelsim/wave_fuse.do
58,7 → 58,6
add wave -noupdate -group sequencer -expand -group M /test_fuse/dut/sequencer_/M3
add wave -noupdate -group sequencer -expand -group M /test_fuse/dut/sequencer_/M4
add wave -noupdate -group sequencer -expand -group M /test_fuse/dut/sequencer_/M5
add wave -noupdate -group sequencer -expand -group M /test_fuse/dut/sequencer_/M6
add wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T1
add wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T2
add wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T3
65,14 → 64,13
add wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T4
add wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T5
add wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T6
add wave -noupdate -group opcode /test_fuse/dut/instruction_reg_/ctl_ir_we
add wave -noupdate -group opcode /test_fuse/dut/instruction_reg_/opcode
add wave -noupdate -group opcode /test_fuse/dut/ir_/ctl_ir_we
add wave -noupdate -group opcode /test_fuse/dut/ir_/opcode
add wave -noupdate -group db -radix hexadecimal /test_fuse/dut/db0
add wave -noupdate -group db -radix hexadecimal /test_fuse/dut/db1
add wave -noupdate -group db -radix hexadecimal /test_fuse/dut/db2
add wave -noupdate -group {bus control} /test_fuse/dut/bus_control_/ctl_bus_ff_oe
add wave -noupdate -group {bus control} /test_fuse/dut/bus_control_/ctl_bus_zero_oe
add wave -noupdate -group {bus control} /test_fuse/dut/bus_control_/ctl_bus_db_oe
add wave -noupdate -group {bus control} /test_fuse/dut/pin_control_/bus_ab_pin_we
add wave -noupdate -group {bus control} /test_fuse/dut/pin_control_/bus_db_pin_oe
add wave -noupdate -group {bus control} /test_fuse/dut/pin_control_/bus_db_pin_re
154,6 → 152,8
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_wz
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_ir
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_pc
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sw_4d_lo
add wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sw_4d_hi
add wave -noupdate -group regfile -radix hexadecimal /test_fuse/dut/reg_file_/db_hi_as
add wave -noupdate -group regfile -radix hexadecimal -childformat {{{/test_fuse/dut/reg_file_/db_lo_as[7]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[6]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[5]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[4]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[3]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[2]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[1]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[0]} -radix hexadecimal}} -subitemconfig {{/test_fuse/dut/reg_file_/db_lo_as[7]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[6]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[5]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[4]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[3]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[2]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[1]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[0]} {-height 15 -radix hexadecimal}} /test_fuse/dut/reg_file_/db_lo_as
add wave -noupdate -group switch /test_fuse/dut/bus_switch_/ctl_sw_mask543_en
161,12 → 161,12
add wave -noupdate -group switch /test_fuse/dut/bus_switch_/ctl_sw_1d
add wave -noupdate -group switch /test_fuse/dut/bus_switch_/ctl_sw_2u
add wave -noupdate -group switch /test_fuse/dut/bus_switch_/ctl_sw_2d
add wave -noupdate -group switch -color Aquamarine /test_fuse/dut/reg_file_/ctl_sw_4d
add wave -noupdate -group switch /test_fuse/dut/reg_control_/ctl_sw_4d
add wave -noupdate -group switch -color Aquamarine /test_fuse/dut/reg_file_/ctl_sw_4u
add wave -noupdate -group {data pins} /test_fuse/dut/data_pins_/bus_db_pin_oe
add wave -noupdate -group {data pins} /test_fuse/dut/data_pins_/bus_db_pin_re
add wave -noupdate -group {data pins} /test_fuse/dut/data_pins_/ctl_bus_db_we
add wave -noupdate -group {data pins} /test_fuse/dut/data_pins_/bus_db_oe
add wave -noupdate -group {data pins} /test_fuse/dut/data_pins_/ctl_bus_db_oe
add wave -noupdate -group {data pins} -radix hexadecimal /test_fuse/dut/data_pins_/D
add wave -noupdate -group {data pins} -radix hexadecimal /test_fuse/dut/data_pins_/db
add wave -noupdate -group {alu
370,7 → 370,7
} -radix hexadecimal /test_fuse/dut/alu_/op2_low
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_inc_cy
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_inc_dec
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_inc_zero
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/clrpc
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_al_we
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_inc_limit6
add wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_bus_inc_oe
/simulation/modelsim/wave_top.do
58,7 → 58,6
add wave -noupdate -group sequencer -expand -group M /test_top/dut/sequencer_/M3
add wave -noupdate -group sequencer -expand -group M /test_top/dut/sequencer_/M4
add wave -noupdate -group sequencer -expand -group M /test_top/dut/sequencer_/M5
add wave -noupdate -group sequencer -expand -group M /test_top/dut/sequencer_/M6
add wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T1
add wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T2
add wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T3
65,14 → 64,13
add wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T4
add wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T5
add wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T6
add wave -noupdate -group opcode /test_top/dut/instruction_reg_/ctl_ir_we
add wave -noupdate -group opcode /test_top/dut/instruction_reg_/opcode
add wave -noupdate -group opcode /test_top/dut/ir_/ctl_ir_we
add wave -noupdate -group opcode /test_top/dut/ir_/opcode
add wave -noupdate -group db -radix hexadecimal /test_top/dut/db0
add wave -noupdate -group db -radix hexadecimal /test_top/dut/db1
add wave -noupdate -group db -radix hexadecimal /test_top/dut/db2
add wave -noupdate -group {bus control} /test_top/dut/bus_control_/ctl_bus_ff_oe
add wave -noupdate -group {bus control} /test_top/dut/bus_control_/ctl_bus_zero_oe
add wave -noupdate -group {bus control} /test_top/dut/bus_control_/ctl_bus_db_oe
add wave -noupdate -group {bus control} /test_top/dut/pin_control_/bus_ab_pin_we
add wave -noupdate -group {bus control} /test_top/dut/pin_control_/bus_db_pin_oe
add wave -noupdate -group {bus control} /test_top/dut/pin_control_/bus_db_pin_re
154,6 → 152,8
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_wz
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_ir
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_pc
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sw_4d_lo
add wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sw_4d_hi
add wave -noupdate -group regfile -radix hexadecimal /test_top/dut/reg_file_/db_hi_as
add wave -noupdate -group regfile -radix hexadecimal -childformat {{{/test_top/dut/reg_file_/db_lo_as[7]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[6]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[5]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[4]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[3]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[2]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[1]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[0]} -radix hexadecimal}} -subitemconfig {{/test_top/dut/reg_file_/db_lo_as[7]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[6]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[5]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[4]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[3]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[2]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[1]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[0]} {-height 15 -radix hexadecimal}} /test_top/dut/reg_file_/db_lo_as
add wave -noupdate -group switch /test_top/dut/bus_switch_/ctl_sw_mask543_en
161,12 → 161,12
add wave -noupdate -group switch /test_top/dut/bus_switch_/ctl_sw_1d
add wave -noupdate -group switch /test_top/dut/bus_switch_/ctl_sw_2u
add wave -noupdate -group switch /test_top/dut/bus_switch_/ctl_sw_2d
add wave -noupdate -group switch -color Aquamarine /test_top/dut/reg_file_/ctl_sw_4d
add wave -noupdate -group switch /test_top/dut/reg_control_/ctl_sw_4d
add wave -noupdate -group switch -color Aquamarine /test_top/dut/reg_file_/ctl_sw_4u
add wave -noupdate -group {data pins} /test_top/dut/data_pins_/bus_db_pin_oe
add wave -noupdate -group {data pins} /test_top/dut/data_pins_/bus_db_pin_re
add wave -noupdate -group {data pins} /test_top/dut/data_pins_/ctl_bus_db_we
add wave -noupdate -group {data pins} /test_top/dut/data_pins_/bus_db_oe
add wave -noupdate -group {data pins} /test_top/dut/data_pins_/ctl_bus_db_oe
add wave -noupdate -group {data pins} -radix hexadecimal /test_top/dut/data_pins_/D
add wave -noupdate -group {data pins} -radix hexadecimal /test_top/dut/data_pins_/db
add wave -noupdate -group {alu
370,7 → 370,7
} -radix hexadecimal /test_top/dut/alu_/op2_low
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_inc_cy
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_inc_dec
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_inc_zero
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/clrpc
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_al_we
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_inc_limit6
add wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_bus_inc_oe
/toplevel.bdf
674,7 → 674,6
(block_io "M3" (input))
(block_io "M4" (input))
(block_io "M5" (input))
(block_io "M6" (input))
(block_io "T1" (input))
(block_io "T2" (input))
(block_io "T3" (input))
1044,7 → 1043,6
(block_io "M3" (output))
(block_io "M4" (output))
(block_io "M5" (output))
(block_io "M6" (output))
(block_io "T1" (output))
(block_io "T2" (output))
(block_io "T3" (output))
/test_top.sv
13,10 → 13,8
z.nINT <= `CLR;
z.nNMI <= `CLR;
z.nBUSRQ <= `CLR;
force dut.z80_top_ifc_n.fpga_reset=1;
z.nRESET <= `SET;
#2 force dut.z80_top_ifc_n.fpga_reset=0;
repeat (3) @(posedge clk);
#2 repeat (3) @(posedge clk);
z.nRESET <= `CLR;
end : init
 
/coremodules.vh
0,0 → 1,559
// Automatically generated by gencoremodules.py
 
clk_delay clk_delay_(
.clk (clk),
.in_intr (in_intr),
.nreset (nreset),
.T1 (T1),
.latch_wait (latch_wait),
.mwait (mwait),
.M1 (M1),
.busrq (busrq),
.setM1 (setM1),
.hold_clk_iorq (hold_clk_iorq),
.hold_clk_wait (hold_clk_wait),
.iorq_Tw (iorq_Tw),
.busack (busack),
.pin_control_oe (pin_control_oe),
.hold_clk_busrq (hold_clk_busrq)
);
 
decode_state decode_state_(
.ctl_state_iy_set (ctl_state_iy_set),
.ctl_state_ixiy_clr (ctl_state_ixiy_clr),
.ctl_state_ixiy_we (ctl_state_ixiy_we),
.ctl_state_halt_set (ctl_state_halt_set),
.ctl_state_tbl_clr (ctl_state_tbl_clr),
.ctl_state_tbl_ed_set (ctl_state_tbl_ed_set),
.ctl_state_tbl_cb_set (ctl_state_tbl_cb_set),
.ctl_state_alu (ctl_state_alu),
.clk (clk),
.address_is_1 (address_is_1),
.ctl_repeat_we (ctl_repeat_we),
.in_intr (in_intr),
.in_nmi (in_nmi),
.nreset (nreset),
.in_halt (in_halt),
.table_cb (table_cb),
.table_ed (table_ed),
.table_xx (table_xx),
.use_ix (use_ix),
.use_ixiy (use_ixiy),
.in_alu (in_alu),
.repeat_en (repeat_en)
);
 
execute execute_(
.ctl_state_iy_set (ctl_state_iy_set),
.ctl_state_ixiy_clr (ctl_state_ixiy_clr),
.ctl_state_ixiy_we (ctl_state_ixiy_we),
.ctl_state_halt_set (ctl_state_halt_set),
.ctl_state_tbl_clr (ctl_state_tbl_clr),
.ctl_state_tbl_ed_set (ctl_state_tbl_ed_set),
.ctl_state_tbl_cb_set (ctl_state_tbl_cb_set),
.ctl_state_alu (ctl_state_alu),
.ctl_repeat_we (ctl_repeat_we),
.ctl_iff1_iff2 (ctl_iff1_iff2),
.ctl_iffx_we (ctl_iffx_we),
.ctl_iffx_bit (ctl_iffx_bit),
.ctl_im_we (ctl_im_we),
.ctl_no_ints (ctl_no_ints),
.ctl_ir_we (ctl_ir_we),
.ctl_mRead (ctl_mRead),
.ctl_mWrite (ctl_mWrite),
.ctl_iorw (ctl_iorw),
.ctl_shift_en (ctl_shift_en),
.ctl_daa_oe (ctl_daa_oe),
.ctl_alu_op_low (ctl_alu_op_low),
.ctl_cond_short (ctl_cond_short),
.ctl_alu_core_hf (ctl_alu_core_hf),
.ctl_eval_cond (ctl_eval_cond),
.ctl_66_oe (ctl_66_oe),
.ctl_pf_sel (ctl_pf_sel),
.ctl_alu_oe (ctl_alu_oe),
.ctl_alu_shift_oe (ctl_alu_shift_oe),
.ctl_alu_op2_oe (ctl_alu_op2_oe),
.ctl_alu_res_oe (ctl_alu_res_oe),
.ctl_alu_op1_oe (ctl_alu_op1_oe),
.ctl_alu_bs_oe (ctl_alu_bs_oe),
.ctl_alu_op1_sel_bus (ctl_alu_op1_sel_bus),
.ctl_alu_op1_sel_low (ctl_alu_op1_sel_low),
.ctl_alu_op1_sel_zero (ctl_alu_op1_sel_zero),
.ctl_alu_op2_sel_zero (ctl_alu_op2_sel_zero),
.ctl_alu_op2_sel_bus (ctl_alu_op2_sel_bus),
.ctl_alu_op2_sel_lq (ctl_alu_op2_sel_lq),
.ctl_alu_sel_op2_neg (ctl_alu_sel_op2_neg),
.ctl_alu_sel_op2_high (ctl_alu_sel_op2_high),
.ctl_alu_core_R (ctl_alu_core_R),
.ctl_alu_core_V (ctl_alu_core_V),
.ctl_alu_core_S (ctl_alu_core_S),
.ctl_flags_oe (ctl_flags_oe),
.ctl_flags_bus (ctl_flags_bus),
.ctl_flags_alu (ctl_flags_alu),
.ctl_flags_nf_set (ctl_flags_nf_set),
.ctl_flags_cf_set (ctl_flags_cf_set),
.ctl_flags_cf_cpl (ctl_flags_cf_cpl),
.ctl_flags_cf_we (ctl_flags_cf_we),
.ctl_flags_sz_we (ctl_flags_sz_we),
.ctl_flags_xy_we (ctl_flags_xy_we),
.ctl_flags_hf_we (ctl_flags_hf_we),
.ctl_flags_pf_we (ctl_flags_pf_we),
.ctl_flags_nf_we (ctl_flags_nf_we),
.ctl_flags_cf2_we (ctl_flags_cf2_we),
.ctl_flags_hf_cpl (ctl_flags_hf_cpl),
.ctl_flags_use_cf2 (ctl_flags_use_cf2),
.ctl_flags_hf2_we (ctl_flags_hf2_we),
.ctl_flags_nf_clr (ctl_flags_nf_clr),
.ctl_alu_zero_16bit (ctl_alu_zero_16bit),
.ctl_flags_cf2_sel_shift (ctl_flags_cf2_sel_shift),
.ctl_flags_cf2_sel_daa (ctl_flags_cf2_sel_daa),
.ctl_sw_4u (ctl_sw_4u),
.ctl_reg_in_hi (ctl_reg_in_hi),
.ctl_reg_in_lo (ctl_reg_in_lo),
.ctl_reg_out_lo (ctl_reg_out_lo),
.ctl_reg_out_hi (ctl_reg_out_hi),
.ctl_reg_exx (ctl_reg_exx),
.ctl_reg_ex_af (ctl_reg_ex_af),
.ctl_reg_ex_de_hl (ctl_reg_ex_de_hl),
.ctl_reg_use_sp (ctl_reg_use_sp),
.ctl_reg_sel_pc (ctl_reg_sel_pc),
.ctl_reg_sel_ir (ctl_reg_sel_ir),
.ctl_reg_sel_wz (ctl_reg_sel_wz),
.ctl_reg_gp_we (ctl_reg_gp_we),
.ctl_reg_not_pc (ctl_reg_not_pc),
.ctl_reg_sys_we_lo (ctl_reg_sys_we_lo),
.ctl_reg_sys_we_hi (ctl_reg_sys_we_hi),
.ctl_reg_sys_we (ctl_reg_sys_we),
.ctl_sw_4d (ctl_sw_4d),
.ctl_reg_gp_hilo (ctl_reg_gp_hilo),
.ctl_reg_gp_sel (ctl_reg_gp_sel),
.ctl_reg_sys_hilo (ctl_reg_sys_hilo),
.ctl_inc_cy (ctl_inc_cy),
.ctl_inc_dec (ctl_inc_dec),
.ctl_al_we (ctl_al_we),
.ctl_inc_limit6 (ctl_inc_limit6),
.ctl_bus_inc_oe (ctl_bus_inc_oe),
.ctl_apin_mux (ctl_apin_mux),
.ctl_apin_mux2 (ctl_apin_mux2),
.ctl_bus_ff_oe (ctl_bus_ff_oe),
.ctl_bus_zero_oe (ctl_bus_zero_oe),
.ctl_sw_1u (ctl_sw_1u),
.ctl_sw_1d (ctl_sw_1d),
.ctl_sw_2u (ctl_sw_2u),
.ctl_sw_2d (ctl_sw_2d),
.ctl_sw_mask543_en (ctl_sw_mask543_en),
.ctl_bus_db_we (ctl_bus_db_we),
.ctl_bus_db_oe (ctl_bus_db_oe),
.nextM (nextM),
.setM1 (setM1),
.fFetch (fFetch),
.fMRead (fMRead),
.fMWrite (fMWrite),
.fIORead (fIORead),
.fIOWrite (fIOWrite),
.pla (pla),
.in_intr (in_intr),
.in_nmi (in_nmi),
.in_halt (in_halt),
.im1 (im1),
.im2 (im2),
.use_ixiy (use_ixiy),
.flags_cond_true (flags_cond_true),
.repeat_en (repeat_en),
.flags_zf (flags_zf),
.flags_nf (flags_nf),
.flags_sf (flags_sf),
.flags_cf (flags_cf),
.M1 (M1),
.M2 (M2),
.M3 (M3),
.M4 (M4),
.M5 (M5),
.T1 (T1),
.T2 (T2),
.T3 (T3),
.T4 (T4),
.T5 (T5),
.T6 (T6)
);
 
interrupts interrupts_(
.ctl_iff1_iff2 (ctl_iff1_iff2),
.nmi (nmi),
.setM1 (setM1),
.intr (intr),
.ctl_iffx_we (ctl_iffx_we),
.ctl_iffx_bit (ctl_iffx_bit),
.ctl_im_we (ctl_im_we),
.clk (clk),
.ctl_no_ints (ctl_no_ints),
.nreset (nreset),
.db (db0[4:3]),
.iff2 (iff2),
.im1 (im1),
.im2 (im2),
.in_nmi (in_nmi),
.in_intr (in_intr)
);
 
ir ir_(
.ctl_ir_we (ctl_ir_we),
.clk (clk),
.nreset (nreset),
.db (db0[7:0]),
.opcode (opcode)
);
 
pin_control pin_control_(
.fFetch (fFetch),
.fMRead (fMRead),
.fMWrite (fMWrite),
.fIORead (fIORead),
.fIOWrite (fIOWrite),
.T1 (T1),
.T2 (T2),
.T3 (T3),
.T4 (T4),
.bus_ab_pin_we (bus_ab_pin_we),
.bus_db_pin_oe (bus_db_pin_oe),
.bus_db_pin_re (bus_db_pin_re)
);
 
pla_decode pla_decode_(
.prefix (prefix),
.opcode (opcode),
.pla (pla)
);
 
resets resets_(
.reset_in (reset_in),
.clk (clk),
.M1 (M1),
.T2 (T2),
.fpga_reset (fpga_reset),
.clrpc (clrpc),
.nreset (nreset)
);
 
memory_ifc memory_ifc_(
.clk (clk),
.nM1_int (nM1_int),
.ctl_mRead (ctl_mRead),
.ctl_mWrite (ctl_mWrite),
.in_intr (in_intr),
.nreset (nreset),
.fIORead (fIORead),
.fIOWrite (fIOWrite),
.setM1 (setM1),
.ctl_iorw (ctl_iorw),
.timings_en (timings_en),
.iorq_Tw (iorq_Tw),
.hold_clk_wait (hold_clk_wait),
.nM1_out (nM1_out),
.nRFSH_out (nRFSH_out),
.nMREQ_out (nMREQ_out),
.nRD_out (nRD_out),
.nWR_out (nWR_out),
.nIORQ_out (nIORQ_out),
.latch_wait (latch_wait)
);
 
sequencer sequencer_(
.clk (clk),
.nextM (nextM),
.setM1 (setM1),
.nreset (nreset),
.hold_clk_iorq (hold_clk_iorq),
.hold_clk_wait (hold_clk_wait),
.hold_clk_busrq (hold_clk_busrq),
.M1 (M1),
.M2 (M2),
.M3 (M3),
.M4 (M4),
.M5 (M5),
.T1 (T1),
.T2 (T2),
.T3 (T3),
.T4 (T4),
.T5 (T5),
.T6 (T6),
.timings_en (timings_en)
);
 
alu_control alu_control_(
.alu_shift_db0 (alu_shift_db0),
.alu_shift_db7 (alu_shift_db7),
.ctl_shift_en (ctl_shift_en),
.alu_low_gt_9 (alu_low_gt_9),
.alu_high_gt_9 (alu_high_gt_9),
.alu_high_eq_9 (alu_high_eq_9),
.ctl_daa_oe (ctl_daa_oe),
.ctl_alu_op_low (ctl_alu_op_low),
.alu_parity_out (alu_parity_out),
.flags_cf (flags_cf),
.flags_zf (flags_zf),
.flags_pf (flags_pf),
.flags_sf (flags_sf),
.ctl_cond_short (ctl_cond_short),
.alu_vf_out (alu_vf_out),
.iff2 (iff2),
.ctl_alu_core_hf (ctl_alu_core_hf),
.ctl_eval_cond (ctl_eval_cond),
.repeat_en (repeat_en),
.flags_cf_latch (flags_cf_latch),
.flags_hf2 (flags_hf2),
.flags_hf (flags_hf),
.ctl_66_oe (ctl_66_oe),
.clk (clk),
.ctl_pf_sel (ctl_pf_sel),
.op543 ({pla[104],pla[103],pla[102]}),
.alu_shift_in (alu_shift_in),
.alu_shift_right (alu_shift_right),
.alu_shift_left (alu_shift_left),
.shift_cf_out (shift_cf_out),
.alu_parity_in (alu_parity_in),
.flags_cond_true (flags_cond_true),
.daa_cf_out (daa_cf_out),
.pf_sel (pf_sel),
.alu_op_low (alu_op_low),
.alu_core_cf_in (alu_core_cf_in),
.db (db1[7:0])
);
 
alu_select alu_select_(
.ctl_alu_oe (ctl_alu_oe),
.ctl_alu_shift_oe (ctl_alu_shift_oe),
.ctl_alu_op2_oe (ctl_alu_op2_oe),
.ctl_alu_res_oe (ctl_alu_res_oe),
.ctl_alu_op1_oe (ctl_alu_op1_oe),
.ctl_alu_bs_oe (ctl_alu_bs_oe),
.ctl_alu_op1_sel_bus (ctl_alu_op1_sel_bus),
.ctl_alu_op1_sel_low (ctl_alu_op1_sel_low),
.ctl_alu_op1_sel_zero (ctl_alu_op1_sel_zero),
.ctl_alu_op2_sel_zero (ctl_alu_op2_sel_zero),
.ctl_alu_op2_sel_bus (ctl_alu_op2_sel_bus),
.ctl_alu_op2_sel_lq (ctl_alu_op2_sel_lq),
.ctl_alu_sel_op2_neg (ctl_alu_sel_op2_neg),
.ctl_alu_sel_op2_high (ctl_alu_sel_op2_high),
.ctl_alu_core_R (ctl_alu_core_R),
.ctl_alu_core_V (ctl_alu_core_V),
.ctl_alu_core_S (ctl_alu_core_S),
.alu_oe (alu_oe),
.alu_shift_oe (alu_shift_oe),
.alu_op2_oe (alu_op2_oe),
.alu_res_oe (alu_res_oe),
.alu_op1_oe (alu_op1_oe),
.alu_bs_oe (alu_bs_oe),
.alu_op1_sel_bus (alu_op1_sel_bus),
.alu_op1_sel_low (alu_op1_sel_low),
.alu_op1_sel_zero (alu_op1_sel_zero),
.alu_op2_sel_zero (alu_op2_sel_zero),
.alu_op2_sel_bus (alu_op2_sel_bus),
.alu_op2_sel_lq (alu_op2_sel_lq),
.alu_sel_op2_neg (alu_sel_op2_neg),
.alu_sel_op2_high (alu_sel_op2_high),
.alu_core_R (alu_core_R),
.alu_core_V (alu_core_V),
.alu_core_S (alu_core_S)
);
 
alu_flags alu_flags_(
.ctl_flags_oe (ctl_flags_oe),
.ctl_flags_bus (ctl_flags_bus),
.ctl_flags_alu (ctl_flags_alu),
.alu_sf_out (alu_sf_out),
.alu_yf_out (alu_yf_out),
.alu_xf_out (alu_xf_out),
.ctl_flags_nf_set (ctl_flags_nf_set),
.alu_zero (alu_zero),
.shift_cf_out (shift_cf_out),
.alu_core_cf_out (alu_core_cf_out),
.daa_cf_out (daa_cf_out),
.ctl_flags_cf_set (ctl_flags_cf_set),
.ctl_flags_cf_cpl (ctl_flags_cf_cpl),
.pf_sel (pf_sel),
.ctl_flags_cf_we (ctl_flags_cf_we),
.ctl_flags_sz_we (ctl_flags_sz_we),
.ctl_flags_xy_we (ctl_flags_xy_we),
.ctl_flags_hf_we (ctl_flags_hf_we),
.ctl_flags_pf_we (ctl_flags_pf_we),
.ctl_flags_nf_we (ctl_flags_nf_we),
.ctl_flags_cf2_we (ctl_flags_cf2_we),
.ctl_flags_hf_cpl (ctl_flags_hf_cpl),
.ctl_flags_use_cf2 (ctl_flags_use_cf2),
.ctl_flags_hf2_we (ctl_flags_hf2_we),
.ctl_flags_nf_clr (ctl_flags_nf_clr),
.ctl_alu_zero_16bit (ctl_alu_zero_16bit),
.clk (clk),
.ctl_flags_cf2_sel_shift (ctl_flags_cf2_sel_shift),
.ctl_flags_cf2_sel_daa (ctl_flags_cf2_sel_daa),
.flags_sf (flags_sf),
.flags_zf (flags_zf),
.flags_hf (flags_hf),
.flags_pf (flags_pf),
.flags_cf (flags_cf),
.flags_nf (flags_nf),
.flags_cf_latch (flags_cf_latch),
.flags_hf2 (flags_hf2),
.db (db1[7:0])
);
 
alu alu_(
.alu_core_R (alu_core_R),
.alu_core_V (alu_core_V),
.alu_core_S (alu_core_S),
.alu_bs_oe (alu_bs_oe),
.alu_parity_in (alu_parity_in),
.alu_oe (alu_oe),
.alu_shift_oe (alu_shift_oe),
.alu_core_cf_in (alu_core_cf_in),
.alu_op2_oe (alu_op2_oe),
.alu_op1_oe (alu_op1_oe),
.alu_res_oe (alu_res_oe),
.alu_op1_sel_low (alu_op1_sel_low),
.alu_op1_sel_zero (alu_op1_sel_zero),
.alu_op1_sel_bus (alu_op1_sel_bus),
.alu_op2_sel_zero (alu_op2_sel_zero),
.alu_op2_sel_bus (alu_op2_sel_bus),
.alu_op2_sel_lq (alu_op2_sel_lq),
.alu_op_low (alu_op_low),
.alu_shift_in (alu_shift_in),
.alu_sel_op2_neg (alu_sel_op2_neg),
.alu_sel_op2_high (alu_sel_op2_high),
.alu_shift_left (alu_shift_left),
.alu_shift_right (alu_shift_right),
.clk (clk),
.bsel (db0[5:3]),
.alu_zero (alu_zero),
.alu_parity_out (alu_parity_out),
.alu_high_eq_9 (alu_high_eq_9),
.alu_high_gt_9 (alu_high_gt_9),
.alu_low_gt_9 (alu_low_gt_9),
.alu_shift_db0 (alu_shift_db0),
.alu_shift_db7 (alu_shift_db7),
.alu_core_cf_out (alu_core_cf_out),
.alu_sf_out (alu_sf_out),
.alu_yf_out (alu_yf_out),
.alu_xf_out (alu_xf_out),
.alu_vf_out (alu_vf_out),
.db (db2[7:0]),
.test_db_high (test_db_high),
.test_db_low (test_db_low)
);
 
reg_file reg_file_(
.reg_sel_sys_lo (reg_sel_sys_lo),
.reg_sel_gp_lo (reg_sel_gp_lo),
.reg_sel_sys_hi (reg_sel_sys_hi),
.reg_sel_gp_hi (reg_sel_gp_hi),
.reg_sel_ir (reg_sel_ir),
.reg_sel_pc (reg_sel_pc),
.ctl_sw_4u (ctl_sw_4u),
.reg_sel_wz (reg_sel_wz),
.reg_sel_sp (reg_sel_sp),
.reg_sel_iy (reg_sel_iy),
.reg_sel_ix (reg_sel_ix),
.reg_sel_hl2 (reg_sel_hl2),
.reg_sel_hl (reg_sel_hl),
.reg_sel_de2 (reg_sel_de2),
.reg_sel_de (reg_sel_de),
.reg_sel_bc2 (reg_sel_bc2),
.reg_sel_bc (reg_sel_bc),
.reg_sel_af2 (reg_sel_af2),
.reg_sel_af (reg_sel_af),
.reg_gp_we (reg_gp_we),
.reg_sys_we_lo (reg_sys_we_lo),
.reg_sys_we_hi (reg_sys_we_hi),
.ctl_reg_in_hi (ctl_reg_in_hi),
.ctl_reg_in_lo (ctl_reg_in_lo),
.ctl_reg_out_lo (ctl_reg_out_lo),
.ctl_reg_out_hi (ctl_reg_out_hi),
.clk (clk),
.reg_sw_4d_lo (reg_sw_4d_lo),
.reg_sw_4d_hi (reg_sw_4d_hi),
.db_hi_as (db_hi_as[7:0]),
.db_hi_ds (db2[7:0]),
.db_lo_as (db_lo_as[7:0]),
.db_lo_ds (db1[7:0])
);
 
reg_control reg_control_(
.ctl_reg_exx (ctl_reg_exx),
.ctl_reg_ex_af (ctl_reg_ex_af),
.ctl_reg_ex_de_hl (ctl_reg_ex_de_hl),
.ctl_reg_use_sp (ctl_reg_use_sp),
.nreset (nreset),
.ctl_reg_sel_pc (ctl_reg_sel_pc),
.ctl_reg_sel_ir (ctl_reg_sel_ir),
.ctl_reg_sel_wz (ctl_reg_sel_wz),
.ctl_reg_gp_we (ctl_reg_gp_we),
.ctl_reg_not_pc (ctl_reg_not_pc),
.use_ixiy (use_ixiy),
.use_ix (use_ix),
.ctl_reg_sys_we_lo (ctl_reg_sys_we_lo),
.ctl_reg_sys_we_hi (ctl_reg_sys_we_hi),
.ctl_reg_sys_we (ctl_reg_sys_we),
.clk (clk),
.ctl_sw_4d (ctl_sw_4d),
.ctl_reg_gp_hilo (ctl_reg_gp_hilo),
.ctl_reg_gp_sel (ctl_reg_gp_sel),
.ctl_reg_sys_hilo (ctl_reg_sys_hilo),
.reg_sel_bc (reg_sel_bc),
.reg_sel_bc2 (reg_sel_bc2),
.reg_sel_ix (reg_sel_ix),
.reg_sel_iy (reg_sel_iy),
.reg_sel_de (reg_sel_de),
.reg_sel_hl (reg_sel_hl),
.reg_sel_de2 (reg_sel_de2),
.reg_sel_hl2 (reg_sel_hl2),
.reg_sel_af (reg_sel_af),
.reg_sel_af2 (reg_sel_af2),
.reg_sel_wz (reg_sel_wz),
.reg_sel_pc (reg_sel_pc),
.reg_sel_ir (reg_sel_ir),
.reg_sel_sp (reg_sel_sp),
.reg_sel_gp_hi (reg_sel_gp_hi),
.reg_sel_gp_lo (reg_sel_gp_lo),
.reg_sel_sys_lo (reg_sel_sys_lo),
.reg_sel_sys_hi (reg_sel_sys_hi),
.reg_gp_we (reg_gp_we),
.reg_sys_we_lo (reg_sys_we_lo),
.reg_sys_we_hi (reg_sys_we_hi),
.reg_sw_4d_lo (reg_sw_4d_lo),
.reg_sw_4d_hi (reg_sw_4d_hi)
);
 
address_latch address_latch_(
.ctl_inc_cy (ctl_inc_cy),
.ctl_inc_dec (ctl_inc_dec),
.ctl_al_we (ctl_al_we),
.ctl_inc_limit6 (ctl_inc_limit6),
.ctl_bus_inc_oe (ctl_bus_inc_oe),
.clk (clk),
.ctl_apin_mux (ctl_apin_mux),
.ctl_apin_mux2 (ctl_apin_mux2),
.clrpc (clrpc),
.nreset (nreset),
.address_is_1 (address_is_1),
.abus ({db_hi_as[7:0], db_lo_as[7:0]}),
.address (address)
);
 
bus_control bus_control_(
.ctl_bus_ff_oe (ctl_bus_ff_oe),
.ctl_bus_zero_oe (ctl_bus_zero_oe),
.db (db0[7:0])
);
 
bus_switch bus_switch_(
.ctl_sw_1u (ctl_sw_1u),
.ctl_sw_1d (ctl_sw_1d),
.ctl_sw_2u (ctl_sw_2u),
.ctl_sw_2d (ctl_sw_2d),
.ctl_sw_mask543_en (ctl_sw_mask543_en),
.bus_sw_1u (bus_sw_1u),
.bus_sw_1d (bus_sw_1d),
.bus_sw_2u (bus_sw_2u),
.bus_sw_2d (bus_sw_2d),
.bus_sw_mask543_en (bus_sw_mask543_en)
);
/globals.vh
80,8 → 80,8
wire ctl_flags_hf2_we;
wire ctl_flags_nf_clr;
wire ctl_alu_zero_16bit;
wire [1:0] ctl_flags_cf2_sel;
wire ctl_sw_4d;
wire ctl_flags_cf2_sel_shift;
wire ctl_flags_cf2_sel_daa;
wire ctl_sw_4u;
wire ctl_reg_in_hi;
wire ctl_reg_in_lo;
99,12 → 99,12
wire ctl_reg_sys_we_lo;
wire ctl_reg_sys_we_hi;
wire ctl_reg_sys_we;
wire ctl_sw_4d;
wire [1:0] ctl_reg_gp_hilo;
wire [1:0] ctl_reg_gp_sel;
wire [1:0] ctl_reg_sys_hilo;
wire ctl_inc_cy;
wire ctl_inc_dec;
wire ctl_inc_zero;
wire ctl_al_we;
wire ctl_inc_limit6;
wire ctl_bus_inc_oe;
112,7 → 112,6
wire ctl_apin_mux2;
wire ctl_bus_ff_oe;
wire ctl_bus_zero_oe;
wire ctl_bus_db_oe;
wire ctl_sw_1u;
wire ctl_sw_1d;
wire ctl_sw_2u;
119,8 → 118,9
wire ctl_sw_2d;
wire ctl_sw_mask543_en;
wire ctl_bus_db_we;
wire ctl_bus_db_oe;
 
// Module: control/execute.sv
// Module: control/execute.v
wire nextM;
wire setM1;
wire fFetch;
130,7 → 130,6
wire fIOWrite;
 
// Module: control/interrupts.v
wire iff1;
wire iff2;
wire im1;
wire im2;
145,7 → 144,7
wire bus_db_pin_oe;
wire bus_db_pin_re;
 
// Module: control/pla_decode.sv
// Module: control/pla_decode.v
wire [104:0] pla;
 
// Module: control/resets.v
167,7 → 166,6
wire M3;
wire M4;
wire M5;
wire M6;
wire T1;
wire T2;
wire T3;
256,6 → 254,8
wire reg_gp_we;
wire reg_sys_we_lo;
wire reg_sys_we_hi;
wire reg_sw_4d_lo;
wire reg_sw_4d_hi;
 
// Module: bus/address_latch.v
wire address_is_1;
264,10 → 264,7
// Module: bus/address_pins.v
wire [15:0] abus;
 
// Module: bus/bus_control.v
wire bus_db_oe;
 
// Module: bus/bus_switch.sv
// Module: bus/bus_switch.v
wire bus_sw_1u;
wire bus_sw_1d;
wire bus_sw_2u;
/gencoremodules.py
0,0 → 1,124
#!/usr/bin/env python3
#
# This script reads and parses all top-level modules and generates a core block
# file containing instantiation of these modules. This generated file is included
# by core.vh
#
#-------------------------------------------------------------------------------
# Copyright (C) 2016 Goran Devic
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the Free
# Software Foundation; either version 2 of the License, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details.
#-------------------------------------------------------------------------------
import os
 
# Define a set of module cross-connections. These are the chip's internal buses
# which we inject as connections as we generate a list of module instances
xconnections = [
['interrupts', 'db', 'db0[4:3]'],
['ir', 'db', 'db0[7:0]'],
['alu_control', 'db', 'db1[7:0]'],
['alu_control', 'op543', '{pla[104],pla[103],pla[102]}'],
['alu_flags', 'db', 'db1[7:0]'],
['alu', 'db', 'db2[7:0]'],
['alu', 'bsel', 'db0[5:3]'],
['reg_file', 'db_hi_ds', 'db2[7:0]'],
['reg_file', 'db_lo_ds', 'db1[7:0]'],
['reg_file', 'db_hi_as', 'db_hi_as[7:0]'],
['reg_file', 'db_lo_as', 'db_lo_as[7:0]'],
['address_latch', 'abus', '{db_hi_as[7:0], db_lo_as[7:0]}'],
['bus_control', 'db', 'db0[7:0]']
]
 
# Define a list of modules that are not used (but listed in 'top-level-files.txt' )
skip_modules = ['address_pins', 'data_pins', 'control_pins_n']
 
# For error-checking, make sure every xconnection entry has been utilized
xcount = len(xconnections)
 
def connect(module, wire):
global xcount
for xconnection in xconnections:
m, w, xcon = xconnection
if module==m and wire==w:
print("Cross-connecting:", module, wire, "->", xcon)
xcount -= 1
return xcon
return wire
 
def parse(wires, lines):
while(len(lines)>0 and lines[0].startswith(');')==False):
line = lines[0].strip()
lines.pop(0)
if len(line)==0 or line[0]=='(' or line[0]=='/':
continue
tokens = line.split()
if len(tokens)>=3 and tokens[0] in ['input', 'output']:
tokens.pop(0)
if len(tokens)>=2 and tokens[0] in ['wire', 'reg']:
tokens.pop(0)
if len(tokens)>=2 and tokens[0].startswith('['):
tokens.pop(0)
if len(tokens)>=2 and tokens[0]=='`include':
include_file = tokens[1].replace('"', '')
with open('../control/' + include_file) as f:
included_lines = f.read().splitlines()
parse(wires, included_lines)
continue
name = tokens[0]
if name.endswith(','):
name = name[:-1]
wires.append(name)
 
with open('../top-level-files.txt') as f:
files = f.read().splitlines()
 
# Create a file that should be included in the top-level core source
with open('coremodules.vh', 'w') as file1:
file1.write("// Automatically generated by gencoremodules.py\n")
 
# Read and parse each file from the list of input files
for infile in files:
if not os.path.isfile('../' + infile):
continue
with open('../' + infile, "r") as f:
lines = f.read().splitlines()
 
# Find 'module' section; read and generate instantiation statement
while(len(lines)>0 and lines[0].startswith('module ')==False):
lines.pop(0)
if len(lines)==0:
continue
 
module_name = lines[0].split()[1]
lines.pop(0)
if module_name.endswith('('):
module_name = module_name[:-1]
if module_name in skip_modules:
continue
 
# Read a list of input/output wires, one per line
wires = []
parse(wires, lines)
 
# Print the names of all parsed signals in a module instantiation format
with open('coremodules.vh', 'a') as file1:
file1.write("\n" + module_name + " " + module_name + "_(\n")
while(len(wires)>0):
wire = wires.pop(0)
terminator = ','
if len(wires)==0:
terminator = "\n);"
file1.write(" ." + wire + " (" + connect(module_name, wire) + ")" + terminator + "\n")
 
assert(xcount==0)
 
# Touch files that include 'coremodules.vh' to ensure it will recompile correctly
os.utime("core.vh", None)
/genglobals.py
1,4 → 1,4
#!/usr/bin/env python
#!/usr/bin/env python3
#
# This script reads and parses selected Verilog and SystemVerilog modules
# and generates a set of Verilog include files for the Z80 top-level block.
36,14 → 36,14
with open('../' + infile, "r") as f:
for line in f:
info = line.split()
if (len(info)>2):
if len(info)>2:
# There can be only one driver for each signal so we read only the outputs
if (info[0]=="output") and (info[1]=="wire" or info[1]=="reg" or info[1]=="logic"):
if info[0]=="output" and (info[1]=="wire" or info[1]=="reg" or info[1]=="logic"):
# There are 2 cases: wires and buses
if info[2].startswith('['):
wires.append(info[2] + ' ' + info[3].translate(None, ';,'))
wires.append(info[2] + ' ' + info[3].strip(';,'))
else:
wires.append(info[2].translate(None, ';,'))
wires.append(info[2].strip(';,'))
 
if len(wires)>0:
with open('globals.vh', 'a') as file1:
59,5 → 59,5
 
# Touch files that include 'globals.vh' to ensure it will recompile correctly
os.utime("core.vh", None)
os.utime("z80_top_direct_n.sv", None)
os.utime("z80_top_direct_n.v", None)
os.utime("z80_top_ifc_n.sv", None)
/core.vh
8,74 → 8,65
// Include a list of top-level signal wires
`include "globals.vh"
 
// Specific to Modelsim, some modules in the schematics need to be pre-initialized
// Specific to simulation, some modules in the schematics need to be pre-initialized
// to avoid starting simulations with unknown values in selected flip flops.
// When synthesized, the CPU RESET input signal will do the work.
reg fpga_reset = 0;
initial begin
fpga_reset = 1;
#1 fpga_reset = 0;
reg fpga_reset = 1;
always @(posedge clk)
begin
fpga_reset <= 0;
end
 
// Define internal data bus partitions separated by data bus switches
// Define internal data bus partitions segmented by data bus switches
wire [7:0] db0; // Segment connecting data pins and IR
wire [7:0] db1; // Segment with ALU
wire [7:0] db1; // Segment leading to the ALU
wire [7:0] db2; // Segment with msb part of the register address-side interface
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Control block
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Collect the PLA instruction decode prefix bitfield
logic [6:0] prefix;
wire [7:0] db_hi_as; // Register file data bus segment high byte
wire [7:0] db_lo_as; // Register file data bus segment low byte
 
wire [6:0] prefix; // Instruction decode PLA prefix bitfield
assign prefix = { ~use_ixiy, use_ixiy, ~in_halt, in_alu, table_xx, table_cb, table_ed };
 
ir instruction_reg_( .*, .db(db0[7:0]) );
pla_decode pla_decode_( .* );
resets reset_block_( .* );
sequencer sequencer_( .* );
wire nM1_int; // External pins timing control
assign nM1_int = !(setM1 | (fFetch & T1));
 
`include "coremodules.vh"
 
// Data path within the CPU in various forms, ending with data pins
data_switch sw2_( .sw_up_en(bus_sw_2u), .sw_down_en(bus_sw_2d), .db_up(db1[7:0]), .db_down(db2[7:0]) );
 
// Data switch SW1 with the data mask
data_switch_mask sw1_( .sw_mask543_en(bus_sw_mask543_en), .sw_up_en(bus_sw_1u), .sw_down_en(bus_sw_1d), .db_up(db0[7:0]), .db_down(db1[7:0]) );
 
/* This SystemVerilog-style code is kept for future reference
// Control block
clk_delay clk_delay_( .* );
decode_state decode_state_( .* );
execute execute_( .* );
interrupts interrupts_( .*, .db(db0[4:3]) );
decode_state decode_state_( .* );
clk_delay clk_delay_( .* );
ir ir_( .*, .db(db0[7:0]) );
pin_control pin_control_( .* );
pla_decode pla_decode_( .* );
resets resets_( .* );
sequencer sequencer_( .* );
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// ALU and ALU control, including the flags
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
alu_control alu_control_( .*, .db(db1[7:0]), .op543({pla[104],pla[103],pla[102]}) );
alu_select alu_select_( .* );
alu_flags alu_flags_( .*, .db(db1[7:0]) );
alu alu_( .*, .db(db2[7:0]), .bsel(db0[5:3]) );
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Register file and register control
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wire [7:0] db_hi_as;
wire [7:0] db_lo_as;
 
reg_file reg_file_( .*, .db_hi_ds(db2[7:0]), .db_lo_ds(db1[7:0]), .db_hi_as(db_hi_as[7:0]), .db_lo_as(db_lo_as[7:0]) );
reg_control reg_control_( .* );
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Address latch (with the incrementer)
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Address latch and the incrementer
address_latch address_latch_( .*, .abus({db_hi_as[7:0], db_lo_as[7:0]}) );
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Misc bus
bus_control bus_control_( .*, .db(db0[7:0]) );
bus_switch bus_switch_( .* );
 
// Timing control of the external pins
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wire nM1_int;
assign nM1_int = !((setM1 & nextM) | (fFetch & T1));
memory_ifc memory_ifc_( .* );
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Data path within the CPU in various forms, ending with data pins
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
bus_switch bus_switch_( .* );
data_switch sw2_( .sw_up_en(bus_sw_2u), .sw_down_en(bus_sw_2d), .db_up(db1[7:0]), .db_down(db2[7:0]) );
 
// Controls writers to the first section of the data bus
bus_control bus_control_( .*, .db(db0[7:0]) );
 
// Data switch SW1 with the data mask
data_switch_mask sw1_( .sw_mask543_en(bus_sw_mask543_en), .sw_up_en(bus_sw_1u), .sw_down_en(bus_sw_1d), .db_up(db0[7:0]), .db_down(db1[7:0]) );
*/
/test_fuse.vh
1,14 → 1,15
// Automatically generated by genfuse.py
 
force dut.resets_.clrpc=0;
force dut.reg_file_.reg_gp_we=0;
force dut.reg_control_.ctl_reg_sys_we=0;
force dut.z80_top_ifc_n.fpga_reset=1;
#2
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 00 NOP");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
139,11 → 140,11
// Preset memory
ram.Mem[0] = 8'h00;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#6 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
177,10 → 178,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode ed67 RRD");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
314,11 → 315,11
// Preset memory
ram.Mem[47582] = 8'h93;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#34 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
353,10 → 354,10
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
if (ram.Mem[47582]!==8'h69) $fdisplay(f,"* Mem[b9de]=%h !=69",ram.Mem[47582]);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode ed6f RLD");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
490,11 → 491,11
// Preset memory
ram.Mem[16444] = 8'hc4;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#34 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
529,10 → 530,10
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
if (ram.Mem[16444]!==8'h45) $fdisplay(f,"* Mem[403c]=%h !=45",ram.Mem[16444]);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 81 ADD A,C");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
665,11 → 666,11
// Preset memory
ram.Mem[56486] = 8'h49;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#6 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
703,10 → 704,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode cb41 BIT 0,C");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
840,11 → 841,11
// Preset memory
ram.Mem[31721] = 8'hf7;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#14 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
878,10 → 879,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode cb93 RES 2,E");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
1015,11 → 1016,11
// Preset memory
ram.Mem[8756] = 8'ha0;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#14 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
1053,10 → 1054,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode cbe5 SET 4,L");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
1190,11 → 1191,11
// Preset memory
ram.Mem[46223] = 8'hcf;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#14 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
1228,10 → 1229,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 8c ADC A,H");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
1364,11 → 1365,11
// Preset memory
ram.Mem[56486] = 8'h49;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#6 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
1402,10 → 1403,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 92 SUB D");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
1538,11 → 1539,11
// Preset memory
ram.Mem[56486] = 8'h49;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#6 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
1576,10 → 1577,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 9d SBC A,L");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
1712,11 → 1713,11
// Preset memory
ram.Mem[56486] = 8'h49;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#6 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
1750,10 → 1751,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode a3 AND E");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
1886,11 → 1887,11
// Preset memory
ram.Mem[56486] = 8'h49;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#6 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
1924,10 → 1925,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode ae XOR (HL)");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
2060,11 → 2061,11
// Preset memory
ram.Mem[56486] = 8'h49;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#12 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
2098,10 → 2099,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode b4 OR H");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
2234,11 → 2235,11
// Preset memory
ram.Mem[56486] = 8'h49;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#6 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
2272,10 → 2273,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode bf CP A");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
2408,11 → 2409,11
// Preset memory
ram.Mem[56486] = 8'h49;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#6 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
2446,10 → 2447,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 43 LD B,E");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
2582,11 → 2583,11
// Preset memory
ram.Mem[41321] = 8'h50;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#6 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
2620,10 → 2621,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 6e LD L,(HL)");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
2756,11 → 2757,11
// Preset memory
ram.Mem[41321] = 8'h50;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#12 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
2794,10 → 2795,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode e3 EX (SP),HL");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
2931,11 → 2932,11
ram.Mem[883] = 8'h8e;
ram.Mem[884] = 8'he1;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#36 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
2971,10 → 2972,10
if (ram.Mem[883]!==8'h22) $fdisplay(f,"* Mem[373]=%h !=22",ram.Mem[883]);
if (ram.Mem[884]!==8'h4d) $fdisplay(f,"* Mem[374]=%h !=4d",ram.Mem[884]);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 03 INC BC");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
3105,11 → 3106,11
// Preset memory
ram.Mem[0] = 8'h03;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#10 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
3143,10 → 3144,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 3b DEC SP");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
3277,11 → 3278,11
// Preset memory
ram.Mem[0] = 8'h3b;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#10 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
3315,10 → 3316,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 07 RLCA");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
3449,11 → 3450,11
// Preset memory
ram.Mem[0] = 8'h07;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#6 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
3487,10 → 3488,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 1f RRA");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
3621,11 → 3622,11
// Preset memory
ram.Mem[0] = 8'h1f;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#6 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
3659,10 → 3660,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode cb09 RRC C");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
3796,11 → 3797,11
// Preset memory
ram.Mem[22982] = 8'h9e;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#14 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
3834,10 → 3835,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode cb11 RL C");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
3971,11 → 3972,11
// Preset memory
ram.Mem[60738] = 8'hb7;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#14 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
4009,10 → 4010,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode cb36 SLL (HL)*");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
4146,11 → 4147,11
// Preset memory
ram.Mem[27960] = 8'hf1;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#28 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
4185,10 → 4186,10
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
if (ram.Mem[27960]!==8'he3) $fdisplay(f,"* Mem[6d38]=%h !=e3",ram.Mem[27960]);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode cb52 BIT 2,D");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
4322,11 → 4323,11
// Preset memory
ram.Mem[44100] = 8'h00;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#14 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
4360,10 → 4361,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode cb93 RES 2,E");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
4497,11 → 4498,11
// Preset memory
ram.Mem[8756] = 8'ha0;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#14 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
4535,10 → 4536,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode cbc4 SET 0,H");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
4672,11 → 4673,11
// Preset memory
ram.Mem[22646] = 8'h9d;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#14 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
4710,10 → 4711,10
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode dd75 LD (IX+d),L");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
4846,11 → 4847,11
ram.Mem[1] = 8'h75;
ram.Mem[2] = 8'h30;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#36 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
4885,10 → 4886,10
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
if (ram.Mem[44668]!==8'h4f) $fdisplay(f,"* Mem[ae7c]=%h !=4f",ram.Mem[44668]);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode dd4e LD C,(IX+d)");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
5023,11 → 5024,11
// Preset memory
ram.Mem[55673] = 8'h76;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
release dut.address_latch_.Q;
#1
#36 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
/z80_top_direct_n.v
0,0 → 1,85
//============================================================================
// Z80 Top level using the direct module declaration
//============================================================================
`timescale 1us/ 100 ns
 
module z80_top_direct_n(
output wire nM1,
output wire nMREQ,
output wire nIORQ,
output wire nRD,
output wire nWR,
output wire nRFSH,
output wire nHALT,
output wire nBUSACK,
 
input wire nWAIT,
input wire nINT,
input wire nNMI,
input wire nRESET,
input wire nBUSRQ,
 
input wire CLK,
output wire [15:0] A,
inout wire [7:0] D
);
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Include core A-Z80 level connecting all internal modules
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`include "core.vh"
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Address, Data and Control bus drivers connecting to external pins
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
address_pins address_pins_(
.clk (clk),
.bus_ab_pin_we (bus_ab_pin_we),
.pin_control_oe (pin_control_oe),
.address (address),
.abus (A)
);
 
data_pins data_pins_(
.bus_db_pin_oe (bus_db_pin_oe),
.bus_db_pin_re (bus_db_pin_re),
.ctl_bus_db_we (ctl_bus_db_we),
.ctl_bus_db_oe (ctl_bus_db_oe),
.clk (clk),
.db (db0),
.D (D)
);
 
control_pins_n control_pins_(
.busack (busack),
.CPUCLK (CLK),
.pin_control_oe(pin_control_oe),
.in_halt (in_halt),
.pin_nWAIT (nWAIT),
.pin_nBUSRQ (nBUSRQ),
.pin_nINT (nINT),
.pin_nNMI (nNMI),
.pin_nRESET (nRESET),
.nM1_out (nM1_out),
.nRFSH_out (nRFSH_out),
.nRD_out (nRD_out),
.nWR_out (nWR_out),
.nIORQ_out (nIORQ_out),
.nMREQ_out (nMREQ_out),
.nmi (nmi),
.busrq (busrq),
.clk (clk),
.intr (intr),
.mwait (mwait),
.reset_in (reset_in),
.pin_nM1 (nM1),
.pin_nMREQ (nMREQ),
.pin_nIORQ (nIORQ),
.pin_nRD (nRD),
.pin_nWR (nWR),
.pin_nRFSH (nRFSH),
.pin_nHALT (nHALT),
.pin_nBUSACK (nBUSACK)
);
 
endmodule

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