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Subversion Repositories a-z80

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  • This comparison shows the changes necessary to convert path 
    /a-z80/trunk/host/basic_de1
    from Rev 8 to Rev 13
    ↔ Reverse comparison
  •

Rev 8 → Rev 13

/basic_de1.qsf
639,6 → 639,7
set_global_assignment -name VERILOG_FILE ../../cpu/registers/reg_file.v
set_global_assignment -name VERILOG_FILE ../../cpu/registers/reg_latch.v
set_global_assignment -name VERILOG_FILE ../common/uart.v
set_global_assignment -name VERILOG_FILE ../common/wait_state.v
set_global_assignment -name VERILOG_FILE basic_de1_fpga.sv
set_global_assignment -name QIP_FILE ram.qip
set_global_assignment -name QIP_FILE pll.qip
/basic_de1_ModelSim.sv
39,7 → 39,7
wire nHALT;
wire nBUSACK;
 
wire nWAIT = 1;
wire nWAIT;
wire nINT = nint;
wire nNMI = nnmi;
wire nBUSRQ = 1;
47,6 → 47,15
wire [15:0] A;
wire [7:0] D;
 
// This is an optional, test feature: add M1/Memory Wait states as described in the Zilog manual
reg nWAIT_M1_sig;
reg nWAIT_Mem_sig;
 
// *** Uncomment one of the following 3 choices ***:
//assign nWAIT = nWAIT_M1_sig; // Add one wait state to an M1 cycle
//assign nWAIT = nWAIT_Mem_sig; // Add one wait state to any memory cycle (M1 + memory read/write)
assign nWAIT = 1; // Do not add wait cycles
 
// ----------------- INTERNAL WIRES -----------------
wire [7:0] RamData; // RamData is a data writer from the RAM module
wire RamWE;
68,6 → 77,18
z80_top_direct_n z80_( .*, .nRESET(reset), .CLK(clk) );
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Instantiate gates to add Wait states to M1 and Memory cycles (for testing)
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wait_state wait_state_inst
(
.CLK(clk),
.nM1(nM1),
.nMREQ((nMREQ === z) ? 1'b1 : nMREQ), // Correct nMREQ from being tri-stated after reset
.nWAIT_M1(nWAIT_M1_sig),
.nWAIT_Mem(nWAIT_Mem_sig)
);
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Instantiate 16Kb of RAM memory
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ram ram_( .address(A[13:0]), .clock(clk), .data(D[7:0]), .wren(RamWE), .q(RamData[7:0]) );
/basic_de1_fpga.sv
59,7 → 59,7
wire nHALT;
wire nBUSACK;
 
wire nWAIT = 1;
wire nWAIT;
wire nBUSRQ = 1;
wire nINT = KEY1;
wire nNMI = KEY2;
67,6 → 67,15
wire [15:0] A;
wire [7:0] D;
 
// This is an optional, test feature: add M1/Memory Wait states as described in the Zilog manual
reg nWAIT_M1_sig;
reg nWAIT_Mem_sig;
 
// *** Uncomment one of the following 3 choices ***:
//assign nWAIT = nWAIT_M1_sig; // Add one wait state to an M1 cycle
//assign nWAIT = nWAIT_Mem_sig; // Add one wait state to any memory cycle (M1 + memory read/write)
assign nWAIT = 1; // Do not add wait cycles
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Instantiate PLL
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
124,6 → 133,18
z80_top_direct_n z80_( .*, .nRESET(reset), .CLK(clk_cpu) );
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Instantiate gates to add Wait states to M1 and Memory cycles (for testing)
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wait_state wait_state_inst
(
.CLK(clk_cpu),
.nM1(nM1),
.nMREQ(nMREQ),
.nWAIT_M1(nWAIT_M1_sig),
.nWAIT_Mem(nWAIT_Mem_sig)
);
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Instantiate 16Kb of RAM memory
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ram ram_( .address(A[13:0]), .clock(pll_clk), .data(D[7:0]), .wren(RamWE), .q(RamData[7:0]) );
/simulation/modelsim/test_host.mpf
441,7 → 441,7
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 43
Project_Files_Count = 44
Project_File_0 = $ROOT/cpu/alu/alu.v
Project_File_P_0 = compile_order 11 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_1 = $ROOT/cpu/alu/alu_bit_select.v
528,6 → 528,8
Project_File_P_41 = compile_order 38 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_42 = $ROOT/host/common/uart.v
Project_File_P_42 = compile_order 42 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder uart group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_43 = $ROOT/host/common/wait_state.v
Project_File_P_43 = compile_order 43 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_Sim_Count = 1
Project_Sim_0 = test_host
Project_Sim_P_0 = timing default -t ps -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_bench_host -assertfile {} -std_output {} -L altera_mf_ver -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 +plusarg {} -coverage 0 vopt_env 1 -wlf {} -assertdebug 0 -std_input {} -sdfnowarn 0
/simulation/modelsim/wave_host.do
41,6 → 41,8
} /test_bench_host/host_/D
add wave -noupdate -expand -group {host
} /test_bench_host/host_/RamData
add wave -noupdate /test_bench_host/host_/nWAIT_M1_sig
add wave -noupdate /test_bench_host/host_/nWAIT_Mem_sig
add wave -noupdate -group {RAM
} /test_bench_host/host_/ram_/address
add wave -noupdate -group {RAM

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