URL
https://opencores.org/ocsvn/a-z80/a-z80/trunk
Subversion Repositories a-z80
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- This comparison shows the changes necessary to convert path
/a-z80
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/trunk/cpu/control/exec_zero.i
File deleted
/trunk/cpu/control/exec_matrix.i
File deleted
/trunk/cpu/control/exec_module.i
File deleted
/trunk/cpu/control/timing_macros.i
1,6 → 1,6
//========================================================================================= |
// This file contains substitute strings for macros used in the Excel timing table and |
// is read and processed by genmatrix.py script to generate exec_matrix.i include file. |
// is read and processed by genmatrix.py script to generate exec_matrix.vh include file. |
// |
// Format of the file: |
// |
/trunk/cpu/control/exec_module.vh
0,0 → 1,127
// Automatically generated by genref.py |
|
// Module: control/decode_state.v |
output logic ctl_state_iy_set, |
output logic ctl_state_ixiy_clr, |
output logic ctl_state_ixiy_we, |
output logic ctl_state_halt_set, |
output logic ctl_state_tbl_clr, |
output logic ctl_state_tbl_ed_set, |
output logic ctl_state_tbl_cb_set, |
output logic ctl_state_alu, |
output logic ctl_repeat_we, |
|
// Module: control/interrupts.v |
output logic ctl_iff1_iff2, |
output logic ctl_iffx_we, |
output logic ctl_iffx_bit, |
output logic ctl_im_we, |
output logic ctl_no_ints, |
|
// Module: control/ir.v |
output logic ctl_ir_we, |
|
// Module: control/memory_ifc.v |
output logic ctl_mRead, |
output logic ctl_mWrite, |
output logic ctl_iorw, |
|
// Module: alu/alu_control.v |
output logic ctl_shift_en, |
output logic ctl_daa_oe, |
output logic ctl_alu_op_low, |
output logic ctl_cond_short, |
output logic ctl_alu_core_hf, |
output logic ctl_eval_cond, |
output logic ctl_66_oe, |
output logic [1:0] ctl_pf_sel, |
|
// Module: alu/alu_select.v |
output logic ctl_alu_oe, |
output logic ctl_alu_shift_oe, |
output logic ctl_alu_op2_oe, |
output logic ctl_alu_res_oe, |
output logic ctl_alu_op1_oe, |
output logic ctl_alu_bs_oe, |
output logic ctl_alu_op1_sel_bus, |
output logic ctl_alu_op1_sel_low, |
output logic ctl_alu_op1_sel_zero, |
output logic ctl_alu_op2_sel_zero, |
output logic ctl_alu_op2_sel_bus, |
output logic ctl_alu_op2_sel_lq, |
output logic ctl_alu_sel_op2_neg, |
output logic ctl_alu_sel_op2_high, |
output logic ctl_alu_core_R, |
output logic ctl_alu_core_V, |
output logic ctl_alu_core_S, |
|
// Module: alu/alu_flags.v |
output logic ctl_flags_oe, |
output logic ctl_flags_bus, |
output logic ctl_flags_alu, |
output logic ctl_flags_nf_set, |
output logic ctl_flags_cf_set, |
output logic ctl_flags_cf_cpl, |
output logic ctl_flags_cf_we, |
output logic ctl_flags_sz_we, |
output logic ctl_flags_xy_we, |
output logic ctl_flags_hf_we, |
output logic ctl_flags_pf_we, |
output logic ctl_flags_nf_we, |
output logic ctl_flags_cf2_we, |
output logic ctl_flags_hf_cpl, |
output logic ctl_flags_use_cf2, |
output logic ctl_flags_hf2_we, |
output logic ctl_flags_nf_clr, |
output logic ctl_alu_zero_16bit, |
output logic [1:0] ctl_flags_cf2_sel, |
|
// Module: registers/reg_file.v |
output logic ctl_sw_4d, |
output logic ctl_sw_4u, |
output logic ctl_reg_in_hi, |
output logic ctl_reg_in_lo, |
output logic ctl_reg_out_lo, |
output logic ctl_reg_out_hi, |
|
// Module: registers/reg_control.v |
output logic ctl_reg_exx, |
output logic ctl_reg_ex_af, |
output logic ctl_reg_ex_de_hl, |
output logic ctl_reg_use_sp, |
output logic ctl_reg_sel_pc, |
output logic ctl_reg_sel_ir, |
output logic ctl_reg_sel_wz, |
output logic ctl_reg_gp_we, |
output logic ctl_reg_not_pc, |
output logic ctl_reg_sys_we_lo, |
output logic ctl_reg_sys_we_hi, |
output logic ctl_reg_sys_we, |
output logic [1:0] ctl_reg_gp_hilo, |
output logic [1:0] ctl_reg_gp_sel, |
output logic [1:0] ctl_reg_sys_hilo, |
|
// Module: bus/address_latch.v |
output logic ctl_inc_cy, |
output logic ctl_inc_dec, |
output logic ctl_inc_zero, |
output logic ctl_al_we, |
output logic ctl_inc_limit6, |
output logic ctl_bus_inc_oe, |
output logic ctl_apin_mux, |
output logic ctl_apin_mux2, |
|
// Module: bus/bus_control.v |
output logic ctl_bus_ff_oe, |
output logic ctl_bus_zero_oe, |
output logic ctl_bus_db_oe, |
|
// Module: bus/bus_switch.sv |
output logic ctl_sw_1u, |
output logic ctl_sw_1d, |
output logic ctl_sw_2u, |
output logic ctl_sw_2d, |
output logic ctl_sw_mask543_en, |
|
// Module: bus/data_pins.v |
output logic ctl_bus_db_we, |
/trunk/cpu/control/exec_matrix.vh
0,0 → 1,4194
// Automatically generated by genmatrix.py |
// 8-bit Load Group |
if (pla[17] && !pla[50]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; setM1=1; end |
end |
|
if (pla[61] && !pla[58] && !pla[59]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2u=1; |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_op1_oe=1; /* OP1 latch */ end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ end |
end |
|
if (use_ixiy && pla[58]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; end |
if (M3 && T1) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T2) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T3) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end |
end |
|
if (~use_ixiy && pla[58]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; end |
if (M2 && T3) begin fMRead=1; nextM=1; setM1=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T2) begin fMRead=1; end |
if (M4 && T3) begin fMRead=1; nextM=1; setM1=1; end |
end |
|
if (use_ixiy && pla[59]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; end |
if (M3 && T1) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T2) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T3) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T5) begin nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end |
end |
|
if (~use_ixiy && pla[59]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mWrite=1; |
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M2 && T1) begin fMWrite=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMWrite=1; end |
if (M2 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
if (M4 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M4 && T2) begin fMWrite=1; end |
if (M4 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (pla[40]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T3) begin fMRead=1; ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T5) begin nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end |
end |
|
if (pla[50] && !pla[40]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; end |
if (M3 && T1) begin fMWrite=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMWrite=1; end |
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
if (M4 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T2) begin fMWrite=1; end |
if (M4 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (pla[8] && pla[13]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mWrite=1; |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M2 && T1) begin fMWrite=1; |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMWrite=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (pla[8] && !pla[13]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; setM1=1; end |
end |
|
if (pla[38] && pla[13]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M4 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M4 && T2) begin fMWrite=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (pla[38] && !pla[13]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin fMRead=1; nextM=1; setM1=1; end |
end |
|
if (pla[83]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_IFF2; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; |
ctl_reg_sel_ir=1; ctl_reg_sys_hilo={!op3,op3}; ctl_sw_4u=1; /* Read either I or R based on op3 (0 or 1) */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T5) begin nextM=1; setM1=1; end |
end |
|
if (pla[57]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; |
ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo={!op3,op3}; ctl_sw_4d=1; /* Write either I or R based on op3 (0 or 1) */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2u=1; |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_op1_oe=1; /* OP1 latch */ end |
if (M1 && T5) begin nextM=1; setM1=1; end |
end |
|
// 16-bit Load Group |
if (pla[7]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1; end |
end |
|
if (pla[30] && pla[13]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M4 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M4 && T2) begin fMWrite=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M5 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M5 && T2) begin fMWrite=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (pla[30] && !pla[13]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M5 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M5 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M5 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
end |
|
if (pla[31] && pla[33]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M4 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M4 && T2) begin fMWrite=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M5 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M5 && T2) begin fMWrite=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (pla[31] && !pla[33]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M5 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M5 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M5 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
end |
|
if (pla[5]) begin |
if (M1 && T4) begin validPLA=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M1 && T5) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M1 && T6) begin nextM=1; setM1=1; end |
end |
|
if (pla[23] && pla[16]) begin |
if (M1 && T4) begin validPLA=1; end |
if (M1 && T5) begin nextM=1; ctl_mWrite=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T1) begin fMWrite=1; |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_apin_mux=1; /* Apin sourced from incrementer */ |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M2 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T1) begin fMWrite=1; |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_apin_mux=1; /* Apin sourced from incrementer */ |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M3 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (pla[23] && !pla[16]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
end |
|
// Exchange, Block Transfer and Search Groups |
if (pla[2]) begin |
if (M1 && T2) begin |
ctl_reg_ex_de_hl=1; /* EX DE,HL */ end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; end |
end |
|
if (pla[39]) begin |
if (M1 && T2) begin |
ctl_reg_ex_af=1; /* EX AF,AF' */ end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; end |
end |
|
if (pla[1]) begin |
if (M1 && T2) begin |
ctl_reg_exx=1; /* EXX */ end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; end |
end |
|
if (pla[10]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T4) begin nextM=1; ctl_mWrite=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T1) begin fMWrite=1; |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_apin_mux=1; /* Apin sourced from incrementer */ |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M4 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M5 && T1) begin fMWrite=1; |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_apin_mux=1; /* Apin sourced from incrementer */ |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M5 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M5 && T3) begin fMWrite=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M5 && T4) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M5 && T5) begin nextM=1; setM1=1; end |
end |
|
if (pla[0]) begin |
begin nonRep=1; /* Non-repeating block instruction */ end |
end |
|
if (pla[12]) begin |
if (M1 && T1) begin |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_use_cf2=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end |
if (M3 && T1) begin fMWrite=1; |
ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit DE, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_use_cf2=1; end |
if (M3 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMWrite=1; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T4) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_repeat_we=1; /* Update repeating flag latch with BC=1 status */ end |
if (M3 && T5) begin nextM=1; setM1=nonRep | !repeat_en; end |
if (M4 && T1) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T2) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T4) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T5) begin nextM=1; setM1=1; end |
end |
|
if (pla[11]) begin |
if (M1 && T1) begin |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_op1_sel_zero=1; /* Zero */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP; |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; |
ctl_flags_use_cf2=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_hf_cpl=flags_nf; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end |
if (M3 && T1) begin |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_use_cf2=1; end |
if (M3 && T3) begin |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T4) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_repeat_we=1; /* Update repeating flag latch with BC=1 status */ end |
if (M3 && T5) begin nextM=1; setM1=nonRep | !repeat_en | flags_zf; end |
if (M4 && T1) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T2) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T4) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T5) begin nextM=1; setM1=1; end |
end |
|
// 8-bit Arithmetic and Logic Group |
if (pla[65] && !pla[52]) begin |
if (M1 && T1) begin /* Which register to be written is decided elsewhere */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_sz_we=1; |
ctl_flags_cf_we=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; end |
end |
|
if (pla[64]) begin |
if (M1 && T1) begin /* Which register to be written is decided elsewhere */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_sz_we=1; |
ctl_flags_cf_we=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; |
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; end |
end |
|
if (use_ixiy && pla[52]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; end |
if (M3 && T1) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T2) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T3) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end |
end |
|
if (!use_ixiy && pla[52]) begin |
if (M1 && T1) begin /* Which register to be written is decided elsewhere */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_sz_we=1; |
ctl_flags_cf_we=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T2) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M4 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; end |
end |
|
if (pla[66] && !pla[53]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; |
ctl_flags_use_cf2=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_hf_cpl=flags_nf; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
if (op4 & op5 & !op3) ctl_bus_zero_oe=1; /* Trying to read flags? Put 0 on the bus instead. */ |
else begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; end /* Read 8-bit GP register */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_zero=1; /* Zero */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf_set=1; /* Set CF going into the ALU core */ |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end |
end |
|
if (pla[75]) begin |
if (M1 && T1) begin |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ |
ctl_alu_sel_op2_neg=1; end |
if (M1 && T4) begin |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ |
ctl_alu_sel_op2_neg=1; end |
end |
|
if ((M2 || M4) && pla[75]) begin |
begin |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ |
ctl_alu_sel_op2_neg=1; end |
end |
|
if (use_ixiy && pla[53]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; end |
if (M3 && T1) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T2) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T3) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end |
end |
|
if (!use_ixiy && pla[53]) begin |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_hf_cpl=flags_nf; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; end |
if (M2 && T3) begin fMRead=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_zero=1; /* Zero */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf_set=1; /* Set CF going into the ALU core */ |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end |
if (M2 && T4) begin nextM=1; ctl_mWrite=1; |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; |
ctl_flags_use_cf2=1; end |
if (M3 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T2) begin fMWrite=1; end |
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T2) begin fMRead=1; end |
if (M4 && T3) begin fMRead=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_zero=1; /* Zero */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf_set=1; /* Set CF going into the ALU core */ |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end |
if (M4 && T4) begin nextM=1; ctl_mWrite=1; |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; |
ctl_flags_use_cf2=1; end |
if (M5 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M5 && T2) begin fMWrite=1; end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
// 16-bit Arithmetic Group |
if (pla[69]) begin |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ end |
if (M2 && T1) begin |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M2 && T2) begin |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_xy_we=1; |
ctl_flags_cf_we=1; end |
if (M2 && T3) begin |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ end |
if (M2 && T4) begin nextM=1; |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M3 && T1) begin |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_xy_we=1; |
ctl_flags_cf_we=1; end |
if (M3 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin nextM=1; setM1=1; end |
end |
|
if (op3 && pla[68]) begin |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ end |
if (M2 && T1) begin |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M2 && T2) begin |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_cf_we=1; end |
if (M2 && T3) begin |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ end |
if (M2 && T4) begin nextM=1; |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M3 && T1) begin |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; |
ctl_flags_cf_we=1; |
ctl_alu_zero_16bit=1; /* 16-bit arithmetic operation uses ZF calculated over 2 bytes */ end |
if (M3 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin nextM=1; setM1=1; end |
end |
|
if (!op3 && pla[68]) begin |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ end |
if (M2 && T1) begin |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M2 && T2) begin |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_cf_we=1; end |
if (M2 && T3) begin |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ end |
if (M2 && T4) begin nextM=1; |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M3 && T1) begin |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; |
ctl_flags_cf_we=1; |
ctl_alu_zero_16bit=1; /* 16-bit arithmetic operation uses ZF calculated over 2 bytes */ end |
if (M3 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin nextM=1; setM1=1; end |
end |
|
if (pla[9]) begin |
if (M1 && T4) begin validPLA=1; |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M1 && T5) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit general purpose register, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M1 && T6) begin nextM=1; setM1=1; end |
end |
|
// General Purpose Arithmetic and CPU Control Groups |
if (pla[77]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; |
ctl_flags_cf_we=1; |
ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=!flags_nf; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_use_cf2=1; |
ctl_flags_hf_cpl=flags_nf; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf2_we=1; /* Write HF2 flag (DAA only) */ |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=2; |
ctl_daa_oe=1; /* Write DAA correction factor to the bus */ |
ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=!flags_nf; end |
end |
|
if (pla[81]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_xy_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; |
ctl_alu_sel_op2_neg=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_hf_cpl=flags_nf; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_op1_sel_zero=1; /* Zero */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; |
ctl_alu_sel_op2_neg=1; end |
end |
|
if (pla[82]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; |
ctl_flags_cf_we=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_op1_sel_zero=1; /* Zero */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; |
ctl_flags_cf_we=1; end |
end |
|
if (pla[89]) begin |
if (M1 && T1) begin |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_xy_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_cf_we=1; ctl_flags_cf_cpl=1; /* CCF */ |
ctl_flags_hf_cpl=!flags_cf; /* Used for CCF */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
end |
|
if (pla[92]) begin |
if (M1 && T1) begin |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_xy_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_cf_set=1; /* Set CF going into the ALU core */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
end |
|
if (pla[95]) begin |
if (M1 && T3) begin |
ctl_state_halt_set=1; /* Enter HALT state */ end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; end |
end |
|
if (pla[97]) begin |
if (M1 && T3) begin |
ctl_iffx_bit=op3; ctl_iffx_we=1; /* DI/EI */ end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end |
end |
|
if (pla[96]) begin |
if (M1 && T3) begin |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_im_we=1; /* IM n ('n' is read by opcode[4:3]) */ end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; end |
end |
|
// Rotate and Shift Group |
if (pla[25]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf_we=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_use_cf2=1; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end |
end |
|
if (~use_ixiy && pla[70] && !pla[55]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf_we=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_use_cf2=1; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_ir_we=1; end |
if (M4 && T2) begin fMRead=1; end |
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end |
if (M5 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf_we=1; end |
if (M5 && T2) begin fMWrite=1; end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (~use_ixiy && pla[70] && pla[55]) begin |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_use_cf2=1; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; end |
if (M2 && T3) begin fMRead=1; end |
if (M2 && T4) begin nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end |
if (M3 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf_we=1; end |
if (M3 && T2) begin fMWrite=1; end |
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_ir_we=1; end |
if (M4 && T2) begin fMRead=1; end |
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end |
if (M5 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf_we=1; end |
if (M5 && T2) begin fMWrite=1; end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (pla[15] && op3) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; end |
if (M3 && T1) begin |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_lq=1; /* Cross-bus wire (see schematic) */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ end |
if (M3 && T4) begin nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_low=1; /* Write low nibble with a high nibble */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ end |
if (M4 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_op2_oe=1; /* OP2 latch */ end |
if (M4 && T2) begin fMWrite=1; |
ctl_alu_op1_oe=1; /* OP1 latch */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ end |
if (M4 && T3) begin fMWrite=1; nextM=1; setM1=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
end |
|
if (pla[15] && !op3) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; end |
if (M3 && T1) begin |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_lq=1; /* Cross-bus wire (see schematic) */ |
ctl_alu_op1_sel_low=1; /* Write low nibble with a high nibble */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ end |
if (M3 && T2) begin |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_op2_oe=1; /* OP2 latch */ end |
if (M3 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_lq=1; /* Cross-bus wire (see schematic) */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ end |
if (M3 && T4) begin nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_low=1; /* Write low nibble with a high nibble */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ end |
if (M4 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_op2_oe=1; /* OP2 latch */ end |
if (M4 && T2) begin fMWrite=1; |
ctl_alu_op1_oe=1; /* OP1 latch */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ end |
if (M4 && T3) begin fMWrite=1; nextM=1; setM1=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
end |
|
// Bit Manipulation Group |
if (~use_ixiy && pla[72] && !pla[55]) begin |
if (M1 && T1) begin |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; |
ctl_flags_sz_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_ir_we=1; end |
if (M4 && T2) begin fMRead=1; end |
if (M4 && T3) begin fMRead=1; end |
if (M4 && T4) begin nextM=1; setM1=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; |
ctl_flags_sz_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
end |
|
if (~use_ixiy && pla[72] && pla[55]) begin |
if (M1 && T1) begin |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; |
ctl_flags_sz_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; end |
if (M2 && T3) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_flags_xy_we=1; end |
if (M2 && T4) begin nextM=1; setM1=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; |
ctl_flags_sz_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_ir_we=1; end |
if (M4 && T2) begin fMRead=1; end |
if (M4 && T3) begin fMRead=1; end |
if (M4 && T4) begin nextM=1; setM1=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; |
ctl_flags_sz_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
end |
|
if (~use_ixiy && pla[74] && !pla[55]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2u=1; |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_ir_we=1; end |
if (M4 && T2) begin fMRead=1; end |
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M5 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M5 && T2) begin fMWrite=1; end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (~use_ixiy && pla[74] && pla[55]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; end |
if (M2 && T3) begin fMRead=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M2 && T4) begin nextM=1; ctl_mWrite=1; |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M3 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T2) begin fMWrite=1; end |
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_ir_we=1; end |
if (M4 && T2) begin fMRead=1; end |
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M5 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M5 && T2) begin fMWrite=1; end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (~use_ixiy && pla[73] && !pla[55]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2u=1; |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_ir_we=1; end |
if (M4 && T2) begin fMRead=1; end |
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end |
if (M5 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end |
if (M5 && T2) begin fMWrite=1; end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (~use_ixiy && pla[73] && pla[55]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; end |
if (M2 && T3) begin fMRead=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end |
if (M2 && T4) begin nextM=1; ctl_mWrite=1; |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end |
if (M3 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T2) begin fMWrite=1; end |
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_ir_we=1; end |
if (M4 && T2) begin fMRead=1; end |
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end |
if (M5 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end |
if (M5 && T2) begin fMWrite=1; end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
// Input and Output Groups |
if (pla[37] && !pla[28]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_iorw=1; end |
if (M3 && T1) begin fIORead=1; |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; ctl_sw_4d=1; /* Read 8-bit general purpose A register, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ /* Which register to be written is decided elsewhere */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T2) begin fIORead=1; end |
if (M3 && T3) begin fIORead=1; end |
if (M3 && T4) begin fIORead=1; nextM=1; setM1=1; end |
end |
|
if (pla[27] && !pla[34]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_iorw=1; end |
if (M2 && T1) begin fIORead=1; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fIORead=1; end |
if (M2 && T3) begin fIORead=1; end |
if (M2 && T4) begin fIORead=1; nextM=1; setM1=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
end |
|
if (pla[37] && pla[28]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_iorw=1; |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; ctl_sw_4d=1; /* Read 8-bit general purpose A register, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fIOWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M3 && T2) begin fIOWrite=1; end |
if (M3 && T3) begin fIOWrite=1; end |
if (M3 && T4) begin fIOWrite=1; nextM=1; setM1=1; end |
end |
|
if (pla[27] && pla[34]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_iorw=1; |
if (op4 & op5 & !op3) ctl_bus_zero_oe=1; /* Trying to read flags? Put 0 on the bus instead. */ |
else begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; end /* Read 8-bit GP register */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M2 && T1) begin fIOWrite=1; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fIOWrite=1; end |
if (M2 && T3) begin fIOWrite=1; end |
if (M2 && T4) begin fIOWrite=1; nextM=1; setM1=1; end |
end |
|
if (pla[91] && pla[21]) begin |
if (M1 && T1) begin |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; end |
if (M1 && T5) begin nextM=1; ctl_iorw=1; end |
if (M2 && T1) begin fIORead=1; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fIORead=1; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_zero=1; /* Zero */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_alu_sel_op2_neg=1; end |
if (M2 && T3) begin fIORead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_cf_we=1; |
ctl_alu_sel_op2_neg=1; end |
if (M2 && T4) begin fIORead=1; nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_nf_we=1; /* Sign bit, to be used with FLAGT source set to "alu" */ |
ctl_alu_sel_op2_neg=1; end |
if (M3 && T1) begin fMWrite=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=nonRep | !repeat_en | flags_zf; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M4 && T1) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T2) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T4) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T5) begin nextM=1; setM1=1; end |
end |
|
if (pla[91] && pla[20]) begin |
if (M1 && T1) begin |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_zero=1; /* Zero */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_alu_sel_op2_neg=1; end |
if (M1 && T5) begin nextM=1; ctl_mRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_alu_sel_op2_neg=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_iorw=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ end |
if (M3 && T1) begin fIOWrite=1; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fIOWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; /* Sign bit, to be used with FLAGT source set to "alu" */ end |
if (M3 && T3) begin fIOWrite=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_cf_we=1; end |
if (M3 && T4) begin fIOWrite=1; nextM=1; setM1=nonRep | !repeat_en | flags_zf; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M4 && T1) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T2) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T4) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T5) begin nextM=1; setM1=1; end |
end |
|
// Jump Group |
if (pla[29]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
if (pla[43]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1; |
if (flags_cond_true) begin /* If cc is true, use WZ instead of PC (for jumps) */ |
ctl_reg_not_pc=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; |
end |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo[1]=1; /* Conditionally selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
end |
|
if (pla[47]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; end |
if (M3 && T1) begin |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; end |
if (M3 && T2) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; end |
if (M3 && T3) begin |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_cf_we=1; end |
if (M3 && T4) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_zero=1; /* Zero */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_alu_sel_op2_neg=flags_sf; end |
if (M3 && T5) begin nextM=1; setM1=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_alu_sel_op2_neg=flags_sf; |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
if (pla[48]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; |
ctl_cond_short=1; /* M1/T3 only: force a short flags condition (SS) */ end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; setM1=!flags_cond_true; end |
if (M3 && T1) begin |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; end |
if (M3 && T2) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; end |
if (M3 && T3) begin |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_cf_we=1; end |
if (M3 && T4) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_zero=1; /* Zero */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_alu_sel_op2_neg=flags_sf; end |
if (M3 && T5) begin nextM=1; setM1=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_alu_sel_op2_neg=flags_sf; |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
if (pla[6]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
if (pla[26]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_zero=1; /* Zero */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_alu_sel_op2_neg=1; end |
if (M1 && T5) begin nextM=1; ctl_mRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_alu_sel_op2_neg=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; setM1=flags_zf; /* Used in DJNZ */ end |
if (M3 && T1) begin |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; end |
if (M3 && T2) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; end |
if (M3 && T3) begin |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_cf_we=1; end |
if (M3 && T4) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_zero=1; /* Zero */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_alu_sel_op2_neg=flags_sf; end |
if (M3 && T5) begin nextM=1; setM1=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_alu_sel_op2_neg=flags_sf; |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
// Call and Return Group |
if (pla[24]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T4) begin nextM=1; ctl_mWrite=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T1) begin fMWrite=1; |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_apin_mux=1; /* Apin sourced from incrementer */ |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M4 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M5 && T1) begin fMWrite=1; |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_apin_mux=1; /* Apin sourced from incrementer */ |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M5 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
if (pla[42]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=!flags_cond_true; setM1=!flags_cond_true; |
ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo[1]=1; /* Conditionally selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T4) begin nextM=1; ctl_mWrite=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T1) begin fMWrite=1; |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_apin_mux=1; /* Apin sourced from incrementer */ |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M4 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M5 && T1) begin fMWrite=1; |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_apin_mux=1; /* Apin sourced from incrementer */ |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M5 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
if (pla[35]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
if (pla[45]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; end |
if (M1 && T5) begin nextM=1; ctl_mRead=1; setM1=!flags_cond_true; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
if (pla[46]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; |
ctl_iff1_iff2=1; /* RETN copies IFF2 into IFF1 */ end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
if (pla[56]) begin |
if (M1 && T3) begin |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_op1_oe=1; /* OP1 latch */ |
ctl_alu_op1_sel_zero=1; /* Zero */ |
ctl_sw_mask543_en=!((in_intr & im2) | in_nmi); |
ctl_sw_1d=!in_nmi; ctl_66_oe=in_nmi; |
ctl_bus_ff_oe=in_intr & im1; end |
if (M1 && T4) begin validPLA=1; end |
if (M1 && T5) begin nextM=1; ctl_mWrite=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ end |
if (M2 && T1) begin fMWrite=1; |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_apin_mux=1; /* Apin sourced from incrementer */ |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1; |
ctl_reg_out_hi=1; /* From the register file into the ALU high byte only */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M2 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T1) begin fMWrite=1; |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_apin_mux=1; /* Apin sourced from incrementer */ |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1; |
ctl_reg_out_lo=1; /* From the register file into the ALU low byte only */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M3 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMWrite=1; nextM=1; ctl_mRead=in_intr & im2; /* RST38 interrupt extension */ setM1=!(in_intr & im2); /* RST38 interrupt extension */ |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
// INTR IM2 continues here... |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4d=1; /* Select 8-bit I register */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2u=1; |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_op1_oe=1; /* OP1 latch */ end |
if (M4 && T2) begin fMRead=1; |
ctl_sw_4u=1; |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_reg_out_lo=1; /* From the register file into the ALU low byte only */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ end |
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M5 && T1) begin fMRead=1; |
ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4d=1; /* Select 8-bit I register */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2u=1; |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_op1_oe=1; /* OP1 latch */ end |
if (M5 && T2) begin fMRead=1; |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M5 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
// CB-Table opcodes |
if (pla[49]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; |
ctl_state_tbl_cb_set=1; setCBED=1; /* CB-table prefix */ end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T3) begin fMRead=1; ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end |
if (M4 && T1) begin |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_ir_we=1; end |
// Loading a new instruction immediately changes PLA wires and continues into the new effective instructions' M4/T1 cycle |
end |
|
// Special Purposes PLA Entries |
if (pla[3]) begin |
if (M1 && T2) begin |
ctl_state_ixiy_we=1; ctl_state_iy_set=op5; setIXIY=1; /* IX/IY prefix */ end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end |
end |
|
if (pla[44]) begin |
if (M1 && T2) begin |
ctl_state_tbl_cb_set=1; setCBED=1; /* CB-table prefix */ end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end |
end |
|
if (pla[51]) begin |
if (M1 && T2) begin |
ctl_state_tbl_ed_set=1; setCBED=1; /* ED-table prefix */ end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end |
end |
|
if (pla[76]) begin |
begin |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; end |
if (M1 && T1) begin |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end |
end |
|
if (pla[78]) begin |
begin |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; end |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end |
end |
|
if (pla[79]) begin |
begin |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; end |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end |
end |
|
if (pla[80]) begin |
begin |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end |
end |
|
if (pla[84]) begin |
begin |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end |
end |
|
if (pla[85]) begin |
begin |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end |
if (M1 && T2) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ end |
end |
|
if (pla[86]) begin |
begin |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end |
if (M1 && T2) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ end |
end |
|
if (pla[88]) begin |
begin |
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end |
if (M1 && T2) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ end |
end |
|
// State machine to compute (IX+d) |
if (ixy_d) begin |
if (T1) begin |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; end |
if (T2) begin |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; end |
if (T3) begin |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end |
if (T4) begin |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_zero=1; /* Zero */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_flags_use_cf2=1; |
ctl_alu_sel_op2_neg=flags_sf; end |
if (T5) begin |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_xy_we=1; |
ctl_alu_sel_op2_neg=flags_sf; |
ctl_state_ixiy_we=1; ctl_state_ixiy_clr=!setIXIY; /* Clear IX/IY flag */ end |
end |
|
// Default instruction fetch (M1) state machine |
if (M1) begin |
if (M1 && T1) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; ctl_apin_mux2=1; /* Apin sourced from AL */ end |
if (M1 && T2) begin |
ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit IR */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_state_ixiy_we=1; ctl_state_ixiy_clr=!setIXIY; /* Clear IX/IY flag */ |
ctl_state_tbl_clr=!setCBED; /* Clear CB/ED prefix */ |
ctl_ir_we=1; |
ctl_bus_zero_oe=in_halt; ctl_bus_ff_oe=(in_intr & (im1 | im2)) | in_nmi; end |
if (M1 && T3) begin |
ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; /* Write 16-bit IR */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; ctl_apin_mux2=1; /* Apin sourced from AL */ |
ctl_inc_limit6=1; /* Limit the incrementer to 6 bits */ end |
if (M1 && T4) begin |
ctl_eval_cond=1; /* Evaluate flags condition based on the opcode[5:3] */ end |
end |
|
/trunk/cpu/control/simulation/modelsim/test_control.mpf
442,7 → 442,7
Project_Version = 6 |
Project_DefaultLib = work |
Project_SortMethod = unused |
Project_Files_Count = 7 |
Project_Files_Count = 8 |
Project_File_0 = $ROOT/cpu/control/interrupts.v |
Project_File_P_0 = compile_order 1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder interrupts group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
Project_File_1 = $ROOT/cpu/control/pin_control.v |
449,14 → 449,16
Project_File_P_1 = compile_order 6 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {pin control} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
Project_File_2 = $ROOT/cpu/control/resets.v |
Project_File_P_2 = compile_order 4 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder reset group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
Project_File_3 = $ROOT/cpu/control/test_interrupts.sv |
Project_File_P_3 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder interrupts group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
Project_File_4 = $ROOT/cpu/control/test_pin_control.sv |
Project_File_P_4 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {pin control} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
Project_File_5 = $ROOT/cpu/control/test_reset.sv |
Project_File_P_5 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder reset group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
Project_File_6 = $ROOT/cpu/control/test_sequencer.sv |
Project_File_P_6 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder sequencer group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
Project_File_3 = $ROOT/cpu/control/sequencer.v |
Project_File_P_3 = compile_order 7 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder sequencer group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
Project_File_4 = $ROOT/cpu/control/test_interrupts.sv |
Project_File_P_4 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder interrupts group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
Project_File_5 = $ROOT/cpu/control/test_pin_control.sv |
Project_File_P_5 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {pin control} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
Project_File_6 = $ROOT/cpu/control/test_reset.sv |
Project_File_P_6 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder reset group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
Project_File_7 = $ROOT/cpu/control/test_sequencer.sv |
Project_File_P_7 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder sequencer group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 |
Project_Sim_Count = 4 |
Project_Sim_0 = Test pin control |
Project_Sim_P_0 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {pin control} +pulse_e {} additional_dus work.test_pin_control -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {} |
/trunk/cpu/control/genmatrix.py
2,8 → 2,8
# |
# This script reads A-Z80 instruction timing data from a spreadsheet text file |
# and generates a Verilog include file defining the control block execution matrix. |
# Macros in the timing spreadsheet are substituted using a list of keys stored |
# in the macros file. See the macro file for the format information. |
# Token keywords in the timing spreadsheet are substituted using a list of keys |
# stored in the macros file. See the macro file for the format information. |
# |
# Input timing file is exported from the Excel file as a TAB-delimited text file. |
# |
167,7 → 167,7
imatrix.append("{0}{1} end".format(state, action)) |
|
# Create a file containing the logic matrix code |
with open('exec_matrix.i', 'w') as file: |
with open('exec_matrix.vh', 'w') as file: |
file.write("// Automatically generated by genmatrix.py\n") |
# If there were errors, print them first (and output to the console) |
if len(errors)>0: |
178,5 → 178,5
for item in imatrix: |
file.write("{}\n".format(item)) |
|
# Touch a file that includes 'exec_matrix.i' to ensure it will recompile correctly |
# Touch a file that includes 'exec_matrix.vh' to ensure it will recompile correctly |
os.utime("execute.sv", None) |
/trunk/cpu/control/execute.sv
22,7 → 22,7
//---------------------------------------------------------- |
// Control signals generated by the instruction execution |
//---------------------------------------------------------- |
`include "exec_module.i" |
`include "exec_module.vh" |
|
output logic nextM, // Last M cycle of any instruction |
output logic setM1, // Last T clock of any instruction |
134,7 → 134,7
// Default assignment of all control outputs to 0 to prevent generating |
// latches. |
//------------------------------------------------------------------------- |
`include "exec_zero.i" |
`include "exec_zero.vh" |
|
// Reset internal control wires |
validPLA = 0; // Every valid PLA entry will set it |
153,7 → 153,7
//------------------------------------------------------------------------- |
// State-based signal assignment |
//------------------------------------------------------------------------- |
`include "exec_matrix.i" |
`include "exec_matrix.vh" |
|
// List more specific combinational signal assignments after the include |
//------------------------------------------------------------------------- |
/trunk/cpu/control/genref.py
25,7 → 25,7
# Create 2 files that should be included in the execution engine block: |
# 1. A module arguments section |
# 2. A file containing the code to initialize control wires to zero |
with open('exec_module.i', 'w') as file1, open('exec_zero.i', 'w') as file0: |
with open('exec_module.vh', 'w') as file1, open('exec_zero.vh', 'w') as file0: |
file1.write("// Automatically generated by genref.py\n") |
file0.write("// Automatically generated by genref.py\n") |
|
45,7 → 45,7
wires.append(info[2] + " " + info[3].translate(None, ';,')) |
|
if len(wires)>0: |
with open('exec_module.i', 'a') as file1, open('exec_zero.i', 'a') as file0: |
with open('exec_module.vh', 'a') as file1, open('exec_zero.vh', 'a') as file0: |
print "MODULE: " + infile |
file0.write("\n// Module: " + infile + "\n") |
file1.write("\n// Module: " + infile + "\n") |
59,5 → 59,5
else: |
file0.write(wire + " = 0;\n") |
|
# Touch a file that includes 'exec_module.i' and 'exec_zero.i' to ensure it will recompile correctly |
# Touch a file that includes 'exec_module.vh' and 'exec_zero.vh' to ensure it will recompile correctly |
os.utime("execute.sv", None) |
/trunk/cpu/control/exec_zero.vh
0,0 → 1,127
// Automatically generated by genref.py |
|
// Module: control/decode_state.v |
ctl_state_iy_set = 0; |
ctl_state_ixiy_clr = 0; |
ctl_state_ixiy_we = 0; |
ctl_state_halt_set = 0; |
ctl_state_tbl_clr = 0; |
ctl_state_tbl_ed_set = 0; |
ctl_state_tbl_cb_set = 0; |
ctl_state_alu = 0; |
ctl_repeat_we = 0; |
|
// Module: control/interrupts.v |
ctl_iff1_iff2 = 0; |
ctl_iffx_we = 0; |
ctl_iffx_bit = 0; |
ctl_im_we = 0; |
ctl_no_ints = 0; |
|
// Module: control/ir.v |
ctl_ir_we = 0; |
|
// Module: control/memory_ifc.v |
ctl_mRead = 0; |
ctl_mWrite = 0; |
ctl_iorw = 0; |
|
// Module: alu/alu_control.v |
ctl_shift_en = 0; |
ctl_daa_oe = 0; |
ctl_alu_op_low = 0; |
ctl_cond_short = 0; |
ctl_alu_core_hf = 0; |
ctl_eval_cond = 0; |
ctl_66_oe = 0; |
ctl_pf_sel = 0; |
|
// Module: alu/alu_select.v |
ctl_alu_oe = 0; |
ctl_alu_shift_oe = 0; |
ctl_alu_op2_oe = 0; |
ctl_alu_res_oe = 0; |
ctl_alu_op1_oe = 0; |
ctl_alu_bs_oe = 0; |
ctl_alu_op1_sel_bus = 0; |
ctl_alu_op1_sel_low = 0; |
ctl_alu_op1_sel_zero = 0; |
ctl_alu_op2_sel_zero = 0; |
ctl_alu_op2_sel_bus = 0; |
ctl_alu_op2_sel_lq = 0; |
ctl_alu_sel_op2_neg = 0; |
ctl_alu_sel_op2_high = 0; |
ctl_alu_core_R = 0; |
ctl_alu_core_V = 0; |
ctl_alu_core_S = 0; |
|
// Module: alu/alu_flags.v |
ctl_flags_oe = 0; |
ctl_flags_bus = 0; |
ctl_flags_alu = 0; |
ctl_flags_nf_set = 0; |
ctl_flags_cf_set = 0; |
ctl_flags_cf_cpl = 0; |
ctl_flags_cf_we = 0; |
ctl_flags_sz_we = 0; |
ctl_flags_xy_we = 0; |
ctl_flags_hf_we = 0; |
ctl_flags_pf_we = 0; |
ctl_flags_nf_we = 0; |
ctl_flags_cf2_we = 0; |
ctl_flags_hf_cpl = 0; |
ctl_flags_use_cf2 = 0; |
ctl_flags_hf2_we = 0; |
ctl_flags_nf_clr = 0; |
ctl_alu_zero_16bit = 0; |
ctl_flags_cf2_sel = 0; |
|
// Module: registers/reg_file.v |
ctl_sw_4d = 0; |
ctl_sw_4u = 0; |
ctl_reg_in_hi = 0; |
ctl_reg_in_lo = 0; |
ctl_reg_out_lo = 0; |
ctl_reg_out_hi = 0; |
|
// Module: registers/reg_control.v |
ctl_reg_exx = 0; |
ctl_reg_ex_af = 0; |
ctl_reg_ex_de_hl = 0; |
ctl_reg_use_sp = 0; |
ctl_reg_sel_pc = 0; |
ctl_reg_sel_ir = 0; |
ctl_reg_sel_wz = 0; |
ctl_reg_gp_we = 0; |
ctl_reg_not_pc = 0; |
ctl_reg_sys_we_lo = 0; |
ctl_reg_sys_we_hi = 0; |
ctl_reg_sys_we = 0; |
ctl_reg_gp_hilo = 0; |
ctl_reg_gp_sel = 0; |
ctl_reg_sys_hilo = 0; |
|
// Module: bus/address_latch.v |
ctl_inc_cy = 0; |
ctl_inc_dec = 0; |
ctl_inc_zero = 0; |
ctl_al_we = 0; |
ctl_inc_limit6 = 0; |
ctl_bus_inc_oe = 0; |
ctl_apin_mux = 0; |
ctl_apin_mux2 = 0; |
|
// Module: bus/bus_control.v |
ctl_bus_ff_oe = 0; |
ctl_bus_zero_oe = 0; |
ctl_bus_db_oe = 0; |
|
// Module: bus/bus_switch.sv |
ctl_sw_1u = 0; |
ctl_sw_1d = 0; |
ctl_sw_2u = 0; |
ctl_sw_2d = 0; |
ctl_sw_mask543_en = 0; |
|
// Module: bus/data_pins.v |
ctl_bus_db_we = 0; |
/trunk/cpu/top-level-files.txt
5,7 → 5,7
------ Control block ------- |
control/clk_delay.v |
control/decode_state.v |
control/exec_module.i |
control/exec_module.vh |
control/execute.sv |
control/interrupts.v |
control/ir.v |
/trunk/cpu/bus/bus_switch.sv
6,7 → 6,7
// This module provides control data bus switch signals. The sole purpose of |
// having these wires defined in this module is to get all control signals |
// (which are processed by genglobals.py) to appear in the list of global |
// control signals ("globals.i") for consistency. |
// control signals ("globals.vh") for consistency. |
//============================================================================ |
|
module bus_switch |
/trunk/cpu/toplevel/globals.i
File deleted
/trunk/cpu/toplevel/test_fuse.i
File deleted
/trunk/cpu/toplevel/core.i
File deleted
/trunk/cpu/toplevel/genfuse.py
92,7 → 92,7
|
#---------------------------- START ----------------------------------- |
# Create a file that should be included in the test_fuse source |
ftest = open('test_fuse.i', 'w') |
ftest = open('test_fuse.vh', 'w') |
ftest.write("// Automatically generated by genfuse.py\n\n") |
|
# Initial pre-test state is reset and control signals asserted |
282,5 → 282,5
ftest.write("`define TOTAL_CLKS " + str(total_clks) + "\n") |
ftest.write("$fdisplay(f,\"=== Tests completed ===\");\n") |
|
# Touch a file that includes 'test_fuse.i' to ensure it will recompile correctly |
# Touch a file that includes 'test_fuse.vh' to ensure it will recompile correctly |
os.utime("test_fuse.sv", None) |
/trunk/cpu/toplevel/z80_top_ifc_n.sv
8,7 → 8,7
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
// Include core A-Z80 level connecting all internal modules |
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
`include "core.i" |
`include "core.vh" |
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
// Address, Data and Control bus drivers connecting to external pins |
/trunk/cpu/toplevel/test_fuse.sv
20,7 → 20,7
|
// Run all the tests and write the result to a file |
f = $fopen("fuse.result.txt"); |
`include "test_fuse.i" |
`include "test_fuse.vh" |
$fclose(f); |
|
end : init |
/trunk/cpu/toplevel/globals.vh
0,0 → 1,291
// Automatically generated by genglobals.py |
|
// Module: control/clk_delay.v |
wire hold_clk_iorq; |
wire hold_clk_wait; |
wire iorq_Tw; |
wire busack; |
wire pin_control_oe; |
wire hold_clk_busrq; |
|
// Module: control/decode_state.v |
wire in_halt; |
wire table_cb; |
wire table_ed; |
wire table_xx; |
wire use_ix; |
wire use_ixiy; |
wire in_alu; |
wire repeat_en; |
|
// Module: control/exec_module.vh |
wire ctl_state_iy_set; |
wire ctl_state_ixiy_clr; |
wire ctl_state_ixiy_we; |
wire ctl_state_halt_set; |
wire ctl_state_tbl_clr; |
wire ctl_state_tbl_ed_set; |
wire ctl_state_tbl_cb_set; |
wire ctl_state_alu; |
wire ctl_repeat_we; |
wire ctl_iff1_iff2; |
wire ctl_iffx_we; |
wire ctl_iffx_bit; |
wire ctl_im_we; |
wire ctl_no_ints; |
wire ctl_ir_we; |
wire ctl_mRead; |
wire ctl_mWrite; |
wire ctl_iorw; |
wire ctl_shift_en; |
wire ctl_daa_oe; |
wire ctl_alu_op_low; |
wire ctl_cond_short; |
wire ctl_alu_core_hf; |
wire ctl_eval_cond; |
wire ctl_66_oe; |
wire [1:0] ctl_pf_sel; |
wire ctl_alu_oe; |
wire ctl_alu_shift_oe; |
wire ctl_alu_op2_oe; |
wire ctl_alu_res_oe; |
wire ctl_alu_op1_oe; |
wire ctl_alu_bs_oe; |
wire ctl_alu_op1_sel_bus; |
wire ctl_alu_op1_sel_low; |
wire ctl_alu_op1_sel_zero; |
wire ctl_alu_op2_sel_zero; |
wire ctl_alu_op2_sel_bus; |
wire ctl_alu_op2_sel_lq; |
wire ctl_alu_sel_op2_neg; |
wire ctl_alu_sel_op2_high; |
wire ctl_alu_core_R; |
wire ctl_alu_core_V; |
wire ctl_alu_core_S; |
wire ctl_flags_oe; |
wire ctl_flags_bus; |
wire ctl_flags_alu; |
wire ctl_flags_nf_set; |
wire ctl_flags_cf_set; |
wire ctl_flags_cf_cpl; |
wire ctl_flags_cf_we; |
wire ctl_flags_sz_we; |
wire ctl_flags_xy_we; |
wire ctl_flags_hf_we; |
wire ctl_flags_pf_we; |
wire ctl_flags_nf_we; |
wire ctl_flags_cf2_we; |
wire ctl_flags_hf_cpl; |
wire ctl_flags_use_cf2; |
wire ctl_flags_hf2_we; |
wire ctl_flags_nf_clr; |
wire ctl_alu_zero_16bit; |
wire [1:0] ctl_flags_cf2_sel; |
wire ctl_sw_4d; |
wire ctl_sw_4u; |
wire ctl_reg_in_hi; |
wire ctl_reg_in_lo; |
wire ctl_reg_out_lo; |
wire ctl_reg_out_hi; |
wire ctl_reg_exx; |
wire ctl_reg_ex_af; |
wire ctl_reg_ex_de_hl; |
wire ctl_reg_use_sp; |
wire ctl_reg_sel_pc; |
wire ctl_reg_sel_ir; |
wire ctl_reg_sel_wz; |
wire ctl_reg_gp_we; |
wire ctl_reg_not_pc; |
wire ctl_reg_sys_we_lo; |
wire ctl_reg_sys_we_hi; |
wire ctl_reg_sys_we; |
wire [1:0] ctl_reg_gp_hilo; |
wire [1:0] ctl_reg_gp_sel; |
wire [1:0] ctl_reg_sys_hilo; |
wire ctl_inc_cy; |
wire ctl_inc_dec; |
wire ctl_inc_zero; |
wire ctl_al_we; |
wire ctl_inc_limit6; |
wire ctl_bus_inc_oe; |
wire ctl_apin_mux; |
wire ctl_apin_mux2; |
wire ctl_bus_ff_oe; |
wire ctl_bus_zero_oe; |
wire ctl_bus_db_oe; |
wire ctl_sw_1u; |
wire ctl_sw_1d; |
wire ctl_sw_2u; |
wire ctl_sw_2d; |
wire ctl_sw_mask543_en; |
wire ctl_bus_db_we; |
|
// Module: control/execute.sv |
wire nextM; |
wire setM1; |
wire fFetch; |
wire fMRead; |
wire fMWrite; |
wire fIORead; |
wire fIOWrite; |
|
// Module: control/interrupts.v |
wire iff1; |
wire iff2; |
wire im1; |
wire im2; |
wire in_nmi; |
wire in_intr; |
|
// Module: control/ir.v |
wire [7:0] opcode; |
|
// Module: control/pin_control.v |
wire bus_ab_pin_we; |
wire bus_db_pin_oe; |
wire bus_db_pin_re; |
|
// Module: control/pla_decode.sv |
wire [104:0] pla; |
|
// Module: control/resets.v |
wire clrpc; |
wire nreset; |
|
// Module: control/memory_ifc.v |
wire nM1_out; |
wire nRFSH_out; |
wire nMREQ_out; |
wire nRD_out; |
wire nWR_out; |
wire nIORQ_out; |
wire latch_wait; |
|
// Module: control/sequencer.v |
wire M1; |
wire M2; |
wire M3; |
wire M4; |
wire M5; |
wire M6; |
wire T1; |
wire T2; |
wire T3; |
wire T4; |
wire T5; |
wire T6; |
wire timings_en; |
|
// Module: alu/alu_control.v |
wire alu_shift_in; |
wire alu_shift_right; |
wire alu_shift_left; |
wire shift_cf_out; |
wire alu_parity_in; |
wire flags_cond_true; |
wire daa_cf_out; |
wire pf_sel; |
wire alu_op_low; |
wire alu_core_cf_in; |
wire [7:0] db; |
|
// Module: alu/alu_select.v |
wire alu_oe; |
wire alu_shift_oe; |
wire alu_op2_oe; |
wire alu_res_oe; |
wire alu_op1_oe; |
wire alu_bs_oe; |
wire alu_op1_sel_bus; |
wire alu_op1_sel_low; |
wire alu_op1_sel_zero; |
wire alu_op2_sel_zero; |
wire alu_op2_sel_bus; |
wire alu_op2_sel_lq; |
wire alu_sel_op2_neg; |
wire alu_sel_op2_high; |
wire alu_core_R; |
wire alu_core_V; |
wire alu_core_S; |
|
// Module: alu/alu_flags.v |
wire flags_sf; |
wire flags_zf; |
wire flags_hf; |
wire flags_pf; |
wire flags_cf; |
wire flags_nf; |
wire flags_cf_latch; |
wire flags_hf2; |
|
// Module: alu/alu.v |
wire alu_zero; |
wire alu_parity_out; |
wire alu_high_eq_9; |
wire alu_high_gt_9; |
wire alu_low_gt_9; |
wire alu_shift_db0; |
wire alu_shift_db7; |
wire alu_core_cf_out; |
wire alu_sf_out; |
wire alu_yf_out; |
wire alu_xf_out; |
wire alu_vf_out; |
wire [3:0] test_db_high; |
wire [3:0] test_db_low; |
|
// Module: registers/reg_control.v |
wire reg_sel_bc; |
wire reg_sel_bc2; |
wire reg_sel_ix; |
wire reg_sel_iy; |
wire reg_sel_de; |
wire reg_sel_hl; |
wire reg_sel_de2; |
wire reg_sel_hl2; |
wire reg_sel_af; |
wire reg_sel_af2; |
wire reg_sel_wz; |
wire reg_sel_pc; |
wire reg_sel_ir; |
wire reg_sel_sp; |
wire reg_sel_gp_hi; |
wire reg_sel_gp_lo; |
wire reg_sel_sys_lo; |
wire reg_sel_sys_hi; |
wire reg_gp_we; |
wire reg_sys_we_lo; |
wire reg_sys_we_hi; |
|
// Module: bus/address_latch.v |
wire address_is_1; |
wire [15:0] address; |
|
// Module: bus/address_pins.v |
wire [15:0] abus; |
|
// Module: bus/bus_control.v |
wire bus_db_oe; |
|
// Module: bus/bus_switch.sv |
wire bus_sw_1u; |
wire bus_sw_1d; |
wire bus_sw_2u; |
wire bus_sw_2d; |
wire bus_sw_mask543_en; |
|
// Module: bus/control_pins_n.v |
wire nmi; |
wire busrq; |
wire clk; |
wire intr; |
wire mwait; |
wire reset_in; |
wire pin_nM1; |
wire pin_nMREQ; |
wire pin_nIORQ; |
wire pin_nRD; |
wire pin_nWR; |
wire pin_nRFSH; |
wire pin_nHALT; |
wire pin_nBUSACK; |
/trunk/cpu/toplevel/z80_top_direct_n.sv
27,7 → 27,7
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
// Include core A-Z80 level connecting all internal modules |
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
`include "core.i" |
`include "core.vh" |
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
// Address, Data and Control bus drivers connecting to external pins |
/trunk/cpu/toplevel/genglobals.py
22,7 → 22,7
files = f.read().splitlines() |
|
# Create a file that should be included in the top-level source |
with open('globals.i', 'w') as file1: |
with open('globals.vh', 'w') as file1: |
file1.write("// Automatically generated by genglobals.py\n") |
|
# Keep track of duplicated symbols across all files |
46,7 → 46,7
wires.append(info[2].translate(None, ';,')) |
|
if len(wires)>0: |
with open('globals.i', 'a') as file1: |
with open('globals.vh', 'a') as file1: |
file1.write("\n// Module: " + infile + "\n") |
for wire in wires: |
# Everything in globals is a wire |
57,7 → 57,7
file1.write("wire " + wire + ";\n") |
globals.append(wire) |
|
# Touch files that include 'globals.i' to ensure it will recompile correctly |
os.utime("core.i", None) |
# Touch files that include 'globals.vh' to ensure it will recompile correctly |
os.utime("core.vh", None) |
os.utime("z80_top_direct_n.sv", None) |
os.utime("z80_top_ifc_n.sv", None) |
/trunk/cpu/toplevel/core.vh
0,0 → 1,81
//============================================================================ |
// A-Z80 core, instantiates and connects all internal blocks. |
// |
// This file is included by the "z80_top_ifc_n" and "z80_top_direct" providing |
// interface binding and direct (no interface) binding. |
//============================================================================ |
|
// Include a list of top-level signal wires |
`include "globals.vh" |
|
// Specific to Modelsim, some modules in the schematics need to be pre-initialized |
// to avoid starting simulations with unknown values in selected flip flops. |
// When synthesized, the CPU RESET input signal will do the work. |
reg fpga_reset = 0; |
initial begin |
fpga_reset = 1; |
#1 fpga_reset = 0; |
end |
|
// Define internal data bus partitions separated by data bus switches |
wire [7:0] db0; // Segment connecting data pins and IR |
wire [7:0] db1; // Segment with ALU |
wire [7:0] db2; // Segment with msb part of the register address-side interface |
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
// Control block |
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
// Collect the PLA instruction decode prefix bitfield |
logic [6:0] prefix; |
assign prefix = { ~use_ixiy, use_ixiy, ~in_halt, in_alu, table_xx, table_cb, table_ed }; |
|
ir instruction_reg_( .*, .db(db0[7:0]) ); |
pla_decode pla_decode_( .* ); |
resets reset_block_( .* ); |
sequencer sequencer_( .* ); |
execute execute_( .* ); |
interrupts interrupts_( .*, .db(db0[4:3]) ); |
decode_state decode_state_( .* ); |
clk_delay clk_delay_( .* ); |
pin_control pin_control_( .* ); |
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
// ALU and ALU control, including the flags |
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
alu_control alu_control_( .*, .db(db1[7:0]), .op543({pla[104],pla[103],pla[102]}) ); |
alu_select alu_select_( .* ); |
alu_flags alu_flags_( .*, .db(db1[7:0]) ); |
alu alu_( .*, .db(db2[7:0]), .bsel(db0[5:3]) ); |
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
// Register file and register control |
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
wire [7:0] db_hi_as; |
wire [7:0] db_lo_as; |
|
reg_file reg_file_( .*, .db_hi_ds(db2[7:0]), .db_lo_ds(db1[7:0]), .db_hi_as(db_hi_as[7:0]), .db_lo_as(db_lo_as[7:0]) ); |
reg_control reg_control_( .* ); |
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
// Address latch (with the incrementer) |
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
address_latch address_latch_( .*, .abus({db_hi_as[7:0], db_lo_as[7:0]}) ); |
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
// Timing control of the external pins |
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
wire nM1_int; |
assign nM1_int = !((setM1 & nextM) | (fFetch & T1)); |
memory_ifc memory_ifc_( .* ); |
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
// Data path within the CPU in various forms, ending with data pins |
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
bus_switch bus_switch_( .* ); |
data_switch sw2_( .sw_up_en(bus_sw_2u), .sw_down_en(bus_sw_2d), .db_up(db1[7:0]), .db_down(db2[7:0]) ); |
|
// Controls writers to the first section of the data bus |
bus_control bus_control_( .*, .db(db0[7:0]) ); |
|
// Data switch SW1 with the data mask |
data_switch_mask sw1_( .sw_mask543_en(bus_sw_mask543_en), .sw_up_en(bus_sw_1u), .sw_down_en(bus_sw_1d), .db_up(db0[7:0]), .db_down(db1[7:0]) ); |
/trunk/cpu/toplevel/test_fuse.vh
0,0 → 1,5065
// Automatically generated by genfuse.py |
|
force dut.reg_file_.reg_gp_we=0; |
force dut.reg_control_.ctl_reg_sys_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
#2 |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode 00 NOP"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'h00; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#6 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h00) $fdisplay(f,"* Reg af a=%h !=00",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h00) $fdisplay(f,"* Reg bc c=%h !=00",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h00) $fdisplay(f,"* Reg bc b=%h !=00",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h00) $fdisplay(f,"* Reg de e=%h !=00",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h00) $fdisplay(f,"* Reg de d=%h !=00",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h00) $fdisplay(f,"* Reg hl l=%h !=00",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h00) $fdisplay(f,"* Reg hl h=%h !=00",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode ed67 RRD"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h24; |
force dut.reg_file_.b2v_latch_af_hi.db=8'h36; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h6a; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'hb1; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'hdb; |
force dut.reg_file_.b2v_latch_de_hi.db=8'ha4; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'hde; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'hb9; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'hed; |
ram.Mem[1] = 8'h67; |
// Preset memory |
ram.Mem[47582] = 8'h93; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#34 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h24) $fdisplay(f,"* Reg af f=%h !=24",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h33) $fdisplay(f,"* Reg af a=%h !=33",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h6a) $fdisplay(f,"* Reg bc c=%h !=6a",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'hb1) $fdisplay(f,"* Reg bc b=%h !=b1",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hdb) $fdisplay(f,"* Reg de e=%h !=db",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'ha4) $fdisplay(f,"* Reg de d=%h !=a4",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'hde) $fdisplay(f,"* Reg hl l=%h !=de",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hb9) $fdisplay(f,"* Reg hl h=%h !=b9",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
if (ram.Mem[47582]!==8'h69) $fdisplay(f,"* Mem[b9de]=%h !=69",ram.Mem[47582]); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode ed6f RLD"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h8b; |
force dut.reg_file_.b2v_latch_af_hi.db=8'h65; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h7a; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h7a; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'hf0; |
force dut.reg_file_.b2v_latch_de_hi.db=8'hec; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'h3c; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'h40; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'hed; |
ram.Mem[1] = 8'h6f; |
// Preset memory |
ram.Mem[16444] = 8'hc4; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#34 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h2d) $fdisplay(f,"* Reg af f=%h !=2d",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h6c) $fdisplay(f,"* Reg af a=%h !=6c",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h7a) $fdisplay(f,"* Reg bc c=%h !=7a",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h7a) $fdisplay(f,"* Reg bc b=%h !=7a",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hf0) $fdisplay(f,"* Reg de e=%h !=f0",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hec) $fdisplay(f,"* Reg de d=%h !=ec",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h3c) $fdisplay(f,"* Reg hl l=%h !=3c",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h40) $fdisplay(f,"* Reg hl h=%h !=40",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
if (ram.Mem[16444]!==8'h45) $fdisplay(f,"* Mem[403c]=%h !=45",ram.Mem[16444]); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode 81 ADD A,C"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h20; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'h81; |
// Preset memory |
ram.Mem[56486] = 8'h49; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#6 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h31) $fdisplay(f,"* Reg af f=%h !=31",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h30) $fdisplay(f,"* Reg af a=%h !=30",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode cb41 BIT 0,C"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'h9e; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h43; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h1b; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'h4e; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h95; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'he9; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'h7b; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'hcb; |
ram.Mem[1] = 8'h41; |
// Preset memory |
ram.Mem[31721] = 8'hf7; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#14 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h10) $fdisplay(f,"* Reg af f=%h !=10",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h9e) $fdisplay(f,"* Reg af a=%h !=9e",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h43) $fdisplay(f,"* Reg bc c=%h !=43",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h1b) $fdisplay(f,"* Reg bc b=%h !=1b",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h4e) $fdisplay(f,"* Reg de e=%h !=4e",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h95) $fdisplay(f,"* Reg de d=%h !=95",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'he9) $fdisplay(f,"* Reg hl l=%h !=e9",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h7b) $fdisplay(f,"* Reg hl h=%h !=7b",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode cb93 RES 2,E"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'hc2; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h05; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h4e; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'hf8; |
force dut.reg_file_.b2v_latch_de_hi.db=8'hb3; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'h34; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'h22; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'hcb; |
ram.Mem[1] = 8'h93; |
// Preset memory |
ram.Mem[8756] = 8'ha0; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#14 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hc2) $fdisplay(f,"* Reg af a=%h !=c2",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h05) $fdisplay(f,"* Reg bc c=%h !=05",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h4e) $fdisplay(f,"* Reg bc b=%h !=4e",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hf8) $fdisplay(f,"* Reg de e=%h !=f8",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hb3) $fdisplay(f,"* Reg de d=%h !=b3",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h34) $fdisplay(f,"* Reg hl l=%h !=34",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h22) $fdisplay(f,"* Reg hl h=%h !=22",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode cbe5 SET 4,L"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'hca; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h0d; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'hdf; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'h88; |
force dut.reg_file_.b2v_latch_de_hi.db=8'hd5; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'h8f; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'hb4; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'hcb; |
ram.Mem[1] = 8'he5; |
// Preset memory |
ram.Mem[46223] = 8'hcf; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#14 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hca) $fdisplay(f,"* Reg af a=%h !=ca",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h0d) $fdisplay(f,"* Reg bc c=%h !=0d",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'hdf) $fdisplay(f,"* Reg bc b=%h !=df",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h88) $fdisplay(f,"* Reg de e=%h !=88",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hd5) $fdisplay(f,"* Reg de d=%h !=d5",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h9f) $fdisplay(f,"* Reg hl l=%h !=9f",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hb4) $fdisplay(f,"* Reg hl h=%h !=b4",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode 8c ADC A,H"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h20; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'h8c; |
// Preset memory |
ram.Mem[56486] = 8'h49; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#6 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h91) $fdisplay(f,"* Reg af f=%h !=91",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hd1) $fdisplay(f,"* Reg af a=%h !=d1",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode 92 SUB D"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h20; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'h92; |
// Preset memory |
ram.Mem[56486] = 8'h49; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#6 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h82) $fdisplay(f,"* Reg af f=%h !=82",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hd5) $fdisplay(f,"* Reg af a=%h !=d5",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode 9d SBC A,L"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h20; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'h9d; |
// Preset memory |
ram.Mem[56486] = 8'h49; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#6 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h1a) $fdisplay(f,"* Reg af f=%h !=1a",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h4f) $fdisplay(f,"* Reg af a=%h !=4f",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode a3 AND E"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h20; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'ha3; |
// Preset memory |
ram.Mem[56486] = 8'h49; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#6 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h14) $fdisplay(f,"* Reg af f=%h !=14",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h05) $fdisplay(f,"* Reg af a=%h !=05",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode ae XOR (HL)"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h20; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'hae; |
// Preset memory |
ram.Mem[56486] = 8'h49; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#12 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'ha8) $fdisplay(f,"* Reg af f=%h !=a8",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hbc) $fdisplay(f,"* Reg af a=%h !=bc",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode b4 OR H"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h20; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'hb4; |
// Preset memory |
ram.Mem[56486] = 8'h49; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#6 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'ha8) $fdisplay(f,"* Reg af f=%h !=a8",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hfd) $fdisplay(f,"* Reg af a=%h !=fd",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode bf CP A"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h20; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'hbf; |
// Preset memory |
ram.Mem[56486] = 8'h49; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#6 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h62) $fdisplay(f,"* Reg af f=%h !=62",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hf5) $fdisplay(f,"* Reg af a=%h !=f5",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode 43 LD B,E"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'h02; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h98; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'hcf; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'hd8; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h90; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'h69; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'ha1; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'h43; |
// Preset memory |
ram.Mem[41321] = 8'h50; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#6 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h02) $fdisplay(f,"* Reg af a=%h !=02",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h98) $fdisplay(f,"* Reg bc c=%h !=98",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'hd8) $fdisplay(f,"* Reg bc b=%h !=d8",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hd8) $fdisplay(f,"* Reg de e=%h !=d8",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h90) $fdisplay(f,"* Reg de d=%h !=90",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h69) $fdisplay(f,"* Reg hl l=%h !=69",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'ha1) $fdisplay(f,"* Reg hl h=%h !=a1",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode 6e LD L,(HL)"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'h02; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h98; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'hcf; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'hd8; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h90; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'h69; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'ha1; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'h6e; |
// Preset memory |
ram.Mem[41321] = 8'h50; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#12 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h02) $fdisplay(f,"* Reg af a=%h !=02",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h98) $fdisplay(f,"* Reg bc c=%h !=98",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'hcf) $fdisplay(f,"* Reg bc b=%h !=cf",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hd8) $fdisplay(f,"* Reg de e=%h !=d8",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h90) $fdisplay(f,"* Reg de d=%h !=90",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h50) $fdisplay(f,"* Reg hl l=%h !=50",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'ha1) $fdisplay(f,"* Reg hl h=%h !=a1",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode e3 EX (SP),HL"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'h22; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'h4d; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h73; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h03; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'he3; |
// Preset memory |
ram.Mem[883] = 8'h8e; |
ram.Mem[884] = 8'he1; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#36 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h00) $fdisplay(f,"* Reg af a=%h !=00",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h00) $fdisplay(f,"* Reg bc c=%h !=00",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h00) $fdisplay(f,"* Reg bc b=%h !=00",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h00) $fdisplay(f,"* Reg de e=%h !=00",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h00) $fdisplay(f,"* Reg de d=%h !=00",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h8e) $fdisplay(f,"* Reg hl l=%h !=8e",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'he1) $fdisplay(f,"* Reg hl h=%h !=e1",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h73) $fdisplay(f,"* Reg sp p=%h !=73",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h03) $fdisplay(f,"* Reg sp s=%h !=03",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
if (ram.Mem[883]!==8'h22) $fdisplay(f,"* Mem[373]=%h !=22",ram.Mem[883]); |
if (ram.Mem[884]!==8'h4d) $fdisplay(f,"* Mem[374]=%h !=4d",ram.Mem[884]); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode 03 INC BC"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h9a; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h78; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'h03; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#10 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h00) $fdisplay(f,"* Reg af a=%h !=00",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h9b) $fdisplay(f,"* Reg bc c=%h !=9b",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h78) $fdisplay(f,"* Reg bc b=%h !=78",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h00) $fdisplay(f,"* Reg de e=%h !=00",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h00) $fdisplay(f,"* Reg de d=%h !=00",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h00) $fdisplay(f,"* Reg hl l=%h !=00",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h00) $fdisplay(f,"* Reg hl h=%h !=00",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode 3b DEC SP"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h36; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h9d; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'h3b; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#10 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h00) $fdisplay(f,"* Reg af a=%h !=00",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h00) $fdisplay(f,"* Reg bc c=%h !=00",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h00) $fdisplay(f,"* Reg bc b=%h !=00",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h00) $fdisplay(f,"* Reg de e=%h !=00",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h00) $fdisplay(f,"* Reg de d=%h !=00",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h00) $fdisplay(f,"* Reg hl l=%h !=00",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h00) $fdisplay(f,"* Reg hl h=%h !=00",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h35) $fdisplay(f,"* Reg sp p=%h !=35",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h9d) $fdisplay(f,"* Reg sp s=%h !=9d",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode 07 RLCA"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'h88; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'h07; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#6 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h01) $fdisplay(f,"* Reg af f=%h !=01",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h11) $fdisplay(f,"* Reg af a=%h !=11",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h00) $fdisplay(f,"* Reg bc c=%h !=00",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h00) $fdisplay(f,"* Reg bc b=%h !=00",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h00) $fdisplay(f,"* Reg de e=%h !=00",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h00) $fdisplay(f,"* Reg de d=%h !=00",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h00) $fdisplay(f,"* Reg hl l=%h !=00",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h00) $fdisplay(f,"* Reg hl h=%h !=00",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode 1f RRA"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'hc4; |
force dut.reg_file_.b2v_latch_af_hi.db=8'h01; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'h1f; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#6 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'hc5) $fdisplay(f,"* Reg af f=%h !=c5",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h00) $fdisplay(f,"* Reg af a=%h !=00",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h00) $fdisplay(f,"* Reg bc c=%h !=00",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h00) $fdisplay(f,"* Reg bc b=%h !=00",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h00) $fdisplay(f,"* Reg de e=%h !=00",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h00) $fdisplay(f,"* Reg de d=%h !=00",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h00) $fdisplay(f,"* Reg hl l=%h !=00",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h00) $fdisplay(f,"* Reg hl h=%h !=00",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode cb09 RRC C"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'h18; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h5c; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h12; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'h97; |
force dut.reg_file_.b2v_latch_de_hi.db=8'hdd; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'hc6; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'h59; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'hcb; |
ram.Mem[1] = 8'h09; |
// Preset memory |
ram.Mem[22982] = 8'h9e; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#14 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h2c) $fdisplay(f,"* Reg af f=%h !=2c",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h18) $fdisplay(f,"* Reg af a=%h !=18",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h2e) $fdisplay(f,"* Reg bc c=%h !=2e",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h12) $fdisplay(f,"* Reg bc b=%h !=12",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h97) $fdisplay(f,"* Reg de e=%h !=97",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hdd) $fdisplay(f,"* Reg de d=%h !=dd",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'hc6) $fdisplay(f,"* Reg hl l=%h !=c6",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h59) $fdisplay(f,"* Reg hl h=%h !=59",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode cb11 RL C"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'h65; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h5c; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'he2; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'h8a; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h4b; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'h42; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'hed; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'hcb; |
ram.Mem[1] = 8'h11; |
// Preset memory |
ram.Mem[60738] = 8'hb7; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#14 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'hac) $fdisplay(f,"* Reg af f=%h !=ac",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h65) $fdisplay(f,"* Reg af a=%h !=65",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'hb8) $fdisplay(f,"* Reg bc c=%h !=b8",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'he2) $fdisplay(f,"* Reg bc b=%h !=e2",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h8a) $fdisplay(f,"* Reg de e=%h !=8a",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h4b) $fdisplay(f,"* Reg de d=%h !=4b",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h42) $fdisplay(f,"* Reg hl l=%h !=42",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hed) $fdisplay(f,"* Reg hl h=%h !=ed",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode cb36 SLL (HL)*"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'h8a; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h85; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h11; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'hde; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h1d; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'h38; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'h6d; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'hcb; |
ram.Mem[1] = 8'h36; |
// Preset memory |
ram.Mem[27960] = 8'hf1; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#28 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'ha1) $fdisplay(f,"* Reg af f=%h !=a1",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h8a) $fdisplay(f,"* Reg af a=%h !=8a",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h85) $fdisplay(f,"* Reg bc c=%h !=85",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h11) $fdisplay(f,"* Reg bc b=%h !=11",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hde) $fdisplay(f,"* Reg de e=%h !=de",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h1d) $fdisplay(f,"* Reg de d=%h !=1d",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h38) $fdisplay(f,"* Reg hl l=%h !=38",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h6d) $fdisplay(f,"* Reg hl h=%h !=6d",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
if (ram.Mem[27960]!==8'he3) $fdisplay(f,"* Mem[6d38]=%h !=e3",ram.Mem[27960]); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode cb52 BIT 2,D"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'h8b; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h7a; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'hff; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'hff; |
force dut.reg_file_.b2v_latch_de_hi.db=8'hb0; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'h44; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'hac; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'hcb; |
ram.Mem[1] = 8'h52; |
// Preset memory |
ram.Mem[44100] = 8'h00; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#14 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h74) $fdisplay(f,"* Reg af f=%h !=74",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h8b) $fdisplay(f,"* Reg af a=%h !=8b",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h7a) $fdisplay(f,"* Reg bc c=%h !=7a",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'hff) $fdisplay(f,"* Reg bc b=%h !=ff",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hff) $fdisplay(f,"* Reg de e=%h !=ff",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hb0) $fdisplay(f,"* Reg de d=%h !=b0",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h44) $fdisplay(f,"* Reg hl l=%h !=44",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hac) $fdisplay(f,"* Reg hl h=%h !=ac",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode cb93 RES 2,E"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'hc2; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h05; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h4e; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'hf8; |
force dut.reg_file_.b2v_latch_de_hi.db=8'hb3; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'h34; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'h22; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'hcb; |
ram.Mem[1] = 8'h93; |
// Preset memory |
ram.Mem[8756] = 8'ha0; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#14 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hc2) $fdisplay(f,"* Reg af a=%h !=c2",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h05) $fdisplay(f,"* Reg bc c=%h !=05",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h4e) $fdisplay(f,"* Reg bc b=%h !=4e",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hf8) $fdisplay(f,"* Reg de e=%h !=f8",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hb3) $fdisplay(f,"* Reg de d=%h !=b3",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h34) $fdisplay(f,"* Reg hl l=%h !=34",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h22) $fdisplay(f,"* Reg hl h=%h !=22",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode cbc4 SET 0,H"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af_hi.db=8'h7e; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h5a; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h54; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'hcf; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h6e; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'h76; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'h58; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'hcb; |
ram.Mem[1] = 8'hc4; |
// Preset memory |
ram.Mem[22646] = 8'h9d; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#14 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h7e) $fdisplay(f,"* Reg af a=%h !=7e",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h5a) $fdisplay(f,"* Reg bc c=%h !=5a",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h54) $fdisplay(f,"* Reg bc b=%h !=54",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hcf) $fdisplay(f,"* Reg de e=%h !=cf",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h6e) $fdisplay(f,"* Reg de d=%h !=6e",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h76) $fdisplay(f,"* Reg hl l=%h !=76",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h59) $fdisplay(f,"* Reg hl h=%h !=59",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode dd75 LD (IX+d),L"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'h72; |
force dut.reg_file_.b2v_latch_af_hi.db=8'h57; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h33; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'he8; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'h3e; |
force dut.reg_file_.b2v_latch_de_hi.db=8'hb6; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'h4f; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'h73; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h4c; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'hae; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'hc2; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'he8; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'hdd; |
ram.Mem[1] = 8'h75; |
ram.Mem[2] = 8'h30; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#36 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h72) $fdisplay(f,"* Reg af f=%h !=72",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h57) $fdisplay(f,"* Reg af a=%h !=57",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h33) $fdisplay(f,"* Reg bc c=%h !=33",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'he8) $fdisplay(f,"* Reg bc b=%h !=e8",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h3e) $fdisplay(f,"* Reg de e=%h !=3e",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hb6) $fdisplay(f,"* Reg de d=%h !=b6",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h4f) $fdisplay(f,"* Reg hl l=%h !=4f",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h73) $fdisplay(f,"* Reg hl h=%h !=73",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h4c) $fdisplay(f,"* Reg ix x=%h !=4c",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'hae) $fdisplay(f,"* Reg ix i=%h !=ae",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'hc2) $fdisplay(f,"* Reg iy y=%h !=c2",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'he8) $fdisplay(f,"* Reg iy i=%h !=e8",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0003) $fdisplay(f,"* PC=%h !=0003",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
if (ram.Mem[44668]!==8'h4f) $fdisplay(f,"* Mem[ae7c]=%h !=4f",ram.Mem[44668]); |
//-------------------------------------------------------------------------------- |
force dut.instruction_reg_.ctl_ir_we=1; |
force dut.instruction_reg_.db=0; |
#2 release dut.instruction_reg_.ctl_ir_we; |
release dut.instruction_reg_.db; |
$fdisplay(f,"Testing opcode dd4e LD C,(IX+d)"); |
// Preset af |
force dut.reg_file_.b2v_latch_af_lo.we=1; |
force dut.reg_file_.b2v_latch_af_hi.we=1; |
force dut.reg_file_.b2v_latch_af_lo.db=8'hf7; |
force dut.reg_file_.b2v_latch_af_hi.db=8'h7b; |
#2 release dut.reg_file_.b2v_latch_af_lo.we; |
release dut.reg_file_.b2v_latch_af_hi.we; |
release dut.reg_file_.b2v_latch_af_lo.db; |
release dut.reg_file_.b2v_latch_af_hi.db; |
// Preset bc |
force dut.reg_file_.b2v_latch_bc_lo.we=1; |
force dut.reg_file_.b2v_latch_bc_hi.we=1; |
force dut.reg_file_.b2v_latch_bc_lo.db=8'h05; |
force dut.reg_file_.b2v_latch_bc_hi.db=8'h66; |
#2 release dut.reg_file_.b2v_latch_bc_lo.we; |
release dut.reg_file_.b2v_latch_bc_hi.we; |
release dut.reg_file_.b2v_latch_bc_lo.db; |
release dut.reg_file_.b2v_latch_bc_hi.db; |
// Preset de |
force dut.reg_file_.b2v_latch_de_lo.we=1; |
force dut.reg_file_.b2v_latch_de_hi.we=1; |
force dut.reg_file_.b2v_latch_de_lo.db=8'h55; |
force dut.reg_file_.b2v_latch_de_hi.db=8'h8d; |
#2 release dut.reg_file_.b2v_latch_de_lo.we; |
release dut.reg_file_.b2v_latch_de_hi.we; |
release dut.reg_file_.b2v_latch_de_lo.db; |
release dut.reg_file_.b2v_latch_de_hi.db; |
// Preset hl |
force dut.reg_file_.b2v_latch_hl_lo.we=1; |
force dut.reg_file_.b2v_latch_hl_hi.we=1; |
force dut.reg_file_.b2v_latch_hl_lo.db=8'hf2; |
force dut.reg_file_.b2v_latch_hl_hi.db=8'hde; |
#2 release dut.reg_file_.b2v_latch_hl_lo.we; |
release dut.reg_file_.b2v_latch_hl_hi.we; |
release dut.reg_file_.b2v_latch_hl_lo.db; |
release dut.reg_file_.b2v_latch_hl_hi.db; |
// Preset af2 |
force dut.reg_file_.b2v_latch_af2_lo.we=1; |
force dut.reg_file_.b2v_latch_af2_hi.we=1; |
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_af2_lo.we; |
release dut.reg_file_.b2v_latch_af2_hi.we; |
release dut.reg_file_.b2v_latch_af2_lo.db; |
release dut.reg_file_.b2v_latch_af2_hi.db; |
// Preset bc2 |
force dut.reg_file_.b2v_latch_bc2_lo.we=1; |
force dut.reg_file_.b2v_latch_bc2_hi.we=1; |
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_bc2_lo.we; |
release dut.reg_file_.b2v_latch_bc2_hi.we; |
release dut.reg_file_.b2v_latch_bc2_lo.db; |
release dut.reg_file_.b2v_latch_bc2_hi.db; |
// Preset de2 |
force dut.reg_file_.b2v_latch_de2_lo.we=1; |
force dut.reg_file_.b2v_latch_de2_hi.we=1; |
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_de2_lo.we; |
release dut.reg_file_.b2v_latch_de2_hi.we; |
release dut.reg_file_.b2v_latch_de2_lo.db; |
release dut.reg_file_.b2v_latch_de2_hi.db; |
// Preset hl2 |
force dut.reg_file_.b2v_latch_hl2_lo.we=1; |
force dut.reg_file_.b2v_latch_hl2_hi.we=1; |
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_hl2_lo.we; |
release dut.reg_file_.b2v_latch_hl2_hi.we; |
release dut.reg_file_.b2v_latch_hl2_lo.db; |
release dut.reg_file_.b2v_latch_hl2_hi.db; |
// Preset ix |
force dut.reg_file_.b2v_latch_ix_lo.we=1; |
force dut.reg_file_.b2v_latch_ix_hi.we=1; |
force dut.reg_file_.b2v_latch_ix_lo.db=8'h4b; |
force dut.reg_file_.b2v_latch_ix_hi.db=8'hd9; |
#2 release dut.reg_file_.b2v_latch_ix_lo.we; |
release dut.reg_file_.b2v_latch_ix_hi.we; |
release dut.reg_file_.b2v_latch_ix_lo.db; |
release dut.reg_file_.b2v_latch_ix_hi.db; |
// Preset iy |
force dut.reg_file_.b2v_latch_iy_lo.we=1; |
force dut.reg_file_.b2v_latch_iy_hi.we=1; |
force dut.reg_file_.b2v_latch_iy_lo.db=8'hfb; |
force dut.reg_file_.b2v_latch_iy_hi.db=8'h17; |
#2 release dut.reg_file_.b2v_latch_iy_lo.we; |
release dut.reg_file_.b2v_latch_iy_hi.we; |
release dut.reg_file_.b2v_latch_iy_lo.db; |
release dut.reg_file_.b2v_latch_iy_hi.db; |
// Preset sp |
force dut.reg_file_.b2v_latch_sp_lo.we=1; |
force dut.reg_file_.b2v_latch_sp_hi.we=1; |
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_sp_lo.we; |
release dut.reg_file_.b2v_latch_sp_hi.we; |
release dut.reg_file_.b2v_latch_sp_lo.db; |
release dut.reg_file_.b2v_latch_sp_hi.db; |
// Preset wz |
force dut.reg_file_.b2v_latch_wz_lo.we=1; |
force dut.reg_file_.b2v_latch_wz_hi.we=1; |
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_wz_lo.we; |
release dut.reg_file_.b2v_latch_wz_hi.we; |
release dut.reg_file_.b2v_latch_wz_lo.db; |
release dut.reg_file_.b2v_latch_wz_hi.db; |
// Preset pc |
force dut.reg_file_.b2v_latch_pc_lo.we=1; |
force dut.reg_file_.b2v_latch_pc_hi.we=1; |
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_pc_lo.we; |
release dut.reg_file_.b2v_latch_pc_hi.we; |
release dut.reg_file_.b2v_latch_pc_lo.db; |
release dut.reg_file_.b2v_latch_pc_hi.db; |
// Preset ir |
force dut.reg_file_.b2v_latch_ir_lo.we=1; |
force dut.reg_file_.b2v_latch_ir_hi.we=1; |
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00; |
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00; |
#2 release dut.reg_file_.b2v_latch_ir_lo.we; |
release dut.reg_file_.b2v_latch_ir_hi.we; |
release dut.reg_file_.b2v_latch_ir_lo.db; |
release dut.reg_file_.b2v_latch_ir_hi.db; |
// Preset memory |
ram.Mem[0] = 8'hdd; |
ram.Mem[1] = 8'h4e; |
ram.Mem[2] = 8'h2e; |
// Preset memory |
ram.Mem[55673] = 8'h76; |
force dut.z80_top_ifc_n.fpga_reset=0; |
force dut.address_latch_.abus=16'h0000; |
release dut.reg_control_.ctl_reg_sys_we; |
release dut.reg_file_.reg_gp_we; |
#3 |
release dut.address_latch_.abus; |
#1 |
#36 // Execute |
force dut.reg_control_.ctl_reg_sys_we=0; |
#2 pc=z.A; |
#2 |
#1 force dut.reg_file_.reg_gp_we=0; |
force dut.z80_top_ifc_n.fpga_reset=1; |
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'hf7) $fdisplay(f,"* Reg af f=%h !=f7",dut.reg_file_.b2v_latch_af_lo.latch); |
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h7b) $fdisplay(f,"* Reg af a=%h !=7b",dut.reg_file_.b2v_latch_af_hi.latch); |
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h76) $fdisplay(f,"* Reg bc c=%h !=76",dut.reg_file_.b2v_latch_bc_lo.latch); |
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h66) $fdisplay(f,"* Reg bc b=%h !=66",dut.reg_file_.b2v_latch_bc_hi.latch); |
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h55) $fdisplay(f,"* Reg de e=%h !=55",dut.reg_file_.b2v_latch_de_lo.latch); |
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h8d) $fdisplay(f,"* Reg de d=%h !=8d",dut.reg_file_.b2v_latch_de_hi.latch); |
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'hf2) $fdisplay(f,"* Reg hl l=%h !=f2",dut.reg_file_.b2v_latch_hl_lo.latch); |
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hde) $fdisplay(f,"* Reg hl h=%h !=de",dut.reg_file_.b2v_latch_hl_hi.latch); |
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch); |
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch); |
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch); |
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch); |
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch); |
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch); |
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch); |
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch); |
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h4b) $fdisplay(f,"* Reg ix x=%h !=4b",dut.reg_file_.b2v_latch_ix_lo.latch); |
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'hd9) $fdisplay(f,"* Reg ix i=%h !=d9",dut.reg_file_.b2v_latch_ix_hi.latch); |
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'hfb) $fdisplay(f,"* Reg iy y=%h !=fb",dut.reg_file_.b2v_latch_iy_lo.latch); |
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h17) $fdisplay(f,"* Reg iy i=%h !=17",dut.reg_file_.b2v_latch_iy_hi.latch); |
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch); |
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch); |
if (pc!==16'h0003) $fdisplay(f,"* PC=%h !=0003",pc); |
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch); |
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch); |
//-------------------------------------------------------------------------------- |
`define TOTAL_CLKS 1559 |
$fdisplay(f,"=== Tests completed ==="); |
/trunk/cpu/deploy/reg_file.v
0,0 → 1,568
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Fri Nov 07 10:28:48 2014" |
|
module reg_file( |
reg_sel_sys_lo, |
reg_sel_gp_lo, |
reg_sel_sys_hi, |
reg_sel_gp_hi, |
reg_sel_ir, |
reg_sel_pc, |
ctl_sw_4d, |
ctl_sw_4u, |
reg_sel_wz, |
reg_sel_sp, |
reg_sel_iy, |
reg_sel_ix, |
reg_sel_hl2, |
reg_sel_hl, |
reg_sel_de2, |
reg_sel_de, |
reg_sel_bc2, |
reg_sel_bc, |
reg_sel_af2, |
reg_sel_af, |
reg_gp_we, |
reg_sys_we_lo, |
reg_sys_we_hi, |
ctl_reg_in_hi, |
ctl_reg_in_lo, |
ctl_reg_out_lo, |
ctl_reg_out_hi, |
clk, |
db_hi_as, |
db_hi_ds, |
db_lo_as, |
db_lo_ds |
); |
|
|
input wire reg_sel_sys_lo; |
input wire reg_sel_gp_lo; |
input wire reg_sel_sys_hi; |
input wire reg_sel_gp_hi; |
input wire reg_sel_ir; |
input wire reg_sel_pc; |
input wire ctl_sw_4d; |
input wire ctl_sw_4u; |
input wire reg_sel_wz; |
input wire reg_sel_sp; |
input wire reg_sel_iy; |
input wire reg_sel_ix; |
input wire reg_sel_hl2; |
input wire reg_sel_hl; |
input wire reg_sel_de2; |
input wire reg_sel_de; |
input wire reg_sel_bc2; |
input wire reg_sel_bc; |
input wire reg_sel_af2; |
input wire reg_sel_af; |
input wire reg_gp_we; |
input wire reg_sys_we_lo; |
input wire reg_sys_we_hi; |
input wire ctl_reg_in_hi; |
input wire ctl_reg_in_lo; |
input wire ctl_reg_out_lo; |
input wire ctl_reg_out_hi; |
input wire clk; |
inout wire [7:0] db_hi_as; |
inout wire [7:0] db_hi_ds; |
inout wire [7:0] db_lo_as; |
inout wire [7:0] db_lo_ds; |
|
wire [7:0] gdfx_temp0; |
wire [7:0] gdfx_temp1; |
wire SYNTHESIZED_WIRE_84; |
wire SYNTHESIZED_WIRE_85; |
wire SYNTHESIZED_WIRE_86; |
wire SYNTHESIZED_WIRE_28; |
wire SYNTHESIZED_WIRE_29; |
wire SYNTHESIZED_WIRE_30; |
wire SYNTHESIZED_WIRE_31; |
wire SYNTHESIZED_WIRE_32; |
wire SYNTHESIZED_WIRE_33; |
wire SYNTHESIZED_WIRE_34; |
wire SYNTHESIZED_WIRE_35; |
wire SYNTHESIZED_WIRE_36; |
wire SYNTHESIZED_WIRE_37; |
wire SYNTHESIZED_WIRE_38; |
wire SYNTHESIZED_WIRE_39; |
wire SYNTHESIZED_WIRE_40; |
wire SYNTHESIZED_WIRE_41; |
wire SYNTHESIZED_WIRE_42; |
wire SYNTHESIZED_WIRE_43; |
wire SYNTHESIZED_WIRE_44; |
wire SYNTHESIZED_WIRE_45; |
wire SYNTHESIZED_WIRE_46; |
wire SYNTHESIZED_WIRE_47; |
wire SYNTHESIZED_WIRE_48; |
wire SYNTHESIZED_WIRE_49; |
wire SYNTHESIZED_WIRE_50; |
wire SYNTHESIZED_WIRE_51; |
wire SYNTHESIZED_WIRE_52; |
wire SYNTHESIZED_WIRE_53; |
wire SYNTHESIZED_WIRE_54; |
wire SYNTHESIZED_WIRE_55; |
wire SYNTHESIZED_WIRE_56; |
wire SYNTHESIZED_WIRE_57; |
wire SYNTHESIZED_WIRE_58; |
wire SYNTHESIZED_WIRE_59; |
wire SYNTHESIZED_WIRE_60; |
wire SYNTHESIZED_WIRE_61; |
wire SYNTHESIZED_WIRE_62; |
wire SYNTHESIZED_WIRE_63; |
wire SYNTHESIZED_WIRE_64; |
wire SYNTHESIZED_WIRE_65; |
wire SYNTHESIZED_WIRE_66; |
wire SYNTHESIZED_WIRE_67; |
wire SYNTHESIZED_WIRE_68; |
wire SYNTHESIZED_WIRE_69; |
wire SYNTHESIZED_WIRE_70; |
wire SYNTHESIZED_WIRE_71; |
wire SYNTHESIZED_WIRE_72; |
wire SYNTHESIZED_WIRE_73; |
wire SYNTHESIZED_WIRE_74; |
wire SYNTHESIZED_WIRE_75; |
wire SYNTHESIZED_WIRE_76; |
wire SYNTHESIZED_WIRE_77; |
wire SYNTHESIZED_WIRE_78; |
wire SYNTHESIZED_WIRE_79; |
wire SYNTHESIZED_WIRE_80; |
wire SYNTHESIZED_WIRE_81; |
wire SYNTHESIZED_WIRE_82; |
wire SYNTHESIZED_WIRE_83; |
|
|
|
|
assign SYNTHESIZED_WIRE_82 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_wz; |
|
assign SYNTHESIZED_WIRE_80 = reg_sel_wz & reg_sel_sys_hi & SYNTHESIZED_WIRE_85; |
|
assign SYNTHESIZED_WIRE_78 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_sp; |
|
assign SYNTHESIZED_WIRE_76 = reg_sel_sp & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; |
|
assign SYNTHESIZED_WIRE_84 = ~reg_sys_we_lo; |
|
assign SYNTHESIZED_WIRE_71 = reg_sel_gp_lo & reg_gp_we & reg_sel_iy; |
|
assign SYNTHESIZED_WIRE_85 = ~reg_sys_we_hi; |
|
assign SYNTHESIZED_WIRE_74 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_pc; |
|
assign SYNTHESIZED_WIRE_67 = reg_sel_gp_lo & reg_gp_we & reg_sel_ix; |
|
assign SYNTHESIZED_WIRE_55 = reg_sel_gp_lo & reg_gp_we & reg_sel_hl2; |
|
assign SYNTHESIZED_WIRE_72 = reg_sel_pc & reg_sel_sys_hi & SYNTHESIZED_WIRE_85; |
|
assign SYNTHESIZED_WIRE_59 = reg_sel_gp_lo & reg_gp_we & reg_sel_hl; |
|
assign SYNTHESIZED_WIRE_47 = reg_sel_gp_lo & reg_gp_we & reg_sel_de2; |
|
assign SYNTHESIZED_WIRE_51 = reg_sel_gp_lo & reg_gp_we & reg_sel_de; |
|
assign SYNTHESIZED_WIRE_81 = reg_sel_wz & reg_sys_we_hi & reg_sel_sys_hi; |
|
assign SYNTHESIZED_WIRE_86 = ~reg_gp_we; |
|
assign SYNTHESIZED_WIRE_70 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_iy; |
|
assign SYNTHESIZED_WIRE_68 = reg_sel_iy & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; |
|
assign SYNTHESIZED_WIRE_39 = reg_sel_gp_lo & reg_gp_we & reg_sel_bc2; |
|
assign SYNTHESIZED_WIRE_43 = reg_sel_gp_lo & reg_gp_we & reg_sel_bc; |
|
assign SYNTHESIZED_WIRE_31 = reg_sel_gp_lo & reg_gp_we & reg_sel_af2; |
|
assign SYNTHESIZED_WIRE_77 = reg_sel_sp & reg_gp_we & reg_sel_gp_hi; |
|
assign SYNTHESIZED_WIRE_66 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_ix; |
|
assign SYNTHESIZED_WIRE_64 = reg_sel_ix & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; |
|
assign SYNTHESIZED_WIRE_35 = reg_sel_gp_lo & reg_gp_we & reg_sel_af; |
|
assign SYNTHESIZED_WIRE_69 = reg_sel_iy & reg_gp_we & reg_sel_gp_hi; |
|
assign SYNTHESIZED_WIRE_63 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_ir; |
|
assign SYNTHESIZED_WIRE_65 = reg_sel_ix & reg_gp_we & reg_sel_gp_hi; |
|
assign SYNTHESIZED_WIRE_53 = reg_sel_hl2 & reg_gp_we & reg_sel_gp_hi; |
|
assign SYNTHESIZED_WIRE_54 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_hl2; |
|
assign SYNTHESIZED_WIRE_52 = reg_sel_hl2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; |
|
assign SYNTHESIZED_WIRE_57 = reg_sel_hl & reg_gp_we & reg_sel_gp_hi; |
|
assign SYNTHESIZED_WIRE_45 = reg_sel_de2 & reg_gp_we & reg_sel_gp_hi; |
|
assign SYNTHESIZED_WIRE_49 = reg_sel_de & reg_gp_we & reg_sel_gp_hi; |
|
assign SYNTHESIZED_WIRE_37 = reg_sel_bc2 & reg_gp_we & reg_sel_gp_hi; |
|
assign SYNTHESIZED_WIRE_58 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_hl; |
|
assign SYNTHESIZED_WIRE_56 = reg_sel_hl & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; |
|
assign SYNTHESIZED_WIRE_75 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_pc; |
|
assign SYNTHESIZED_WIRE_41 = reg_sel_bc & reg_gp_we & reg_sel_gp_hi; |
|
assign SYNTHESIZED_WIRE_29 = reg_sel_af2 & reg_gp_we & reg_sel_gp_hi; |
|
assign SYNTHESIZED_WIRE_33 = reg_sel_af & reg_gp_we & reg_sel_gp_hi; |
|
assign SYNTHESIZED_WIRE_61 = reg_sel_ir & reg_sys_we_hi & reg_sel_sys_hi; |
|
assign SYNTHESIZED_WIRE_46 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_de2; |
|
assign SYNTHESIZED_WIRE_44 = reg_sel_de2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; |
|
assign SYNTHESIZED_WIRE_73 = reg_sel_pc & reg_sys_we_hi & reg_sel_sys_hi; |
|
assign SYNTHESIZED_WIRE_83 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_wz; |
|
assign SYNTHESIZED_WIRE_50 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_de; |
|
assign SYNTHESIZED_WIRE_48 = reg_sel_de & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; |
|
assign SYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_bc2; |
|
assign SYNTHESIZED_WIRE_36 = reg_sel_bc2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; |
|
assign SYNTHESIZED_WIRE_42 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_bc; |
|
assign SYNTHESIZED_WIRE_40 = reg_sel_bc & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; |
|
assign SYNTHESIZED_WIRE_30 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_af2; |
|
assign SYNTHESIZED_WIRE_28 = reg_sel_af2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; |
|
assign SYNTHESIZED_WIRE_62 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_ir; |
|
assign SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_af; |
|
assign SYNTHESIZED_WIRE_32 = reg_sel_af & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; |
|
assign SYNTHESIZED_WIRE_60 = reg_sel_ir & reg_sel_sys_hi & SYNTHESIZED_WIRE_85; |
|
assign SYNTHESIZED_WIRE_79 = reg_sel_gp_lo & reg_gp_we & reg_sel_sp; |
|
|
reg_latch b2v_latch_af2_hi( |
.oe(SYNTHESIZED_WIRE_28), |
.we(SYNTHESIZED_WIRE_29), |
.clk(clk), |
.db(gdfx_temp1) |
); |
|
|
reg_latch b2v_latch_af2_lo( |
.oe(SYNTHESIZED_WIRE_30), |
.we(SYNTHESIZED_WIRE_31), |
.clk(clk), |
.db(gdfx_temp0) |
); |
|
|
reg_latch b2v_latch_af_hi( |
.oe(SYNTHESIZED_WIRE_32), |
.we(SYNTHESIZED_WIRE_33), |
.clk(clk), |
.db(gdfx_temp1) |
); |
|
|
reg_latch b2v_latch_af_lo( |
.oe(SYNTHESIZED_WIRE_34), |
.we(SYNTHESIZED_WIRE_35), |
.clk(clk), |
.db(gdfx_temp0) |
); |
|
|
reg_latch b2v_latch_bc2_hi( |
.oe(SYNTHESIZED_WIRE_36), |
.we(SYNTHESIZED_WIRE_37), |
.clk(clk), |
.db(gdfx_temp1) |
); |
|
|
reg_latch b2v_latch_bc2_lo( |
.oe(SYNTHESIZED_WIRE_38), |
.we(SYNTHESIZED_WIRE_39), |
.clk(clk), |
.db(gdfx_temp0) |
); |
|
|
reg_latch b2v_latch_bc_hi( |
.oe(SYNTHESIZED_WIRE_40), |
.we(SYNTHESIZED_WIRE_41), |
.clk(clk), |
.db(gdfx_temp1) |
); |
|
|
reg_latch b2v_latch_bc_lo( |
.oe(SYNTHESIZED_WIRE_42), |
.we(SYNTHESIZED_WIRE_43), |
.clk(clk), |
.db(gdfx_temp0) |
); |
|
|
reg_latch b2v_latch_de2_hi( |
.oe(SYNTHESIZED_WIRE_44), |
.we(SYNTHESIZED_WIRE_45), |
.clk(clk), |
.db(gdfx_temp1) |
); |
|
|
reg_latch b2v_latch_de2_lo( |
.oe(SYNTHESIZED_WIRE_46), |
.we(SYNTHESIZED_WIRE_47), |
.clk(clk), |
.db(gdfx_temp0) |
); |
|
|
reg_latch b2v_latch_de_hi( |
.oe(SYNTHESIZED_WIRE_48), |
.we(SYNTHESIZED_WIRE_49), |
.clk(clk), |
.db(gdfx_temp1) |
); |
|
|
reg_latch b2v_latch_de_lo( |
.oe(SYNTHESIZED_WIRE_50), |
.we(SYNTHESIZED_WIRE_51), |
.clk(clk), |
.db(gdfx_temp0) |
); |
|
|
reg_latch b2v_latch_hl2_hi( |
.oe(SYNTHESIZED_WIRE_52), |
.we(SYNTHESIZED_WIRE_53), |
.clk(clk), |
.db(gdfx_temp1) |
); |
|
|
reg_latch b2v_latch_hl2_lo( |
.oe(SYNTHESIZED_WIRE_54), |
.we(SYNTHESIZED_WIRE_55), |
.clk(clk), |
.db(gdfx_temp0) |
); |
|
|
reg_latch b2v_latch_hl_hi( |
.oe(SYNTHESIZED_WIRE_56), |
.we(SYNTHESIZED_WIRE_57), |
.clk(clk), |
.db(gdfx_temp1) |
); |
|
|
reg_latch b2v_latch_hl_lo( |
.oe(SYNTHESIZED_WIRE_58), |
.we(SYNTHESIZED_WIRE_59), |
.clk(clk), |
.db(gdfx_temp0) |
); |
|
|
reg_latch b2v_latch_ir_hi( |
.oe(SYNTHESIZED_WIRE_60), |
.we(SYNTHESIZED_WIRE_61), |
.clk(clk), |
.db(db_hi_as) |
); |
|
|
reg_latch b2v_latch_ir_lo( |
.oe(SYNTHESIZED_WIRE_62), |
.we(SYNTHESIZED_WIRE_63), |
.clk(clk), |
.db(db_lo_as) |
); |
|
|
reg_latch b2v_latch_ix_hi( |
.oe(SYNTHESIZED_WIRE_64), |
.we(SYNTHESIZED_WIRE_65), |
.clk(clk), |
.db(gdfx_temp1) |
); |
|
|
reg_latch b2v_latch_ix_lo( |
.oe(SYNTHESIZED_WIRE_66), |
.we(SYNTHESIZED_WIRE_67), |
.clk(clk), |
.db(gdfx_temp0) |
); |
|
|
reg_latch b2v_latch_iy_hi( |
.oe(SYNTHESIZED_WIRE_68), |
.we(SYNTHESIZED_WIRE_69), |
.clk(clk), |
.db(gdfx_temp1) |
); |
|
|
reg_latch b2v_latch_iy_lo( |
.oe(SYNTHESIZED_WIRE_70), |
.we(SYNTHESIZED_WIRE_71), |
.clk(clk), |
.db(gdfx_temp0) |
); |
|
|
reg_latch b2v_latch_pc_hi( |
.oe(SYNTHESIZED_WIRE_72), |
.we(SYNTHESIZED_WIRE_73), |
.clk(clk), |
.db(db_hi_as) |
); |
|
|
reg_latch b2v_latch_pc_lo( |
.oe(SYNTHESIZED_WIRE_74), |
.we(SYNTHESIZED_WIRE_75), |
.clk(clk), |
.db(db_lo_as) |
); |
|
|
reg_latch b2v_latch_sp_hi( |
.oe(SYNTHESIZED_WIRE_76), |
.we(SYNTHESIZED_WIRE_77), |
.clk(clk), |
.db(gdfx_temp1) |
); |
|
|
reg_latch b2v_latch_sp_lo( |
.oe(SYNTHESIZED_WIRE_78), |
.we(SYNTHESIZED_WIRE_79), |
.clk(clk), |
.db(gdfx_temp0) |
); |
|
|
reg_latch b2v_latch_wz_hi( |
.oe(SYNTHESIZED_WIRE_80), |
.we(SYNTHESIZED_WIRE_81), |
.clk(clk), |
.db(gdfx_temp1) |
); |
|
|
reg_latch b2v_latch_wz_lo( |
.oe(SYNTHESIZED_WIRE_82), |
.we(SYNTHESIZED_WIRE_83), |
.clk(clk), |
.db(gdfx_temp0) |
); |
|
assign gdfx_temp0[7] = ctl_sw_4u ? db_lo_as[7] : 1'bz; |
assign gdfx_temp0[6] = ctl_sw_4u ? db_lo_as[6] : 1'bz; |
assign gdfx_temp0[5] = ctl_sw_4u ? db_lo_as[5] : 1'bz; |
assign gdfx_temp0[4] = ctl_sw_4u ? db_lo_as[4] : 1'bz; |
assign gdfx_temp0[3] = ctl_sw_4u ? db_lo_as[3] : 1'bz; |
assign gdfx_temp0[2] = ctl_sw_4u ? db_lo_as[2] : 1'bz; |
assign gdfx_temp0[1] = ctl_sw_4u ? db_lo_as[1] : 1'bz; |
assign gdfx_temp0[0] = ctl_sw_4u ? db_lo_as[0] : 1'bz; |
|
assign db_lo_as[7] = ctl_sw_4d ? gdfx_temp0[7] : 1'bz; |
assign db_lo_as[6] = ctl_sw_4d ? gdfx_temp0[6] : 1'bz; |
assign db_lo_as[5] = ctl_sw_4d ? gdfx_temp0[5] : 1'bz; |
assign db_lo_as[4] = ctl_sw_4d ? gdfx_temp0[4] : 1'bz; |
assign db_lo_as[3] = ctl_sw_4d ? gdfx_temp0[3] : 1'bz; |
assign db_lo_as[2] = ctl_sw_4d ? gdfx_temp0[2] : 1'bz; |
assign db_lo_as[1] = ctl_sw_4d ? gdfx_temp0[1] : 1'bz; |
assign db_lo_as[0] = ctl_sw_4d ? gdfx_temp0[0] : 1'bz; |
|
assign gdfx_temp1[7] = ctl_sw_4u ? db_hi_as[7] : 1'bz; |
assign gdfx_temp1[6] = ctl_sw_4u ? db_hi_as[6] : 1'bz; |
assign gdfx_temp1[5] = ctl_sw_4u ? db_hi_as[5] : 1'bz; |
assign gdfx_temp1[4] = ctl_sw_4u ? db_hi_as[4] : 1'bz; |
assign gdfx_temp1[3] = ctl_sw_4u ? db_hi_as[3] : 1'bz; |
assign gdfx_temp1[2] = ctl_sw_4u ? db_hi_as[2] : 1'bz; |
assign gdfx_temp1[1] = ctl_sw_4u ? db_hi_as[1] : 1'bz; |
assign gdfx_temp1[0] = ctl_sw_4u ? db_hi_as[0] : 1'bz; |
|
assign db_hi_as[7] = ctl_sw_4d ? gdfx_temp1[7] : 1'bz; |
assign db_hi_as[6] = ctl_sw_4d ? gdfx_temp1[6] : 1'bz; |
assign db_hi_as[5] = ctl_sw_4d ? gdfx_temp1[5] : 1'bz; |
assign db_hi_as[4] = ctl_sw_4d ? gdfx_temp1[4] : 1'bz; |
assign db_hi_as[3] = ctl_sw_4d ? gdfx_temp1[3] : 1'bz; |
assign db_hi_as[2] = ctl_sw_4d ? gdfx_temp1[2] : 1'bz; |
assign db_hi_as[1] = ctl_sw_4d ? gdfx_temp1[1] : 1'bz; |
assign db_hi_as[0] = ctl_sw_4d ? gdfx_temp1[0] : 1'bz; |
|
assign db_lo_ds[7] = ctl_reg_out_lo ? gdfx_temp0[7] : 1'bz; |
assign db_lo_ds[6] = ctl_reg_out_lo ? gdfx_temp0[6] : 1'bz; |
assign db_lo_ds[5] = ctl_reg_out_lo ? gdfx_temp0[5] : 1'bz; |
assign db_lo_ds[4] = ctl_reg_out_lo ? gdfx_temp0[4] : 1'bz; |
assign db_lo_ds[3] = ctl_reg_out_lo ? gdfx_temp0[3] : 1'bz; |
assign db_lo_ds[2] = ctl_reg_out_lo ? gdfx_temp0[2] : 1'bz; |
assign db_lo_ds[1] = ctl_reg_out_lo ? gdfx_temp0[1] : 1'bz; |
assign db_lo_ds[0] = ctl_reg_out_lo ? gdfx_temp0[0] : 1'bz; |
|
assign gdfx_temp0[7] = ctl_reg_in_lo ? db_lo_ds[7] : 1'bz; |
assign gdfx_temp0[6] = ctl_reg_in_lo ? db_lo_ds[6] : 1'bz; |
assign gdfx_temp0[5] = ctl_reg_in_lo ? db_lo_ds[5] : 1'bz; |
assign gdfx_temp0[4] = ctl_reg_in_lo ? db_lo_ds[4] : 1'bz; |
assign gdfx_temp0[3] = ctl_reg_in_lo ? db_lo_ds[3] : 1'bz; |
assign gdfx_temp0[2] = ctl_reg_in_lo ? db_lo_ds[2] : 1'bz; |
assign gdfx_temp0[1] = ctl_reg_in_lo ? db_lo_ds[1] : 1'bz; |
assign gdfx_temp0[0] = ctl_reg_in_lo ? db_lo_ds[0] : 1'bz; |
|
assign db_hi_ds[7] = ctl_reg_out_hi ? gdfx_temp1[7] : 1'bz; |
assign db_hi_ds[6] = ctl_reg_out_hi ? gdfx_temp1[6] : 1'bz; |
assign db_hi_ds[5] = ctl_reg_out_hi ? gdfx_temp1[5] : 1'bz; |
assign db_hi_ds[4] = ctl_reg_out_hi ? gdfx_temp1[4] : 1'bz; |
assign db_hi_ds[3] = ctl_reg_out_hi ? gdfx_temp1[3] : 1'bz; |
assign db_hi_ds[2] = ctl_reg_out_hi ? gdfx_temp1[2] : 1'bz; |
assign db_hi_ds[1] = ctl_reg_out_hi ? gdfx_temp1[1] : 1'bz; |
assign db_hi_ds[0] = ctl_reg_out_hi ? gdfx_temp1[0] : 1'bz; |
|
assign gdfx_temp1[7] = ctl_reg_in_hi ? db_hi_ds[7] : 1'bz; |
assign gdfx_temp1[6] = ctl_reg_in_hi ? db_hi_ds[6] : 1'bz; |
assign gdfx_temp1[5] = ctl_reg_in_hi ? db_hi_ds[5] : 1'bz; |
assign gdfx_temp1[4] = ctl_reg_in_hi ? db_hi_ds[4] : 1'bz; |
assign gdfx_temp1[3] = ctl_reg_in_hi ? db_hi_ds[3] : 1'bz; |
assign gdfx_temp1[2] = ctl_reg_in_hi ? db_hi_ds[2] : 1'bz; |
assign gdfx_temp1[1] = ctl_reg_in_hi ? db_hi_ds[1] : 1'bz; |
assign gdfx_temp1[0] = ctl_reg_in_hi ? db_hi_ds[0] : 1'bz; |
|
|
endmodule |
/trunk/cpu/deploy/reg_control.v
0,0 → 1,291
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Fri Oct 31 20:41:01 2014" |
|
module reg_control( |
ctl_reg_exx, |
ctl_reg_ex_af, |
ctl_reg_ex_de_hl, |
ctl_reg_use_sp, |
nreset, |
ctl_reg_sel_pc, |
ctl_reg_sel_ir, |
ctl_reg_sel_wz, |
ctl_reg_gp_we, |
ctl_reg_not_pc, |
use_ixiy, |
use_ix, |
ctl_reg_sys_we_lo, |
ctl_reg_sys_we_hi, |
ctl_reg_sys_we, |
clk, |
ctl_reg_gp_hilo, |
ctl_reg_gp_sel, |
ctl_reg_sys_hilo, |
reg_sel_bc, |
reg_sel_bc2, |
reg_sel_ix, |
reg_sel_iy, |
reg_sel_de, |
reg_sel_hl, |
reg_sel_de2, |
reg_sel_hl2, |
reg_sel_af, |
reg_sel_af2, |
reg_sel_wz, |
reg_sel_pc, |
reg_sel_ir, |
reg_sel_sp, |
reg_sel_gp_hi, |
reg_sel_gp_lo, |
reg_sel_sys_lo, |
reg_sel_sys_hi, |
reg_gp_we, |
reg_sys_we_lo, |
reg_sys_we_hi |
); |
|
|
input wire ctl_reg_exx; |
input wire ctl_reg_ex_af; |
input wire ctl_reg_ex_de_hl; |
input wire ctl_reg_use_sp; |
input wire nreset; |
input wire ctl_reg_sel_pc; |
input wire ctl_reg_sel_ir; |
input wire ctl_reg_sel_wz; |
input wire ctl_reg_gp_we; |
input wire ctl_reg_not_pc; |
input wire use_ixiy; |
input wire use_ix; |
input wire ctl_reg_sys_we_lo; |
input wire ctl_reg_sys_we_hi; |
input wire ctl_reg_sys_we; |
input wire clk; |
input wire [1:0] ctl_reg_gp_hilo; |
input wire [1:0] ctl_reg_gp_sel; |
input wire [1:0] ctl_reg_sys_hilo; |
output wire reg_sel_bc; |
output wire reg_sel_bc2; |
output wire reg_sel_ix; |
output wire reg_sel_iy; |
output wire reg_sel_de; |
output wire reg_sel_hl; |
output wire reg_sel_de2; |
output wire reg_sel_hl2; |
output wire reg_sel_af; |
output wire reg_sel_af2; |
output wire reg_sel_wz; |
output wire reg_sel_pc; |
output wire reg_sel_ir; |
output wire reg_sel_sp; |
output wire reg_sel_gp_hi; |
output wire reg_sel_gp_lo; |
output wire reg_sel_sys_lo; |
output wire reg_sel_sys_hi; |
output wire reg_gp_we; |
output wire reg_sys_we_lo; |
output wire reg_sys_we_hi; |
|
reg bank_af; |
reg bank_exx; |
reg bank_hl_de1; |
reg bank_hl_de2; |
wire SYNTHESIZED_WIRE_49; |
wire SYNTHESIZED_WIRE_50; |
wire SYNTHESIZED_WIRE_2; |
wire SYNTHESIZED_WIRE_51; |
wire SYNTHESIZED_WIRE_52; |
wire SYNTHESIZED_WIRE_5; |
wire SYNTHESIZED_WIRE_53; |
wire SYNTHESIZED_WIRE_10; |
wire SYNTHESIZED_WIRE_54; |
wire SYNTHESIZED_WIRE_55; |
wire SYNTHESIZED_WIRE_56; |
wire SYNTHESIZED_WIRE_57; |
wire SYNTHESIZED_WIRE_21; |
wire SYNTHESIZED_WIRE_23; |
wire SYNTHESIZED_WIRE_24; |
wire SYNTHESIZED_WIRE_25; |
wire SYNTHESIZED_WIRE_30; |
wire SYNTHESIZED_WIRE_31; |
wire SYNTHESIZED_WIRE_32; |
wire SYNTHESIZED_WIRE_58; |
wire SYNTHESIZED_WIRE_34; |
wire SYNTHESIZED_WIRE_36; |
wire SYNTHESIZED_WIRE_37; |
wire SYNTHESIZED_WIRE_38; |
wire SYNTHESIZED_WIRE_39; |
wire SYNTHESIZED_WIRE_40; |
wire SYNTHESIZED_WIRE_41; |
wire SYNTHESIZED_WIRE_42; |
wire SYNTHESIZED_WIRE_43; |
wire SYNTHESIZED_WIRE_44; |
wire SYNTHESIZED_WIRE_45; |
wire SYNTHESIZED_WIRE_46; |
wire SYNTHESIZED_WIRE_47; |
|
assign reg_sel_wz = ctl_reg_sel_wz; |
assign reg_sel_ir = ctl_reg_sel_ir; |
assign reg_sel_gp_hi = ctl_reg_gp_hilo[1]; |
assign reg_sel_gp_lo = ctl_reg_gp_hilo[0]; |
assign reg_sel_sys_lo = ctl_reg_sys_hilo[0]; |
assign reg_sel_sys_hi = ctl_reg_sys_hilo[1]; |
assign reg_gp_we = ctl_reg_gp_we; |
|
|
|
assign reg_sel_bc = SYNTHESIZED_WIRE_49 & SYNTHESIZED_WIRE_50; |
|
assign reg_sel_af = SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_51; |
|
assign SYNTHESIZED_WIRE_51 = SYNTHESIZED_WIRE_52 & SYNTHESIZED_WIRE_5; |
|
assign reg_sel_sp = SYNTHESIZED_WIRE_52 & ctl_reg_use_sp; |
|
assign SYNTHESIZED_WIRE_5 = ~ctl_reg_use_sp; |
|
assign reg_sel_ix = SYNTHESIZED_WIRE_53 & use_ix; |
|
assign SYNTHESIZED_WIRE_37 = ctl_reg_ex_de_hl & SYNTHESIZED_WIRE_50; |
|
assign reg_sel_iy = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_10; |
|
assign reg_sel_af2 = bank_af & SYNTHESIZED_WIRE_51; |
|
assign SYNTHESIZED_WIRE_2 = ~bank_af; |
|
assign SYNTHESIZED_WIRE_45 = SYNTHESIZED_WIRE_54 & SYNTHESIZED_WIRE_55; |
|
assign SYNTHESIZED_WIRE_44 = bank_hl_de2 & SYNTHESIZED_WIRE_56; |
|
assign SYNTHESIZED_WIRE_40 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_55; |
|
assign SYNTHESIZED_WIRE_47 = bank_hl_de2 & SYNTHESIZED_WIRE_55; |
|
assign SYNTHESIZED_WIRE_46 = SYNTHESIZED_WIRE_54 & SYNTHESIZED_WIRE_56; |
|
assign reg_sel_de = SYNTHESIZED_WIRE_50 & SYNTHESIZED_WIRE_21; |
|
assign reg_sel_hl = SYNTHESIZED_WIRE_50 & SYNTHESIZED_WIRE_23; |
|
assign reg_sel_de2 = bank_exx & SYNTHESIZED_WIRE_24; |
|
assign reg_sel_hl2 = bank_exx & SYNTHESIZED_WIRE_25; |
|
assign SYNTHESIZED_WIRE_39 = bank_hl_de1 & SYNTHESIZED_WIRE_56; |
|
assign SYNTHESIZED_WIRE_50 = ~bank_exx; |
|
assign SYNTHESIZED_WIRE_43 = bank_hl_de1 & SYNTHESIZED_WIRE_55; |
|
assign SYNTHESIZED_WIRE_42 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_56; |
|
assign SYNTHESIZED_WIRE_49 = SYNTHESIZED_WIRE_30 & SYNTHESIZED_WIRE_31; |
|
assign SYNTHESIZED_WIRE_57 = ~bank_hl_de1; |
|
assign reg_sys_we_hi = ctl_reg_sys_we | ctl_reg_sys_we_hi; |
|
assign reg_sel_pc = ctl_reg_sel_pc & SYNTHESIZED_WIRE_32; |
|
assign SYNTHESIZED_WIRE_55 = SYNTHESIZED_WIRE_58 & SYNTHESIZED_WIRE_34; |
|
assign SYNTHESIZED_WIRE_32 = ~ctl_reg_not_pc; |
|
assign SYNTHESIZED_WIRE_36 = ~ctl_reg_gp_sel[1]; |
|
assign reg_sys_we_lo = ctl_reg_sys_we_lo | ctl_reg_sys_we; |
|
assign SYNTHESIZED_WIRE_53 = SYNTHESIZED_WIRE_58 & use_ixiy; |
|
assign SYNTHESIZED_WIRE_41 = ~ctl_reg_gp_sel[0]; |
|
assign SYNTHESIZED_WIRE_38 = ctl_reg_ex_de_hl & bank_exx; |
|
assign SYNTHESIZED_WIRE_34 = ~use_ixiy; |
|
assign SYNTHESIZED_WIRE_56 = ctl_reg_gp_sel[0] & SYNTHESIZED_WIRE_36; |
|
assign SYNTHESIZED_WIRE_10 = ~use_ix; |
|
assign SYNTHESIZED_WIRE_54 = ~bank_hl_de2; |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
bank_hl_de1 <= 0; |
end |
else |
bank_hl_de1 <= bank_hl_de1 ^ SYNTHESIZED_WIRE_37; |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
bank_hl_de2 <= 0; |
end |
else |
bank_hl_de2 <= bank_hl_de2 ^ SYNTHESIZED_WIRE_38; |
end |
|
assign SYNTHESIZED_WIRE_23 = SYNTHESIZED_WIRE_39 | SYNTHESIZED_WIRE_40; |
|
assign SYNTHESIZED_WIRE_58 = SYNTHESIZED_WIRE_41 & ctl_reg_gp_sel[1]; |
|
assign SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_42 | SYNTHESIZED_WIRE_43; |
|
assign SYNTHESIZED_WIRE_25 = SYNTHESIZED_WIRE_44 | SYNTHESIZED_WIRE_45; |
|
assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_46 | SYNTHESIZED_WIRE_47; |
|
assign SYNTHESIZED_WIRE_52 = ctl_reg_gp_sel[0] & ctl_reg_gp_sel[1]; |
|
assign SYNTHESIZED_WIRE_30 = ~ctl_reg_gp_sel[0]; |
|
assign SYNTHESIZED_WIRE_31 = ~ctl_reg_gp_sel[1]; |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
bank_exx <= 0; |
end |
else |
bank_exx <= bank_exx ^ ctl_reg_exx; |
end |
|
assign reg_sel_bc2 = SYNTHESIZED_WIRE_49 & bank_exx; |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
bank_af <= 0; |
end |
else |
bank_af <= bank_af ^ ctl_reg_ex_af; |
end |
|
|
endmodule |
/trunk/cpu/deploy/address_pins.v
0,0 → 1,69
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Sun Nov 16 16:56:05 2014" |
|
module address_pins( |
clk, |
bus_ab_pin_we, |
pin_control_oe, |
address, |
abus |
); |
|
|
input wire clk; |
input wire bus_ab_pin_we; |
input wire pin_control_oe; |
input wire [15:0] address; |
output wire [15:0] abus; |
|
wire SYNTHESIZED_WIRE_0; |
reg [15:0] DFFE_apin_latch; |
|
|
|
|
|
always@(posedge SYNTHESIZED_WIRE_0) |
begin |
if (bus_ab_pin_we) |
begin |
DFFE_apin_latch[15:0] <= address[15:0]; |
end |
end |
|
assign abus[15] = pin_control_oe ? DFFE_apin_latch[15] : 1'bz; |
assign abus[14] = pin_control_oe ? DFFE_apin_latch[14] : 1'bz; |
assign abus[13] = pin_control_oe ? DFFE_apin_latch[13] : 1'bz; |
assign abus[12] = pin_control_oe ? DFFE_apin_latch[12] : 1'bz; |
assign abus[11] = pin_control_oe ? DFFE_apin_latch[11] : 1'bz; |
assign abus[10] = pin_control_oe ? DFFE_apin_latch[10] : 1'bz; |
assign abus[9] = pin_control_oe ? DFFE_apin_latch[9] : 1'bz; |
assign abus[8] = pin_control_oe ? DFFE_apin_latch[8] : 1'bz; |
assign abus[7] = pin_control_oe ? DFFE_apin_latch[7] : 1'bz; |
assign abus[6] = pin_control_oe ? DFFE_apin_latch[6] : 1'bz; |
assign abus[5] = pin_control_oe ? DFFE_apin_latch[5] : 1'bz; |
assign abus[4] = pin_control_oe ? DFFE_apin_latch[4] : 1'bz; |
assign abus[3] = pin_control_oe ? DFFE_apin_latch[3] : 1'bz; |
assign abus[2] = pin_control_oe ? DFFE_apin_latch[2] : 1'bz; |
assign abus[1] = pin_control_oe ? DFFE_apin_latch[1] : 1'bz; |
assign abus[0] = pin_control_oe ? DFFE_apin_latch[0] : 1'bz; |
|
assign SYNTHESIZED_WIRE_0 = ~clk; |
|
|
endmodule |
/trunk/cpu/deploy/interrupts.v
0,0 → 1,249
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Sun Nov 09 09:11:22 2014" |
|
module interrupts( |
ctl_iff1_iff2, |
nmi, |
setM1, |
intr, |
ctl_iffx_we, |
ctl_iffx_bit, |
ctl_im_we, |
clk, |
ctl_no_ints, |
nreset, |
db, |
iff1, |
iff2, |
im1, |
im2, |
in_nmi, |
in_intr |
); |
|
|
input wire ctl_iff1_iff2; |
input wire nmi; |
input wire setM1; |
input wire intr; |
input wire ctl_iffx_we; |
input wire ctl_iffx_bit; |
input wire ctl_im_we; |
input wire clk; |
input wire ctl_no_ints; |
input wire nreset; |
input wire [1:0] db; |
output wire iff1; |
output wire iff2; |
output reg im1; |
output reg im2; |
output wire in_nmi; |
output wire in_intr; |
|
reg iff_ALTERA_SYNTHESIZED1; |
wire in_intr_ALTERA_SYNTHESIZED; |
reg in_nmi_ALTERA_SYNTHESIZED; |
reg int_armed; |
reg nmi_armed; |
wire test1; |
wire SYNTHESIZED_WIRE_0; |
reg DFFE_instIFF2; |
wire SYNTHESIZED_WIRE_1; |
wire SYNTHESIZED_WIRE_2; |
wire SYNTHESIZED_WIRE_3; |
wire SYNTHESIZED_WIRE_4; |
wire SYNTHESIZED_WIRE_5; |
reg DFFE_inst44; |
wire SYNTHESIZED_WIRE_21; |
wire SYNTHESIZED_WIRE_7; |
wire SYNTHESIZED_WIRE_8; |
wire SYNTHESIZED_WIRE_9; |
wire SYNTHESIZED_WIRE_10; |
wire SYNTHESIZED_WIRE_11; |
wire SYNTHESIZED_WIRE_12; |
wire SYNTHESIZED_WIRE_13; |
wire SYNTHESIZED_WIRE_14; |
wire SYNTHESIZED_WIRE_15; |
wire SYNTHESIZED_WIRE_16; |
wire SYNTHESIZED_WIRE_17; |
wire SYNTHESIZED_WIRE_19; |
wire SYNTHESIZED_WIRE_20; |
|
assign iff2 = DFFE_instIFF2; |
assign SYNTHESIZED_WIRE_10 = 1; |
|
|
|
assign SYNTHESIZED_WIRE_2 = ctl_iffx_bit & SYNTHESIZED_WIRE_0; |
|
assign SYNTHESIZED_WIRE_1 = ctl_iff1_iff2 & DFFE_instIFF2; |
|
assign SYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2; |
|
assign SYNTHESIZED_WIRE_17 = ctl_iffx_we | ctl_iff1_iff2; |
|
assign SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_3 & nreset; |
|
assign SYNTHESIZED_WIRE_0 = ~ctl_iff1_iff2; |
|
assign SYNTHESIZED_WIRE_4 = ~db[0]; |
|
assign SYNTHESIZED_WIRE_5 = ~in_nmi_ALTERA_SYNTHESIZED; |
|
assign SYNTHESIZED_WIRE_20 = db[1] & db[0]; |
|
assign SYNTHESIZED_WIRE_19 = db[1] & SYNTHESIZED_WIRE_4; |
|
|
assign in_intr_ALTERA_SYNTHESIZED = SYNTHESIZED_WIRE_5 & DFFE_inst44; |
|
assign SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_7; |
|
assign SYNTHESIZED_WIRE_13 = iff_ALTERA_SYNTHESIZED1 & intr; |
|
assign test1 = setM1 & SYNTHESIZED_WIRE_8; |
|
|
always@(posedge nmi or negedge SYNTHESIZED_WIRE_9) |
begin |
if (!SYNTHESIZED_WIRE_9) |
begin |
nmi_armed <= 0; |
end |
else |
begin |
nmi_armed <= SYNTHESIZED_WIRE_10; |
end |
end |
|
assign SYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_11 & nreset; |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
in_nmi_ALTERA_SYNTHESIZED <= 0; |
end |
else |
if (test1) |
begin |
in_nmi_ALTERA_SYNTHESIZED <= nmi_armed; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_inst44 <= 0; |
end |
else |
if (test1) |
begin |
DFFE_inst44 <= int_armed; |
end |
end |
|
|
always@(posedge clk or negedge SYNTHESIZED_WIRE_12) |
begin |
if (!SYNTHESIZED_WIRE_12) |
begin |
int_armed <= 0; |
end |
else |
begin |
int_armed <= SYNTHESIZED_WIRE_13; |
end |
end |
|
assign SYNTHESIZED_WIRE_9 = SYNTHESIZED_WIRE_14 & nreset; |
|
assign SYNTHESIZED_WIRE_8 = ~ctl_no_ints; |
|
|
always@(posedge clk or negedge SYNTHESIZED_WIRE_15) |
begin |
if (!SYNTHESIZED_WIRE_15) |
begin |
iff_ALTERA_SYNTHESIZED1 <= 0; |
end |
else |
if (SYNTHESIZED_WIRE_17) |
begin |
iff_ALTERA_SYNTHESIZED1 <= SYNTHESIZED_WIRE_16; |
end |
end |
|
|
always@(posedge clk or negedge SYNTHESIZED_WIRE_21) |
begin |
if (!SYNTHESIZED_WIRE_21) |
begin |
DFFE_instIFF2 <= 0; |
end |
else |
if (ctl_iffx_we) |
begin |
DFFE_instIFF2 <= ctl_iffx_bit; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
im1 <= 0; |
end |
else |
if (ctl_im_we) |
begin |
im1 <= SYNTHESIZED_WIRE_19; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
im2 <= 0; |
end |
else |
if (ctl_im_we) |
begin |
im2 <= SYNTHESIZED_WIRE_20; |
end |
end |
|
assign SYNTHESIZED_WIRE_3 = ~in_intr_ALTERA_SYNTHESIZED; |
|
assign SYNTHESIZED_WIRE_11 = ~in_intr_ALTERA_SYNTHESIZED; |
|
assign SYNTHESIZED_WIRE_7 = ~in_nmi_ALTERA_SYNTHESIZED; |
|
assign SYNTHESIZED_WIRE_14 = ~in_nmi_ALTERA_SYNTHESIZED; |
|
assign iff1 = iff_ALTERA_SYNTHESIZED1; |
assign in_nmi = in_nmi_ALTERA_SYNTHESIZED; |
assign in_intr = in_intr_ALTERA_SYNTHESIZED; |
|
endmodule |
/trunk/cpu/deploy/alu_select.v
0,0 → 1,114
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Mon Oct 13 11:59:39 2014" |
|
module alu_select( |
ctl_alu_oe, |
ctl_alu_shift_oe, |
ctl_alu_op2_oe, |
ctl_alu_res_oe, |
ctl_alu_op1_oe, |
ctl_alu_bs_oe, |
ctl_alu_op1_sel_bus, |
ctl_alu_op1_sel_low, |
ctl_alu_op1_sel_zero, |
ctl_alu_op2_sel_zero, |
ctl_alu_op2_sel_bus, |
ctl_alu_op2_sel_lq, |
ctl_alu_sel_op2_neg, |
ctl_alu_sel_op2_high, |
ctl_alu_core_R, |
ctl_alu_core_V, |
ctl_alu_core_S, |
alu_oe, |
alu_shift_oe, |
alu_op2_oe, |
alu_res_oe, |
alu_op1_oe, |
alu_bs_oe, |
alu_op1_sel_bus, |
alu_op1_sel_low, |
alu_op1_sel_zero, |
alu_op2_sel_zero, |
alu_op2_sel_bus, |
alu_op2_sel_lq, |
alu_sel_op2_neg, |
alu_sel_op2_high, |
alu_core_R, |
alu_core_V, |
alu_core_S |
); |
|
|
input wire ctl_alu_oe; |
input wire ctl_alu_shift_oe; |
input wire ctl_alu_op2_oe; |
input wire ctl_alu_res_oe; |
input wire ctl_alu_op1_oe; |
input wire ctl_alu_bs_oe; |
input wire ctl_alu_op1_sel_bus; |
input wire ctl_alu_op1_sel_low; |
input wire ctl_alu_op1_sel_zero; |
input wire ctl_alu_op2_sel_zero; |
input wire ctl_alu_op2_sel_bus; |
input wire ctl_alu_op2_sel_lq; |
input wire ctl_alu_sel_op2_neg; |
input wire ctl_alu_sel_op2_high; |
input wire ctl_alu_core_R; |
input wire ctl_alu_core_V; |
input wire ctl_alu_core_S; |
output wire alu_oe; |
output wire alu_shift_oe; |
output wire alu_op2_oe; |
output wire alu_res_oe; |
output wire alu_op1_oe; |
output wire alu_bs_oe; |
output wire alu_op1_sel_bus; |
output wire alu_op1_sel_low; |
output wire alu_op1_sel_zero; |
output wire alu_op2_sel_zero; |
output wire alu_op2_sel_bus; |
output wire alu_op2_sel_lq; |
output wire alu_sel_op2_neg; |
output wire alu_sel_op2_high; |
output wire alu_core_R; |
output wire alu_core_V; |
output wire alu_core_S; |
|
|
assign alu_oe = ctl_alu_oe; |
assign alu_shift_oe = ctl_alu_shift_oe; |
assign alu_op2_oe = ctl_alu_op2_oe; |
assign alu_res_oe = ctl_alu_res_oe; |
assign alu_op1_oe = ctl_alu_op1_oe; |
assign alu_bs_oe = ctl_alu_bs_oe; |
assign alu_op1_sel_bus = ctl_alu_op1_sel_bus; |
assign alu_op1_sel_low = ctl_alu_op1_sel_low; |
assign alu_op1_sel_zero = ctl_alu_op1_sel_zero; |
assign alu_op2_sel_zero = ctl_alu_op2_sel_zero; |
assign alu_op2_sel_bus = ctl_alu_op2_sel_bus; |
assign alu_op2_sel_lq = ctl_alu_op2_sel_lq; |
assign alu_sel_op2_neg = ctl_alu_sel_op2_neg; |
assign alu_sel_op2_high = ctl_alu_sel_op2_high; |
assign alu_core_R = ctl_alu_core_R; |
assign alu_core_V = ctl_alu_core_V; |
assign alu_core_S = ctl_alu_core_S; |
|
|
|
|
endmodule |
/trunk/cpu/deploy/decode_state.v
0,0 → 1,180
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Fri Oct 31 20:27:41 2014" |
|
module decode_state( |
ctl_state_iy_set, |
ctl_state_ixiy_clr, |
ctl_state_ixiy_we, |
ctl_state_halt_set, |
ctl_state_tbl_clr, |
ctl_state_tbl_ed_set, |
ctl_state_tbl_cb_set, |
ctl_state_alu, |
clk, |
address_is_1, |
ctl_repeat_we, |
in_intr, |
in_nmi, |
nreset, |
in_halt, |
table_cb, |
table_ed, |
table_xx, |
use_ix, |
use_ixiy, |
in_alu, |
repeat_en |
); |
|
|
input wire ctl_state_iy_set; |
input wire ctl_state_ixiy_clr; |
input wire ctl_state_ixiy_we; |
input wire ctl_state_halt_set; |
input wire ctl_state_tbl_clr; |
input wire ctl_state_tbl_ed_set; |
input wire ctl_state_tbl_cb_set; |
input wire ctl_state_alu; |
input wire clk; |
input wire address_is_1; |
input wire ctl_repeat_we; |
input wire in_intr; |
input wire in_nmi; |
input wire nreset; |
output reg in_halt; |
output wire table_cb; |
output wire table_ed; |
output wire table_xx; |
output wire use_ix; |
output wire use_ixiy; |
output wire in_alu; |
output wire repeat_en; |
|
reg DFFE_instNonRep; |
reg DFFE_instIY1; |
reg DFFE_inst4; |
reg DFFE_instED; |
reg DFFE_instCB; |
wire SYNTHESIZED_WIRE_0; |
wire SYNTHESIZED_WIRE_4; |
wire SYNTHESIZED_WIRE_3; |
|
assign in_alu = ctl_state_alu; |
assign table_cb = DFFE_instCB; |
assign table_ed = DFFE_instED; |
assign use_ix = DFFE_inst4; |
|
|
|
assign repeat_en = ~DFFE_instNonRep; |
|
assign SYNTHESIZED_WIRE_4 = ctl_state_tbl_clr | ctl_state_tbl_ed_set | ctl_state_tbl_cb_set; |
|
assign use_ixiy = DFFE_instIY1 | DFFE_inst4; |
|
assign table_xx = ~(DFFE_instED | DFFE_instCB); |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_inst4 <= 0; |
end |
else |
if (ctl_state_ixiy_we) |
begin |
DFFE_inst4 <= SYNTHESIZED_WIRE_0; |
end |
end |
|
assign SYNTHESIZED_WIRE_0 = ~(ctl_state_iy_set | ctl_state_ixiy_clr); |
|
assign SYNTHESIZED_WIRE_3 = in_nmi | in_intr; |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_instCB <= 0; |
end |
else |
if (SYNTHESIZED_WIRE_4) |
begin |
DFFE_instCB <= ctl_state_tbl_cb_set; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_instED <= 0; |
end |
else |
if (SYNTHESIZED_WIRE_4) |
begin |
DFFE_instED <= ctl_state_tbl_ed_set; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
in_halt <= 0; |
end |
else |
begin |
in_halt <= ~in_halt & ctl_state_halt_set | in_halt & ~SYNTHESIZED_WIRE_3; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_instIY1 <= 0; |
end |
else |
if (ctl_state_ixiy_we) |
begin |
DFFE_instIY1 <= ctl_state_iy_set; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_instNonRep <= 0; |
end |
else |
if (ctl_repeat_we) |
begin |
DFFE_instNonRep <= address_is_1; |
end |
end |
|
|
endmodule |
/trunk/cpu/deploy/alu_mux_2z.v
0,0 → 1,49
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Fri Oct 31 21:18:33 2014" |
|
module alu_mux_2z( |
sel_a, |
sel_zero, |
a, |
ena, |
Q |
); |
|
|
input wire sel_a; |
input wire sel_zero; |
input wire [3:0] a; |
output wire ena; |
output wire [3:0] Q; |
|
wire [3:0] SYNTHESIZED_WIRE_0; |
wire SYNTHESIZED_WIRE_1; |
|
|
|
|
assign SYNTHESIZED_WIRE_0 = a & {sel_a,sel_a,sel_a,sel_a}; |
|
assign ena = sel_a | sel_zero; |
|
assign Q = SYNTHESIZED_WIRE_0 & {SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1}; |
|
assign SYNTHESIZED_WIRE_1 = ~sel_zero; |
|
|
endmodule |
/trunk/cpu/deploy/pin_control.v
0,0 → 1,89
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Sun Nov 16 21:18:37 2014" |
|
module pin_control( |
fFetch, |
fMRead, |
fMWrite, |
fIORead, |
fIOWrite, |
T1, |
T2, |
T3, |
T4, |
bus_ab_pin_we, |
bus_db_pin_oe, |
bus_db_pin_re |
); |
|
|
input wire fFetch; |
input wire fMRead; |
input wire fMWrite; |
input wire fIORead; |
input wire fIOWrite; |
input wire T1; |
input wire T2; |
input wire T3; |
input wire T4; |
output wire bus_ab_pin_we; |
output wire bus_db_pin_oe; |
output wire bus_db_pin_re; |
|
wire SYNTHESIZED_WIRE_0; |
wire SYNTHESIZED_WIRE_1; |
wire SYNTHESIZED_WIRE_2; |
wire SYNTHESIZED_WIRE_3; |
wire SYNTHESIZED_WIRE_4; |
wire SYNTHESIZED_WIRE_5; |
wire SYNTHESIZED_WIRE_6; |
wire SYNTHESIZED_WIRE_7; |
wire SYNTHESIZED_WIRE_8; |
wire SYNTHESIZED_WIRE_9; |
|
|
|
|
assign SYNTHESIZED_WIRE_9 = fFetch | fMWrite | fMRead | fIORead | fIOWrite | fIOWrite; |
|
assign SYNTHESIZED_WIRE_7 = T3 | T2; |
|
assign bus_db_pin_oe = SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1; |
|
assign SYNTHESIZED_WIRE_3 = T3 & fIORead; |
|
assign bus_db_pin_re = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4; |
|
assign bus_ab_pin_we = SYNTHESIZED_WIRE_5 | SYNTHESIZED_WIRE_6; |
|
assign SYNTHESIZED_WIRE_8 = T2 | T3 | T4; |
|
assign SYNTHESIZED_WIRE_1 = fMWrite & SYNTHESIZED_WIRE_7; |
|
assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_8 & fIOWrite; |
|
assign SYNTHESIZED_WIRE_4 = T2 & fFetch; |
|
assign SYNTHESIZED_WIRE_2 = T2 & fMRead; |
|
assign SYNTHESIZED_WIRE_6 = T3 & fFetch; |
|
assign SYNTHESIZED_WIRE_5 = T1 & SYNTHESIZED_WIRE_9; |
|
|
endmodule |
/trunk/cpu/deploy/control_pins_n.v
0,0 → 1,112
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Sun Nov 16 23:06:14 2014" |
|
module control_pins_n( |
busack, |
CPUCLK, |
pin_control_oe, |
in_halt, |
pin_nWAIT, |
pin_nBUSRQ, |
pin_nINT, |
pin_nNMI, |
pin_nRESET, |
nM1_out, |
nRFSH_out, |
nRD_out, |
nWR_out, |
nIORQ_out, |
nMREQ_out, |
nmi, |
busrq, |
clk, |
intr, |
mwait, |
reset_in, |
pin_nM1, |
pin_nMREQ, |
pin_nIORQ, |
pin_nRD, |
pin_nWR, |
pin_nRFSH, |
pin_nHALT, |
pin_nBUSACK |
); |
|
|
input wire busack; |
input wire CPUCLK; |
input wire pin_control_oe; |
input wire in_halt; |
input wire pin_nWAIT; |
input wire pin_nBUSRQ; |
input wire pin_nINT; |
input wire pin_nNMI; |
input wire pin_nRESET; |
input wire nM1_out; |
input wire nRFSH_out; |
input wire nRD_out; |
input wire nWR_out; |
input wire nIORQ_out; |
input wire nMREQ_out; |
output wire nmi; |
output wire busrq; |
output wire clk; |
output wire intr; |
output wire mwait; |
output wire reset_in; |
output wire pin_nM1; |
output wire pin_nMREQ; |
output wire pin_nIORQ; |
output wire pin_nRD; |
output wire pin_nWR; |
output wire pin_nRFSH; |
output wire pin_nHALT; |
output wire pin_nBUSACK; |
|
|
assign clk = CPUCLK; |
assign pin_nM1 = nM1_out; |
assign pin_nRFSH = nRFSH_out; |
|
|
|
assign pin_nMREQ = pin_control_oe ? nMREQ_out : 1'bz; |
|
assign pin_nIORQ = pin_control_oe ? nIORQ_out : 1'bz; |
|
assign pin_nRD = pin_control_oe ? nRD_out : 1'bz; |
|
assign pin_nWR = pin_control_oe ? nWR_out : 1'bz; |
|
assign busrq = ~pin_nBUSRQ; |
|
assign pin_nHALT = ~in_halt; |
|
assign mwait = ~pin_nWAIT; |
|
assign pin_nBUSACK = ~busack; |
|
assign intr = ~pin_nINT; |
|
assign nmi = ~pin_nNMI; |
|
assign reset_in = ~pin_nRESET; |
|
|
endmodule |
/trunk/cpu/deploy/reg_latch.v
0,0 → 1,56
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Fri Nov 07 10:28:37 2014" |
|
module reg_latch( |
we, |
oe, |
clk, |
db |
); |
|
|
input wire we; |
input wire oe; |
input wire clk; |
inout wire [7:0] db; |
|
reg [7:0] latch; |
|
|
|
|
assign db[7] = oe ? latch[7] : 1'bz; |
assign db[6] = oe ? latch[6] : 1'bz; |
assign db[5] = oe ? latch[5] : 1'bz; |
assign db[4] = oe ? latch[4] : 1'bz; |
assign db[3] = oe ? latch[3] : 1'bz; |
assign db[2] = oe ? latch[2] : 1'bz; |
assign db[1] = oe ? latch[1] : 1'bz; |
assign db[0] = oe ? latch[0] : 1'bz; |
|
|
always@(posedge clk) |
begin |
if (we) |
begin |
latch[7:0] <= db[7:0]; |
end |
end |
|
|
endmodule |
/trunk/cpu/deploy/alu_core.v
0,0 → 1,100
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Mon Oct 13 12:17:04 2014" |
|
module alu_core( |
cy_in, |
S, |
V, |
R, |
op1, |
op2, |
cy_out, |
vf_out, |
result |
); |
|
|
input wire cy_in; |
input wire S; |
input wire V; |
input wire R; |
input wire [3:0] op1; |
input wire [3:0] op2; |
output wire cy_out; |
output wire vf_out; |
output wire [3:0] result; |
|
wire [3:0] result_ALTERA_SYNTHESIZED; |
wire SYNTHESIZED_WIRE_0; |
wire SYNTHESIZED_WIRE_1; |
wire SYNTHESIZED_WIRE_5; |
wire SYNTHESIZED_WIRE_3; |
|
assign cy_out = SYNTHESIZED_WIRE_3; |
|
|
|
|
alu_slice b2v_alu_slice_bit_0( |
.cy_in(cy_in), |
.op1(op1[0]), |
.op2(op2[0]), |
.S(S), |
.V(V), |
.R(R), |
.result(result_ALTERA_SYNTHESIZED[0]), |
.cy_out(SYNTHESIZED_WIRE_0)); |
|
|
alu_slice b2v_alu_slice_bit_1( |
.cy_in(SYNTHESIZED_WIRE_0), |
.op1(op1[1]), |
.op2(op2[1]), |
.S(S), |
.V(V), |
.R(R), |
.result(result_ALTERA_SYNTHESIZED[1]), |
.cy_out(SYNTHESIZED_WIRE_1)); |
|
|
alu_slice b2v_alu_slice_bit_2( |
.cy_in(SYNTHESIZED_WIRE_1), |
.op1(op1[2]), |
.op2(op2[2]), |
.S(S), |
.V(V), |
.R(R), |
.result(result_ALTERA_SYNTHESIZED[2]), |
.cy_out(SYNTHESIZED_WIRE_5)); |
|
|
alu_slice b2v_alu_slice_bit_3( |
.cy_in(SYNTHESIZED_WIRE_5), |
.op1(op1[3]), |
.op2(op2[3]), |
.S(S), |
.V(V), |
.R(R), |
.result(result_ALTERA_SYNTHESIZED[3]), |
.cy_out(SYNTHESIZED_WIRE_3)); |
|
assign vf_out = SYNTHESIZED_WIRE_3 ^ SYNTHESIZED_WIRE_5; |
|
assign result = result_ALTERA_SYNTHESIZED; |
|
endmodule |
/trunk/cpu/deploy/bus_control.v
0,0 → 1,62
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Mon Oct 13 12:39:04 2014" |
|
module bus_control( |
ctl_bus_ff_oe, |
ctl_bus_zero_oe, |
ctl_bus_db_oe, |
bus_db_oe, |
db |
); |
|
|
input wire ctl_bus_ff_oe; |
input wire ctl_bus_zero_oe; |
input wire ctl_bus_db_oe; |
output wire bus_db_oe; |
inout wire [7:0] db; |
|
wire [7:0] bus; |
wire [7:0] vcc; |
wire SYNTHESIZED_WIRE_3; |
wire SYNTHESIZED_WIRE_2; |
|
|
|
|
assign db[7] = SYNTHESIZED_WIRE_3 ? bus[7] : 1'bz; |
assign db[6] = SYNTHESIZED_WIRE_3 ? bus[6] : 1'bz; |
assign db[5] = SYNTHESIZED_WIRE_3 ? bus[5] : 1'bz; |
assign db[4] = SYNTHESIZED_WIRE_3 ? bus[4] : 1'bz; |
assign db[3] = SYNTHESIZED_WIRE_3 ? bus[3] : 1'bz; |
assign db[2] = SYNTHESIZED_WIRE_3 ? bus[2] : 1'bz; |
assign db[1] = SYNTHESIZED_WIRE_3 ? bus[1] : 1'bz; |
assign db[0] = SYNTHESIZED_WIRE_3 ? bus[0] : 1'bz; |
|
|
assign bus = {ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe} & vcc; |
|
assign SYNTHESIZED_WIRE_2 = ~SYNTHESIZED_WIRE_3; |
|
assign bus_db_oe = ctl_bus_db_oe & SYNTHESIZED_WIRE_2; |
|
assign SYNTHESIZED_WIRE_3 = ctl_bus_ff_oe | ctl_bus_zero_oe; |
|
assign vcc = 8'b11111111; |
|
endmodule |
/trunk/cpu/deploy/sequencer.v
0,0 → 1,299
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Sun Nov 16 23:11:10 2014" |
|
module sequencer( |
clk, |
nextM, |
setM1, |
nreset, |
hold_clk_iorq, |
hold_clk_wait, |
hold_clk_busrq, |
M1, |
M2, |
M3, |
M4, |
M5, |
M6, |
T1, |
T2, |
T3, |
T4, |
T5, |
T6, |
timings_en |
); |
|
|
input wire clk; |
input wire nextM; |
input wire setM1; |
input wire nreset; |
input wire hold_clk_iorq; |
input wire hold_clk_wait; |
input wire hold_clk_busrq; |
output wire M1; |
output wire M2; |
output wire M3; |
output wire M4; |
output wire M5; |
output reg M6; |
output wire T1; |
output wire T2; |
output wire T3; |
output wire T4; |
output wire T5; |
output reg T6; |
output wire timings_en; |
|
wire ena_M; |
wire ena_T; |
reg DFFE_M4_ff; |
wire SYNTHESIZED_WIRE_20; |
reg DFFE_M5_ff; |
reg DFFE_T1_ff; |
wire SYNTHESIZED_WIRE_21; |
reg DFFE_T2_ff; |
reg DFFE_T3_ff; |
reg DFFE_T4_ff; |
reg DFFE_T5_ff; |
reg DFFE_M1_ff; |
reg DFFE_M2_ff; |
reg DFFE_M3_ff; |
wire SYNTHESIZED_WIRE_10; |
wire SYNTHESIZED_WIRE_11; |
wire SYNTHESIZED_WIRE_12; |
wire SYNTHESIZED_WIRE_13; |
wire SYNTHESIZED_WIRE_14; |
wire SYNTHESIZED_WIRE_15; |
wire SYNTHESIZED_WIRE_16; |
wire SYNTHESIZED_WIRE_17; |
wire SYNTHESIZED_WIRE_18; |
wire SYNTHESIZED_WIRE_19; |
|
assign M1 = DFFE_M1_ff; |
assign M2 = DFFE_M2_ff; |
assign M3 = DFFE_M3_ff; |
assign M4 = DFFE_M4_ff; |
assign M5 = DFFE_M5_ff; |
assign T1 = DFFE_T1_ff; |
assign T2 = DFFE_T2_ff; |
assign T3 = DFFE_T3_ff; |
assign T4 = DFFE_T4_ff; |
assign T5 = DFFE_T5_ff; |
|
|
|
assign SYNTHESIZED_WIRE_13 = DFFE_M4_ff & SYNTHESIZED_WIRE_20; |
|
assign SYNTHESIZED_WIRE_14 = DFFE_M5_ff & SYNTHESIZED_WIRE_20; |
|
assign SYNTHESIZED_WIRE_15 = DFFE_T1_ff & SYNTHESIZED_WIRE_21; |
|
assign SYNTHESIZED_WIRE_16 = DFFE_T2_ff & SYNTHESIZED_WIRE_21; |
|
assign SYNTHESIZED_WIRE_17 = DFFE_T3_ff & SYNTHESIZED_WIRE_21; |
|
assign SYNTHESIZED_WIRE_18 = DFFE_T4_ff & SYNTHESIZED_WIRE_21; |
|
assign SYNTHESIZED_WIRE_19 = DFFE_T5_ff & SYNTHESIZED_WIRE_21; |
|
assign SYNTHESIZED_WIRE_10 = DFFE_M1_ff & SYNTHESIZED_WIRE_20; |
|
assign SYNTHESIZED_WIRE_11 = DFFE_M2_ff & SYNTHESIZED_WIRE_20; |
|
assign SYNTHESIZED_WIRE_12 = DFFE_M3_ff & SYNTHESIZED_WIRE_20; |
|
assign ena_T = ~(hold_clk_iorq | hold_clk_wait | hold_clk_busrq); |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_M1_ff <= 1; |
end |
else |
if (ena_M) |
begin |
DFFE_M1_ff <= setM1; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_M2_ff <= 0; |
end |
else |
if (ena_M) |
begin |
DFFE_M2_ff <= SYNTHESIZED_WIRE_10; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_M3_ff <= 0; |
end |
else |
if (ena_M) |
begin |
DFFE_M3_ff <= SYNTHESIZED_WIRE_11; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_M4_ff <= 0; |
end |
else |
if (ena_M) |
begin |
DFFE_M4_ff <= SYNTHESIZED_WIRE_12; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_M5_ff <= 0; |
end |
else |
if (ena_M) |
begin |
DFFE_M5_ff <= SYNTHESIZED_WIRE_13; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
M6 <= 0; |
end |
else |
if (ena_M) |
begin |
M6 <= SYNTHESIZED_WIRE_14; |
end |
end |
|
assign SYNTHESIZED_WIRE_21 = ~ena_M; |
|
assign SYNTHESIZED_WIRE_20 = ~setM1; |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_T1_ff <= 1; |
end |
else |
if (ena_T) |
begin |
DFFE_T1_ff <= ena_M; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_T2_ff <= 0; |
end |
else |
if (ena_T) |
begin |
DFFE_T2_ff <= SYNTHESIZED_WIRE_15; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_T3_ff <= 0; |
end |
else |
if (ena_T) |
begin |
DFFE_T3_ff <= SYNTHESIZED_WIRE_16; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_T4_ff <= 0; |
end |
else |
if (ena_T) |
begin |
DFFE_T4_ff <= SYNTHESIZED_WIRE_17; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_T5_ff <= 0; |
end |
else |
if (ena_T) |
begin |
DFFE_T5_ff <= SYNTHESIZED_WIRE_18; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
T6 <= 0; |
end |
else |
if (ena_T) |
begin |
T6 <= SYNTHESIZED_WIRE_19; |
end |
end |
|
assign ena_M = nextM; |
assign timings_en = ena_T; |
|
endmodule |
/trunk/cpu/deploy/data_switch.v
0,0 → 1,55
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Mon Oct 13 12:33:19 2014" |
|
module data_switch( |
sw_up_en, |
sw_down_en, |
db_down, |
db_up |
); |
|
|
input wire sw_up_en; |
input wire sw_down_en; |
inout wire [7:0] db_down; |
inout wire [7:0] db_up; |
|
|
|
|
|
assign db_up[7] = sw_up_en ? db_down[7] : 1'bz; |
assign db_up[6] = sw_up_en ? db_down[6] : 1'bz; |
assign db_up[5] = sw_up_en ? db_down[5] : 1'bz; |
assign db_up[4] = sw_up_en ? db_down[4] : 1'bz; |
assign db_up[3] = sw_up_en ? db_down[3] : 1'bz; |
assign db_up[2] = sw_up_en ? db_down[2] : 1'bz; |
assign db_up[1] = sw_up_en ? db_down[1] : 1'bz; |
assign db_up[0] = sw_up_en ? db_down[0] : 1'bz; |
|
assign db_down[7] = sw_down_en ? db_up[7] : 1'bz; |
assign db_down[6] = sw_down_en ? db_up[6] : 1'bz; |
assign db_down[5] = sw_down_en ? db_up[5] : 1'bz; |
assign db_down[4] = sw_down_en ? db_up[4] : 1'bz; |
assign db_down[3] = sw_down_en ? db_up[3] : 1'bz; |
assign db_down[2] = sw_down_en ? db_up[2] : 1'bz; |
assign db_down[1] = sw_down_en ? db_up[1] : 1'bz; |
assign db_down[0] = sw_down_en ? db_up[0] : 1'bz; |
|
|
endmodule |
/trunk/cpu/deploy/alu_mux_2.v
0,0 → 1,48
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Mon Oct 13 12:10:35 2014" |
|
module alu_mux_2( |
sel1, |
in1, |
in0, |
out |
); |
|
|
input wire sel1; |
input wire in1; |
input wire in0; |
output wire out; |
|
wire SYNTHESIZED_WIRE_0; |
wire SYNTHESIZED_WIRE_1; |
wire SYNTHESIZED_WIRE_2; |
|
|
|
|
assign SYNTHESIZED_WIRE_2 = in0 & SYNTHESIZED_WIRE_0; |
|
assign SYNTHESIZED_WIRE_1 = in1 & sel1; |
|
assign out = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2; |
|
assign SYNTHESIZED_WIRE_0 = ~sel1; |
|
|
endmodule |
/trunk/cpu/deploy/bus_switch.sv
0,0 → 1,41
//============================================================================ |
// Bus switch in bus A-Z80 CPU |
// |
// Copyright 2014 Goran Devic |
// |
// This module provides control data bus switch signals. The sole purpose of |
// having these wires defined in this module is to get all control signals |
// (which are processed by genglobals.py) to appear in the list of global |
// control signals ("globals.vh") for consistency. |
//============================================================================ |
|
module bus_switch |
( |
input wire ctl_sw_1u, // Control input for the SW1 upstream |
input wire ctl_sw_1d, // Control input for the SW1 downstream |
|
input wire ctl_sw_2u, // Control input for the SW2 upstream |
input wire ctl_sw_2d, // Control input for the SW2 downstream |
|
input wire ctl_sw_mask543_en, // Enables masking [5:3] on the data bus switch 1 |
|
//-------------------------------------------------------------------- |
|
output wire bus_sw_1u, // SW1 upstream |
output wire bus_sw_1d, // SW1 downstream |
|
output wire bus_sw_2u, // SW2 upstream |
output wire bus_sw_2d, // SW2 downstream |
|
output wire bus_sw_mask543_en // Affects SW1 downstream |
); |
|
assign bus_sw_1u = ctl_sw_1u; |
assign bus_sw_1d = ctl_sw_1d; |
|
assign bus_sw_2u = ctl_sw_2u; |
assign bus_sw_2d = ctl_sw_2d; |
|
assign bus_sw_mask543_en = ctl_sw_mask543_en; |
|
endmodule |
/trunk/cpu/deploy/z80_top_direct_n.sv
0,0 → 1,54
//============================================================================ |
// Z80 Top level using the direct module declaration |
//============================================================================ |
`timescale 1us/ 100 ns |
|
module z80_top_direct_n( |
output wire nM1, |
output wire nMREQ, |
output wire nIORQ, |
output wire nRD, |
output wire nWR, |
output wire nRFSH, |
output wire nHALT, |
output wire nBUSACK, |
|
input wire nWAIT, |
input wire nINT, |
input wire nNMI, |
input wire nRESET, |
input wire nBUSRQ, |
|
input wire CLK, |
output wire [15:0] A, |
inout wire [7:0] D |
); |
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
// Include core A-Z80 level connecting all internal modules |
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
`include "core.vh" |
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
// Address, Data and Control bus drivers connecting to external pins |
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
address_pins address_pins_( .*, .abus(A[15:0]) ); |
data_pins data_pins_ ( .*, .db(db0[7:0]), .D(D[7:0]) ); |
control_pins_n control_pins_( .*, |
.pin_nM1 (nM1), |
.pin_nMREQ (nMREQ), |
.pin_nIORQ (nIORQ), |
.pin_nRD (nRD), |
.pin_nWR (nWR), |
.pin_nRFSH (nRFSH), |
.pin_nHALT (nHALT), |
.pin_nWAIT (nWAIT), |
.pin_nBUSACK (nBUSACK), |
.pin_nINT (nINT), |
.pin_nNMI (nNMI), |
.pin_nRESET (nRESET), |
.pin_nBUSRQ (nBUSRQ), |
.CPUCLK (CLK) |
); |
|
endmodule |
/trunk/cpu/deploy/alu_flags.v
0,0 → 1,348
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Sun Oct 19 14:48:51 2014" |
|
module alu_flags( |
ctl_flags_oe, |
ctl_flags_bus, |
ctl_flags_alu, |
alu_sf_out, |
alu_yf_out, |
alu_xf_out, |
ctl_flags_nf_set, |
alu_zero, |
shift_cf_out, |
alu_core_cf_out, |
daa_cf_out, |
ctl_flags_cf_set, |
ctl_flags_cf_cpl, |
pf_sel, |
ctl_flags_cf_we, |
ctl_flags_sz_we, |
ctl_flags_xy_we, |
ctl_flags_hf_we, |
ctl_flags_pf_we, |
ctl_flags_nf_we, |
ctl_flags_cf2_we, |
ctl_flags_hf_cpl, |
ctl_flags_use_cf2, |
ctl_flags_hf2_we, |
ctl_flags_nf_clr, |
ctl_alu_zero_16bit, |
clk, |
ctl_flags_cf2_sel, |
flags_sf, |
flags_zf, |
flags_hf, |
flags_pf, |
flags_cf, |
flags_nf, |
flags_cf_latch, |
flags_hf2, |
db |
); |
|
|
input wire ctl_flags_oe; |
input wire ctl_flags_bus; |
input wire ctl_flags_alu; |
input wire alu_sf_out; |
input wire alu_yf_out; |
input wire alu_xf_out; |
input wire ctl_flags_nf_set; |
input wire alu_zero; |
input wire shift_cf_out; |
input wire alu_core_cf_out; |
input wire daa_cf_out; |
input wire ctl_flags_cf_set; |
input wire ctl_flags_cf_cpl; |
input wire pf_sel; |
input wire ctl_flags_cf_we; |
input wire ctl_flags_sz_we; |
input wire ctl_flags_xy_we; |
input wire ctl_flags_hf_we; |
input wire ctl_flags_pf_we; |
input wire ctl_flags_nf_we; |
input wire ctl_flags_cf2_we; |
input wire ctl_flags_hf_cpl; |
input wire ctl_flags_use_cf2; |
input wire ctl_flags_hf2_we; |
input wire ctl_flags_nf_clr; |
input wire ctl_alu_zero_16bit; |
input wire clk; |
input wire [1:0] ctl_flags_cf2_sel; |
output wire flags_sf; |
output wire flags_zf; |
output wire flags_hf; |
output wire flags_pf; |
output wire flags_cf; |
output wire flags_nf; |
output wire flags_cf_latch; |
output reg flags_hf2; |
inout wire [7:0] db; |
|
reg flags_xf; |
reg flags_yf; |
wire SYNTHESIZED_WIRE_0; |
reg DFFE_inst_latch_hf; |
wire SYNTHESIZED_WIRE_1; |
wire SYNTHESIZED_WIRE_2; |
wire SYNTHESIZED_WIRE_3; |
wire SYNTHESIZED_WIRE_4; |
wire SYNTHESIZED_WIRE_5; |
wire SYNTHESIZED_WIRE_6; |
wire SYNTHESIZED_WIRE_7; |
wire SYNTHESIZED_WIRE_8; |
reg SYNTHESIZED_WIRE_38; |
wire SYNTHESIZED_WIRE_9; |
wire SYNTHESIZED_WIRE_10; |
wire SYNTHESIZED_WIRE_11; |
wire SYNTHESIZED_WIRE_12; |
wire SYNTHESIZED_WIRE_13; |
wire SYNTHESIZED_WIRE_14; |
wire SYNTHESIZED_WIRE_15; |
wire SYNTHESIZED_WIRE_16; |
wire SYNTHESIZED_WIRE_17; |
wire SYNTHESIZED_WIRE_18; |
wire SYNTHESIZED_WIRE_19; |
wire SYNTHESIZED_WIRE_20; |
wire SYNTHESIZED_WIRE_21; |
wire SYNTHESIZED_WIRE_22; |
reg DFFE_inst_latch_sf; |
wire SYNTHESIZED_WIRE_23; |
reg DFFE_inst_latch_pf; |
reg DFFE_inst_latch_nf; |
wire SYNTHESIZED_WIRE_24; |
wire SYNTHESIZED_WIRE_25; |
wire SYNTHESIZED_WIRE_26; |
wire SYNTHESIZED_WIRE_27; |
wire SYNTHESIZED_WIRE_28; |
wire SYNTHESIZED_WIRE_39; |
wire SYNTHESIZED_WIRE_31; |
wire SYNTHESIZED_WIRE_32; |
wire SYNTHESIZED_WIRE_33; |
wire SYNTHESIZED_WIRE_34; |
wire SYNTHESIZED_WIRE_35; |
wire SYNTHESIZED_WIRE_36; |
reg DFFE_inst_latch_cf; |
reg DFFE_inst_latch_cf2; |
wire SYNTHESIZED_WIRE_37; |
|
assign flags_sf = DFFE_inst_latch_sf; |
assign flags_zf = SYNTHESIZED_WIRE_38; |
assign flags_hf = SYNTHESIZED_WIRE_23; |
assign flags_pf = DFFE_inst_latch_pf; |
assign flags_cf = SYNTHESIZED_WIRE_24; |
assign flags_nf = DFFE_inst_latch_nf; |
assign flags_cf_latch = DFFE_inst_latch_cf; |
assign SYNTHESIZED_WIRE_37 = 0; |
|
|
|
assign SYNTHESIZED_WIRE_27 = ctl_flags_cf_we & SYNTHESIZED_WIRE_0; |
|
assign SYNTHESIZED_WIRE_10 = db[7] & ctl_flags_bus; |
|
assign SYNTHESIZED_WIRE_17 = alu_xf_out & ctl_flags_alu; |
|
assign SYNTHESIZED_WIRE_20 = db[2] & ctl_flags_bus; |
|
assign SYNTHESIZED_WIRE_19 = pf_sel & ctl_flags_alu; |
|
assign SYNTHESIZED_WIRE_3 = db[1] & ctl_flags_bus; |
|
assign SYNTHESIZED_WIRE_23 = DFFE_inst_latch_hf ^ ctl_flags_hf_cpl; |
|
assign SYNTHESIZED_WIRE_22 = db[0] & ctl_flags_bus; |
|
assign SYNTHESIZED_WIRE_21 = ctl_flags_alu & alu_core_cf_out; |
|
assign SYNTHESIZED_WIRE_0 = ~ctl_flags_cf2_we; |
|
assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_1 ^ ctl_flags_cf_cpl; |
|
assign SYNTHESIZED_WIRE_2 = alu_sf_out & ctl_flags_alu; |
|
assign SYNTHESIZED_WIRE_9 = alu_sf_out & ctl_flags_alu; |
|
assign SYNTHESIZED_WIRE_6 = ctl_flags_nf_set | SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3; |
|
assign SYNTHESIZED_WIRE_36 = SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_5; |
|
|
assign SYNTHESIZED_WIRE_31 = SYNTHESIZED_WIRE_6 & SYNTHESIZED_WIRE_7; |
|
assign SYNTHESIZED_WIRE_7 = ~ctl_flags_nf_clr; |
|
assign SYNTHESIZED_WIRE_8 = ~ctl_alu_zero_16bit; |
|
assign SYNTHESIZED_WIRE_5 = SYNTHESIZED_WIRE_8 | SYNTHESIZED_WIRE_38; |
|
assign SYNTHESIZED_WIRE_12 = db[6] & ctl_flags_bus; |
|
assign SYNTHESIZED_WIRE_33 = SYNTHESIZED_WIRE_9 | SYNTHESIZED_WIRE_10; |
|
assign SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12; |
|
assign SYNTHESIZED_WIRE_35 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14; |
|
assign SYNTHESIZED_WIRE_39 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16; |
|
assign SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18; |
|
assign SYNTHESIZED_WIRE_32 = SYNTHESIZED_WIRE_19 | SYNTHESIZED_WIRE_20; |
|
assign SYNTHESIZED_WIRE_11 = alu_zero & ctl_flags_alu; |
|
assign SYNTHESIZED_WIRE_26 = SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22; |
|
assign db[7] = ctl_flags_oe ? DFFE_inst_latch_sf : 1'bz; |
|
assign SYNTHESIZED_WIRE_14 = db[5] & ctl_flags_bus; |
|
assign db[6] = ctl_flags_oe ? SYNTHESIZED_WIRE_38 : 1'bz; |
|
assign db[5] = ctl_flags_oe ? flags_yf : 1'bz; |
|
assign db[4] = ctl_flags_oe ? SYNTHESIZED_WIRE_23 : 1'bz; |
|
assign db[3] = ctl_flags_oe ? flags_xf : 1'bz; |
|
assign db[2] = ctl_flags_oe ? DFFE_inst_latch_pf : 1'bz; |
|
assign db[1] = ctl_flags_oe ? DFFE_inst_latch_nf : 1'bz; |
|
assign db[0] = ctl_flags_oe ? SYNTHESIZED_WIRE_24 : 1'bz; |
|
assign SYNTHESIZED_WIRE_13 = alu_yf_out & ctl_flags_alu; |
|
assign SYNTHESIZED_WIRE_1 = ctl_flags_cf_set | SYNTHESIZED_WIRE_25; |
|
assign SYNTHESIZED_WIRE_16 = db[4] & ctl_flags_bus; |
|
assign SYNTHESIZED_WIRE_15 = alu_core_cf_out & ctl_flags_alu; |
|
assign SYNTHESIZED_WIRE_18 = db[3] & ctl_flags_bus; |
|
|
always@(posedge clk) |
begin |
if (SYNTHESIZED_WIRE_27) |
begin |
DFFE_inst_latch_cf <= SYNTHESIZED_WIRE_26; |
end |
end |
|
|
always@(posedge clk) |
begin |
if (ctl_flags_cf2_we) |
begin |
DFFE_inst_latch_cf2 <= SYNTHESIZED_WIRE_28; |
end |
end |
|
|
always@(posedge clk) |
begin |
if (ctl_flags_hf_we) |
begin |
DFFE_inst_latch_hf <= SYNTHESIZED_WIRE_39; |
end |
end |
|
|
always@(posedge clk) |
begin |
if (ctl_flags_hf2_we) |
begin |
flags_hf2 <= SYNTHESIZED_WIRE_39; |
end |
end |
|
|
always@(posedge clk) |
begin |
if (ctl_flags_nf_we) |
begin |
DFFE_inst_latch_nf <= SYNTHESIZED_WIRE_31; |
end |
end |
|
|
always@(posedge clk) |
begin |
if (ctl_flags_pf_we) |
begin |
DFFE_inst_latch_pf <= SYNTHESIZED_WIRE_32; |
end |
end |
|
|
always@(posedge clk) |
begin |
if (ctl_flags_sz_we) |
begin |
DFFE_inst_latch_sf <= SYNTHESIZED_WIRE_33; |
end |
end |
|
|
always@(posedge clk) |
begin |
if (ctl_flags_xy_we) |
begin |
flags_xf <= SYNTHESIZED_WIRE_34; |
end |
end |
|
|
always@(posedge clk) |
begin |
if (ctl_flags_xy_we) |
begin |
flags_yf <= SYNTHESIZED_WIRE_35; |
end |
end |
|
|
always@(posedge clk) |
begin |
if (ctl_flags_sz_we) |
begin |
SYNTHESIZED_WIRE_38 <= SYNTHESIZED_WIRE_36; |
end |
end |
|
|
alu_mux_2 b2v_inst_mux_cf( |
.in0(DFFE_inst_latch_cf), |
.in1(DFFE_inst_latch_cf2), |
.sel1(ctl_flags_use_cf2), |
.out(SYNTHESIZED_WIRE_25)); |
|
|
alu_mux_4 b2v_inst_mux_cf2( |
.in0(alu_core_cf_out), |
.in1(shift_cf_out), |
.in2(daa_cf_out), |
.in3(SYNTHESIZED_WIRE_37), |
.sel(ctl_flags_cf2_sel), |
.out(SYNTHESIZED_WIRE_28)); |
|
|
endmodule |
/trunk/cpu/deploy/alu_mux_4.v
0,0 → 1,61
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Mon Oct 13 12:05:38 2014" |
|
module alu_mux_4( |
in0, |
in1, |
in2, |
in3, |
sel, |
out |
); |
|
|
input wire in0; |
input wire in1; |
input wire in2; |
input wire in3; |
input wire [1:0] sel; |
output wire out; |
|
wire SYNTHESIZED_WIRE_8; |
wire SYNTHESIZED_WIRE_9; |
wire SYNTHESIZED_WIRE_4; |
wire SYNTHESIZED_WIRE_5; |
wire SYNTHESIZED_WIRE_6; |
wire SYNTHESIZED_WIRE_7; |
|
|
|
|
assign SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_8 & SYNTHESIZED_WIRE_9 & in0; |
|
assign SYNTHESIZED_WIRE_7 = sel[0] & SYNTHESIZED_WIRE_9 & in1; |
|
assign SYNTHESIZED_WIRE_5 = SYNTHESIZED_WIRE_8 & sel[1] & in2; |
|
assign SYNTHESIZED_WIRE_6 = sel[0] & sel[1] & in3; |
|
assign out = SYNTHESIZED_WIRE_4 | SYNTHESIZED_WIRE_5 | SYNTHESIZED_WIRE_6 | SYNTHESIZED_WIRE_7; |
|
assign SYNTHESIZED_WIRE_8 = ~sel[0]; |
|
assign SYNTHESIZED_WIRE_9 = ~sel[1]; |
|
|
endmodule |
/trunk/cpu/deploy/alu_slice.v
0,0 → 1,76
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Mon Oct 13 11:51:12 2014" |
|
module alu_slice( |
op2, |
op1, |
cy_in, |
R, |
S, |
V, |
cy_out, |
result |
); |
|
|
input wire op2; |
input wire op1; |
input wire cy_in; |
input wire R; |
input wire S; |
input wire V; |
output wire cy_out; |
output wire result; |
|
wire SYNTHESIZED_WIRE_0; |
wire SYNTHESIZED_WIRE_1; |
wire SYNTHESIZED_WIRE_2; |
wire SYNTHESIZED_WIRE_3; |
wire SYNTHESIZED_WIRE_4; |
wire SYNTHESIZED_WIRE_5; |
wire SYNTHESIZED_WIRE_10; |
wire SYNTHESIZED_WIRE_7; |
wire SYNTHESIZED_WIRE_8; |
|
|
|
|
assign SYNTHESIZED_WIRE_0 = op2 | cy_in | op1; |
|
assign SYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_0 & SYNTHESIZED_WIRE_1; |
|
assign SYNTHESIZED_WIRE_4 = cy_in & op2 & op1; |
|
assign result = ~SYNTHESIZED_WIRE_2; |
|
assign SYNTHESIZED_WIRE_2 = ~(SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4); |
|
assign SYNTHESIZED_WIRE_5 = op2 | op1; |
|
assign SYNTHESIZED_WIRE_7 = cy_in & SYNTHESIZED_WIRE_5; |
|
assign SYNTHESIZED_WIRE_8 = op1 & op2; |
|
assign cy_out = ~(R | SYNTHESIZED_WIRE_10); |
|
assign SYNTHESIZED_WIRE_10 = ~(SYNTHESIZED_WIRE_7 | SYNTHESIZED_WIRE_8 | S); |
|
assign SYNTHESIZED_WIRE_1 = V | SYNTHESIZED_WIRE_10; |
|
|
endmodule |
/trunk/cpu/deploy/exec_module.vh
0,0 → 1,127
// Automatically generated by genref.py |
|
// Module: control/decode_state.v |
output logic ctl_state_iy_set, |
output logic ctl_state_ixiy_clr, |
output logic ctl_state_ixiy_we, |
output logic ctl_state_halt_set, |
output logic ctl_state_tbl_clr, |
output logic ctl_state_tbl_ed_set, |
output logic ctl_state_tbl_cb_set, |
output logic ctl_state_alu, |
output logic ctl_repeat_we, |
|
// Module: control/interrupts.v |
output logic ctl_iff1_iff2, |
output logic ctl_iffx_we, |
output logic ctl_iffx_bit, |
output logic ctl_im_we, |
output logic ctl_no_ints, |
|
// Module: control/ir.v |
output logic ctl_ir_we, |
|
// Module: control/memory_ifc.v |
output logic ctl_mRead, |
output logic ctl_mWrite, |
output logic ctl_iorw, |
|
// Module: alu/alu_control.v |
output logic ctl_shift_en, |
output logic ctl_daa_oe, |
output logic ctl_alu_op_low, |
output logic ctl_cond_short, |
output logic ctl_alu_core_hf, |
output logic ctl_eval_cond, |
output logic ctl_66_oe, |
output logic [1:0] ctl_pf_sel, |
|
// Module: alu/alu_select.v |
output logic ctl_alu_oe, |
output logic ctl_alu_shift_oe, |
output logic ctl_alu_op2_oe, |
output logic ctl_alu_res_oe, |
output logic ctl_alu_op1_oe, |
output logic ctl_alu_bs_oe, |
output logic ctl_alu_op1_sel_bus, |
output logic ctl_alu_op1_sel_low, |
output logic ctl_alu_op1_sel_zero, |
output logic ctl_alu_op2_sel_zero, |
output logic ctl_alu_op2_sel_bus, |
output logic ctl_alu_op2_sel_lq, |
output logic ctl_alu_sel_op2_neg, |
output logic ctl_alu_sel_op2_high, |
output logic ctl_alu_core_R, |
output logic ctl_alu_core_V, |
output logic ctl_alu_core_S, |
|
// Module: alu/alu_flags.v |
output logic ctl_flags_oe, |
output logic ctl_flags_bus, |
output logic ctl_flags_alu, |
output logic ctl_flags_nf_set, |
output logic ctl_flags_cf_set, |
output logic ctl_flags_cf_cpl, |
output logic ctl_flags_cf_we, |
output logic ctl_flags_sz_we, |
output logic ctl_flags_xy_we, |
output logic ctl_flags_hf_we, |
output logic ctl_flags_pf_we, |
output logic ctl_flags_nf_we, |
output logic ctl_flags_cf2_we, |
output logic ctl_flags_hf_cpl, |
output logic ctl_flags_use_cf2, |
output logic ctl_flags_hf2_we, |
output logic ctl_flags_nf_clr, |
output logic ctl_alu_zero_16bit, |
output logic [1:0] ctl_flags_cf2_sel, |
|
// Module: registers/reg_file.v |
output logic ctl_sw_4d, |
output logic ctl_sw_4u, |
output logic ctl_reg_in_hi, |
output logic ctl_reg_in_lo, |
output logic ctl_reg_out_lo, |
output logic ctl_reg_out_hi, |
|
// Module: registers/reg_control.v |
output logic ctl_reg_exx, |
output logic ctl_reg_ex_af, |
output logic ctl_reg_ex_de_hl, |
output logic ctl_reg_use_sp, |
output logic ctl_reg_sel_pc, |
output logic ctl_reg_sel_ir, |
output logic ctl_reg_sel_wz, |
output logic ctl_reg_gp_we, |
output logic ctl_reg_not_pc, |
output logic ctl_reg_sys_we_lo, |
output logic ctl_reg_sys_we_hi, |
output logic ctl_reg_sys_we, |
output logic [1:0] ctl_reg_gp_hilo, |
output logic [1:0] ctl_reg_gp_sel, |
output logic [1:0] ctl_reg_sys_hilo, |
|
// Module: bus/address_latch.v |
output logic ctl_inc_cy, |
output logic ctl_inc_dec, |
output logic ctl_inc_zero, |
output logic ctl_al_we, |
output logic ctl_inc_limit6, |
output logic ctl_bus_inc_oe, |
output logic ctl_apin_mux, |
output logic ctl_apin_mux2, |
|
// Module: bus/bus_control.v |
output logic ctl_bus_ff_oe, |
output logic ctl_bus_zero_oe, |
output logic ctl_bus_db_oe, |
|
// Module: bus/bus_switch.sv |
output logic ctl_sw_1u, |
output logic ctl_sw_1d, |
output logic ctl_sw_2u, |
output logic ctl_sw_2d, |
output logic ctl_sw_mask543_en, |
|
// Module: bus/data_pins.v |
output logic ctl_bus_db_we, |
/trunk/cpu/deploy/alu_mux_8.v
0,0 → 1,84
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Mon Oct 13 12:04:13 2014" |
|
module alu_mux_8( |
in0, |
in1, |
in2, |
in3, |
in4, |
in5, |
in6, |
in7, |
sel, |
out |
); |
|
|
input wire in0; |
input wire in1; |
input wire in2; |
input wire in3; |
input wire in4; |
input wire in5; |
input wire in6; |
input wire in7; |
input wire [2:0] sel; |
output wire out; |
|
wire SYNTHESIZED_WIRE_20; |
wire SYNTHESIZED_WIRE_21; |
wire SYNTHESIZED_WIRE_22; |
wire SYNTHESIZED_WIRE_12; |
wire SYNTHESIZED_WIRE_13; |
wire SYNTHESIZED_WIRE_14; |
wire SYNTHESIZED_WIRE_15; |
wire SYNTHESIZED_WIRE_16; |
wire SYNTHESIZED_WIRE_17; |
wire SYNTHESIZED_WIRE_18; |
wire SYNTHESIZED_WIRE_19; |
|
|
|
|
assign SYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_22 & in0; |
|
assign SYNTHESIZED_WIRE_14 = sel[0] & SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_22 & in1; |
|
assign SYNTHESIZED_WIRE_13 = SYNTHESIZED_WIRE_20 & sel[1] & SYNTHESIZED_WIRE_22 & in2; |
|
assign SYNTHESIZED_WIRE_15 = sel[0] & sel[1] & SYNTHESIZED_WIRE_22 & in3; |
|
assign SYNTHESIZED_WIRE_17 = SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_21 & sel[2] & in4; |
|
assign SYNTHESIZED_WIRE_16 = sel[0] & SYNTHESIZED_WIRE_21 & sel[2] & in5; |
|
assign SYNTHESIZED_WIRE_18 = SYNTHESIZED_WIRE_20 & sel[1] & sel[2] & in6; |
|
assign SYNTHESIZED_WIRE_19 = sel[0] & sel[1] & sel[2] & in7; |
|
assign out = SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14 | SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16 | SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18 | SYNTHESIZED_WIRE_19; |
|
assign SYNTHESIZED_WIRE_20 = ~sel[0]; |
|
assign SYNTHESIZED_WIRE_21 = ~sel[1]; |
|
assign SYNTHESIZED_WIRE_22 = ~sel[2]; |
|
|
endmodule |
/trunk/cpu/deploy/data_pins.v
0,0 → 1,86
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Thu Nov 06 23:28:26 2014" |
|
module data_pins( |
bus_db_pin_oe, |
bus_db_pin_re, |
ctl_bus_db_we, |
bus_db_oe, |
clk, |
D, |
db |
); |
|
|
input wire bus_db_pin_oe; |
input wire bus_db_pin_re; |
input wire ctl_bus_db_we; |
input wire bus_db_oe; |
input wire clk; |
inout wire [7:0] D; |
inout wire [7:0] db; |
|
reg [7:0] dout; |
wire [7:0] SYNTHESIZED_WIRE_0; |
wire SYNTHESIZED_WIRE_1; |
wire SYNTHESIZED_WIRE_2; |
wire [7:0] SYNTHESIZED_WIRE_3; |
wire [7:0] SYNTHESIZED_WIRE_4; |
|
|
|
|
|
always@(posedge SYNTHESIZED_WIRE_1) |
begin |
if (SYNTHESIZED_WIRE_2) |
begin |
dout[7:0] <= SYNTHESIZED_WIRE_0[7:0]; |
end |
end |
|
assign SYNTHESIZED_WIRE_4 = {ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we} & db; |
|
assign SYNTHESIZED_WIRE_3 = {bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re} & D; |
|
assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4; |
|
assign SYNTHESIZED_WIRE_2 = ctl_bus_db_we | bus_db_pin_re; |
|
assign db[7] = bus_db_oe ? dout[7] : 1'bz; |
assign db[6] = bus_db_oe ? dout[6] : 1'bz; |
assign db[5] = bus_db_oe ? dout[5] : 1'bz; |
assign db[4] = bus_db_oe ? dout[4] : 1'bz; |
assign db[3] = bus_db_oe ? dout[3] : 1'bz; |
assign db[2] = bus_db_oe ? dout[2] : 1'bz; |
assign db[1] = bus_db_oe ? dout[1] : 1'bz; |
assign db[0] = bus_db_oe ? dout[0] : 1'bz; |
|
assign D[7] = bus_db_pin_oe ? dout[7] : 1'bz; |
assign D[6] = bus_db_pin_oe ? dout[6] : 1'bz; |
assign D[5] = bus_db_pin_oe ? dout[5] : 1'bz; |
assign D[4] = bus_db_pin_oe ? dout[4] : 1'bz; |
assign D[3] = bus_db_pin_oe ? dout[3] : 1'bz; |
assign D[2] = bus_db_pin_oe ? dout[2] : 1'bz; |
assign D[1] = bus_db_pin_oe ? dout[1] : 1'bz; |
assign D[0] = bus_db_pin_oe ? dout[0] : 1'bz; |
|
assign SYNTHESIZED_WIRE_1 = ~clk; |
|
|
endmodule |
/trunk/cpu/deploy/resets.v
0,0 → 1,109
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Sun Nov 09 09:13:38 2014" |
|
module resets( |
reset_in, |
clk, |
M1, |
T2, |
fpga_reset, |
clrpc, |
nreset |
); |
|
|
input wire reset_in; |
input wire clk; |
input wire M1; |
input wire T2; |
input wire fpga_reset; |
output reg clrpc; |
output wire nreset; |
|
wire nclk; |
reg x1; |
wire x2; |
wire x3; |
wire SYNTHESIZED_WIRE_8; |
wire SYNTHESIZED_WIRE_1; |
wire SYNTHESIZED_WIRE_9; |
wire SYNTHESIZED_WIRE_3; |
reg DFF_res; |
wire SYNTHESIZED_WIRE_6; |
|
assign nreset = SYNTHESIZED_WIRE_6; |
|
|
|
|
always@(posedge nclk or negedge SYNTHESIZED_WIRE_8) |
begin |
if (!SYNTHESIZED_WIRE_8) |
begin |
x1 <= 1; |
end |
else |
begin |
x1 <= ~x1 & reset_in | x1 & ~SYNTHESIZED_WIRE_1; |
end |
end |
|
assign SYNTHESIZED_WIRE_1 = ~reset_in; |
|
assign x2 = x1 & SYNTHESIZED_WIRE_9; |
|
assign SYNTHESIZED_WIRE_9 = M1 & T2; |
|
assign x3 = x1 & SYNTHESIZED_WIRE_3; |
|
assign SYNTHESIZED_WIRE_6 = ~DFF_res; |
|
assign SYNTHESIZED_WIRE_3 = ~SYNTHESIZED_WIRE_9; |
|
assign nclk = ~clk; |
|
assign SYNTHESIZED_WIRE_8 = ~fpga_reset; |
|
|
always@(posedge clk or negedge SYNTHESIZED_WIRE_8) |
begin |
if (!SYNTHESIZED_WIRE_8) |
begin |
DFF_res <= 1; |
end |
else |
begin |
DFF_res <= x3; |
end |
end |
|
|
always@(posedge nclk or negedge SYNTHESIZED_WIRE_6) |
begin |
if (!SYNTHESIZED_WIRE_6) |
begin |
clrpc <= 0; |
end |
else |
begin |
clrpc <= ~clrpc & x2 | clrpc & ~SYNTHESIZED_WIRE_9; |
end |
end |
|
|
endmodule |
/trunk/cpu/deploy/ir.v
0,0 → 1,46
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Fri Oct 31 20:07:47 2014" |
|
module ir( |
ctl_ir_we, |
clk, |
db, |
opcode |
); |
|
|
input wire ctl_ir_we; |
input wire clk; |
input wire [7:0] db; |
output reg [7:0] opcode; |
|
|
|
|
|
|
always@(posedge clk) |
begin |
if (ctl_ir_we) |
begin |
opcode[7:0] <= db[7:0]; |
end |
end |
|
|
endmodule |
/trunk/cpu/deploy/alu_prep_daa.v
0,0 → 1,63
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Mon Oct 13 12:01:36 2014" |
|
module alu_prep_daa( |
high, |
low, |
low_gt_9, |
high_eq_9, |
high_gt_9 |
); |
|
|
input wire [3:0] high; |
input wire [3:0] low; |
output wire low_gt_9; |
output wire high_eq_9; |
output wire high_gt_9; |
|
wire SYNTHESIZED_WIRE_0; |
wire SYNTHESIZED_WIRE_1; |
wire SYNTHESIZED_WIRE_2; |
wire SYNTHESIZED_WIRE_3; |
wire SYNTHESIZED_WIRE_4; |
wire SYNTHESIZED_WIRE_5; |
|
|
|
|
assign SYNTHESIZED_WIRE_4 = ~high[2]; |
|
assign SYNTHESIZED_WIRE_1 = low[3] & low[2]; |
|
assign SYNTHESIZED_WIRE_3 = high[3] & high[2]; |
|
assign SYNTHESIZED_WIRE_0 = low[3] & low[1]; |
|
assign low_gt_9 = SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1; |
|
assign SYNTHESIZED_WIRE_2 = high[3] & high[1]; |
|
assign high_gt_9 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3; |
|
assign SYNTHESIZED_WIRE_5 = ~high[1]; |
|
assign high_eq_9 = high[3] & high[0] & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_5; |
|
|
endmodule |
/trunk/cpu/deploy/alu_shifter_core.v
0,0 → 1,142
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Mon Oct 13 11:55:31 2014" |
|
module alu_shifter_core( |
shift_in, |
shift_right, |
shift_left, |
db, |
shift_db0, |
shift_db7, |
out_high, |
out_low |
); |
|
|
input wire shift_in; |
input wire shift_right; |
input wire shift_left; |
input wire [7:0] db; |
output wire shift_db0; |
output wire shift_db7; |
output wire [3:0] out_high; |
output wire [3:0] out_low; |
|
wire [3:0] out_high_ALTERA_SYNTHESIZED; |
wire [3:0] out_low_ALTERA_SYNTHESIZED; |
wire SYNTHESIZED_WIRE_32; |
wire SYNTHESIZED_WIRE_8; |
wire SYNTHESIZED_WIRE_9; |
wire SYNTHESIZED_WIRE_10; |
wire SYNTHESIZED_WIRE_11; |
wire SYNTHESIZED_WIRE_12; |
wire SYNTHESIZED_WIRE_13; |
wire SYNTHESIZED_WIRE_14; |
wire SYNTHESIZED_WIRE_15; |
wire SYNTHESIZED_WIRE_16; |
wire SYNTHESIZED_WIRE_17; |
wire SYNTHESIZED_WIRE_18; |
wire SYNTHESIZED_WIRE_19; |
wire SYNTHESIZED_WIRE_20; |
wire SYNTHESIZED_WIRE_21; |
wire SYNTHESIZED_WIRE_22; |
wire SYNTHESIZED_WIRE_23; |
wire SYNTHESIZED_WIRE_24; |
wire SYNTHESIZED_WIRE_25; |
wire SYNTHESIZED_WIRE_26; |
wire SYNTHESIZED_WIRE_27; |
wire SYNTHESIZED_WIRE_28; |
wire SYNTHESIZED_WIRE_29; |
wire SYNTHESIZED_WIRE_30; |
wire SYNTHESIZED_WIRE_31; |
|
assign shift_db0 = db[0]; |
assign shift_db7 = db[7]; |
|
|
|
assign SYNTHESIZED_WIRE_9 = shift_in & shift_left; |
|
assign SYNTHESIZED_WIRE_8 = db[0] & SYNTHESIZED_WIRE_32; |
|
assign SYNTHESIZED_WIRE_10 = db[1] & shift_right; |
|
assign SYNTHESIZED_WIRE_12 = db[0] & shift_left; |
|
assign SYNTHESIZED_WIRE_11 = db[1] & SYNTHESIZED_WIRE_32; |
|
assign SYNTHESIZED_WIRE_13 = db[2] & shift_right; |
|
assign SYNTHESIZED_WIRE_15 = db[1] & shift_left; |
|
assign SYNTHESIZED_WIRE_14 = db[2] & SYNTHESIZED_WIRE_32; |
|
assign SYNTHESIZED_WIRE_16 = db[3] & shift_right; |
|
assign SYNTHESIZED_WIRE_18 = db[2] & shift_left; |
|
assign SYNTHESIZED_WIRE_17 = db[3] & SYNTHESIZED_WIRE_32; |
|
assign SYNTHESIZED_WIRE_19 = db[4] & shift_right; |
|
assign SYNTHESIZED_WIRE_21 = db[3] & shift_left; |
|
assign SYNTHESIZED_WIRE_20 = db[4] & SYNTHESIZED_WIRE_32; |
|
assign SYNTHESIZED_WIRE_22 = db[5] & shift_right; |
|
assign SYNTHESIZED_WIRE_24 = db[4] & shift_left; |
|
assign SYNTHESIZED_WIRE_23 = db[5] & SYNTHESIZED_WIRE_32; |
|
assign SYNTHESIZED_WIRE_25 = db[6] & shift_right; |
|
assign SYNTHESIZED_WIRE_27 = db[5] & shift_left; |
|
assign SYNTHESIZED_WIRE_26 = db[6] & SYNTHESIZED_WIRE_32; |
|
assign SYNTHESIZED_WIRE_28 = db[7] & shift_right; |
|
assign SYNTHESIZED_WIRE_30 = db[6] & shift_left; |
|
assign SYNTHESIZED_WIRE_29 = db[7] & SYNTHESIZED_WIRE_32; |
|
assign SYNTHESIZED_WIRE_31 = shift_in & shift_right; |
|
assign SYNTHESIZED_WIRE_32 = ~(shift_right | shift_left); |
|
assign out_low_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_8 | SYNTHESIZED_WIRE_9 | SYNTHESIZED_WIRE_10; |
|
assign out_low_ALTERA_SYNTHESIZED[1] = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13; |
|
assign out_low_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_14 | SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16; |
|
assign out_low_ALTERA_SYNTHESIZED[3] = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18 | SYNTHESIZED_WIRE_19; |
|
assign out_high_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_20 | SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22; |
|
assign out_high_ALTERA_SYNTHESIZED[1] = SYNTHESIZED_WIRE_23 | SYNTHESIZED_WIRE_24 | SYNTHESIZED_WIRE_25; |
|
assign out_high_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_26 | SYNTHESIZED_WIRE_27 | SYNTHESIZED_WIRE_28; |
|
assign out_high_ALTERA_SYNTHESIZED[3] = SYNTHESIZED_WIRE_29 | SYNTHESIZED_WIRE_30 | SYNTHESIZED_WIRE_31; |
|
assign out_high = out_high_ALTERA_SYNTHESIZED; |
assign out_low = out_low_ALTERA_SYNTHESIZED; |
|
endmodule |
/trunk/cpu/deploy/alu_bit_select.v
0,0 → 1,64
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Mon Oct 13 12:21:31 2014" |
|
module alu_bit_select( |
bsel, |
bs_out_high, |
bs_out_low |
); |
|
|
input wire [2:0] bsel; |
output wire [3:0] bs_out_high; |
output wire [3:0] bs_out_low; |
|
wire [3:0] bs_out_high_ALTERA_SYNTHESIZED; |
wire [3:0] bs_out_low_ALTERA_SYNTHESIZED; |
wire SYNTHESIZED_WIRE_12; |
wire SYNTHESIZED_WIRE_13; |
wire SYNTHESIZED_WIRE_14; |
|
|
|
|
assign bs_out_low_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14; |
|
assign bs_out_low_ALTERA_SYNTHESIZED[1] = bsel[0] & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14; |
|
assign bs_out_low_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_12 & bsel[1] & SYNTHESIZED_WIRE_14; |
|
assign bs_out_low_ALTERA_SYNTHESIZED[3] = bsel[0] & bsel[1] & SYNTHESIZED_WIRE_14; |
|
assign bs_out_high_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & bsel[2]; |
|
assign bs_out_high_ALTERA_SYNTHESIZED[1] = bsel[0] & SYNTHESIZED_WIRE_13 & bsel[2]; |
|
assign bs_out_high_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_12 & bsel[1] & bsel[2]; |
|
assign bs_out_high_ALTERA_SYNTHESIZED[3] = bsel[0] & bsel[1] & bsel[2]; |
|
assign SYNTHESIZED_WIRE_12 = ~bsel[0]; |
|
assign SYNTHESIZED_WIRE_13 = ~bsel[1]; |
|
assign SYNTHESIZED_WIRE_14 = ~bsel[2]; |
|
assign bs_out_high = bs_out_high_ALTERA_SYNTHESIZED; |
assign bs_out_low = bs_out_low_ALTERA_SYNTHESIZED; |
|
endmodule |
/trunk/cpu/deploy/address_mux.v
0,0 → 1,48
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Sat Nov 08 09:37:58 2014" |
|
module address_mux( |
select, |
in0, |
in1, |
out |
); |
|
|
input wire select; |
input wire [15:0] in0; |
input wire [15:0] in1; |
output wire [15:0] out; |
|
wire SYNTHESIZED_WIRE_0; |
wire [15:0] SYNTHESIZED_WIRE_1; |
wire [15:0] SYNTHESIZED_WIRE_2; |
|
|
|
|
assign SYNTHESIZED_WIRE_1 = in0 & {SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0}; |
|
assign SYNTHESIZED_WIRE_2 = in1 & {select,select,select,select,select,select,select,select,select,select,select,select,select,select,select,select}; |
|
assign SYNTHESIZED_WIRE_0 = ~select; |
|
assign out = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2; |
|
|
endmodule |
/trunk/cpu/deploy/exec_matrix.vh
0,0 → 1,4194
// Automatically generated by genmatrix.py |
// 8-bit Load Group |
if (pla[17] && !pla[50]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; setM1=1; end |
end |
|
if (pla[61] && !pla[58] && !pla[59]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2u=1; |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_op1_oe=1; /* OP1 latch */ end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ end |
end |
|
if (use_ixiy && pla[58]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; end |
if (M3 && T1) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T2) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T3) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end |
end |
|
if (~use_ixiy && pla[58]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; end |
if (M2 && T3) begin fMRead=1; nextM=1; setM1=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T2) begin fMRead=1; end |
if (M4 && T3) begin fMRead=1; nextM=1; setM1=1; end |
end |
|
if (use_ixiy && pla[59]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; end |
if (M3 && T1) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T2) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T3) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T5) begin nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end |
end |
|
if (~use_ixiy && pla[59]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mWrite=1; |
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M2 && T1) begin fMWrite=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMWrite=1; end |
if (M2 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
if (M4 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M4 && T2) begin fMWrite=1; end |
if (M4 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (pla[40]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T3) begin fMRead=1; ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T5) begin nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end |
end |
|
if (pla[50] && !pla[40]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; end |
if (M3 && T1) begin fMWrite=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMWrite=1; end |
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
if (M4 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T2) begin fMWrite=1; end |
if (M4 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (pla[8] && pla[13]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mWrite=1; |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M2 && T1) begin fMWrite=1; |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMWrite=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (pla[8] && !pla[13]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; setM1=1; end |
end |
|
if (pla[38] && pla[13]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M4 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M4 && T2) begin fMWrite=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (pla[38] && !pla[13]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin fMRead=1; nextM=1; setM1=1; end |
end |
|
if (pla[83]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_IFF2; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; |
ctl_reg_sel_ir=1; ctl_reg_sys_hilo={!op3,op3}; ctl_sw_4u=1; /* Read either I or R based on op3 (0 or 1) */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T5) begin nextM=1; setM1=1; end |
end |
|
if (pla[57]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; |
ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo={!op3,op3}; ctl_sw_4d=1; /* Write either I or R based on op3 (0 or 1) */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2u=1; |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_op1_oe=1; /* OP1 latch */ end |
if (M1 && T5) begin nextM=1; setM1=1; end |
end |
|
// 16-bit Load Group |
if (pla[7]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1; end |
end |
|
if (pla[30] && pla[13]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M4 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M4 && T2) begin fMWrite=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M5 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M5 && T2) begin fMWrite=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (pla[30] && !pla[13]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M5 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M5 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M5 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
end |
|
if (pla[31] && pla[33]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M4 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M4 && T2) begin fMWrite=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M5 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M5 && T2) begin fMWrite=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (pla[31] && !pla[33]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M5 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M5 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M5 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
end |
|
if (pla[5]) begin |
if (M1 && T4) begin validPLA=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M1 && T5) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M1 && T6) begin nextM=1; setM1=1; end |
end |
|
if (pla[23] && pla[16]) begin |
if (M1 && T4) begin validPLA=1; end |
if (M1 && T5) begin nextM=1; ctl_mWrite=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T1) begin fMWrite=1; |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_apin_mux=1; /* Apin sourced from incrementer */ |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M2 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T1) begin fMWrite=1; |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_apin_mux=1; /* Apin sourced from incrementer */ |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M3 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (pla[23] && !pla[16]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
end |
|
// Exchange, Block Transfer and Search Groups |
if (pla[2]) begin |
if (M1 && T2) begin |
ctl_reg_ex_de_hl=1; /* EX DE,HL */ end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; end |
end |
|
if (pla[39]) begin |
if (M1 && T2) begin |
ctl_reg_ex_af=1; /* EX AF,AF' */ end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; end |
end |
|
if (pla[1]) begin |
if (M1 && T2) begin |
ctl_reg_exx=1; /* EXX */ end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; end |
end |
|
if (pla[10]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T4) begin nextM=1; ctl_mWrite=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T1) begin fMWrite=1; |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_apin_mux=1; /* Apin sourced from incrementer */ |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M4 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M5 && T1) begin fMWrite=1; |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_apin_mux=1; /* Apin sourced from incrementer */ |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M5 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M5 && T3) begin fMWrite=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M5 && T4) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M5 && T5) begin nextM=1; setM1=1; end |
end |
|
if (pla[0]) begin |
begin nonRep=1; /* Non-repeating block instruction */ end |
end |
|
if (pla[12]) begin |
if (M1 && T1) begin |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_use_cf2=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end |
if (M3 && T1) begin fMWrite=1; |
ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit DE, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_use_cf2=1; end |
if (M3 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMWrite=1; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T4) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_repeat_we=1; /* Update repeating flag latch with BC=1 status */ end |
if (M3 && T5) begin nextM=1; setM1=nonRep | !repeat_en; end |
if (M4 && T1) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T2) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T4) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T5) begin nextM=1; setM1=1; end |
end |
|
if (pla[11]) begin |
if (M1 && T1) begin |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_op1_sel_zero=1; /* Zero */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP; |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; |
ctl_flags_use_cf2=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_hf_cpl=flags_nf; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end |
if (M3 && T1) begin |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_use_cf2=1; end |
if (M3 && T3) begin |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T4) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_repeat_we=1; /* Update repeating flag latch with BC=1 status */ end |
if (M3 && T5) begin nextM=1; setM1=nonRep | !repeat_en | flags_zf; end |
if (M4 && T1) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T2) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T4) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T5) begin nextM=1; setM1=1; end |
end |
|
// 8-bit Arithmetic and Logic Group |
if (pla[65] && !pla[52]) begin |
if (M1 && T1) begin /* Which register to be written is decided elsewhere */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_sz_we=1; |
ctl_flags_cf_we=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; end |
end |
|
if (pla[64]) begin |
if (M1 && T1) begin /* Which register to be written is decided elsewhere */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_sz_we=1; |
ctl_flags_cf_we=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; |
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; end |
end |
|
if (use_ixiy && pla[52]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; end |
if (M3 && T1) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T2) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T3) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end |
end |
|
if (!use_ixiy && pla[52]) begin |
if (M1 && T1) begin /* Which register to be written is decided elsewhere */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_sz_we=1; |
ctl_flags_cf_we=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T2) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M4 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; end |
end |
|
if (pla[66] && !pla[53]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; |
ctl_flags_use_cf2=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_hf_cpl=flags_nf; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
if (op4 & op5 & !op3) ctl_bus_zero_oe=1; /* Trying to read flags? Put 0 on the bus instead. */ |
else begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; end /* Read 8-bit GP register */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_zero=1; /* Zero */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf_set=1; /* Set CF going into the ALU core */ |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end |
end |
|
if (pla[75]) begin |
if (M1 && T1) begin |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ |
ctl_alu_sel_op2_neg=1; end |
if (M1 && T4) begin |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ |
ctl_alu_sel_op2_neg=1; end |
end |
|
if ((M2 || M4) && pla[75]) begin |
begin |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ |
ctl_alu_sel_op2_neg=1; end |
end |
|
if (use_ixiy && pla[53]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; end |
if (M3 && T1) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T2) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T3) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end |
end |
|
if (!use_ixiy && pla[53]) begin |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_hf_cpl=flags_nf; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; end |
if (M2 && T3) begin fMRead=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_zero=1; /* Zero */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf_set=1; /* Set CF going into the ALU core */ |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end |
if (M2 && T4) begin nextM=1; ctl_mWrite=1; |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; |
ctl_flags_use_cf2=1; end |
if (M3 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T2) begin fMWrite=1; end |
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T2) begin fMRead=1; end |
if (M4 && T3) begin fMRead=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_zero=1; /* Zero */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf_set=1; /* Set CF going into the ALU core */ |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end |
if (M4 && T4) begin nextM=1; ctl_mWrite=1; |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; |
ctl_flags_use_cf2=1; end |
if (M5 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M5 && T2) begin fMWrite=1; end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
// 16-bit Arithmetic Group |
if (pla[69]) begin |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ end |
if (M2 && T1) begin |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M2 && T2) begin |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_xy_we=1; |
ctl_flags_cf_we=1; end |
if (M2 && T3) begin |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ end |
if (M2 && T4) begin nextM=1; |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M3 && T1) begin |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_xy_we=1; |
ctl_flags_cf_we=1; end |
if (M3 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin nextM=1; setM1=1; end |
end |
|
if (op3 && pla[68]) begin |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ end |
if (M2 && T1) begin |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M2 && T2) begin |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_cf_we=1; end |
if (M2 && T3) begin |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ end |
if (M2 && T4) begin nextM=1; |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M3 && T1) begin |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; |
ctl_flags_cf_we=1; |
ctl_alu_zero_16bit=1; /* 16-bit arithmetic operation uses ZF calculated over 2 bytes */ end |
if (M3 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin nextM=1; setM1=1; end |
end |
|
if (!op3 && pla[68]) begin |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ end |
if (M2 && T1) begin |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M2 && T2) begin |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_cf_we=1; end |
if (M2 && T3) begin |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ end |
if (M2 && T4) begin nextM=1; |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M3 && T1) begin |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; |
ctl_flags_cf_we=1; |
ctl_alu_zero_16bit=1; /* 16-bit arithmetic operation uses ZF calculated over 2 bytes */ end |
if (M3 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin nextM=1; setM1=1; end |
end |
|
if (pla[9]) begin |
if (M1 && T4) begin validPLA=1; |
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M1 && T5) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit general purpose register, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end |
if (M1 && T6) begin nextM=1; setM1=1; end |
end |
|
// General Purpose Arithmetic and CPU Control Groups |
if (pla[77]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; |
ctl_flags_cf_we=1; |
ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=!flags_nf; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_use_cf2=1; |
ctl_flags_hf_cpl=flags_nf; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf2_we=1; /* Write HF2 flag (DAA only) */ |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=2; |
ctl_daa_oe=1; /* Write DAA correction factor to the bus */ |
ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=!flags_nf; end |
end |
|
if (pla[81]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_xy_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; |
ctl_alu_sel_op2_neg=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_hf_cpl=flags_nf; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_op1_sel_zero=1; /* Zero */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; |
ctl_alu_sel_op2_neg=1; end |
end |
|
if (pla[82]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; |
ctl_flags_cf_we=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_op1_sel_zero=1; /* Zero */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; |
ctl_flags_cf_we=1; end |
end |
|
if (pla[89]) begin |
if (M1 && T1) begin |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_xy_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_cf_we=1; ctl_flags_cf_cpl=1; /* CCF */ |
ctl_flags_hf_cpl=!flags_cf; /* Used for CCF */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
end |
|
if (pla[92]) begin |
if (M1 && T1) begin |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_xy_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_cf_set=1; /* Set CF going into the ALU core */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
end |
|
if (pla[95]) begin |
if (M1 && T3) begin |
ctl_state_halt_set=1; /* Enter HALT state */ end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; end |
end |
|
if (pla[97]) begin |
if (M1 && T3) begin |
ctl_iffx_bit=op3; ctl_iffx_we=1; /* DI/EI */ end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end |
end |
|
if (pla[96]) begin |
if (M1 && T3) begin |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_im_we=1; /* IM n ('n' is read by opcode[4:3]) */ end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; end |
end |
|
// Rotate and Shift Group |
if (pla[25]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf_we=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_use_cf2=1; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end |
end |
|
if (~use_ixiy && pla[70] && !pla[55]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf_we=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_use_cf2=1; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_ir_we=1; end |
if (M4 && T2) begin fMRead=1; end |
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end |
if (M5 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf_we=1; end |
if (M5 && T2) begin fMWrite=1; end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (~use_ixiy && pla[70] && pla[55]) begin |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ |
ctl_flags_use_cf2=1; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; end |
if (M2 && T3) begin fMRead=1; end |
if (M2 && T4) begin nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end |
if (M3 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf_we=1; end |
if (M3 && T2) begin fMWrite=1; end |
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_ir_we=1; end |
if (M4 && T2) begin fMRead=1; end |
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end |
if (M5 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; |
ctl_flags_cf_we=1; end |
if (M5 && T2) begin fMWrite=1; end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (pla[15] && op3) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; end |
if (M3 && T1) begin |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_lq=1; /* Cross-bus wire (see schematic) */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ end |
if (M3 && T4) begin nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_low=1; /* Write low nibble with a high nibble */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ end |
if (M4 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_op2_oe=1; /* OP2 latch */ end |
if (M4 && T2) begin fMWrite=1; |
ctl_alu_op1_oe=1; /* OP1 latch */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ end |
if (M4 && T3) begin fMWrite=1; nextM=1; setM1=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
end |
|
if (pla[15] && !op3) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; end |
if (M3 && T1) begin |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_lq=1; /* Cross-bus wire (see schematic) */ |
ctl_alu_op1_sel_low=1; /* Write low nibble with a high nibble */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ end |
if (M3 && T2) begin |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_op2_oe=1; /* OP2 latch */ end |
if (M3 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_lq=1; /* Cross-bus wire (see schematic) */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ end |
if (M3 && T4) begin nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_low=1; /* Write low nibble with a high nibble */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ end |
if (M4 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_op2_oe=1; /* OP2 latch */ end |
if (M4 && T2) begin fMWrite=1; |
ctl_alu_op1_oe=1; /* OP1 latch */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ end |
if (M4 && T3) begin fMWrite=1; nextM=1; setM1=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
end |
|
// Bit Manipulation Group |
if (~use_ixiy && pla[72] && !pla[55]) begin |
if (M1 && T1) begin |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; |
ctl_flags_sz_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_ir_we=1; end |
if (M4 && T2) begin fMRead=1; end |
if (M4 && T3) begin fMRead=1; end |
if (M4 && T4) begin nextM=1; setM1=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; |
ctl_flags_sz_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
end |
|
if (~use_ixiy && pla[72] && pla[55]) begin |
if (M1 && T1) begin |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; |
ctl_flags_sz_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; end |
if (M2 && T3) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_flags_xy_we=1; end |
if (M2 && T4) begin nextM=1; setM1=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; |
ctl_flags_sz_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_ir_we=1; end |
if (M4 && T2) begin fMRead=1; end |
if (M4 && T3) begin fMRead=1; end |
if (M4 && T4) begin nextM=1; setM1=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; |
ctl_flags_sz_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
end |
|
if (~use_ixiy && pla[74] && !pla[55]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2u=1; |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_ir_we=1; end |
if (M4 && T2) begin fMRead=1; end |
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M5 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M5 && T2) begin fMWrite=1; end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (~use_ixiy && pla[74] && pla[55]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; end |
if (M2 && T3) begin fMRead=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M2 && T4) begin nextM=1; ctl_mWrite=1; |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M3 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T2) begin fMWrite=1; end |
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_ir_we=1; end |
if (M4 && T2) begin fMRead=1; end |
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M5 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M5 && T2) begin fMWrite=1; end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (~use_ixiy && pla[73] && !pla[55]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2u=1; |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_ir_we=1; end |
if (M4 && T2) begin fMRead=1; end |
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end |
if (M5 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end |
if (M5 && T2) begin fMWrite=1; end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
if (~use_ixiy && pla[73] && pla[55]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; end |
if (M2 && T3) begin fMRead=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end |
if (M2 && T4) begin nextM=1; ctl_mWrite=1; |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end |
if (M3 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T2) begin fMWrite=1; end |
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_ir_we=1; end |
if (M4 && T2) begin fMRead=1; end |
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end |
if (M5 && T1) begin fMWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end |
if (M5 && T2) begin fMWrite=1; end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end |
end |
|
// Input and Output Groups |
if (pla[37] && !pla[28]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_iorw=1; end |
if (M3 && T1) begin fIORead=1; |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; ctl_sw_4d=1; /* Read 8-bit general purpose A register, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ /* Which register to be written is decided elsewhere */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T2) begin fIORead=1; end |
if (M3 && T3) begin fIORead=1; end |
if (M3 && T4) begin fIORead=1; nextM=1; setM1=1; end |
end |
|
if (pla[27] && !pla[34]) begin |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */ |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_iorw=1; end |
if (M2 && T1) begin fIORead=1; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fIORead=1; end |
if (M2 && T3) begin fIORead=1; end |
if (M2 && T4) begin fIORead=1; nextM=1; setM1=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
end |
|
if (pla[37] && pla[28]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_iorw=1; |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; ctl_sw_4d=1; /* Read 8-bit general purpose A register, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fIOWrite=1; |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M3 && T2) begin fIOWrite=1; end |
if (M3 && T3) begin fIOWrite=1; end |
if (M3 && T4) begin fIOWrite=1; nextM=1; setM1=1; end |
end |
|
if (pla[27] && pla[34]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_iorw=1; |
if (op4 & op5 & !op3) ctl_bus_zero_oe=1; /* Trying to read flags? Put 0 on the bus instead. */ |
else begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; end /* Read 8-bit GP register */ |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M2 && T1) begin fIOWrite=1; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fIOWrite=1; end |
if (M2 && T3) begin fIOWrite=1; end |
if (M2 && T4) begin fIOWrite=1; nextM=1; setM1=1; end |
end |
|
if (pla[91] && pla[21]) begin |
if (M1 && T1) begin |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; end |
if (M1 && T5) begin nextM=1; ctl_iorw=1; end |
if (M2 && T1) begin fIORead=1; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fIORead=1; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_zero=1; /* Zero */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_alu_sel_op2_neg=1; end |
if (M2 && T3) begin fIORead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_cf_we=1; |
ctl_alu_sel_op2_neg=1; end |
if (M2 && T4) begin fIORead=1; nextM=1; ctl_mWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_nf_we=1; /* Sign bit, to be used with FLAGT source set to "alu" */ |
ctl_alu_sel_op2_neg=1; end |
if (M3 && T1) begin fMWrite=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=nonRep | !repeat_en | flags_zf; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M4 && T1) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T2) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T4) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T5) begin nextM=1; setM1=1; end |
end |
|
if (pla[91] && pla[20]) begin |
if (M1 && T1) begin |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end |
if (M1 && T2) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_zero=1; /* Zero */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_alu_sel_op2_neg=1; end |
if (M1 && T5) begin nextM=1; ctl_mRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_alu_sel_op2_neg=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_iorw=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ end |
if (M3 && T1) begin fIOWrite=1; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fIOWrite=1; |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_flags_nf_we=1; /* Sign bit, to be used with FLAGT source set to "alu" */ end |
if (M3 && T3) begin fIOWrite=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_cf_we=1; end |
if (M3 && T4) begin fIOWrite=1; nextM=1; setM1=nonRep | !repeat_en | flags_zf; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M4 && T1) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T2) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T4) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T5) begin nextM=1; setM1=1; end |
end |
|
// Jump Group |
if (pla[29]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
if (pla[43]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1; |
if (flags_cond_true) begin /* If cc is true, use WZ instead of PC (for jumps) */ |
ctl_reg_not_pc=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; |
end |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo[1]=1; /* Conditionally selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
end |
|
if (pla[47]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; end |
if (M3 && T1) begin |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; end |
if (M3 && T2) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; end |
if (M3 && T3) begin |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_cf_we=1; end |
if (M3 && T4) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_zero=1; /* Zero */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_alu_sel_op2_neg=flags_sf; end |
if (M3 && T5) begin nextM=1; setM1=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_alu_sel_op2_neg=flags_sf; |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
if (pla[48]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; |
ctl_cond_short=1; /* M1/T3 only: force a short flags condition (SS) */ end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; setM1=!flags_cond_true; end |
if (M3 && T1) begin |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; end |
if (M3 && T2) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; end |
if (M3 && T3) begin |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_cf_we=1; end |
if (M3 && T4) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_zero=1; /* Zero */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_alu_sel_op2_neg=flags_sf; end |
if (M3 && T5) begin nextM=1; setM1=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_alu_sel_op2_neg=flags_sf; |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
if (pla[6]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
if (pla[26]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_zero=1; /* Zero */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_alu_sel_op2_neg=1; end |
if (M1 && T5) begin nextM=1; ctl_mRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_sz_we=1; |
ctl_alu_sel_op2_neg=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; setM1=flags_zf; /* Used in DJNZ */ end |
if (M3 && T1) begin |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; end |
if (M3 && T2) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; end |
if (M3 && T3) begin |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_cf_we=1; end |
if (M3 && T4) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_zero=1; /* Zero */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_alu_sel_op2_neg=flags_sf; end |
if (M3 && T5) begin nextM=1; setM1=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_alu_sel_op2_neg=flags_sf; |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
// Call and Return Group |
if (pla[24]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T4) begin nextM=1; ctl_mWrite=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T1) begin fMWrite=1; |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_apin_mux=1; /* Apin sourced from incrementer */ |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M4 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M5 && T1) begin fMWrite=1; |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_apin_mux=1; /* Apin sourced from incrementer */ |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M5 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
if (pla[42]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=!flags_cond_true; setM1=!flags_cond_true; |
ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo[1]=1; /* Conditionally selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T4) begin nextM=1; ctl_mWrite=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T1) begin fMWrite=1; |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_apin_mux=1; /* Apin sourced from incrementer */ |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M4 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M5 && T1) begin fMWrite=1; |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_apin_mux=1; /* Apin sourced from incrementer */ |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M5 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
if (pla[35]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
if (pla[45]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; end |
if (M1 && T4) begin validPLA=1; end |
if (M1 && T5) begin nextM=1; ctl_mRead=1; setM1=!flags_cond_true; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
if (pla[46]) begin |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; |
ctl_iff1_iff2=1; /* RETN copies IFF2 into IFF1 */ end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
if (pla[56]) begin |
if (M1 && T3) begin |
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_op1_oe=1; /* OP1 latch */ |
ctl_alu_op1_sel_zero=1; /* Zero */ |
ctl_sw_mask543_en=!((in_intr & im2) | in_nmi); |
ctl_sw_1d=!in_nmi; ctl_66_oe=in_nmi; |
ctl_bus_ff_oe=in_intr & im1; end |
if (M1 && T4) begin validPLA=1; end |
if (M1 && T5) begin nextM=1; ctl_mWrite=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ end |
if (M2 && T1) begin fMWrite=1; |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_apin_mux=1; /* Apin sourced from incrementer */ |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1; |
ctl_reg_out_hi=1; /* From the register file into the ALU high byte only */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M2 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1; |
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M3 && T1) begin fMWrite=1; |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_apin_mux=1; /* Apin sourced from incrementer */ |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1; |
ctl_reg_out_lo=1; /* From the register file into the ALU low byte only */ |
ctl_sw_2u=1; |
ctl_sw_1u=1; |
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end |
if (M3 && T2) begin fMWrite=1; |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMWrite=1; nextM=1; ctl_mRead=in_intr & im2; /* RST38 interrupt extension */ setM1=!(in_intr & im2); /* RST38 interrupt extension */ |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
// INTR IM2 continues here... |
if (M4 && T1) begin fMRead=1; |
ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4d=1; /* Select 8-bit I register */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2u=1; |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_op1_oe=1; /* OP1 latch */ end |
if (M4 && T2) begin fMRead=1; |
ctl_sw_4u=1; |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ |
ctl_reg_out_lo=1; /* From the register file into the ALU low byte only */ |
ctl_sw_2d=1; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ end |
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end |
if (M5 && T1) begin fMRead=1; |
ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4d=1; /* Select 8-bit I register */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2u=1; |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_op1_oe=1; /* OP1 latch */ end |
if (M5 && T2) begin fMRead=1; |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M5 && T3) begin fMRead=1; nextM=1; setM1=1; |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end |
end |
|
// CB-Table opcodes |
if (pla[49]) begin |
if (M1 && T3) begin |
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_bus=1; /* Load FLAGT from the data bus */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; |
ctl_flags_xy_we=1; |
ctl_flags_hf_we=1; |
ctl_flags_pf_we=1; |
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */ |
ctl_flags_cf_we=1; |
ctl_state_tbl_cb_set=1; setCBED=1; /* CB-table prefix */ end |
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end |
if (M2 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M2 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; end |
if (M3 && T1) begin fMRead=1; |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T2) begin fMRead=1; |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T3) begin fMRead=1; ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end |
if (M3 && T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end |
if (M4 && T1) begin |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_alu_bs_oe=1; /* Bit-selector unit */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_ir_we=1; end |
// Loading a new instruction immediately changes PLA wires and continues into the new effective instructions' M4/T1 cycle |
end |
|
// Special Purposes PLA Entries |
if (pla[3]) begin |
if (M1 && T2) begin |
ctl_state_ixiy_we=1; ctl_state_iy_set=op5; setIXIY=1; /* IX/IY prefix */ end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end |
end |
|
if (pla[44]) begin |
if (M1 && T2) begin |
ctl_state_tbl_cb_set=1; setCBED=1; /* CB-table prefix */ end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end |
end |
|
if (pla[51]) begin |
if (M1 && T2) begin |
ctl_state_tbl_ed_set=1; setCBED=1; /* ED-table prefix */ end |
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; |
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end |
end |
|
if (pla[76]) begin |
begin |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; end |
if (M1 && T1) begin |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end |
end |
|
if (pla[78]) begin |
begin |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; end |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end |
end |
|
if (pla[79]) begin |
begin |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_nf_we=1; ctl_flags_nf_set=1; end |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end |
end |
|
if (pla[80]) begin |
begin |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end |
end |
|
if (pla[84]) begin |
begin |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end |
end |
|
if (pla[85]) begin |
begin |
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end |
if (M1 && T2) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ end |
end |
|
if (pla[86]) begin |
begin |
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end |
if (M1 && T2) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ end |
end |
|
if (pla[88]) begin |
begin |
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end |
if (M1 && T1) begin |
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; |
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */ |
ctl_flags_xy_we=1; |
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end |
if (M1 && T2) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ end |
end |
|
// State machine to compute (IX+d) |
if (ixy_d) begin |
if (T1) begin |
ctl_sw_2d=1; |
ctl_sw_1d=1; |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_bus=1; /* Internal bus */ |
ctl_flags_sz_we=1; end |
if (T2) begin |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_sw_2d=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (ctl_alu_op_low) begin |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; |
end else begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; end |
if (T3) begin |
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */ |
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */ |
ctl_sw_2u=1; |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end |
if (T4) begin |
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op2_sel_zero=1; /* Zero */ |
ctl_alu_op1_sel_bus=1; /* Internal bus */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_hf_we=1; |
ctl_flags_use_cf2=1; |
ctl_alu_sel_op2_neg=flags_sf; end |
if (T5) begin |
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */ |
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */ |
ctl_flags_alu=1; /* Load FLAGT from the ALU */ |
ctl_alu_oe=1; /* Enable ALU onto the data bus */ |
ctl_alu_res_oe=1; /* Result latch */ |
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ |
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; |
if (!ctl_alu_op_low) begin |
ctl_alu_core_hf=1; |
end |
ctl_flags_xy_we=1; |
ctl_alu_sel_op2_neg=flags_sf; |
ctl_state_ixiy_we=1; ctl_state_ixiy_clr=!setIXIY; /* Clear IX/IY flag */ end |
end |
|
// Default instruction fetch (M1) state machine |
if (M1) begin |
if (M1 && T1) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; ctl_apin_mux2=1; /* Apin sourced from AL */ end |
if (M1 && T2) begin |
ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit IR */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ |
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ |
ctl_state_ixiy_we=1; ctl_state_ixiy_clr=!setIXIY; /* Clear IX/IY flag */ |
ctl_state_tbl_clr=!setCBED; /* Clear CB/ED prefix */ |
ctl_ir_we=1; |
ctl_bus_zero_oe=in_halt; ctl_bus_ff_oe=(in_intr & (im1 | im2)) | in_nmi; end |
if (M1 && T3) begin |
ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; /* Write 16-bit IR */ |
ctl_inc_cy=pc_inc; /* Increment */ |
ctl_bus_inc_oe=1; ctl_apin_mux2=1; /* Apin sourced from AL */ |
ctl_inc_limit6=1; /* Limit the incrementer to 6 bits */ end |
if (M1 && T4) begin |
ctl_eval_cond=1; /* Evaluate flags condition based on the opcode[5:3] */ end |
end |
|
/trunk/cpu/deploy/alu_control.v
0,0 → 1,250
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Tue Oct 21 20:41:52 2014" |
|
module alu_control( |
alu_shift_db0, |
alu_shift_db7, |
ctl_shift_en, |
alu_low_gt_9, |
alu_high_gt_9, |
alu_high_eq_9, |
ctl_daa_oe, |
ctl_alu_op_low, |
alu_parity_out, |
flags_cf, |
flags_zf, |
flags_pf, |
flags_sf, |
ctl_cond_short, |
alu_vf_out, |
iff2, |
ctl_alu_core_hf, |
ctl_eval_cond, |
repeat_en, |
flags_cf_latch, |
flags_hf2, |
flags_hf, |
ctl_66_oe, |
clk, |
ctl_pf_sel, |
op543, |
alu_shift_in, |
alu_shift_right, |
alu_shift_left, |
shift_cf_out, |
alu_parity_in, |
flags_cond_true, |
daa_cf_out, |
pf_sel, |
alu_op_low, |
alu_core_cf_in, |
db |
); |
|
|
input wire alu_shift_db0; |
input wire alu_shift_db7; |
input wire ctl_shift_en; |
input wire alu_low_gt_9; |
input wire alu_high_gt_9; |
input wire alu_high_eq_9; |
input wire ctl_daa_oe; |
input wire ctl_alu_op_low; |
input wire alu_parity_out; |
input wire flags_cf; |
input wire flags_zf; |
input wire flags_pf; |
input wire flags_sf; |
input wire ctl_cond_short; |
input wire alu_vf_out; |
input wire iff2; |
input wire ctl_alu_core_hf; |
input wire ctl_eval_cond; |
input wire repeat_en; |
input wire flags_cf_latch; |
input wire flags_hf2; |
input wire flags_hf; |
input wire ctl_66_oe; |
input wire clk; |
input wire [1:0] ctl_pf_sel; |
input wire [2:0] op543; |
output wire alu_shift_in; |
output wire alu_shift_right; |
output wire alu_shift_left; |
output wire shift_cf_out; |
output wire alu_parity_in; |
output reg flags_cond_true; |
output wire daa_cf_out; |
output wire pf_sel; |
output wire alu_op_low; |
output wire alu_core_cf_in; |
output wire [7:0] db; |
|
wire condition; |
wire [7:0] out; |
wire [1:0] sel; |
wire SYNTHESIZED_WIRE_0; |
wire SYNTHESIZED_WIRE_1; |
wire SYNTHESIZED_WIRE_2; |
reg DFFE_latch_pf_tmp; |
wire SYNTHESIZED_WIRE_20; |
wire SYNTHESIZED_WIRE_21; |
wire SYNTHESIZED_WIRE_7; |
wire SYNTHESIZED_WIRE_8; |
wire SYNTHESIZED_WIRE_9; |
wire SYNTHESIZED_WIRE_10; |
wire SYNTHESIZED_WIRE_11; |
wire SYNTHESIZED_WIRE_12; |
wire SYNTHESIZED_WIRE_13; |
wire SYNTHESIZED_WIRE_14; |
wire SYNTHESIZED_WIRE_15; |
wire SYNTHESIZED_WIRE_16; |
wire SYNTHESIZED_WIRE_22; |
wire SYNTHESIZED_WIRE_18; |
|
assign alu_op_low = ctl_alu_op_low; |
assign daa_cf_out = SYNTHESIZED_WIRE_21; |
assign SYNTHESIZED_WIRE_22 = 0; |
assign SYNTHESIZED_WIRE_18 = 1; |
|
|
|
assign condition = SYNTHESIZED_WIRE_0 ^ SYNTHESIZED_WIRE_1; |
|
|
|
assign db[7] = SYNTHESIZED_WIRE_2 ? out[7] : 1'bz; |
assign db[6] = SYNTHESIZED_WIRE_2 ? out[6] : 1'bz; |
assign db[5] = SYNTHESIZED_WIRE_2 ? out[5] : 1'bz; |
assign db[4] = SYNTHESIZED_WIRE_2 ? out[4] : 1'bz; |
assign db[3] = SYNTHESIZED_WIRE_2 ? out[3] : 1'bz; |
assign db[2] = SYNTHESIZED_WIRE_2 ? out[2] : 1'bz; |
assign db[1] = SYNTHESIZED_WIRE_2 ? out[1] : 1'bz; |
assign db[0] = SYNTHESIZED_WIRE_2 ? out[0] : 1'bz; |
|
assign alu_shift_right = ctl_shift_en & op543[0]; |
|
assign alu_parity_in = ctl_alu_op_low | DFFE_latch_pf_tmp; |
|
assign SYNTHESIZED_WIRE_2 = ctl_66_oe | ctl_daa_oe; |
|
assign sel[0] = op543[1]; |
|
|
assign out[1] = SYNTHESIZED_WIRE_20; |
|
|
assign out[2] = SYNTHESIZED_WIRE_20; |
|
|
assign out[5] = SYNTHESIZED_WIRE_21; |
|
|
assign out[6] = SYNTHESIZED_WIRE_21; |
|
|
assign alu_shift_left = ctl_shift_en & SYNTHESIZED_WIRE_7; |
|
assign SYNTHESIZED_WIRE_21 = ctl_66_oe | alu_high_gt_9 | flags_cf_latch | SYNTHESIZED_WIRE_8; |
|
assign SYNTHESIZED_WIRE_9 = flags_hf2 | alu_low_gt_9; |
|
assign SYNTHESIZED_WIRE_8 = alu_low_gt_9 & alu_high_eq_9; |
|
assign SYNTHESIZED_WIRE_20 = SYNTHESIZED_WIRE_9 | ctl_66_oe; |
|
assign SYNTHESIZED_WIRE_0 = ~op543[0]; |
|
assign sel[1] = op543[2] & SYNTHESIZED_WIRE_10; |
|
assign SYNTHESIZED_WIRE_12 = alu_shift_db0 & op543[0]; |
|
assign SYNTHESIZED_WIRE_13 = alu_shift_db7 & SYNTHESIZED_WIRE_11; |
|
assign shift_cf_out = SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13; |
|
assign SYNTHESIZED_WIRE_16 = ctl_alu_core_hf & flags_hf; |
|
assign SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_14 & flags_cf; |
|
assign alu_core_cf_in = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16; |
|
assign SYNTHESIZED_WIRE_14 = ~ctl_alu_core_hf; |
|
|
always@(posedge clk) |
begin |
if (ctl_eval_cond) |
begin |
flags_cond_true <= condition; |
end |
end |
|
|
alu_mux_4 b2v_inst_cond_mux( |
.in0(flags_zf), |
.in1(flags_cf), |
.in2(flags_pf), |
.in3(flags_sf), |
.sel(sel), |
.out(SYNTHESIZED_WIRE_1)); |
|
|
alu_mux_4 b2v_inst_pf_sel( |
.in0(alu_parity_out), |
.in1(alu_vf_out), |
.in2(iff2), |
.in3(repeat_en), |
.sel(ctl_pf_sel), |
.out(pf_sel)); |
|
|
alu_mux_8 b2v_inst_shift_mux( |
.in0(alu_shift_db7), |
.in1(alu_shift_db0), |
.in2(flags_cf_latch), |
.in3(flags_cf_latch), |
.in4(SYNTHESIZED_WIRE_22), |
.in5(alu_shift_db7), |
.in6(SYNTHESIZED_WIRE_18), |
.in7(SYNTHESIZED_WIRE_22), |
.sel(op543), |
.out(alu_shift_in)); |
|
|
always@(posedge clk) |
begin |
if (ctl_alu_op_low) |
begin |
DFFE_latch_pf_tmp <= alu_parity_out; |
end |
end |
|
assign SYNTHESIZED_WIRE_7 = ~op543[0]; |
|
assign SYNTHESIZED_WIRE_11 = ~op543[0]; |
|
assign SYNTHESIZED_WIRE_10 = ~ctl_cond_short; |
|
|
assign out[3] = 0; |
assign out[7] = 0; |
assign out[0] = 0; |
assign out[4] = 0; |
|
endmodule |
/trunk/cpu/deploy/alu.v
0,0 → 1,384
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Fri Nov 07 19:44:45 2014" |
|
module alu( |
alu_core_R, |
alu_core_V, |
alu_core_S, |
alu_bs_oe, |
alu_parity_in, |
alu_oe, |
alu_shift_oe, |
alu_core_cf_in, |
alu_op2_oe, |
alu_op1_oe, |
alu_res_oe, |
alu_op1_sel_low, |
alu_op1_sel_zero, |
alu_op1_sel_bus, |
alu_op2_sel_zero, |
alu_op2_sel_bus, |
alu_op2_sel_lq, |
alu_op_low, |
alu_shift_in, |
alu_sel_op2_neg, |
alu_sel_op2_high, |
alu_shift_left, |
alu_shift_right, |
clk, |
bsel, |
alu_zero, |
alu_parity_out, |
alu_high_eq_9, |
alu_high_gt_9, |
alu_low_gt_9, |
alu_shift_db0, |
alu_shift_db7, |
alu_core_cf_out, |
alu_sf_out, |
alu_yf_out, |
alu_xf_out, |
alu_vf_out, |
db, |
test_db_high, |
test_db_low |
); |
|
|
input wire alu_core_R; |
input wire alu_core_V; |
input wire alu_core_S; |
input wire alu_bs_oe; |
input wire alu_parity_in; |
input wire alu_oe; |
input wire alu_shift_oe; |
input wire alu_core_cf_in; |
input wire alu_op2_oe; |
input wire alu_op1_oe; |
input wire alu_res_oe; |
input wire alu_op1_sel_low; |
input wire alu_op1_sel_zero; |
input wire alu_op1_sel_bus; |
input wire alu_op2_sel_zero; |
input wire alu_op2_sel_bus; |
input wire alu_op2_sel_lq; |
input wire alu_op_low; |
input wire alu_shift_in; |
input wire alu_sel_op2_neg; |
input wire alu_sel_op2_high; |
input wire alu_shift_left; |
input wire alu_shift_right; |
input wire clk; |
input wire [2:0] bsel; |
output wire alu_zero; |
output wire alu_parity_out; |
output wire alu_high_eq_9; |
output wire alu_high_gt_9; |
output wire alu_low_gt_9; |
output wire alu_shift_db0; |
output wire alu_shift_db7; |
output wire alu_core_cf_out; |
output wire alu_sf_out; |
output wire alu_yf_out; |
output wire alu_xf_out; |
output wire alu_vf_out; |
inout wire [7:0] db; |
output wire [3:0] test_db_high; |
output wire [3:0] test_db_low; |
|
wire [3:0] alu_op1; |
wire [3:0] alu_op2; |
wire [3:0] db_high; |
wire [3:0] db_low; |
reg [3:0] op1_high; |
reg [3:0] op1_low; |
reg [3:0] op2_high; |
reg [3:0] op2_low; |
wire [3:0] result_hi; |
reg [3:0] result_lo; |
wire [3:0] SYNTHESIZED_WIRE_0; |
wire [3:0] SYNTHESIZED_WIRE_1; |
wire [3:0] SYNTHESIZED_WIRE_2; |
wire [3:0] SYNTHESIZED_WIRE_3; |
wire SYNTHESIZED_WIRE_35; |
wire [3:0] SYNTHESIZED_WIRE_5; |
wire [3:0] SYNTHESIZED_WIRE_7; |
wire [3:0] SYNTHESIZED_WIRE_8; |
wire SYNTHESIZED_WIRE_9; |
wire [3:0] SYNTHESIZED_WIRE_10; |
wire [3:0] SYNTHESIZED_WIRE_11; |
wire [3:0] SYNTHESIZED_WIRE_12; |
wire [3:0] SYNTHESIZED_WIRE_13; |
wire [3:0] SYNTHESIZED_WIRE_14; |
wire [3:0] SYNTHESIZED_WIRE_15; |
wire [3:0] SYNTHESIZED_WIRE_16; |
wire SYNTHESIZED_WIRE_17; |
wire [3:0] SYNTHESIZED_WIRE_18; |
wire SYNTHESIZED_WIRE_36; |
wire SYNTHESIZED_WIRE_20; |
wire [3:0] SYNTHESIZED_WIRE_21; |
wire SYNTHESIZED_WIRE_23; |
wire [3:0] SYNTHESIZED_WIRE_24; |
wire SYNTHESIZED_WIRE_37; |
wire SYNTHESIZED_WIRE_26; |
wire [3:0] SYNTHESIZED_WIRE_27; |
wire SYNTHESIZED_WIRE_29; |
wire SYNTHESIZED_WIRE_30; |
wire SYNTHESIZED_WIRE_31; |
wire SYNTHESIZED_WIRE_32; |
wire [3:0] SYNTHESIZED_WIRE_33; |
wire [3:0] SYNTHESIZED_WIRE_34; |
|
|
|
|
assign db_low[3] = alu_bs_oe ? SYNTHESIZED_WIRE_0[3] : 1'bz; |
assign db_low[2] = alu_bs_oe ? SYNTHESIZED_WIRE_0[2] : 1'bz; |
assign db_low[1] = alu_bs_oe ? SYNTHESIZED_WIRE_0[1] : 1'bz; |
assign db_low[0] = alu_bs_oe ? SYNTHESIZED_WIRE_0[0] : 1'bz; |
|
assign db_high[3] = alu_bs_oe ? SYNTHESIZED_WIRE_1[3] : 1'bz; |
assign db_high[2] = alu_bs_oe ? SYNTHESIZED_WIRE_1[2] : 1'bz; |
assign db_high[1] = alu_bs_oe ? SYNTHESIZED_WIRE_1[1] : 1'bz; |
assign db_high[0] = alu_bs_oe ? SYNTHESIZED_WIRE_1[0] : 1'bz; |
|
|
alu_core b2v_core( |
.cy_in(alu_core_cf_in), |
.S(alu_core_S), |
.V(alu_core_V), |
.R(alu_core_R), |
.op1(alu_op1), |
.op2(alu_op2), |
.cy_out(alu_core_cf_out), |
.vf_out(alu_vf_out), |
.result(result_hi)); |
|
assign db[3] = alu_oe ? db_low[3] : 1'bz; |
assign db[2] = alu_oe ? db_low[2] : 1'bz; |
assign db[1] = alu_oe ? db_low[1] : 1'bz; |
assign db[0] = alu_oe ? db_low[0] : 1'bz; |
|
assign db[7] = alu_oe ? db_high[3] : 1'bz; |
assign db[6] = alu_oe ? db_high[2] : 1'bz; |
assign db[5] = alu_oe ? db_high[1] : 1'bz; |
assign db[4] = alu_oe ? db_high[0] : 1'bz; |
|
|
alu_bit_select b2v_input_bit_select( |
.bsel(bsel), |
.bs_out_high(SYNTHESIZED_WIRE_1), |
.bs_out_low(SYNTHESIZED_WIRE_0)); |
|
|
alu_shifter_core b2v_input_shift( |
.shift_in(alu_shift_in), |
.shift_left(alu_shift_left), |
.shift_right(alu_shift_right), |
.db(db), |
.shift_db0(alu_shift_db0), |
.shift_db7(alu_shift_db7), |
.out_high(SYNTHESIZED_WIRE_34), |
.out_low(SYNTHESIZED_WIRE_33)); |
|
|
always@(posedge clk) |
begin |
if (alu_op_low) |
begin |
result_lo[3:0] <= result_hi[3:0]; |
end |
end |
|
assign alu_op1 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3; |
|
assign SYNTHESIZED_WIRE_17 = ~alu_op_low; |
|
assign db_low[3] = alu_op2_oe ? op2_low[3] : 1'bz; |
assign db_low[2] = alu_op2_oe ? op2_low[2] : 1'bz; |
assign db_low[1] = alu_op2_oe ? op2_low[1] : 1'bz; |
assign db_low[0] = alu_op2_oe ? op2_low[0] : 1'bz; |
|
assign db_high[3] = alu_op2_oe ? op2_high[3] : 1'bz; |
assign db_high[2] = alu_op2_oe ? op2_high[2] : 1'bz; |
assign db_high[1] = alu_op2_oe ? op2_high[1] : 1'bz; |
assign db_high[0] = alu_op2_oe ? op2_high[0] : 1'bz; |
|
assign SYNTHESIZED_WIRE_5 = ~op2_low; |
|
assign SYNTHESIZED_WIRE_7 = ~op2_high; |
|
assign SYNTHESIZED_WIRE_12 = op2_low & {SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35}; |
|
assign SYNTHESIZED_WIRE_11 = {alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg} & SYNTHESIZED_WIRE_5; |
|
assign SYNTHESIZED_WIRE_14 = op2_high & {SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35}; |
|
assign SYNTHESIZED_WIRE_13 = {alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg} & SYNTHESIZED_WIRE_7; |
|
assign SYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_8 & {SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9}; |
|
assign SYNTHESIZED_WIRE_15 = {alu_sel_op2_high,alu_sel_op2_high,alu_sel_op2_high,alu_sel_op2_high} & SYNTHESIZED_WIRE_10; |
|
assign SYNTHESIZED_WIRE_8 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12; |
|
assign SYNTHESIZED_WIRE_10 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14; |
|
assign alu_op2 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16; |
|
assign SYNTHESIZED_WIRE_35 = ~alu_sel_op2_neg; |
|
assign SYNTHESIZED_WIRE_9 = ~alu_sel_op2_high; |
|
assign db_low[3] = alu_res_oe ? result_lo[3] : 1'bz; |
assign db_low[2] = alu_res_oe ? result_lo[2] : 1'bz; |
assign db_low[1] = alu_res_oe ? result_lo[1] : 1'bz; |
assign db_low[0] = alu_res_oe ? result_lo[0] : 1'bz; |
|
assign db_high[3] = alu_res_oe ? result_hi[3] : 1'bz; |
assign db_high[2] = alu_res_oe ? result_hi[2] : 1'bz; |
assign db_high[1] = alu_res_oe ? result_hi[1] : 1'bz; |
assign db_high[0] = alu_res_oe ? result_hi[0] : 1'bz; |
|
assign SYNTHESIZED_WIRE_3 = op1_low & {alu_op_low,alu_op_low,alu_op_low,alu_op_low}; |
|
assign SYNTHESIZED_WIRE_2 = {SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17} & op1_high; |
|
|
always@(posedge SYNTHESIZED_WIRE_36) |
begin |
if (SYNTHESIZED_WIRE_20) |
begin |
op1_high[3:0] <= SYNTHESIZED_WIRE_18[3:0]; |
end |
end |
|
|
always@(posedge SYNTHESIZED_WIRE_36) |
begin |
if (SYNTHESIZED_WIRE_23) |
begin |
op1_low[3:0] <= SYNTHESIZED_WIRE_21[3:0]; |
end |
end |
|
|
always@(posedge SYNTHESIZED_WIRE_37) |
begin |
if (SYNTHESIZED_WIRE_26) |
begin |
op2_high[3:0] <= SYNTHESIZED_WIRE_24[3:0]; |
end |
end |
|
|
always@(posedge SYNTHESIZED_WIRE_37) |
begin |
if (SYNTHESIZED_WIRE_29) |
begin |
op2_low[3:0] <= SYNTHESIZED_WIRE_27[3:0]; |
end |
end |
|
assign db_low[3] = alu_op1_oe ? op1_low[3] : 1'bz; |
assign db_low[2] = alu_op1_oe ? op1_low[2] : 1'bz; |
assign db_low[1] = alu_op1_oe ? op1_low[1] : 1'bz; |
assign db_low[0] = alu_op1_oe ? op1_low[0] : 1'bz; |
|
assign db_high[3] = alu_op1_oe ? op1_high[3] : 1'bz; |
assign db_high[2] = alu_op1_oe ? op1_high[2] : 1'bz; |
assign db_high[1] = alu_op1_oe ? op1_high[1] : 1'bz; |
assign db_high[0] = alu_op1_oe ? op1_high[0] : 1'bz; |
|
assign SYNTHESIZED_WIRE_36 = ~clk; |
|
assign SYNTHESIZED_WIRE_37 = ~clk; |
|
|
alu_mux_2z b2v_op1_latch_mux_high( |
.sel_a(alu_op1_sel_bus), |
.sel_zero(alu_op1_sel_zero), |
.a(db_high), |
.ena(SYNTHESIZED_WIRE_20), |
.Q(SYNTHESIZED_WIRE_18)); |
|
|
alu_mux_3z b2v_op1_latch_mux_low( |
.sel_a(alu_op1_sel_bus), |
.sel_b(alu_op1_sel_low), |
.sel_zero(alu_op1_sel_zero), |
.a(db_low), |
.b(db_high), |
.ena(SYNTHESIZED_WIRE_23), |
.Q(SYNTHESIZED_WIRE_21)); |
|
|
alu_mux_3z b2v_op2_latch_mux_high( |
.sel_a(alu_op2_sel_bus), |
.sel_b(alu_op2_sel_lq), |
.sel_zero(alu_op2_sel_zero), |
.a(db_high), |
.b(db_low), |
.ena(SYNTHESIZED_WIRE_26), |
.Q(SYNTHESIZED_WIRE_24)); |
|
|
alu_mux_3z b2v_op2_latch_mux_low( |
.sel_a(alu_op2_sel_bus), |
.sel_b(alu_op2_sel_lq), |
.sel_zero(alu_op2_sel_zero), |
.a(db_low), |
.b(alu_op1), |
.ena(SYNTHESIZED_WIRE_29), |
.Q(SYNTHESIZED_WIRE_27)); |
|
assign alu_parity_out = SYNTHESIZED_WIRE_30 ^ result_hi[0]; |
|
assign SYNTHESIZED_WIRE_30 = SYNTHESIZED_WIRE_31 ^ result_hi[1]; |
|
assign SYNTHESIZED_WIRE_31 = SYNTHESIZED_WIRE_32 ^ result_hi[2]; |
|
assign SYNTHESIZED_WIRE_32 = alu_parity_in ^ result_hi[3]; |
|
|
alu_prep_daa b2v_prep_daa( |
.high(op1_high), |
.low(op1_low), |
.low_gt_9(alu_low_gt_9), |
.high_gt_9(alu_high_gt_9), |
.high_eq_9(alu_high_eq_9)); |
|
assign db_low[3] = alu_shift_oe ? SYNTHESIZED_WIRE_33[3] : 1'bz; |
assign db_low[2] = alu_shift_oe ? SYNTHESIZED_WIRE_33[2] : 1'bz; |
assign db_low[1] = alu_shift_oe ? SYNTHESIZED_WIRE_33[1] : 1'bz; |
assign db_low[0] = alu_shift_oe ? SYNTHESIZED_WIRE_33[0] : 1'bz; |
|
assign db_high[3] = alu_shift_oe ? SYNTHESIZED_WIRE_34[3] : 1'bz; |
assign db_high[2] = alu_shift_oe ? SYNTHESIZED_WIRE_34[2] : 1'bz; |
assign db_high[1] = alu_shift_oe ? SYNTHESIZED_WIRE_34[1] : 1'bz; |
assign db_high[0] = alu_shift_oe ? SYNTHESIZED_WIRE_34[0] : 1'bz; |
|
assign alu_zero = ~(db_low[2] | db_low[1] | db_low[3] | db_high[1] | db_high[0] | db_high[2] | db_low[0] | db_high[3]); |
|
assign alu_sf_out = db_high[3]; |
assign alu_yf_out = db_high[1]; |
assign alu_xf_out = db_low[3]; |
assign test_db_high = db_high; |
assign test_db_low = db_low; |
|
endmodule |
/trunk/cpu/deploy/inc_dec.v
0,0 → 1,181
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Mon Oct 13 12:30:20 2014" |
|
module inc_dec( |
carry_in, |
limit6, |
decrement, |
d, |
address |
); |
|
|
input wire carry_in; |
input wire limit6; |
input wire decrement; |
input wire [15:0] d; |
output wire [15:0] address; |
|
wire [15:0] address_ALTERA_SYNTHESIZED; |
wire SYNTHESIZED_WIRE_40; |
wire SYNTHESIZED_WIRE_41; |
wire SYNTHESIZED_WIRE_42; |
wire SYNTHESIZED_WIRE_43; |
wire SYNTHESIZED_WIRE_44; |
wire SYNTHESIZED_WIRE_5; |
wire SYNTHESIZED_WIRE_45; |
wire SYNTHESIZED_WIRE_46; |
wire SYNTHESIZED_WIRE_47; |
wire SYNTHESIZED_WIRE_48; |
wire SYNTHESIZED_WIRE_49; |
wire SYNTHESIZED_WIRE_50; |
wire SYNTHESIZED_WIRE_12; |
wire SYNTHESIZED_WIRE_51; |
wire SYNTHESIZED_WIRE_52; |
wire SYNTHESIZED_WIRE_53; |
wire SYNTHESIZED_WIRE_16; |
wire SYNTHESIZED_WIRE_22; |
wire SYNTHESIZED_WIRE_25; |
wire SYNTHESIZED_WIRE_31; |
wire SYNTHESIZED_WIRE_34; |
wire SYNTHESIZED_WIRE_35; |
wire SYNTHESIZED_WIRE_36; |
wire SYNTHESIZED_WIRE_37; |
wire SYNTHESIZED_WIRE_38; |
wire SYNTHESIZED_WIRE_39; |
|
|
|
|
assign SYNTHESIZED_WIRE_34 = carry_in & SYNTHESIZED_WIRE_40 & SYNTHESIZED_WIRE_41 & SYNTHESIZED_WIRE_42 & SYNTHESIZED_WIRE_43 & SYNTHESIZED_WIRE_44 & SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_45; |
|
assign SYNTHESIZED_WIRE_51 = SYNTHESIZED_WIRE_46 & SYNTHESIZED_WIRE_47 & SYNTHESIZED_WIRE_48 & SYNTHESIZED_WIRE_49 & SYNTHESIZED_WIRE_50 & SYNTHESIZED_WIRE_12; |
|
assign SYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_51 & SYNTHESIZED_WIRE_52 & SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_16; |
|
|
inc_dec_2bit b2v_dual_adder_0( |
.carry_borrow_in(carry_in), |
.d1_in(d[1]), |
.d0_in(d[0]), |
.dec1_in(SYNTHESIZED_WIRE_40), |
.dec0_in(SYNTHESIZED_WIRE_41), |
.carry_borrow_out(SYNTHESIZED_WIRE_22), |
.d1_out(address_ALTERA_SYNTHESIZED[1]), |
.d0_out(address_ALTERA_SYNTHESIZED[0])); |
|
|
inc_dec_2bit b2v_dual_adder_10( |
.carry_borrow_in(SYNTHESIZED_WIRE_51), |
.d1_in(d[13]), |
.d0_in(d[12]), |
.dec1_in(SYNTHESIZED_WIRE_53), |
.dec0_in(SYNTHESIZED_WIRE_52), |
.carry_borrow_out(SYNTHESIZED_WIRE_37), |
.d1_out(address_ALTERA_SYNTHESIZED[13]), |
.d0_out(address_ALTERA_SYNTHESIZED[12])); |
|
|
inc_dec_2bit b2v_dual_adder_2( |
.carry_borrow_in(SYNTHESIZED_WIRE_22), |
.d1_in(d[3]), |
.d0_in(d[2]), |
.dec1_in(SYNTHESIZED_WIRE_45), |
.dec0_in(SYNTHESIZED_WIRE_42), |
.carry_borrow_out(SYNTHESIZED_WIRE_25), |
.d1_out(address_ALTERA_SYNTHESIZED[3]), |
.d0_out(address_ALTERA_SYNTHESIZED[2])); |
|
|
inc_dec_2bit b2v_dual_adder_4( |
.carry_borrow_in(SYNTHESIZED_WIRE_25), |
.d1_in(d[5]), |
.d0_in(d[4]), |
.dec1_in(SYNTHESIZED_WIRE_43), |
.dec0_in(SYNTHESIZED_WIRE_44), |
.carry_borrow_out(SYNTHESIZED_WIRE_39), |
.d1_out(address_ALTERA_SYNTHESIZED[5]), |
.d0_out(address_ALTERA_SYNTHESIZED[4])); |
|
|
inc_dec_2bit b2v_dual_adder_7( |
.carry_borrow_in(SYNTHESIZED_WIRE_47), |
.d1_in(d[8]), |
.d0_in(d[7]), |
.dec1_in(SYNTHESIZED_WIRE_46), |
.dec0_in(SYNTHESIZED_WIRE_48), |
.carry_borrow_out(SYNTHESIZED_WIRE_31), |
.d1_out(address_ALTERA_SYNTHESIZED[8]), |
.d0_out(address_ALTERA_SYNTHESIZED[7])); |
|
|
inc_dec_2bit b2v_dual_adder_9( |
.carry_borrow_in(SYNTHESIZED_WIRE_31), |
.d1_in(d[10]), |
.d0_in(d[9]), |
.dec1_in(SYNTHESIZED_WIRE_50), |
.dec0_in(SYNTHESIZED_WIRE_49), |
.carry_borrow_out(SYNTHESIZED_WIRE_36), |
.d1_out(address_ALTERA_SYNTHESIZED[10]), |
.d0_out(address_ALTERA_SYNTHESIZED[9])); |
|
assign SYNTHESIZED_WIRE_47 = SYNTHESIZED_WIRE_34 & SYNTHESIZED_WIRE_35; |
|
assign SYNTHESIZED_WIRE_35 = ~limit6; |
|
assign SYNTHESIZED_WIRE_41 = d[0] ^ decrement; |
|
assign SYNTHESIZED_WIRE_40 = d[1] ^ decrement; |
|
assign SYNTHESIZED_WIRE_50 = d[10] ^ decrement; |
|
assign SYNTHESIZED_WIRE_12 = d[11] ^ decrement; |
|
assign address_ALTERA_SYNTHESIZED[11] = SYNTHESIZED_WIRE_36 ^ d[11]; |
|
assign SYNTHESIZED_WIRE_52 = d[12] ^ decrement; |
|
assign SYNTHESIZED_WIRE_53 = d[13] ^ decrement; |
|
assign SYNTHESIZED_WIRE_16 = d[14] ^ decrement; |
|
assign address_ALTERA_SYNTHESIZED[14] = SYNTHESIZED_WIRE_37 ^ d[14]; |
|
assign address_ALTERA_SYNTHESIZED[15] = SYNTHESIZED_WIRE_38 ^ d[15]; |
|
assign SYNTHESIZED_WIRE_42 = d[2] ^ decrement; |
|
assign SYNTHESIZED_WIRE_45 = d[3] ^ decrement; |
|
assign SYNTHESIZED_WIRE_44 = d[4] ^ decrement; |
|
assign SYNTHESIZED_WIRE_43 = d[5] ^ decrement; |
|
assign SYNTHESIZED_WIRE_5 = d[6] ^ decrement; |
|
assign address_ALTERA_SYNTHESIZED[6] = SYNTHESIZED_WIRE_39 ^ d[6]; |
|
assign SYNTHESIZED_WIRE_48 = d[7] ^ decrement; |
|
assign SYNTHESIZED_WIRE_46 = d[8] ^ decrement; |
|
assign SYNTHESIZED_WIRE_49 = d[9] ^ decrement; |
|
assign address = address_ALTERA_SYNTHESIZED; |
|
endmodule |
/trunk/cpu/deploy/execute.sv
0,0 → 1,192
//============================================================================= |
// This module implements the instruction execute state logic. |
// |
// Copyright (C) 2014 Goran Devic |
// |
// This program is free software; you can redistribute it and/or modify it |
// under the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 of the License, or (at your option) |
// any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
// more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program; if not, write to the Free Software Foundation, Inc., |
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
//============================================================================= |
module execute |
( |
//---------------------------------------------------------- |
// Control signals generated by the instruction execution |
//---------------------------------------------------------- |
`include "exec_module.vh" |
|
output logic nextM, // Last M cycle of any instruction |
output logic setM1, // Last T clock of any instruction |
output logic fFetch, // Function: opcode fetch cycle ("M1") |
output logic fMRead, // Function: memory read cycle |
output logic fMWrite, // Function: memory write cycle |
output logic fIORead, // Function: IO Read cycle |
output logic fIOWrite, // Function: IO Write cycle |
|
//---------------------------------------------------------- |
// Inputs from the instruction decode PLA |
//---------------------------------------------------------- |
input wire [104:0] pla, // Statically decoded instructions |
|
//---------------------------------------------------------- |
// Inputs from various blocks |
//---------------------------------------------------------- |
input wire fpga_reset, // Internal fpga test mode |
input wire nreset, // Internal reset signal |
input wire clk, // Internal clock signal |
input wire in_intr, // Servicing maskable interrupt |
input wire in_nmi, // Servicing non-maskable interrupt |
input wire in_halt, // Currently in HALT mode |
input wire im1, // Interrupt Mode 1 |
input wire im2, // Interrupt Mode 2 |
input wire use_ixiy, // Special decode signal |
input wire flags_cond_true, // Flags condition is true |
input wire repeat_en, // Enable repeat of a block instruction |
input wire flags_zf, // ZF to test a condition |
input wire flags_nf, // NF to test for subtraction |
input wire flags_sf, // SF to test for 8-bit sign of a value |
input wire flags_cf, // CF to set HF for CCF |
|
//---------------------------------------------------------- |
// Machine and clock cycles |
//---------------------------------------------------------- |
input wire M1, // Machine cycle #1 |
input wire M2, // Machine cycle #2 |
input wire M3, // Machine cycle #3 |
input wire M4, // Machine cycle #4 |
input wire M5, // Machine cycle #5 |
input wire M6, // Machine cycle #6 |
input wire T1, // T-cycle #1 |
input wire T2, // T-cycle #2 |
input wire T3, // T-cycle #3 |
input wire T4, // T-cycle #4 |
input wire T5, // T-cycle #5 |
input wire T6 // T-cycle #6 |
); |
|
// Detects unknown instructions by signalling the known ones |
logic validPLA; // Valid PLA asserts this wire |
// Activates a state machine to compute WZ=IX+d; takes 5T cycles |
logic ixy_d; // Compute WX=IX+d |
// Signals the setting of IX/IY and CB/ED prefix flags; inhibits clearing them |
logic setIXIY; // Set IX/IY flag at the next T cycle |
logic setCBED; // Set CB or ED flag at the next T cycle |
// Holds asserted by non-repeating versions of block instructions (LDI/CPI,...) |
logic nonRep; // Non-repeating block instruction |
// Suspends incrementing PC through address latch unless in HALT or interrupt mode |
logic pc_inc; // Normally defaults to 1 |
|
//---------------------------------------------------------- |
// Define various shortcuts to field naming |
//---------------------------------------------------------- |
`define GP_REG_BC 2'h0 |
`define GP_REG_DE 2'h1 |
`define GP_REG_HL 2'h2 |
`define GP_REG_AF 2'h3 |
|
`define PFSEL_P 2'h0 |
`define PFSEL_V 2'h1 |
`define PFSEL_IFF2 2'h2 |
`define PFSEL_REP 2'h3 |
|
//---------------------------------------------------------- |
// Make available different sections of the opcode byte |
//---------------------------------------------------------- |
wire op5; |
wire op4; |
wire op3; |
wire op2; |
wire op1; |
wire op0; |
assign op5 = pla[104]; |
assign op4 = pla[103]; |
assign op3 = pla[102]; |
assign op2 = pla[101]; |
assign op1 = pla[100]; |
assign op0 = pla[99]; |
|
wire [1:0] op54; |
wire [1:0] op21; |
|
assign op54 = { pla[104], pla[103] }; |
assign op21 = { pla[101], pla[100] }; |
|
//----------------------------------------------------------- |
// 8-bit register selections needs to swizzle mux for A and F |
//----------------------------------------------------------- |
wire rsel3; |
wire rsel0; |
assign rsel3 = op3 ^ (op4 & op5); |
assign rsel0 = op0 ^ (op1 & op2); |
|
always_comb |
begin |
//------------------------------------------------------------------------- |
// Default assignment of all control outputs to 0 to prevent generating |
// latches. |
//------------------------------------------------------------------------- |
`include "exec_zero.vh" |
|
// Reset internal control wires |
validPLA = 0; // Every valid PLA entry will set it |
nextM = 0; // Set to advance to the next M cycle |
setM1 = 0; // Set on a last M/T cycle of an instruction |
|
// Reset global machine cycle functions |
fFetch = M1; // Fetch is simply always M1 |
fMRead = 0; fMWrite = 0; fIORead = 0; fIOWrite = 0; |
ixy_d = 0; |
setIXIY = 0; |
setCBED = 0; |
nonRep = 0; |
pc_inc = 1; |
|
//------------------------------------------------------------------------- |
// State-based signal assignment |
//------------------------------------------------------------------------- |
`include "exec_matrix.vh" |
|
// List more specific combinational signal assignments after the include |
//------------------------------------------------------------------------- |
// Reset control |
//------------------------------------------------------------------------- |
if (!nreset) begin |
// Clear the address latch, PC and IR registers |
ctl_inc_zero = 1; // Force 0 to the output of incrementer |
ctl_inc_cy = 0; // Don't increment, pass-through |
ctl_al_we = 1; // Write 0 to the address latch |
setM1 = 1; // Arm to start executing at M1/T1 |
nextM = 1; // Arm to start executing at M1/T1 |
|
// Clear instruction opcode register |
ctl_bus_zero_oe = 1; // Output 0 on the data bus section 0 |
ctl_ir_we = 1; // And write it into the instruction register |
end |
|
//------------------------------------------------------------------------- |
// At M1/T4 advance an instruction if it did not trigger any PLA entry |
//------------------------------------------------------------------------- |
if (M1 && T4 && !validPLA) begin |
nextM = 1; // Complete the default M1 cycle |
setM1 = 1; // Set next M1 cycle |
end |
|
//------------------------------------------------------------------------- |
// The last cycle of an instruction is also the first cycle of the next one |
//------------------------------------------------------------------------- |
if (setM1) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; // Select 16-bit PC |
ctl_al_we=1; // Write the PC into the address latch |
end |
end |
|
endmodule |
/trunk/cpu/deploy/alu_mux_3z.v
0,0 → 1,59
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Fri Oct 31 21:08:42 2014" |
|
module alu_mux_3z( |
sel_zero, |
sel_a, |
sel_b, |
a, |
b, |
ena, |
Q |
); |
|
|
input wire sel_zero; |
input wire sel_a; |
input wire sel_b; |
input wire [3:0] a; |
input wire [3:0] b; |
output wire ena; |
output wire [3:0] Q; |
|
wire [3:0] SYNTHESIZED_WIRE_0; |
wire SYNTHESIZED_WIRE_1; |
wire [3:0] SYNTHESIZED_WIRE_2; |
wire [3:0] SYNTHESIZED_WIRE_3; |
|
|
|
|
assign SYNTHESIZED_WIRE_3 = a & {sel_a,sel_a,sel_a,sel_a}; |
|
assign Q = SYNTHESIZED_WIRE_0 & {SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1}; |
|
assign SYNTHESIZED_WIRE_1 = ~sel_zero; |
|
assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3; |
|
assign ena = sel_a | sel_b | sel_zero; |
|
assign SYNTHESIZED_WIRE_2 = b & {sel_b,sel_b,sel_b,sel_b}; |
|
|
endmodule |
/trunk/cpu/deploy/clk_delay.v
0,0 → 1,155
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Sun Nov 16 23:41:11 2014" |
|
module clk_delay( |
clk, |
in_intr, |
nreset, |
T1, |
latch_wait, |
mwait, |
M1, |
busrq, |
setM1, |
hold_clk_iorq, |
hold_clk_wait, |
iorq_Tw, |
busack, |
pin_control_oe, |
hold_clk_busrq |
); |
|
|
input wire clk; |
input wire in_intr; |
input wire nreset; |
input wire T1; |
input wire latch_wait; |
input wire mwait; |
input wire M1; |
input wire busrq; |
input wire setM1; |
output wire hold_clk_iorq; |
output wire hold_clk_wait; |
output wire iorq_Tw; |
output wire busack; |
output wire pin_control_oe; |
output wire hold_clk_busrq; |
|
reg hold_clk_busrq_ALTERA_SYNTHESIZED; |
wire SYNTHESIZED_WIRE_6; |
wire SYNTHESIZED_WIRE_1; |
reg DFF_inst5; |
reg SYNTHESIZED_WIRE_7; |
reg SYNTHESIZED_WIRE_8; |
wire SYNTHESIZED_WIRE_3; |
wire SYNTHESIZED_WIRE_4; |
wire SYNTHESIZED_WIRE_5; |
reg DFFE_inst; |
|
assign hold_clk_wait = DFFE_inst; |
assign iorq_Tw = DFF_inst5; |
|
|
|
|
always@(posedge SYNTHESIZED_WIRE_6 or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_inst <= 0; |
end |
else |
if (SYNTHESIZED_WIRE_1) |
begin |
DFFE_inst <= mwait; |
end |
end |
|
|
always@(posedge SYNTHESIZED_WIRE_6 or negedge nreset) |
begin |
if (!nreset) |
begin |
SYNTHESIZED_WIRE_8 <= 0; |
end |
else |
begin |
SYNTHESIZED_WIRE_8 <= busrq; |
end |
end |
|
assign hold_clk_iorq = DFF_inst5 | SYNTHESIZED_WIRE_7; |
|
assign busack = SYNTHESIZED_WIRE_8 & hold_clk_busrq_ALTERA_SYNTHESIZED; |
|
assign pin_control_oe = SYNTHESIZED_WIRE_3 & nreset; |
|
assign SYNTHESIZED_WIRE_5 = hold_clk_busrq_ALTERA_SYNTHESIZED | setM1; |
|
assign SYNTHESIZED_WIRE_3 = ~hold_clk_busrq_ALTERA_SYNTHESIZED; |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
SYNTHESIZED_WIRE_7 <= 0; |
end |
else |
begin |
SYNTHESIZED_WIRE_7 <= SYNTHESIZED_WIRE_4; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
hold_clk_busrq_ALTERA_SYNTHESIZED <= 0; |
end |
else |
if (SYNTHESIZED_WIRE_5) |
begin |
hold_clk_busrq_ALTERA_SYNTHESIZED <= SYNTHESIZED_WIRE_8; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFF_inst5 <= 0; |
end |
else |
begin |
DFF_inst5 <= SYNTHESIZED_WIRE_7; |
end |
end |
|
assign SYNTHESIZED_WIRE_4 = in_intr & M1 & T1; |
|
assign SYNTHESIZED_WIRE_1 = latch_wait | DFFE_inst; |
|
assign SYNTHESIZED_WIRE_6 = ~clk; |
|
assign hold_clk_busrq = hold_clk_busrq_ALTERA_SYNTHESIZED; |
|
endmodule |
/trunk/cpu/deploy/memory_ifc.v
0,0 → 1,423
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Sun Nov 16 21:11:14 2014" |
|
module memory_ifc( |
clk, |
nM1_int, |
ctl_mRead, |
ctl_mWrite, |
in_intr, |
nreset, |
fIORead, |
fIOWrite, |
setM1, |
ctl_iorw, |
timings_en, |
iorq_Tw, |
hold_clk_wait, |
nM1_out, |
nRFSH_out, |
nMREQ_out, |
nRD_out, |
nWR_out, |
nIORQ_out, |
latch_wait |
); |
|
|
input wire clk; |
input wire nM1_int; |
input wire ctl_mRead; |
input wire ctl_mWrite; |
input wire in_intr; |
input wire nreset; |
input wire fIORead; |
input wire fIOWrite; |
input wire setM1; |
input wire ctl_iorw; |
input wire timings_en; |
input wire iorq_Tw; |
input wire hold_clk_wait; |
output wire nM1_out; |
output wire nRFSH_out; |
output wire nMREQ_out; |
output wire nRD_out; |
output wire nWR_out; |
output wire nIORQ_out; |
output wire latch_wait; |
|
wire intr_iorq; |
wire ioRead; |
wire iorq; |
wire ioWrite; |
wire m1_mreq; |
wire mrd_mreq; |
wire mwr_mreq; |
reg mwr_wr; |
wire nMEMRQ_int; |
wire nq2; |
reg q1; |
reg q2; |
reg wait_iorq; |
reg wait_m1; |
reg wait_mrd; |
reg wait_mwr; |
wire SYNTHESIZED_WIRE_0; |
reg DFFE_m1_ff3; |
wire SYNTHESIZED_WIRE_1; |
reg SYNTHESIZED_WIRE_15; |
reg DFFE_iorq_ff4; |
reg SYNTHESIZED_WIRE_16; |
reg DFFE_mrd_ff3; |
reg DFFE_intr_ff3; |
wire SYNTHESIZED_WIRE_2; |
reg SYNTHESIZED_WIRE_17; |
reg SYNTHESIZED_WIRE_18; |
wire SYNTHESIZED_WIRE_19; |
wire SYNTHESIZED_WIRE_4; |
reg DFFE_iorq_ff1; |
reg DFFE_m1_ff1; |
reg DFFE_mrd_ff1; |
reg DFFE_mwr_ff1; |
reg DFFE_mreq_ff2; |
|
assign nM1_out = SYNTHESIZED_WIRE_18; |
|
|
|
assign nMREQ_out = SYNTHESIZED_WIRE_0 & nMEMRQ_int; |
|
assign ioRead = iorq & fIORead; |
|
assign SYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 | wait_m1); |
|
assign m1_mreq = ~(in_intr | SYNTHESIZED_WIRE_1); |
|
assign iorq = SYNTHESIZED_WIRE_15 | DFFE_iorq_ff4 | SYNTHESIZED_WIRE_16; |
|
assign ioWrite = iorq & fIOWrite; |
|
assign latch_wait = wait_mrd | wait_iorq | wait_m1 | wait_mwr; |
|
assign nMEMRQ_int = ~(m1_mreq | mrd_mreq | mwr_mreq); |
|
assign nRD_out = ~(m1_mreq | mrd_mreq | ioRead); |
|
assign mrd_mreq = DFFE_mrd_ff3 | wait_mrd; |
|
assign nWR_out = ~(ioWrite | mwr_wr); |
|
assign mwr_mreq = mwr_wr | wait_mwr; |
|
assign nIORQ_out = ~(intr_iorq | iorq); |
|
assign SYNTHESIZED_WIRE_4 = ~hold_clk_wait; |
|
assign intr_iorq = DFFE_intr_ff3 | wait_iorq; |
|
assign SYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_17); |
|
assign nRFSH_out = ~(nq2 & SYNTHESIZED_WIRE_18); |
|
|
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset) |
begin |
if (!nreset) |
begin |
wait_iorq <= 0; |
end |
else |
begin |
wait_iorq <= iorq_Tw; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_intr_ff3 <= 0; |
end |
else |
if (SYNTHESIZED_WIRE_4) |
begin |
DFFE_intr_ff3 <= wait_iorq; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_iorq_ff1 <= 0; |
end |
else |
if (timings_en) |
begin |
DFFE_iorq_ff1 <= ctl_iorw; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
SYNTHESIZED_WIRE_16 <= 0; |
end |
else |
if (timings_en) |
begin |
SYNTHESIZED_WIRE_16 <= DFFE_iorq_ff1; |
end |
end |
|
|
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset) |
begin |
if (!nreset) |
begin |
SYNTHESIZED_WIRE_15 <= 0; |
end |
else |
if (timings_en) |
begin |
SYNTHESIZED_WIRE_15 <= SYNTHESIZED_WIRE_16; |
end |
end |
|
|
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_iorq_ff4 <= 0; |
end |
else |
if (timings_en) |
begin |
DFFE_iorq_ff4 <= SYNTHESIZED_WIRE_15; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
SYNTHESIZED_WIRE_18 <= 0; |
end |
else |
if (timings_en) |
begin |
SYNTHESIZED_WIRE_18 <= nM1_int; |
end |
end |
|
|
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_m1_ff1 <= 1; |
end |
else |
if (timings_en) |
begin |
DFFE_m1_ff1 <= setM1; |
end |
end |
|
|
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset) |
begin |
if (!nreset) |
begin |
wait_m1 <= 0; |
end |
else |
if (timings_en) |
begin |
wait_m1 <= DFFE_m1_ff1; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_m1_ff3 <= 0; |
end |
else |
if (timings_en) |
begin |
DFFE_m1_ff3 <= wait_m1; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_mrd_ff1 <= 0; |
end |
else |
if (timings_en) |
begin |
DFFE_mrd_ff1 <= ctl_mRead; |
end |
end |
|
|
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset) |
begin |
if (!nreset) |
begin |
wait_mrd <= 0; |
end |
else |
if (timings_en) |
begin |
wait_mrd <= DFFE_mrd_ff1; |
end |
end |
|
|
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_mrd_ff3 <= 0; |
end |
else |
if (timings_en) |
begin |
DFFE_mrd_ff3 <= wait_mrd; |
end |
end |
|
|
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset) |
begin |
if (!nreset) |
begin |
SYNTHESIZED_WIRE_17 <= 0; |
end |
else |
if (timings_en) |
begin |
SYNTHESIZED_WIRE_17 <= SYNTHESIZED_WIRE_18; |
end |
end |
|
|
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_mreq_ff2 <= 0; |
end |
else |
if (timings_en) |
begin |
DFFE_mreq_ff2 <= SYNTHESIZED_WIRE_17; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
DFFE_mwr_ff1 <= 0; |
end |
else |
if (timings_en) |
begin |
DFFE_mwr_ff1 <= ctl_mWrite; |
end |
end |
|
|
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset) |
begin |
if (!nreset) |
begin |
wait_mwr <= 0; |
end |
else |
if (timings_en) |
begin |
wait_mwr <= DFFE_mwr_ff1; |
end |
end |
|
|
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset) |
begin |
if (!nreset) |
begin |
mwr_wr <= 0; |
end |
else |
if (timings_en) |
begin |
mwr_wr <= wait_mwr; |
end |
end |
|
assign SYNTHESIZED_WIRE_19 = ~clk; |
|
assign nq2 = ~q2; |
|
assign SYNTHESIZED_WIRE_2 = ~DFFE_mreq_ff2; |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
q1 <= 0; |
end |
else |
if (timings_en) |
begin |
q1 <= SYNTHESIZED_WIRE_18; |
end |
end |
|
|
always@(posedge clk or negedge nreset) |
begin |
if (!nreset) |
begin |
q2 <= 0; |
end |
else |
if (timings_en) |
begin |
q2 <= q1; |
end |
end |
|
|
endmodule |
/trunk/cpu/deploy/exec_zero.vh
0,0 → 1,127
// Automatically generated by genref.py |
|
// Module: control/decode_state.v |
ctl_state_iy_set = 0; |
ctl_state_ixiy_clr = 0; |
ctl_state_ixiy_we = 0; |
ctl_state_halt_set = 0; |
ctl_state_tbl_clr = 0; |
ctl_state_tbl_ed_set = 0; |
ctl_state_tbl_cb_set = 0; |
ctl_state_alu = 0; |
ctl_repeat_we = 0; |
|
// Module: control/interrupts.v |
ctl_iff1_iff2 = 0; |
ctl_iffx_we = 0; |
ctl_iffx_bit = 0; |
ctl_im_we = 0; |
ctl_no_ints = 0; |
|
// Module: control/ir.v |
ctl_ir_we = 0; |
|
// Module: control/memory_ifc.v |
ctl_mRead = 0; |
ctl_mWrite = 0; |
ctl_iorw = 0; |
|
// Module: alu/alu_control.v |
ctl_shift_en = 0; |
ctl_daa_oe = 0; |
ctl_alu_op_low = 0; |
ctl_cond_short = 0; |
ctl_alu_core_hf = 0; |
ctl_eval_cond = 0; |
ctl_66_oe = 0; |
ctl_pf_sel = 0; |
|
// Module: alu/alu_select.v |
ctl_alu_oe = 0; |
ctl_alu_shift_oe = 0; |
ctl_alu_op2_oe = 0; |
ctl_alu_res_oe = 0; |
ctl_alu_op1_oe = 0; |
ctl_alu_bs_oe = 0; |
ctl_alu_op1_sel_bus = 0; |
ctl_alu_op1_sel_low = 0; |
ctl_alu_op1_sel_zero = 0; |
ctl_alu_op2_sel_zero = 0; |
ctl_alu_op2_sel_bus = 0; |
ctl_alu_op2_sel_lq = 0; |
ctl_alu_sel_op2_neg = 0; |
ctl_alu_sel_op2_high = 0; |
ctl_alu_core_R = 0; |
ctl_alu_core_V = 0; |
ctl_alu_core_S = 0; |
|
// Module: alu/alu_flags.v |
ctl_flags_oe = 0; |
ctl_flags_bus = 0; |
ctl_flags_alu = 0; |
ctl_flags_nf_set = 0; |
ctl_flags_cf_set = 0; |
ctl_flags_cf_cpl = 0; |
ctl_flags_cf_we = 0; |
ctl_flags_sz_we = 0; |
ctl_flags_xy_we = 0; |
ctl_flags_hf_we = 0; |
ctl_flags_pf_we = 0; |
ctl_flags_nf_we = 0; |
ctl_flags_cf2_we = 0; |
ctl_flags_hf_cpl = 0; |
ctl_flags_use_cf2 = 0; |
ctl_flags_hf2_we = 0; |
ctl_flags_nf_clr = 0; |
ctl_alu_zero_16bit = 0; |
ctl_flags_cf2_sel = 0; |
|
// Module: registers/reg_file.v |
ctl_sw_4d = 0; |
ctl_sw_4u = 0; |
ctl_reg_in_hi = 0; |
ctl_reg_in_lo = 0; |
ctl_reg_out_lo = 0; |
ctl_reg_out_hi = 0; |
|
// Module: registers/reg_control.v |
ctl_reg_exx = 0; |
ctl_reg_ex_af = 0; |
ctl_reg_ex_de_hl = 0; |
ctl_reg_use_sp = 0; |
ctl_reg_sel_pc = 0; |
ctl_reg_sel_ir = 0; |
ctl_reg_sel_wz = 0; |
ctl_reg_gp_we = 0; |
ctl_reg_not_pc = 0; |
ctl_reg_sys_we_lo = 0; |
ctl_reg_sys_we_hi = 0; |
ctl_reg_sys_we = 0; |
ctl_reg_gp_hilo = 0; |
ctl_reg_gp_sel = 0; |
ctl_reg_sys_hilo = 0; |
|
// Module: bus/address_latch.v |
ctl_inc_cy = 0; |
ctl_inc_dec = 0; |
ctl_inc_zero = 0; |
ctl_al_we = 0; |
ctl_inc_limit6 = 0; |
ctl_bus_inc_oe = 0; |
ctl_apin_mux = 0; |
ctl_apin_mux2 = 0; |
|
// Module: bus/bus_control.v |
ctl_bus_ff_oe = 0; |
ctl_bus_zero_oe = 0; |
ctl_bus_db_oe = 0; |
|
// Module: bus/bus_switch.sv |
ctl_sw_1u = 0; |
ctl_sw_1d = 0; |
ctl_sw_2u = 0; |
ctl_sw_2d = 0; |
ctl_sw_mask543_en = 0; |
|
// Module: bus/data_pins.v |
ctl_bus_db_we = 0; |
/trunk/cpu/deploy/globals.vh
0,0 → 1,291
// Automatically generated by genglobals.py |
|
// Module: control/clk_delay.v |
wire hold_clk_iorq; |
wire hold_clk_wait; |
wire iorq_Tw; |
wire busack; |
wire pin_control_oe; |
wire hold_clk_busrq; |
|
// Module: control/decode_state.v |
wire in_halt; |
wire table_cb; |
wire table_ed; |
wire table_xx; |
wire use_ix; |
wire use_ixiy; |
wire in_alu; |
wire repeat_en; |
|
// Module: control/exec_module.vh |
wire ctl_state_iy_set; |
wire ctl_state_ixiy_clr; |
wire ctl_state_ixiy_we; |
wire ctl_state_halt_set; |
wire ctl_state_tbl_clr; |
wire ctl_state_tbl_ed_set; |
wire ctl_state_tbl_cb_set; |
wire ctl_state_alu; |
wire ctl_repeat_we; |
wire ctl_iff1_iff2; |
wire ctl_iffx_we; |
wire ctl_iffx_bit; |
wire ctl_im_we; |
wire ctl_no_ints; |
wire ctl_ir_we; |
wire ctl_mRead; |
wire ctl_mWrite; |
wire ctl_iorw; |
wire ctl_shift_en; |
wire ctl_daa_oe; |
wire ctl_alu_op_low; |
wire ctl_cond_short; |
wire ctl_alu_core_hf; |
wire ctl_eval_cond; |
wire ctl_66_oe; |
wire [1:0] ctl_pf_sel; |
wire ctl_alu_oe; |
wire ctl_alu_shift_oe; |
wire ctl_alu_op2_oe; |
wire ctl_alu_res_oe; |
wire ctl_alu_op1_oe; |
wire ctl_alu_bs_oe; |
wire ctl_alu_op1_sel_bus; |
wire ctl_alu_op1_sel_low; |
wire ctl_alu_op1_sel_zero; |
wire ctl_alu_op2_sel_zero; |
wire ctl_alu_op2_sel_bus; |
wire ctl_alu_op2_sel_lq; |
wire ctl_alu_sel_op2_neg; |
wire ctl_alu_sel_op2_high; |
wire ctl_alu_core_R; |
wire ctl_alu_core_V; |
wire ctl_alu_core_S; |
wire ctl_flags_oe; |
wire ctl_flags_bus; |
wire ctl_flags_alu; |
wire ctl_flags_nf_set; |
wire ctl_flags_cf_set; |
wire ctl_flags_cf_cpl; |
wire ctl_flags_cf_we; |
wire ctl_flags_sz_we; |
wire ctl_flags_xy_we; |
wire ctl_flags_hf_we; |
wire ctl_flags_pf_we; |
wire ctl_flags_nf_we; |
wire ctl_flags_cf2_we; |
wire ctl_flags_hf_cpl; |
wire ctl_flags_use_cf2; |
wire ctl_flags_hf2_we; |
wire ctl_flags_nf_clr; |
wire ctl_alu_zero_16bit; |
wire [1:0] ctl_flags_cf2_sel; |
wire ctl_sw_4d; |
wire ctl_sw_4u; |
wire ctl_reg_in_hi; |
wire ctl_reg_in_lo; |
wire ctl_reg_out_lo; |
wire ctl_reg_out_hi; |
wire ctl_reg_exx; |
wire ctl_reg_ex_af; |
wire ctl_reg_ex_de_hl; |
wire ctl_reg_use_sp; |
wire ctl_reg_sel_pc; |
wire ctl_reg_sel_ir; |
wire ctl_reg_sel_wz; |
wire ctl_reg_gp_we; |
wire ctl_reg_not_pc; |
wire ctl_reg_sys_we_lo; |
wire ctl_reg_sys_we_hi; |
wire ctl_reg_sys_we; |
wire [1:0] ctl_reg_gp_hilo; |
wire [1:0] ctl_reg_gp_sel; |
wire [1:0] ctl_reg_sys_hilo; |
wire ctl_inc_cy; |
wire ctl_inc_dec; |
wire ctl_inc_zero; |
wire ctl_al_we; |
wire ctl_inc_limit6; |
wire ctl_bus_inc_oe; |
wire ctl_apin_mux; |
wire ctl_apin_mux2; |
wire ctl_bus_ff_oe; |
wire ctl_bus_zero_oe; |
wire ctl_bus_db_oe; |
wire ctl_sw_1u; |
wire ctl_sw_1d; |
wire ctl_sw_2u; |
wire ctl_sw_2d; |
wire ctl_sw_mask543_en; |
wire ctl_bus_db_we; |
|
// Module: control/execute.sv |
wire nextM; |
wire setM1; |
wire fFetch; |
wire fMRead; |
wire fMWrite; |
wire fIORead; |
wire fIOWrite; |
|
// Module: control/interrupts.v |
wire iff1; |
wire iff2; |
wire im1; |
wire im2; |
wire in_nmi; |
wire in_intr; |
|
// Module: control/ir.v |
wire [7:0] opcode; |
|
// Module: control/pin_control.v |
wire bus_ab_pin_we; |
wire bus_db_pin_oe; |
wire bus_db_pin_re; |
|
// Module: control/pla_decode.sv |
wire [104:0] pla; |
|
// Module: control/resets.v |
wire clrpc; |
wire nreset; |
|
// Module: control/memory_ifc.v |
wire nM1_out; |
wire nRFSH_out; |
wire nMREQ_out; |
wire nRD_out; |
wire nWR_out; |
wire nIORQ_out; |
wire latch_wait; |
|
// Module: control/sequencer.v |
wire M1; |
wire M2; |
wire M3; |
wire M4; |
wire M5; |
wire M6; |
wire T1; |
wire T2; |
wire T3; |
wire T4; |
wire T5; |
wire T6; |
wire timings_en; |
|
// Module: alu/alu_control.v |
wire alu_shift_in; |
wire alu_shift_right; |
wire alu_shift_left; |
wire shift_cf_out; |
wire alu_parity_in; |
wire flags_cond_true; |
wire daa_cf_out; |
wire pf_sel; |
wire alu_op_low; |
wire alu_core_cf_in; |
wire [7:0] db; |
|
// Module: alu/alu_select.v |
wire alu_oe; |
wire alu_shift_oe; |
wire alu_op2_oe; |
wire alu_res_oe; |
wire alu_op1_oe; |
wire alu_bs_oe; |
wire alu_op1_sel_bus; |
wire alu_op1_sel_low; |
wire alu_op1_sel_zero; |
wire alu_op2_sel_zero; |
wire alu_op2_sel_bus; |
wire alu_op2_sel_lq; |
wire alu_sel_op2_neg; |
wire alu_sel_op2_high; |
wire alu_core_R; |
wire alu_core_V; |
wire alu_core_S; |
|
// Module: alu/alu_flags.v |
wire flags_sf; |
wire flags_zf; |
wire flags_hf; |
wire flags_pf; |
wire flags_cf; |
wire flags_nf; |
wire flags_cf_latch; |
wire flags_hf2; |
|
// Module: alu/alu.v |
wire alu_zero; |
wire alu_parity_out; |
wire alu_high_eq_9; |
wire alu_high_gt_9; |
wire alu_low_gt_9; |
wire alu_shift_db0; |
wire alu_shift_db7; |
wire alu_core_cf_out; |
wire alu_sf_out; |
wire alu_yf_out; |
wire alu_xf_out; |
wire alu_vf_out; |
wire [3:0] test_db_high; |
wire [3:0] test_db_low; |
|
// Module: registers/reg_control.v |
wire reg_sel_bc; |
wire reg_sel_bc2; |
wire reg_sel_ix; |
wire reg_sel_iy; |
wire reg_sel_de; |
wire reg_sel_hl; |
wire reg_sel_de2; |
wire reg_sel_hl2; |
wire reg_sel_af; |
wire reg_sel_af2; |
wire reg_sel_wz; |
wire reg_sel_pc; |
wire reg_sel_ir; |
wire reg_sel_sp; |
wire reg_sel_gp_hi; |
wire reg_sel_gp_lo; |
wire reg_sel_sys_lo; |
wire reg_sel_sys_hi; |
wire reg_gp_we; |
wire reg_sys_we_lo; |
wire reg_sys_we_hi; |
|
// Module: bus/address_latch.v |
wire address_is_1; |
wire [15:0] address; |
|
// Module: bus/address_pins.v |
wire [15:0] abus; |
|
// Module: bus/bus_control.v |
wire bus_db_oe; |
|
// Module: bus/bus_switch.sv |
wire bus_sw_1u; |
wire bus_sw_1d; |
wire bus_sw_2u; |
wire bus_sw_2d; |
wire bus_sw_mask543_en; |
|
// Module: bus/control_pins_n.v |
wire nmi; |
wire busrq; |
wire clk; |
wire intr; |
wire mwait; |
wire reset_in; |
wire pin_nM1; |
wire pin_nMREQ; |
wire pin_nIORQ; |
wire pin_nRD; |
wire pin_nWR; |
wire pin_nRFSH; |
wire pin_nHALT; |
wire pin_nBUSACK; |
/trunk/cpu/deploy/core.vh
0,0 → 1,81
//============================================================================ |
// A-Z80 core, instantiates and connects all internal blocks. |
// |
// This file is included by the "z80_top_ifc_n" and "z80_top_direct" providing |
// interface binding and direct (no interface) binding. |
//============================================================================ |
|
// Include a list of top-level signal wires |
`include "globals.vh" |
|
// Specific to Modelsim, some modules in the schematics need to be pre-initialized |
// to avoid starting simulations with unknown values in selected flip flops. |
// When synthesized, the CPU RESET input signal will do the work. |
reg fpga_reset = 0; |
initial begin |
fpga_reset = 1; |
#1 fpga_reset = 0; |
end |
|
// Define internal data bus partitions separated by data bus switches |
wire [7:0] db0; // Segment connecting data pins and IR |
wire [7:0] db1; // Segment with ALU |
wire [7:0] db2; // Segment with msb part of the register address-side interface |
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
// Control block |
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
// Collect the PLA instruction decode prefix bitfield |
logic [6:0] prefix; |
assign prefix = { ~use_ixiy, use_ixiy, ~in_halt, in_alu, table_xx, table_cb, table_ed }; |
|
ir instruction_reg_( .*, .db(db0[7:0]) ); |
pla_decode pla_decode_( .* ); |
resets reset_block_( .* ); |
sequencer sequencer_( .* ); |
execute execute_( .* ); |
interrupts interrupts_( .*, .db(db0[4:3]) ); |
decode_state decode_state_( .* ); |
clk_delay clk_delay_( .* ); |
pin_control pin_control_( .* ); |
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
// ALU and ALU control, including the flags |
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
alu_control alu_control_( .*, .db(db1[7:0]), .op543({pla[104],pla[103],pla[102]}) ); |
alu_select alu_select_( .* ); |
alu_flags alu_flags_( .*, .db(db1[7:0]) ); |
alu alu_( .*, .db(db2[7:0]), .bsel(db0[5:3]) ); |
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
// Register file and register control |
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
wire [7:0] db_hi_as; |
wire [7:0] db_lo_as; |
|
reg_file reg_file_( .*, .db_hi_ds(db2[7:0]), .db_lo_ds(db1[7:0]), .db_hi_as(db_hi_as[7:0]), .db_lo_as(db_lo_as[7:0]) ); |
reg_control reg_control_( .* ); |
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
// Address latch (with the incrementer) |
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
address_latch address_latch_( .*, .abus({db_hi_as[7:0], db_lo_as[7:0]}) ); |
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
// Timing control of the external pins |
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
wire nM1_int; |
assign nM1_int = !((setM1 & nextM) | (fFetch & T1)); |
memory_ifc memory_ifc_( .* ); |
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
// Data path within the CPU in various forms, ending with data pins |
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
bus_switch bus_switch_( .* ); |
data_switch sw2_( .sw_up_en(bus_sw_2u), .sw_down_en(bus_sw_2d), .db_up(db1[7:0]), .db_down(db2[7:0]) ); |
|
// Controls writers to the first section of the data bus |
bus_control bus_control_( .*, .db(db0[7:0]) ); |
|
// Data switch SW1 with the data mask |
data_switch_mask sw1_( .sw_mask543_en(bus_sw_mask543_en), .sw_up_en(bus_sw_1u), .sw_down_en(bus_sw_1d), .db_up(db0[7:0]), .db_down(db1[7:0]) ); |
/trunk/cpu/deploy/address_latch.v
0,0 → 1,121
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Sat Nov 08 12:52:27 2014" |
|
module address_latch( |
ctl_inc_cy, |
ctl_inc_dec, |
ctl_inc_zero, |
ctl_al_we, |
ctl_inc_limit6, |
ctl_bus_inc_oe, |
clk, |
ctl_apin_mux, |
ctl_apin_mux2, |
address_is_1, |
abus, |
address |
); |
|
|
input wire ctl_inc_cy; |
input wire ctl_inc_dec; |
input wire ctl_inc_zero; |
input wire ctl_al_we; |
input wire ctl_inc_limit6; |
input wire ctl_bus_inc_oe; |
input wire clk; |
input wire ctl_apin_mux; |
input wire ctl_apin_mux2; |
output wire address_is_1; |
inout wire [15:0] abus; |
output wire [15:0] address; |
|
reg [15:0] Q; |
wire SYNTHESIZED_WIRE_0; |
wire SYNTHESIZED_WIRE_1; |
wire SYNTHESIZED_WIRE_2; |
wire [15:0] SYNTHESIZED_WIRE_3; |
wire [15:0] SYNTHESIZED_WIRE_8; |
wire SYNTHESIZED_WIRE_5; |
wire [15:0] SYNTHESIZED_WIRE_6; |
|
|
|
|
|
always@(posedge clk) |
begin |
if (ctl_al_we) |
begin |
Q[15:0] <= abus[15:0]; |
end |
end |
|
assign SYNTHESIZED_WIRE_2 = ~ctl_inc_zero; |
|
assign address_is_1 = ~(SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1); |
|
assign SYNTHESIZED_WIRE_8 = {SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2} & SYNTHESIZED_WIRE_3; |
|
assign abus[15] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_8[15] : 1'bz; |
assign abus[14] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_8[14] : 1'bz; |
assign abus[13] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_8[13] : 1'bz; |
assign abus[12] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_8[12] : 1'bz; |
assign abus[11] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_8[11] : 1'bz; |
assign abus[10] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_8[10] : 1'bz; |
assign abus[9] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_8[9] : 1'bz; |
assign abus[8] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_8[8] : 1'bz; |
assign abus[7] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_8[7] : 1'bz; |
assign abus[6] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_8[6] : 1'bz; |
assign abus[5] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_8[5] : 1'bz; |
assign abus[4] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_8[4] : 1'bz; |
assign abus[3] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_8[3] : 1'bz; |
assign abus[2] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_8[2] : 1'bz; |
assign abus[1] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_8[1] : 1'bz; |
assign abus[0] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_8[0] : 1'bz; |
|
assign SYNTHESIZED_WIRE_0 = Q[7] | Q[5] | Q[6] | Q[4] | Q[2] | Q[3] | Q[1] | SYNTHESIZED_WIRE_5; |
|
assign SYNTHESIZED_WIRE_1 = Q[15] | Q[13] | Q[14] | Q[12] | Q[10] | Q[11] | Q[9] | Q[8]; |
|
|
address_mux b2v_inst7( |
.select(ctl_apin_mux2), |
.in0(SYNTHESIZED_WIRE_6), |
.in1(Q), |
.out(address)); |
|
|
inc_dec b2v_inst_inc_dec( |
.limit6(ctl_inc_limit6), |
.decrement(ctl_inc_dec), |
.carry_in(ctl_inc_cy), |
.d(Q), |
.address(SYNTHESIZED_WIRE_3)); |
|
|
address_mux b2v_mux( |
.select(ctl_apin_mux), |
.in0(abus), |
.in1(SYNTHESIZED_WIRE_8), |
.out(SYNTHESIZED_WIRE_6)); |
|
assign SYNTHESIZED_WIRE_5 = ~Q[0]; |
|
|
endmodule |
/trunk/cpu/deploy/pla_decode.sv
0,0 → 1,137
//===================================================================================== |
// This file is automatically generated by the z80_pla_checker tool. Do not edit! |
// |
// Copyright (C) 2014 Goran Devic |
// |
// This program is free software; you can redistribute it and/or modify it |
// under the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 of the License, or (at your option) |
// any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
// more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program; if not, write to the Free Software Foundation, Inc., |
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
//===================================================================================== |
module pla_decode (opcode, prefix, pla); |
|
input wire [6:0] prefix; |
input wire [7:0] opcode; |
output reg [104:0] pla; |
|
always_comb |
begin |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXX1_1010X0XX) pla[ 0]=1'b1; else pla[ 0]=1'b0; // ldx/cpx/inx/outx brk |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_11011001) pla[ 1]=1'b1; else pla[ 1]=1'b0; // exx |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_11101011) pla[ 2]=1'b1; else pla[ 2]=1'b0; // ex de,hl |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_11X11101) pla[ 3]=1'b1; else pla[ 3]=1'b0; // IX/IY prefix |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXX1_010XX111) pla[ 4]=1'b1; else pla[ 4]=1'b0; // ld x,a/a,x |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_11111001) pla[ 5]=1'b1; else pla[ 5]=1'b0; // ld sp,hl |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_11101001) pla[ 6]=1'b1; else pla[ 6]=1'b0; // jp hl |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_00XX0001) pla[ 7]=1'b1; else pla[ 7]=1'b0; // ld rr,nn |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_000XX010) pla[ 8]=1'b1; else pla[ 8]=1'b0; // ld (rr),a/a,(rr) |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_00XXX011) pla[ 9]=1'b1; else pla[ 9]=1'b0; // inc/dec rr |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_11100011) pla[ 10]=1'b1; else pla[ 10]=1'b0; // ex (sp),hl |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXX1_101XX001) pla[ 11]=1'b1; else pla[ 11]=1'b0; // cpi/cpir/cpd/cpdr |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXX1_101XX000) pla[ 12]=1'b1; else pla[ 12]=1'b0; // ldi/ldir/ldd/lddr |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_00XX0010) pla[ 13]=1'b1; else pla[ 13]=1'b0; // ld direction |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_00XX1011) pla[ 14]=1'b1; else pla[ 14]=1'b0; // dec rr |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXX1_0110X111) pla[ 15]=1'b1; else pla[ 15]=1'b0; // rrd/rld |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_11XX0101) pla[ 16]=1'b1; else pla[ 16]=1'b0; // push rr |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_00XXX110) pla[ 17]=1'b1; else pla[ 17]=1'b0; // ld r,n |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXX1_101XX011) pla[ 20]=1'b1; else pla[ 20]=1'b0; // outx/otxr |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXX1_101XX010) pla[ 21]=1'b1; else pla[ 21]=1'b0; // inx/inxr |
if ({prefix[6:0], opcode[7:0]} ==? 15'b1XXXXXX_11001011) pla[ 22]=1'b1; else pla[ 22]=1'b0; // CB prefix w/o IX/IY |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_11XX0X01) pla[ 23]=1'b1; else pla[ 23]=1'b0; // push/pop |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_11001101) pla[ 24]=1'b1; else pla[ 24]=1'b0; // call nn |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_000XX111) pla[ 25]=1'b1; else pla[ 25]=1'b0; // rlca/rla/rrca/rra |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_00010000) pla[ 26]=1'b1; else pla[ 26]=1'b0; // djnz e |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXX1_01XXX00X) pla[ 27]=1'b1; else pla[ 27]=1'b0; // in/out r,(c) |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_11010011) pla[ 28]=1'b1; else pla[ 28]=1'b0; // out (n),a |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_11000011) pla[ 29]=1'b1; else pla[ 29]=1'b0; // jp nn |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_0010X010) pla[ 30]=1'b1; else pla[ 30]=1'b0; // ld hl,(nn)/(nn),hl |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXX1_01XXX011) pla[ 31]=1'b1; else pla[ 31]=1'b0; // ld rr,(nn)/(nn),rr |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXX1_01XX0011) pla[ 33]=1'b1; else pla[ 33]=1'b0; // ld direction |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXX1_01XXX001) pla[ 34]=1'b1; else pla[ 34]=1'b0; // out (c),r |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_11001001) pla[ 35]=1'b1; else pla[ 35]=1'b0; // ret |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_1101X011) pla[ 37]=1'b1; else pla[ 37]=1'b0; // out (n),a/a,(n) |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_0011X010) pla[ 38]=1'b1; else pla[ 38]=1'b0; // ld (nn),a/a,(nn) |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_00001000) pla[ 39]=1'b1; else pla[ 39]=1'b0; // ex af,af' |
if ({prefix[6:0], opcode[7:0]} ==? 15'bX1XX1XX_00110110) pla[ 40]=1'b1; else pla[ 40]=1'b0; // ld (ix+d),n |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_11XXX100) pla[ 42]=1'b1; else pla[ 42]=1'b0; // call cc,nn |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_11XXX010) pla[ 43]=1'b1; else pla[ 43]=1'b0; // jp cc,nn |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_11001011) pla[ 44]=1'b1; else pla[ 44]=1'b0; // CB prefix |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_11XXX000) pla[ 45]=1'b1; else pla[ 45]=1'b0; // ret cc |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXX1_01XXX101) pla[ 46]=1'b1; else pla[ 46]=1'b0; // reti/retn |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_00011000) pla[ 47]=1'b1; else pla[ 47]=1'b0; // jr e |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_001XX000) pla[ 48]=1'b1; else pla[ 48]=1'b0; // jr ss,e |
if ({prefix[6:0], opcode[7:0]} ==? 15'bX1XXXXX_11001011) pla[ 49]=1'b1; else pla[ 49]=1'b0; // CB prefix with IX/IY |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_00110110) pla[ 50]=1'b1; else pla[ 50]=1'b0; // ld (hl),n |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_11101101) pla[ 51]=1'b1; else pla[ 51]=1'b0; // ED prefix |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_10XXX110) pla[ 52]=1'b1; else pla[ 52]=1'b0; // add/sub/and/or/xor/cp (hl) |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_0011010X) pla[ 53]=1'b1; else pla[ 53]=1'b0; // inc/dec (hl) |
if ({prefix[6:0], opcode[7:0]} ==? 15'bX1XXX1X_XXXXXXXX) pla[ 54]=1'b1; else pla[ 54]=1'b0; // Every CB with IX/IY |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXX1X_XXXXX110) pla[ 55]=1'b1; else pla[ 55]=1'b0; // Every CB op (hl) |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_11XXX111) pla[ 56]=1'b1; else pla[ 56]=1'b0; // rst p |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXX1_0100X111) pla[ 57]=1'b1; else pla[ 57]=1'b0; // ld i,a/r,a |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXX1X1XX_01XXX110) pla[ 58]=1'b1; else pla[ 58]=1'b0; // ld r,(hl) |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXX1X1XX_01110XXX) pla[ 59]=1'b1; else pla[ 59]=1'b0; // ld (hl),r |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_01XXXXXX) pla[ 61]=1'b1; else pla[ 61]=1'b0; // ld r,r' |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXX1X_XXXXXXXX) pla[ 62]=1'b1; else pla[ 62]=1'b0; // For all CB opcodes |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_11XXX110) pla[ 64]=1'b1; else pla[ 64]=1'b0; // add/sub/and/or/xor/cmp a,imm |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_10XXXXXX) pla[ 65]=1'b1; else pla[ 65]=1'b0; // add/sub/and/or/xor/cmp a,r |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_00XXX10X) pla[ 66]=1'b1; else pla[ 66]=1'b0; // inc/dec r |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXX1_01XXX000) pla[ 67]=1'b1; else pla[ 67]=1'b0; // in |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXX1_01XXX010) pla[ 68]=1'b1; else pla[ 68]=1'b0; // adc/sbc hl,rr |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_00XX1001) pla[ 69]=1'b1; else pla[ 69]=1'b0; // add hl,rr |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXX1X_00XXXXXX) pla[ 70]=1'b1; else pla[ 70]=1'b0; // rlc r |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXX1X_01XXXXXX) pla[ 72]=1'b1; else pla[ 72]=1'b0; // bit b,r |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXX1X_10XXXXXX) pla[ 73]=1'b1; else pla[ 73]=1'b0; // res b,r |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXX1X_11XXXXXX) pla[ 74]=1'b1; else pla[ 74]=1'b0; // set b,r |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_00XXX101) pla[ 75]=1'b1; else pla[ 75]=1'b0; // dec r |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXX1XXX_XX111XXX) pla[ 76]=1'b1; else pla[ 76]=1'b0; // 111 (CP) |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_00100111) pla[ 77]=1'b1; else pla[ 77]=1'b0; // daa |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXX1XXX_XX010XXX) pla[ 78]=1'b1; else pla[ 78]=1'b0; // 010 (SUB) |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXX1XXX_XX011XXX) pla[ 79]=1'b1; else pla[ 79]=1'b0; // 011 (SBC) |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXX1XXX_XX001XXX) pla[ 80]=1'b1; else pla[ 80]=1'b0; // 001 (ADC) |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_00101111) pla[ 81]=1'b1; else pla[ 81]=1'b0; // cpl |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXX1_01XXX100) pla[ 82]=1'b1; else pla[ 82]=1'b0; // neg |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXX1_0101X111) pla[ 83]=1'b1; else pla[ 83]=1'b0; // ld a,i/a,r |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXX1XXX_XX000XXX) pla[ 84]=1'b1; else pla[ 84]=1'b0; // 000 (ADD) |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXX1XXX_XX100XXX) pla[ 85]=1'b1; else pla[ 85]=1'b0; // 100 (AND) |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXX1XXX_XX110XXX) pla[ 86]=1'b1; else pla[ 86]=1'b0; // 110 (OR) |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXX1XXX_XX101XXX) pla[ 88]=1'b1; else pla[ 88]=1'b0; // 101 (XOR) |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_00111111) pla[ 89]=1'b1; else pla[ 89]=1'b0; // ccf |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXX1_101XX01X) pla[ 91]=1'b1; else pla[ 91]=1'b0; // inx/outx/inxr/otxr |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_00110111) pla[ 92]=1'b1; else pla[ 92]=1'b0; // scf |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_01110110) pla[ 95]=1'b1; else pla[ 95]=1'b0; // halt |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXX1_01XXX110) pla[ 96]=1'b1; else pla[ 96]=1'b0; // im n |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXX1XX_1111X011) pla[ 97]=1'b1; else pla[ 97]=1'b0; // di/ei |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXXX_XXXXXXX1) pla[ 99]=1'b1; else pla[ 99]=1'b0; // opcode[0] |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXXX_XXXXXX1X) pla[100]=1'b1; else pla[100]=1'b0; // opcode[1] |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXXX_XXXXX1XX) pla[101]=1'b1; else pla[101]=1'b0; // opcode[2] |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXXX_XXXX1XXX) pla[102]=1'b1; else pla[102]=1'b0; // opcode[3] |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXXX_XXX1XXXX) pla[103]=1'b1; else pla[103]=1'b0; // opcode[4] |
if ({prefix[6:0], opcode[7:0]} ==? 15'bXXXXXXX_XX1XXXXX) pla[104]=1'b1; else pla[104]=1'b0; // opcode[5] |
|
// Duplicate or ignored entries |
pla[ 18]=1'b0; // ldi/ldir/ldd/lddr |
pla[ 19]=1'b0; // cpi/cpir/cpd/cpdr |
pla[ 32]=1'b0; // ld i,a/a,i/r,a/a,r |
pla[ 36]=1'b0; // ld(rr),a/a,(rr) |
pla[ 41]=1'b0; // IX/IY |
pla[ 60]=1'b0; // rrd/rld |
pla[ 63]=1'b0; // ld r,* |
pla[ 71]=1'b0; // rlca/rla/rrca/rra |
pla[ 87]=1'b0; // ld a,i / ld a,r |
pla[ 90]=1'b0; // djnz * |
pla[ 93]=1'b0; // cpi/cpir/cpd/cpdr |
pla[ 94]=1'b0; // ldi/ldir/ldd/lddr |
pla[ 98]=1'b0; // out (*),a/in a,(*) |
end |
|
endmodule |
/trunk/cpu/deploy/inc_dec_2bit.v
0,0 → 1,54
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Mon Oct 13 12:26:57 2014" |
|
module inc_dec_2bit( |
carry_borrow_in, |
d1_in, |
d0_in, |
dec1_in, |
dec0_in, |
carry_borrow_out, |
d1_out, |
d0_out |
); |
|
|
input wire carry_borrow_in; |
input wire d1_in; |
input wire d0_in; |
input wire dec1_in; |
input wire dec0_in; |
output wire carry_borrow_out; |
output wire d1_out; |
output wire d0_out; |
|
wire SYNTHESIZED_WIRE_0; |
|
|
|
|
assign SYNTHESIZED_WIRE_0 = dec0_in & carry_borrow_in; |
|
assign carry_borrow_out = dec0_in & dec1_in & carry_borrow_in; |
|
assign d1_out = d1_in ^ SYNTHESIZED_WIRE_0; |
|
assign d0_out = carry_borrow_in ^ d0_in; |
|
|
endmodule |
/trunk/cpu/deploy/data_switch_mask.v
0,0 → 1,68
// Copyright (C) 1991-2013 Altera Corporation |
// Your use of Altera Corporation's design tools, logic functions |
// and other software and tools, and its AMPP partner logic |
// functions, and any output files from any of the foregoing |
// (including device programming or simulation files), and any |
// associated documentation or information are expressly subject |
// to the terms and conditions of the Altera Program License |
// Subscription Agreement, Altera MegaCore Function License |
// Agreement, or other applicable license agreement, including, |
// without limitation, that your use is for the sole purpose of |
// programming logic devices manufactured by Altera and sold by |
// Altera or its authorized distributors. Please refer to the |
// applicable agreement for further details. |
|
// PROGRAM "Quartus II 64-Bit" |
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" |
// CREATED "Mon Oct 13 12:32:03 2014" |
|
module data_switch_mask( |
sw_up_en, |
sw_down_en, |
sw_mask543_en, |
db_down, |
db_up |
); |
|
|
input wire sw_up_en; |
input wire sw_down_en; |
input wire sw_mask543_en; |
inout wire [7:0] db_down; |
inout wire [7:0] db_up; |
|
wire SYNTHESIZED_WIRE_4; |
wire [1:0] SYNTHESIZED_WIRE_1; |
wire [2:0] SYNTHESIZED_WIRE_2; |
|
|
|
|
assign SYNTHESIZED_WIRE_4 = ~sw_mask543_en; |
|
assign SYNTHESIZED_WIRE_1 = db_up[7:6] & {SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_4}; |
|
assign db_down[7] = sw_down_en ? SYNTHESIZED_WIRE_1[1] : 1'bz; |
assign db_down[6] = sw_down_en ? SYNTHESIZED_WIRE_1[0] : 1'bz; |
|
assign db_down[2] = sw_down_en ? SYNTHESIZED_WIRE_2[2] : 1'bz; |
assign db_down[1] = sw_down_en ? SYNTHESIZED_WIRE_2[1] : 1'bz; |
assign db_down[0] = sw_down_en ? SYNTHESIZED_WIRE_2[0] : 1'bz; |
|
assign SYNTHESIZED_WIRE_2 = db_up[2:0] & {SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_4}; |
|
assign db_up[7] = sw_up_en ? db_down[7] : 1'bz; |
assign db_up[6] = sw_up_en ? db_down[6] : 1'bz; |
assign db_up[5] = sw_up_en ? db_down[5] : 1'bz; |
assign db_up[4] = sw_up_en ? db_down[4] : 1'bz; |
assign db_up[3] = sw_up_en ? db_down[3] : 1'bz; |
assign db_up[2] = sw_up_en ? db_down[2] : 1'bz; |
assign db_up[1] = sw_up_en ? db_down[1] : 1'bz; |
assign db_up[0] = sw_up_en ? db_down[0] : 1'bz; |
|
assign db_down[5] = sw_down_en ? db_up[5] : 1'bz; |
assign db_down[4] = sw_down_en ? db_up[4] : 1'bz; |
assign db_down[3] = sw_down_en ? db_up[3] : 1'bz; |
|
|
endmodule |
/trunk/cpu/deploy/readme.txt
0,0 → 1,14
A-Z80 Release/Deployment files |
============================== |
This folder contains all Verilog/SystemVerilog files needed to deploy and use |
the CPU. Simply include all *.v and *.sv files in your project and make sure |
that those few remaining files (*.vh) are accessible to be included. |
|
An example of using deployment files is a "host/zxspectrum" project. |
|
Note: These files are manually picked and copied from their respective modules. |
That means there is always a risk of them getting out of date in some |
scenarios. |
|
Alternatively, you may want to include CPU files from their original location. |
An example of doing that is a "host/basic" project. |
/trunk/docs/A-Z80_UsersGuide.pdf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/trunk/docs/A-Z80_UsersGuide.docx
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/trunk/host/zxspectrum/zxspectrum_board.qsf
590,45 → 590,45
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON |
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON |
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA |
set_global_assignment -name VERILOG_FILE ../../cpu/registers/reg_latch.v |
set_global_assignment -name VERILOG_FILE ../../cpu/registers/reg_file.v |
set_global_assignment -name VERILOG_FILE ../../cpu/registers/reg_control.v |
set_global_assignment -name VERILOG_FILE ../../cpu/control/sequencer.v |
set_global_assignment -name VERILOG_FILE ../../cpu/control/resets.v |
set_global_assignment -name VERILOG_FILE ../../cpu/control/ir.v |
set_global_assignment -name VERILOG_FILE ../../cpu/control/interrupts.v |
set_global_assignment -name VERILOG_FILE ../../cpu/control/decode_state.v |
set_global_assignment -name VERILOG_FILE ../../cpu/control/clk_delay.v |
set_global_assignment -name VERILOG_FILE ../../cpu/control/pin_control.v |
set_global_assignment -name SYSTEMVERILOG_FILE ../../cpu/control/pla_decode.sv |
set_global_assignment -name VERILOG_FILE ../../cpu/control/memory_ifc.v |
set_global_assignment -name SYSTEMVERILOG_FILE ../../cpu/control/execute.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ../../cpu/bus/bus_switch.sv |
set_global_assignment -name VERILOG_FILE ../../cpu/bus/inc_dec_2bit.v |
set_global_assignment -name VERILOG_FILE ../../cpu/bus/inc_dec.v |
set_global_assignment -name VERILOG_FILE ../../cpu/bus/data_switch_mask.v |
set_global_assignment -name VERILOG_FILE ../../cpu/bus/data_switch.v |
set_global_assignment -name VERILOG_FILE ../../cpu/bus/data_pins.v |
set_global_assignment -name VERILOG_FILE ../../cpu/bus/control_pins_n.v |
set_global_assignment -name VERILOG_FILE ../../cpu/bus/bus_control.v |
set_global_assignment -name VERILOG_FILE ../../cpu/bus/address_pins.v |
set_global_assignment -name VERILOG_FILE ../../cpu/bus/address_latch.v |
set_global_assignment -name VERILOG_FILE ../../cpu/bus/address_mux.v |
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_slice.v |
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_shifter_core.v |
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_select.v |
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_prep_daa.v |
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_mux_8.v |
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_mux_4.v |
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_mux_3z.v |
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_mux_2z.v |
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_mux_2.v |
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_flags.v |
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_core.v |
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_control.v |
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_bit_select.v |
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu.v |
set_global_assignment -name SYSTEMVERILOG_FILE ../../cpu/toplevel/z80_top_direct_n.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ../../cpu/deploy/z80_top_direct_n.sv |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/sequencer.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/resets.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/reg_latch.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/reg_file.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/reg_control.v |
set_global_assignment -name SYSTEMVERILOG_FILE ../../cpu/deploy/pla_decode.sv |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/pin_control.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/memory_ifc.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/ir.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/interrupts.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/inc_dec_2bit.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/inc_dec.v |
set_global_assignment -name SYSTEMVERILOG_FILE ../../cpu/deploy/execute.sv |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/decode_state.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/data_switch_mask.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/data_switch.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/data_pins.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/control_pins_n.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/clk_delay.v |
set_global_assignment -name SYSTEMVERILOG_FILE ../../cpu/deploy/bus_switch.sv |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/bus_control.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_slice.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_shifter_core.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_select.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_prep_daa.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_mux_8.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_mux_4.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_mux_3z.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_mux_2z.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_mux_2.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_flags.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_core.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_control.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_bit_select.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/address_pins.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/address_mux.v |
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/address_latch.v |
set_global_assignment -name SYSTEMVERILOG_FILE ula/zx_kbd.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ula/video.sv |
set_global_assignment -name SYSTEMVERILOG_FILE ula/ula.sv |