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URL https://opencores.org/ocsvn/ac97/ac97/trunk

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  • This comparison shows the changes necessary to convert path 
    /ac97/trunk/syn
    from Rev 17 to Rev 20
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Rev 17 → Rev 20

/bin/read.dc
0,0 → 1,66
###############################################################################
#
# Pre Synthesis Script
#
# This script only reads in the design and saves it in a DB file
#
# Author: Rudolf Usselmann
# rudi@asics.ws
#
# Revision:
# 3/7/01 RU Initial Sript
#
#
###############################################################################
 
# ==============================================
# Setup Design Parameters
source ../bin/design_spec.dc
 
# ==============================================
# Setup Libraries
source ../bin/lib_spec.dc
 
# ==============================================
# Setup File IO
 
append log_file ../log/$active_design "_pre.log"
append pre_comp_db_file ../out/$design_name "_pre.db"
sh rm -f $log_file
 
# ==============================================
# Setup Misc Variables
 
set hdlin_enable_vpp true ;# Important - this enables 'ifdefs
 
# ==============================================
# Read Design
 
echo "+++++++++ Analyzing all design files ..." >> $log_file
 
foreach module $design_files {
echo "+++++++++ Reading: $module" >> $log_file
echo +++++++++ Reading: $module
set module_file_name ""
append module_file_name $module ".v"
analyze -f verilog $module_file_name >> $log_file
elaborate $module >> $log_file
}
 
current_design $active_design
 
echo "+++++++++ Linking Design ..." >> $log_file
link >> $log_file
 
echo "+++++++++ Uniquifying Design ..." >> $log_file
uniquify >> $log_file
 
echo "+++++++++ Checking Design ..." >> $log_file
check_design >> $log_file
 
# ==============================================
# Save Design
echo "+++++++++ Saving Design ..." >> $log_file
write_file -hierarchy -format db -output $pre_comp_db_file
 
 
/bin/comp.dc
0,0 → 1,125
###############################################################################
#
# Actual Synthesis Script
#
# This script does the actual synthesis
#
# Author: Rudolf Usselmann
# rudi@asics.ws
#
# Revision:
# 3/7/01 RU Initial Sript
#
#
###############################################################################
 
# ==============================================
# Setup Design Parameters
source ../bin/design_spec.dc
 
# ==============================================
# Setup Libraries
source ../bin/lib_spec.dc
 
# ==============================================
# Setup File IO
 
set junk_file /dev/null
append log_file ../log/$active_design "_cmp.log"
append pre_comp_db_file ../out/$design_name "_pre.db"
append post_comp_db_file ../out/$design_name ".db"
append post_syn_verilog_file ../out/$design_name "_ps.v"
 
sh rm -f $log_file
# ==============================================
# Setup Misc Variables
 
set hdlin_enable_vpp true ;# Important - this enables 'ifdefs
 
# ==============================================
# Read Design
 
echo "+++++++++ Reading Design ..." >> $log_file
read_file $pre_comp_db_file >> $log_file
 
# ==============================================
# Operating conditions
 
echo "+++++++++ Setting up Operation Conditions ..." >> $log_file
current_design $design_name
set_operating_conditions WORST >> $log_file
 
# ==============================================
# Setup Clocks and Resets
 
echo "+++++++++ Setting up Clocks ..." >> $log_file
 
set_drive 0 [find port {*clk}]
# !!! WISHBONE Clock !!!
set clock_period 5
create_clock -period $clock_period clk
set_clock_skew -uncertainty 0.1 clk
set_clock_transition 0.5 clk
set_dont_touch_network clk
 
# !!! BIT Clock !!!
set clock_period 500
create_clock -period $clock_period bit_clk
set_clock_skew -uncertainty 0.1 bit_clk
set_clock_transition 0.5 bit_clk
set_dont_touch_network bit_clk
# !!! Reset !!!
set_drive 0 [find port {rst*}]
set_dont_touch_network [find port {rst*}]
 
# ==============================================
# Setup IOs
 
echo "+++++++++ Setting up IOs ..." >> $log_file
 
# Need to spell out external IOs
 
set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file
set_load 0.2 [all_outputs]
 
set_input_delay -max 1 -clock clk [all_inputs]
set_output_delay -max 1 -clock clk [all_outputs]
 
set_input_delay -max 1 -clock bit_clk sdata_in
set_output_delay -max 1 -clock bit_clk sdata_out
 
# ==============================================
# Setup Area Constrains
set_max_area 0.0
 
# ==============================================
# Force Ultra
set_ultra_optimization -f
 
# ==============================================
# Compile Design
 
echo "+++++++++ Starting Compile ..." >> $log_file
#compile -map_effort medium -area_effort medium -ungroup_all >> $log_file
compile -map_effort low -area_effort low >> $log_file
#compile -map_effort high -area_effort high -ungroup_all >> $log_file
#compile -map_effort high -area_effort high -auto_ungroup >> $log_file
 
# ==============================================
# Write Out the optimized design
 
echo "+++++++++ Saving Optimized Design ..." >> $log_file
write_file -format verilog -output $post_syn_verilog_file
write_file -hierarchy -format db -output $post_comp_db_file
 
# ==============================================
# Create Some Basic Reports
 
echo "+++++++++ Reporting Final Results ..." >> $log_file
report_timing -nworst 10 >> $log_file
report_area >> $log_file
 
 
 
/bin/lib_spec.dc
0,0 → 1,36
###############################################################################
#
# Library Specification
#
# Author: Rudolf Usselmann
# rudi@asics.ws
#
# Revision:
# 3/7/01 RU Initial Sript
#
#
###############################################################################
 
# ==============================================
# Setup Libraries
 
set search_path [list $search_path . \
/tools/dc_libraries/umc/umc_0.18/UMCL18U250D2_2.1/design_compiler/ \
$hdl_src_dir]
 
set snps [getenv "SYNOPSYS"]
 
set synthetic_library ""
append synthetic_library $snps "/libraries/syn/dw01.sldb "
append synthetic_library $snps "/libraries/syn/dw02.sldb "
append synthetic_library $snps "/libraries/syn/dw03.sldb "
append synthetic_library $snps "/libraries/syn/dw04.sldb "
append synthetic_library $snps "/libraries/syn/dw05.sldb "
append synthetic_library $snps "/libraries/syn/dw06.sldb "
append synthetic_library $snps "/libraries/syn/dw07.sldb "
 
set target_library { umcl18u250t2_typ.db }
set link_library ""
append link_library $target_library " " $synthetic_library
set symbol_library { umcl18u250t2.sdb }
 
/bin/design_spec.dc
0,0 → 1,26
###############################################################################
#
# Design Specification
#
# Author: Rudolf Usselmann
# rudi@asics.ws
#
# Revision:
# 3/7/01 RU Initial Sript
#
#
###############################################################################
 
# ==============================================
# Setup Design Parameters
 
set design_files {ac97_fifo_ctrl ac97_dma_req ac97_cra ac97_prc ac97_soc ac97_in_fifo ac97_rf ac97_sout ac97_dma_if ac97_int ac97_rst ac97_out_fifo ac97_sin ac97_wb_if ac97_top}
 
set design_name ac97_top
set active_design ac97_top
# Next Statement defines all clocks and resets in the design
set special_net {rst clk bit_clk}
set hdl_src_dir ../../rtl/verilog/
 

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