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/adv_dbg_tb.v
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//////////////////////////////////////////////////////////////////////
//// ////
//// adv_dbg_tb.v ////
//// ////
//// ////
//// Testbench for the SoC Advanced Debug Interface. ////
//// ////
//// Author(s): ////
//// Nathan Yawn (nathan.yawn@opencores.org) ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: adv_dbg_tb.v,v $
// Revision 1.4 2009/05/17 20:54:55 Nathan
// Changed email address to opencores.org
//
// Revision 1.3 2008/07/11 08:18:47 Nathan
// Added a bit to the CPU test. Added the hack that allows the driver to work with a Xilinx BSCAN device.
//
 
 
`include "tap_defines.v"
`include "dbg_defines.v"
`include "dbg_wb_defines.v"
 
 
// Polynomial for the CRC calculation
// Yes, it's backwards. Yes, this is on purpose.
// To decrease logic + routing, we want to shift the CRC calculation
// in the same direction we use to shift the data out, LSB first.
`define DBG_CRC_POLY 32'hedb88320
 
// These are indicies into an array which hold values for the JTAG outputs
`define JTAG_TMS 0
`define JTAG_TCK 1
`define JTAG_TDO 2
 
`define JTAG_TMS_bit 3'h1
`define JTAG_TCK_bit 3'h2
`define JTAG_TDO_bit 3'h4
 
`define wait_jtag_period #50
 
 
module adv_debug_tb (
 
jtag_tck_o,
jtag_tms_o,
jtag_tdo_o,
jtag_tdi_i,
 
wb_clk_o,
sys_rstn_o
 
 
);
 
output jtag_tck_o;
output jtag_tms_o;
output jtag_tdo_o;
input jtag_tdi_i;
output wb_clk_o;
output sys_rstn_o;
 
// Connections to the JTAG TAP
reg jtag_tck_o;
reg jtag_tms_o;
reg jtag_tdo_o;
wire jtag_tdi_i;
 
reg wb_clk_o;
reg sys_rst_o;
reg sys_rstn_o;
reg test_enabled;
 
// Data which will be written to the WB interface
reg [31:0] static_data32 [0:15];
reg [15:0] static_data16 [0:15];
reg [7:0] static_data8 [0:15];
 
// Arrays to hold data read back from the WB interface, for comparison
reg [31:0] input_data32 [0:15];
reg [15:0] input_data16 [0:15];
reg [7:0] input_data8 [0:15];
 
reg [32:0] err_data; // holds the contents of the error register from the various modules
 
reg failed;
integer i;
 
initial
begin
jtag_tck_o = 1'b0;
jtag_tms_o = 1'b0;
jtag_tdo_o = 1'b0;
end
 
// Provide the wishbone / CPU / system clock
initial
begin
wb_clk_o = 1'b0;
forever #5 wb_clk_o = ~wb_clk_o;
end
 
initial
begin
sys_rstn_o = 1'b1;
#200 sys_rstn_o = 1'b0;
#5000 sys_rstn_o = 1'b1;
end
 
 
// Start the test (and reset the wishbone)
initial
begin
test_enabled = 1'b0;
 
// Init the memory
initialize_memory(32'h0,32'h16);
 
#5 test_enabled<= 1'b1;
end
 
// This is the main test procedure
always @ (posedge test_enabled)
begin
 
$display("Starting advanced debug test");
reset_jtag;
#6000;
check_idcode;
#1000;
// Select the debug module in the IR
set_ir(`DEBUG);
#1000;
`ifdef DBG_CPU0_SUPPORTED
// STALL the CPU, so it won't interfere with WB tests
// Select the CPU0 unit in the debug module
#1000;
$display("Selecting CPU0 module at time %t", $time);
select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
 
// Set the stall bit...holding the CPU in reset prevents WB access (?)
$display("Setting reset and stall bits at time %t", $time);
write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h2); // idx, idxlen, data, datalen
#1000;
`endif
///////////////////////////////////////////////////////////////////
// Test the Wishbone unit
////////////////////////////////////////////////////////////////////
`ifdef DBG_WISHBONE_SUPPORTED
// Select the WB unit in the debug module
#1000;
$display("Selecting Wishbone module at time %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
// Reset the error bit
write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h1); // idx, idxlen, data, datalen
#1000;
/////////////////////////////////
// Test 8-bit WB access
failed = 0;
$display("Testing WB 8-bit burst write at time %t: resetting ", $time);
do_module_burst_write(3'h1, 16'd16, 32'h87); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
#1000;
$display("Testing WB 8-bit burst read at time %t", $time);
do_module_burst_read(3'h1, 16'd16, 32'h87);
#1000;
for(i = 0; i < 16; i = i+1) begin
if(static_data8[i] != input_data8[i]) begin
failed = 1;
$display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data8[i], input_data8[i]);
end
end
if(!failed) $display("8-bit read/write OK!");
/////////////////////////////////
// Test 16-bit WB access
failed = 0;
$display("Testing WB 16-bit burst write at time %t", $time);
do_module_burst_write(3'h2, 16'd16, 32'h22); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
#1000;
$display("Testing WB 16-bit burst read at time %t", $time);
do_module_burst_read(3'h2, 16'd16, 32'h22);
#1000;
for(i = 0; i < 16; i = i+1) begin
if(static_data16[i] != input_data16[i]) begin
failed = 1;
$display("16-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data16[i], input_data16[i]);
end
end
if(!failed) $display("16-bit read/write OK!");
////////////////////////////////////
// Test 32-bit WB access
failed = 0;
$display("Testing WB 32-bit burst write at time %t", $time);
do_module_burst_write(3'h4, 16'd16, 32'h100); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
#1000;
$display("Testing WB 32-bit burst read at time %t", $time);
do_module_burst_read(3'h4, 16'd16, 32'h100);
#1000;
for(i = 0; i < 16; i = i+1) begin
if(static_data32[i] != input_data32[i]) begin
failed = 1;
$display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data32[i], input_data32[i]);
end
end
if(!failed) $display("32-bit read/write OK!");
////////////////////////////////
// Test error register
err_data = 33'h0;
// Select and reset the error register
write_module_internal_register(`DBG_WB_INTREG_ERROR, `DBG_WB_REGSELECT_SIZE, 64'h1, 8'h1); // regidx,idxlen,writedata, datalen;
//i_wb.cycle_response(`ERR_RESPONSE, 2, 0); // response type, wait cycles, retry_cycles
do_module_burst_write(3'h4, 16'd4, 32'hdeaddead); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
read_module_internal_register(8'd33, err_data); // get the error register
$display("Error bit is %d, error address is %x", err_data[0], err_data>>1);
 
`endif // WB module supported
///////////////////////////////////////////////////////////////////
// Test CPU0 unit
////////////////////////////////////////////////////////////////////
`ifdef DBG_CPU0_SUPPORTED
// Select the CPU0 unit in the debug module
#1000;
$display("Selecting CPU0 module at time %t", $time);
select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
 
// Set the stall bit (clear the reset bit)
$display("Setting reset and stall bits at time %t", $time);
write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h2); // idx, idxlen, data, datalen
#1000;
// Make sure CPU stalled
$display("Testing reset and stall bits at time %t", $time);
read_module_internal_register(8'd2, err_data); // We assume the register is already selected
$display("Reset and stall bits are %x", err_data);
#1000;
 
// Write some opcodes into the memory
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
 
static_data32[0] = 32'hE0000005;/* l.xor r0,r0,r0 */
static_data32[1] = 32'h9C200000; /* l.addi r1,r0,0x0 */
static_data32[2] = 32'h18400000;/* l.movhi r2,0x4000 */
static_data32[3] = 32'hA8420030;/* l.ori r2,r2,0x30 */
static_data32[4] = 32'h9C210001;/* l.addi r1,r1,1 */
static_data32[5] = 32'h9C210001; /* l.addi r1,r1,1 */
static_data32[6] = 32'hD4020800;/* l.sw 0(r2),r1 */
static_data32[7] = 32'h9C210001;/* l.addi r1,r1,1 */
static_data32[8] = 32'h84620000;/* l.lwz r3,0(r2) */
static_data32[9] = 32'h03FFFFFB;/* l.j loop2 */
static_data32[10] = 32'hE0211800;/* l.add r1,r1,r3 */
 
do_module_burst_write(3'h4, 16'd11, 32'h0); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
 
#1000;
select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
 
#1000;
$display("Enabling CPU exceptions at time %t", $time);
static_data32[0] = 32'h1; // enable exceptions
do_module_burst_write(3'h4, 16'd1, 32'd17); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
 
#1000;
$display("Set \'trap causes stall\' at time %t", $time);
static_data32[0] = 32'h00002000; // Trap causes stall
do_module_burst_write(3'h4, 16'd1, (6 << 11)+20); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
 
#1000;
$display("Set PC at time %t", $time);
static_data32[0] = 32'h0; // Set PC
do_module_burst_write(3'h4, 16'd1, 32'd16); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
 
#1000;
$display("Set step bit at time %t", $time);
static_data32[0] = (1 << 22); // set step bit
do_module_burst_write(3'h4, 16'd1, (6<<11) + 16); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
 
// Unstall x11
for(i = 0; i < 11; i = i + 1)
begin
#1000;
$display("Unstall (%d/11) at time %t", i, $time);
write_module_internal_register(32'h0, 8'h1, 32'h0, 8'h2); // idx, idxlen, data, datalen
end
 
#1000;
#1000;
#1000;
 
$display("Getting NPC at time %t", $time);
do_module_burst_read(3'h4, 16'd1, 32'd16);
$display("NPC = %x, expected 0x00000010", input_data32[0]);
$display("Getting PPC at time %t", $time);
do_module_burst_read(3'h4, 16'd1, 32'd18);
$display("PPC = %x, expected 0x00000028", input_data32[0]);
#1000;
$display("Getting R1 at time %t", $time);
do_module_burst_read(3'h4, 16'd1, 32'h401); // Word size, count, addr; save old instr
$display("R1 = %d, expected 5", input_data32[0]);
#1000;
$display("Un-set step bit at %t", $time);
static_data32[0] = 32'h0; // Trap causes stall
do_module_burst_write(3'h4, 16'd1, (6 << 11)+16);
// Put a trap instr at 0x20
#1000;
$display("Select WB at %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
#1000;
$display("Save old instr at %t", $time);
do_module_burst_read(3'h4, 16'd1, 32'h20); // Save old instr
#1000;
$display("Put trap instr at %t", $time);
static_data32[0] = 32'h21000001; /* l.trap */
do_module_burst_write(3'h4, 16'd1, 32'h20); // put new instr
#1000;
$display("Select CPU0 at %t", $time);
select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
#1000;
$display("Set PC to 0x24 at %t", $time);
static_data32[0] = 32'h24;
do_module_burst_write(3'h4, 16'd1, 32'd16); // Set PC to 0x24
#1000;
$display("Unstall at time %t", $time);
write_module_internal_register(32'h0, 8'h1, 32'h0, 8'h2); // idx, idxlen, data, datalen
 
// We assume it stalls again here...
#1000;
 
err_data = 1;
while(err_data != 0)
begin
$display("Testing for stall at %t", $time);
read_module_internal_register(8'd2, err_data); // We assume the register is already selected
#1000;
end
 
 
// *** The software self-test does 2 separate reads here...
$display("Getting NPC at time %t", $time);
do_module_burst_read(3'h4, 16'd3, 32'd16);
$display("NPC = %x, expected 0x00000024", input_data32[0]);
$display("PPC = %x, expected 0x00000020", input_data32[2]);
 
 
 
`endif
 
end
 
task initialize_memory;
input [31:0] start_addr;
input [31:0] length;
integer i;
reg [31:0] addr;
begin
 
for (i=0; i<length; i=i+1)
begin
static_data32[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
static_data16[i] <= {i[7:0], i[7:0]+ 2'd1};
static_data8[i] <= i[7:0];
end
end
endtask
 
 
///////////////////////////////////////////////////////////////////////////
// Higher-level chain manipulation functions
 
// calculate the CRC, up to 32 bits at a time
task compute_crc;
input [31:0] crc_in;
input [31:0] data_in;
input [5:0] length_bits;
output [31:0] crc_out;
integer i;
reg [31:0] d;
reg [31:0] c;
begin
crc_out = crc_in;
for(i = 0; i < length_bits; i = i+1) begin
d = (data_in[i]) ? 32'hffffffff : 32'h0;
c = (crc_out[0]) ? 32'hffffffff : 32'h0;
//crc_out = {crc_out[30:0], 1'b0}; // original
crc_out = crc_out >> 1;
crc_out = crc_out ^ ((d ^ c) & `DBG_CRC_POLY);
//$display("CRC Itr %d, inbit = %d, crc = 0x%x", i, data_in[i], crc_out);
end
end
endtask
 
task check_idcode;
reg [63:0] readdata;
reg[31:0] idcode;
begin
set_ir(`IDCODE);
// Read the IDCODE in the DR
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_read_write_stream(64'h0, 8'd32, 1, readdata); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
idcode = readdata[31:0];
$display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);
end
endtask;
 
task select_debug_module;
input [1:0] moduleid;
reg validid;
begin
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream({1'b1,moduleid}, 8'h3, 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
$display("Selecting module (%0x)", moduleid);
// Read back the status to make sure a valid chain is selected
/* Pointless, the newly selected module would respond instead...
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
read_write_bit(`JTAG_TMS_bit, validid); // get data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
if(validid) $display("Selected valid module (%0x)", moduleid);
else $display("Failed to select module (%0x)", moduleid);
*/
end
endtask
 
 
task send_module_burst_command;
input [3:0] opcode;
input [31:0] address;
input [15:0] burstlength;
reg [63:0] streamdata;
begin
streamdata = {11'h0,1'b0,opcode,address,burstlength};
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream(streamdata, 8'd53, 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
end
endtask
 
task select_module_internal_register; // Really just a read, with discarded data
input [31:0] regidx;
input [7:0] len; // the length of the register index data, we assume not more than 32
reg[63:0] streamdata;
begin
streamdata = 64'h0;
streamdata = streamdata | regidx;
streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream(streamdata, (len+5), 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
end
endtask
 
task read_module_internal_register; // We assume the register is already selected
//input [31:0] regidx;
input [7:0] len; // the length of the data desired, we assume a max of 64 bits
output [63:0] instream;
reg [63:0] bitmask;
begin
instream = 64'h0;
// We shift out all 0's, which is a NOP to the debug unit
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
// Shift at least 5 bits, as this is the min, for a valid NOP
jtag_read_write_stream(64'h0, len+4,1,instream); // exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
bitmask = 64'hffffffffffffffff;
bitmask = bitmask << len;
bitmask = ~bitmask;
instream = instream & bitmask; // Cut off any unwanted excess bits
end
endtask
 
task write_module_internal_register;
input [31:0] regidx; // the length of the register index data
input [7:0] idxlen;
input [63:0] writedata;
input [7:0] datalen; // the length of the data to write. We assume the two length combined are 59 or less.
reg[63:0] streamdata;
begin
streamdata = 64'h0; // This will 0 the toplevel/module select bit
streamdata = streamdata | writedata;
streamdata = streamdata | (regidx << datalen);
streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream(streamdata, (idxlen+datalen+5), 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
end
endtask
 
// This includes the sending of the burst command
task do_module_burst_read;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] instream;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o; // temp signal...
reg [31:0] crc_read;
reg [5:0] word_size_bits;
begin
$display("Doing burst read, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
instream = 64'h0;
word_size_bits = word_size_bytes << 3;
crc_calc_i = 32'hffffffff;
// Send the command
case (word_size_bytes)
3'h1: opcode = `DBG_WB_CMD_BREAD8;
3'h2: opcode = `DBG_WB_CMD_BREAD16;
3'h4: opcode = `DBG_WB_CMD_BREAD32;
default:
begin
$display("Tried burst read with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
opcode = `DBG_WB_CMD_BREAD32;
end
endcase
send_module_burst_command(opcode,start_address, word_count); // returns to state idle
// This charming kludge provides ONE TCK, in case a xilinx BSCAN TAP is used,
// because the FSM needs it between the read burst command and the actual
// read burst. Blech.
#500;
set_ir(`IDCODE);
#500;
set_ir(`DEBUG);
#500;
// Get us back to shift_dr mode to read a burst
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
// Now, repeat...
for(i = 0; i < word_count; i=i+1) begin
// Get 1 status bit, then word_size_bytes*8 bits
status = 1'b0;
j = 0;
while(!status) begin
read_write_bit(3'h0, status);
j = j + 1;
end
if(j > 1) begin
$display("Took %0d tries before good status bit during burst read", j);
end
jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream);
//$display("Read 0x%0x", instream[31:0]);
compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o);
crc_calc_i = crc_calc_o;
if(word_size_bytes == 1) input_data8[i] = instream[7:0];
else if(word_size_bytes == 2) input_data16[i] = instream[15:0];
else input_data32[i] = instream[31:0];
end
// Read the data CRC from the debug module.
jtag_read_write_stream(64'h0, 6'd32, 1, crc_read);
if(crc_calc_o != crc_read) $display("CRC ERROR! Computed 0x%x, read CRC 0x%x", crc_calc_o, crc_read);
else $display("CRC OK!");
// Finally, shift out 5 0's, to make the next command a NOP
// Not necessary, debug unit won't latch a new opcode at the end of a burst
//jtag_write_stream(64'h0, 8'h5, 1);
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
end
endtask
 
 
task do_module_burst_write;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] dataword;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o;
reg crc_match;
reg [5:0] word_size_bits;
begin
$display("Doing burst write, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
word_size_bits = word_size_bytes << 3;
crc_calc_i = 32'hffffffff;
// Send the command
case (word_size_bytes)
3'h1: opcode = `DBG_WB_CMD_BWRITE8;
3'h2: opcode = `DBG_WB_CMD_BWRITE16;
3'h4: opcode = `DBG_WB_CMD_BWRITE32;
default:
begin
$display("Tried burst write with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
opcode = `DBG_WB_CMD_BWRITE32;
end
endcase
send_module_burst_command(opcode, start_address, word_count); // returns to state idle
// Get us back to shift_dr mode to write a burst
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
 
// Write a start bit (a 1) so it knows when to start counting
write_bit(`JTAG_TDO_bit);
 
// Now, repeat...
for(i = 0; i < word_count; i=i+1) begin
// Write word_size_bytes*8 bits, then get 1 status bit
if(word_size_bytes == 4) dataword = {32'h0, static_data32[i]};
else if(word_size_bytes == 2) dataword = {48'h0, static_data16[i]};
else dataword = {56'h0, static_data8[i]};
jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0);
compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o);
crc_calc_i = crc_calc_o;
// Check if WB bus is ready
// *** THIS WILL NOT WORK IF THERE IS MORE THAN 1 DEVICE IN THE JTAG CHAIN!!!
status = 1'b0;
read_write_bit(3'h0, status);
if(!status) begin
$display("Bad status bit during burst write, index %d", i);
end
//$display("Wrote 0x%0x", dataword);
end
// Send the CRC we computed
jtag_write_stream(crc_calc_o, 6'd32,0);
// Read the 'CRC match' bit, and go to exit1_dr
read_write_bit(`JTAG_TMS_bit, crc_match);
if(!crc_match) $display("CRC ERROR! match bit after write is %d (computed CRC 0x%x)", crc_match, crc_calc_o);
else $display("CRC OK!");
// Finally, shift out 5 0's, to make the next command a NOP
// Not necessary, module will not latch new opcode during burst
//jtag_write_stream(64'h0, 8'h5, 1);
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
end
 
endtask
 
 
// Puts a value in the TAP IR, assuming we start in IDLE state.
// Returns to IDLE state when finished
task set_ir;
input [3:0] irval;
begin
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(`JTAG_TMS_bit); // select_ir_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream({60'h0,irval}, 8'h4, 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
end
endtask
 
// Resets the TAP and puts it into idle mode
task reset_jtag;
integer i;
begin
for(i = 0; i < 8; i=i+1) begin
write_bit(`JTAG_TMS_bit); // 5 TMS should put us in test_logic_reset mode
end
write_bit(3'h0); // idle
end
endtask
 
 
////////////////////////////////////////////////////////////////////////////
// Tasks to write or read-write a string of data
 
task jtag_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
integer i;
integer databit;
reg [2:0] bits;
begin
for(i = 0; i < (len-1); i=i+1) begin
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
write_bit(bits);
end
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
write_bit(bits);
end
endtask
 
 
task jtag_read_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
output [63:0] instream;
integer i;
integer databit;
reg [2:0] bits;
reg inbit;
begin
instream = 64'h0;
for(i = 0; i < (len-1); i=i+1) begin
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
read_write_bit(bits, inbit);
instream = (instream | (inbit << i));
end
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
read_write_bit(bits, inbit);
instream = (instream | (inbit << (len-1)));
end
endtask
 
/////////////////////////////////////////////////////////////////////////
// Tasks which write or readwrite a single bit (including clocking)
 
task write_bit;
input [2:0] bitvals;
begin
// Set data
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
// Raise clock
jtag_out(bitvals | `JTAG_TCK_bit);
`wait_jtag_period;
// drop clock (making output available in the SHIFT_xR states)
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
end
endtask
 
task read_write_bit;
input [2:0] bitvals;
output l_tdi_val;
begin
// read bit state
l_tdi_val <= jtag_tdi_i;
// Set data
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
// Raise clock
jtag_out(bitvals | `JTAG_TCK_bit);
`wait_jtag_period;
// drop clock (making output available in the SHIFT_xR states)
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
end
endtask
 
/////////////////////////////////////////////////////////////////
// Basic functions to set the state of the JTAG TAP I/F bits
 
task jtag_out;
input [2:0] bitvals;
begin
 
jtag_tck_o <= bitvals[`JTAG_TCK];
jtag_tms_o <= bitvals[`JTAG_TMS];
jtag_tdo_o <= bitvals[`JTAG_TDO];
end
endtask
 
 
task jtag_inout;
input [2:0] bitvals;
output l_tdi_val;
begin
 
jtag_tck_o <= bitvals[`JTAG_TCK];
jtag_tms_o <= bitvals[`JTAG_TMS];
jtag_tdo_o <= bitvals[`JTAG_TDO];
 
l_tdi_val <= jtag_tdi_i;
end
endtask
 
endmodule
/wave.do
0,0 → 1,499
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /xsv_fpga_top/jtag_tdi
add wave -noupdate -format Logic /xsv_fpga_top/jtag_tms
add wave -noupdate -format Logic /xsv_fpga_top/jtag_tck
add wave -noupdate -format Logic /xsv_fpga_top/jtag_tdo
add wave -noupdate -format Logic /xsv_fpga_top/debug_select
add wave -noupdate -divider {Top level signals}
add wave -noupdate -format Logic /xsv_fpga_top/clk
add wave -noupdate -format Logic /xsv_fpga_top/rstn
add wave -noupdate -format Logic /xsv_fpga_top/rst_r
add wave -noupdate -format Logic /xsv_fpga_top/wb_rst
add wave -noupdate -format Logic /xsv_fpga_top/cpu_rst
add wave -noupdate -divider {Top-level CPU dbg}
add wave -noupdate -format Literal /xsv_fpga_top/dbg_lss
add wave -noupdate -format Literal /xsv_fpga_top/dbg_is
add wave -noupdate -format Literal /xsv_fpga_top/dbg_wp
add wave -noupdate -format Logic /xsv_fpga_top/dbg_bp
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_dat_dbg
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_dat_risc
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_adr
add wave -noupdate -format Logic /xsv_fpga_top/dbg_ewt
add wave -noupdate -format Logic /xsv_fpga_top/dbg_stall
add wave -noupdate -format Logic /xsv_fpga_top/dbg_we
add wave -noupdate -format Logic /xsv_fpga_top/dbg_stb
add wave -noupdate -format Logic /xsv_fpga_top/dbg_ack
add wave -noupdate -divider {CPU IWB}
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_clk_i
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_rst_i
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_ack_i
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_err_i
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_rty_i
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/iwb_dat_i
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_cyc_o
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/iwb_adr_o
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_stb_o
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_we_o
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/iwb_sel_o
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/iwb_dat_o
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_cab_o
add wave -noupdate -divider {DBG WB signals}
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/wb_dm_adr_o
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/wb_dm_dat_i
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/wb_dm_dat_o
add wave -noupdate -format Literal /xsv_fpga_top/wb_dm_sel_o
add wave -noupdate -format Logic /xsv_fpga_top/wb_dm_we_o
add wave -noupdate -format Logic /xsv_fpga_top/wb_dm_stb_o
add wave -noupdate -format Logic /xsv_fpga_top/wb_dm_cyc_o
add wave -noupdate -format Logic /xsv_fpga_top/wb_dm_cab_o
add wave -noupdate -format Logic /xsv_fpga_top/wb_dm_ack_i
add wave -noupdate -format Logic /xsv_fpga_top/wb_dm_err_i
add wave -noupdate -divider {DBG WB BIU}
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/tck_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/rst_i
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/data_i
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/data_o
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/addr_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/strobe_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/rd_wrn_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/rdy_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/err_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/word_size_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_clk_i
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_adr_o
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_dat_o
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_dat_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_cyc_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_stb_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_sel_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_we_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_ack_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_cab_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_err_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_cti_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_bte_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/sel_reg
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/addr_reg
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/data_in_reg
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/data_out_reg
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wr_reg
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/str_sync
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/rdy_sync
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/err_reg
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/rdy_sync_tff1
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/rdy_sync_tff2
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/rdy_sync_tff2q
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/str_sync_wbff1
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/str_sync_wbff2
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/str_sync_wbff2q
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/data_o_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/rdy_sync_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/err_en
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/be_dec
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/start_toggle
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/swapped_data_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/swapped_data_out
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_fsm_state
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/next_fsm_state
add wave -noupdate -divider {DBG WB Module}
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/tck_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/module_tdo_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/tdi_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/capture_dr_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/shift_dr_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/update_dr_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_register_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/module_select_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/top_inhibit_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/rst_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_clk_i
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_adr_o
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_dat_o
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_dat_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_cyc_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_stb_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_sel_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_we_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_ack_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_cab_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_err_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_cti_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_bte_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/address_counter
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/bit_count
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/word_count
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/operation
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_out_shift_reg
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/internal_register_select
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/internal_reg_error
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/addr_sel
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/addr_ct_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/op_reg_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/bit_ct_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/bit_ct_rst
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/word_ct_sel
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/word_ct_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/out_reg_ld_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/out_reg_shift_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/out_reg_data_sel
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/tdo_output_sel
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu_strobe
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_clr
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_in_sel
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_shift_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/regsel_ld_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/intreg_ld_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/error_reg_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu_clr_err
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/word_count_zero
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/bit_count_max
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/module_cmd
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu_ready
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu_err
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/burst_instruction
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/intreg_instruction
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/intreg_write
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/rd_op
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_match
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/bit_count_32
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/word_size_bits
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/word_size_bytes
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/incremented_address
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_to_addr_counter
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_to_word_counter
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/decremented_word_count
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/address_data_in
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/count_data_in
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/operation_in
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_to_biu
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_from_biu
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/crc_data_out
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_data_in
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_serial_out
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/reg_select_data
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/out_reg_data
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_from_internal_reg
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu_rst
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/module_state
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/module_next_state
add wave -noupdate -divider {DBG Top}
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/tck_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/tdi_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/tdo_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/rst_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/shift_dr_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/pause_dr_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/update_dr_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/capture_dr_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/debug_select_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_clk_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/wb_adr_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/wb_dat_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/wb_dat_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_cyc_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_stb_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/wb_sel_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_we_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_ack_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_cab_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_err_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/wb_cti_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/wb_bte_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_clk_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/cpu0_addr_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/cpu0_data_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/cpu0_data_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_bp_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_stall_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_stb_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_we_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_ack_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_rst_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/tdo_wb
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/tdo_cpu0
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/tdo_cpu1
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/input_shift_reg
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/module_id_reg
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/select_inhibit
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/module_inhibit
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/select_cmd
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/module_id_in
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/module_selects
add wave -noupdate -divider {DBG CPU0 Module}
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/tck_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/module_tdo_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/tdi_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/capture_dr_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/shift_dr_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/update_dr_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_register_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/module_select_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/top_inhibit_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/rst_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_clk_i
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_addr_o
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_data_i
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_data_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_stb_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_we_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_ack_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_rst_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_bp_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_stall_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/address_counter
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/bit_count
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/word_count
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/operation
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_out_shift_reg
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/internal_register_select
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/internal_reg_status
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/addr_sel
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/addr_ct_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/op_reg_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/bit_ct_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/bit_ct_rst
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/word_ct_sel
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/word_ct_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/out_reg_ld_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/out_reg_shift_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/out_reg_data_sel
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/tdo_output_sel
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/biu_strobe
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_clr
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_in_sel
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_shift_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/regsel_ld_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/intreg_ld_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/word_count_zero
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/bit_count_max
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/module_cmd
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/biu_ready
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/burst_instruction
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/intreg_instruction
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/intreg_write
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/rd_op
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_match
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/bit_count_32
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/word_size_bits
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/address_increment
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/incremented_address
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_to_addr_counter
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_to_word_counter
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/decremented_word_count
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/address_data_in
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/count_data_in
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/operation_in
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_to_biu
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_from_biu
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_data_out
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_data_in
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_serial_out
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/reg_select_data
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/out_reg_data
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_from_internal_reg
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/status_reg_wr
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/module_state
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/module_next_state
add wave -noupdate -divider {DBG CPU0 BIU}
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/tck_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rst_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/data_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/data_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/addr_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/strobe_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rd_wrn_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rdy_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_clk_i
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_addr_o
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_data_i
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_data_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_stb_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_we_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_ack_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/addr_reg
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/data_in_reg
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/data_out_reg
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/wr_reg
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/str_sync
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_tff1
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_tff2
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_tff2q
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/str_sync_wbff1
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/str_sync_wbff2
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/str_sync_wbff2q
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/data_o_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/start_toggle
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_fsm_state
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/next_fsm_state
add wave -noupdate -divider {CPU debug unit}
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/clk
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/rst
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcpu_cycstb_i
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcpu_we_i
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcpu_adr_i
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcpu_dat_lsu
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcpu_dat_dc
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/icpu_cycstb_i
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/ex_freeze
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/branch_op
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/ex_insn
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/id_pc
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/spr_dat_npc
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/rf_dataw
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/du_dsr
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/du_stall
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/du_addr
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/du_dat_i
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/du_dat_o
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/du_read
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/du_write
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/du_except
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/du_hwbkpt
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/spr_cs
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/spr_write
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/spr_addr
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/spr_dat_i
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/spr_dat_o
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_stall_i
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_ewt_i
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dbg_lss_o
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dbg_is_o
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dbg_wp_o
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_bp_o
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_stb_i
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_we_i
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dbg_adr_i
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dbg_dat_i
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dbg_dat_o
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_ack_o
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dmr1
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dmr2
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dsr
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/drr
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr0
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr1
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr2
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr3
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr4
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr5
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr6
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr7
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr0
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr1
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr2
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr3
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr4
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr5
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr6
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr7
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dwcr0
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dwcr1
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dmr1_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dmr2_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dsr_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/drr_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr0_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr1_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr2_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr3_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr4_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr5_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr6_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr7_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr0_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr1_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr2_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr3_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr4_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr5_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr6_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr7_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dwcr0_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dwcr1_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_bp_r
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/except_stop
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/tbia_dat_o
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/tbim_dat_o
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/tbar_dat_o
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/tbts_dat_o
add wave -noupdate -divider {CPU SPRs}
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/clk
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/rst
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/flagforw
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/flag_we
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/flag
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/cyforw
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/cy_we
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/carry
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/addrbase
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/addrofs
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/dat_i
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/alu_op
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/branch_op
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/epcr
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/eear
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/esr
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/except_started
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/to_wbmux
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/epcr_we
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/eear_we
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/esr_we
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/pc_we
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/sr_we
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/to_sr
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/sr
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_cfgr
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_rf
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_npc
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_ppc
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_mac
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_pic
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_tt
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_pm
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_dmmu
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_immu
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_du
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_addr
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_o
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_cs
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_we
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/du_addr
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/du_dat_du
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/du_read
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/du_write
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/du_dat_cpu
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/write_spr
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/read_spr
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/cfgr_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/rf_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/npc_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/ppc_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/sr_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/epcr_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/eear_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/esr_sel
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/sys_data
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/du_access
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/sprs_op
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/unqualified_cs
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {6180 ps} 0}
configure wave -namecolwidth 391
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {6180 ps}
/xsv_fpga_top.v
0,0 → 1,911
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1K test application for XESS XSV board, Top Level ////
//// ////
//// This file is part of the OR1K test application ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Top level instantiating all the blocks. ////
//// ////
//// To Do: ////
//// - nothing really ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: xsv_fpga_top.v,v $
// Revision 1.3 2008/07/11 08:22:17 Nathan
// Added code to make the native TAP simulate a Xilinx BSCAN device, and code to simulate the behavior of the xilinx_internal_jtag module. The adv_dbg_module should get inputs that emulate the xilinx_internal_jtag device outputs.
//
// Revision 1.10 2004/04/05 08:44:35 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.8 2003/04/07 21:05:58 lampret
// WB = 1/2 RISC clock test code enabled.
//
// Revision 1.7 2003/04/07 01:28:17 lampret
// Adding OR1200_CLMODE_1TO2 test code.
//
// Revision 1.6 2002/08/12 05:35:12 lampret
// rty_i are unused - tied to zero.
//
// Revision 1.5 2002/03/29 20:58:51 lampret
// Changed hardcoded address for fake MC to use a define.
//
// Revision 1.4 2002/03/29 16:30:47 lampret
// Fixed port names that changed.
//
// Revision 1.3 2002/03/29 15:50:03 lampret
// Added response from memory controller (addr 0x60000000)
//
// Revision 1.2 2002/03/21 17:39:16 lampret
// Fixed some typos
//
//
 
`include "xsv_fpga_defines.v"
//`include "bench_defines.v"
 
module xsv_fpga_top (
 
//
// Global signals
//
//clk,
//rstn,
 
// UART signals
uart_stx, uart_srx
// SDRAM signals
/*
sdram_clk_i, sdram_addr_o, sdram_ba_o, sdram_dqm_o,
sdram_we_o, sdram_cas_o, sdram_ras_o,
sdram_cke_o, sdram_cs_o, sdram_data_io
*/
);
 
//
// I/O Ports
//
 
//
// Global
//
//input clk;
//input rstn;
 
// UART
input uart_srx;
output uart_stx;
 
// SDRAM
/*
input sdram_clk_i;
output [11:0] sdram_addr_o;
output [1:0] sdram_ba_o;
output [3:0] sdram_dqm_o;
output sdram_we_o;
output sdram_cas_o;
output sdram_ras_o;
output sdram_cke_o;
output sdram_cs_o;
inout [31:0] sdram_data_io;
*/
 
//
// Internal wires
//
 
wire clk;
wire rstn;
 
//
// Debug core master i/f wires
//
wire [31:0] wb_dm_adr_o;
wire [31:0] wb_dm_dat_i;
wire [31:0] wb_dm_dat_o;
wire [3:0] wb_dm_sel_o;
wire wb_dm_we_o;
wire wb_dm_stb_o;
wire wb_dm_cyc_o;
wire wb_dm_cab_o;
wire wb_dm_ack_i;
wire wb_dm_err_i;
 
//
// Debug <-> RISC wires
//
wire [3:0] dbg_lss;
wire [1:0] dbg_is;
wire [10:0] dbg_wp;
wire dbg_bp;
wire [31:0] dbg_dat_dbg;
wire [31:0] dbg_dat_risc;
wire [31:0] dbg_adr;
wire dbg_ewt;
wire dbg_stall;
wire dbg_we;
wire dbg_stb;
wire dbg_ack;
wire dbg_cpu0_rst;
 
//
// TAP<->dbg_interface
//
wire debug_rst;
wire debug_select;
wire debug_tdi;
wire debug_tdo;
wire shift_dr;
wire pause_dr;
wire update_dr;
wire capture_dr;
wire drck; // To emulate the BSCAN_VIRTEX/SPARTAN devices
 
//
// RISC instruction master i/f wires
//
wire [31:0] wb_rim_adr_o;
wire wb_rim_cyc_o;
wire [31:0] wb_rim_dat_i;
wire [31:0] wb_rim_dat_o;
wire [3:0] wb_rim_sel_o;
wire wb_rim_ack_i;
wire wb_rim_err_i;
wire wb_rim_rty_i = 1'b0;
wire wb_rim_we_o;
wire wb_rim_stb_o;
wire wb_rim_cab_o;
//wire [31:0] wb_rif_adr;
//reg prefix_flash;
 
//
// RISC data master i/f wires
//
wire [31:0] wb_rdm_adr_o;
wire wb_rdm_cyc_o;
wire [31:0] wb_rdm_dat_i;
wire [31:0] wb_rdm_dat_o;
wire [3:0] wb_rdm_sel_o;
wire wb_rdm_ack_i;
wire wb_rdm_err_i;
wire wb_rdm_rty_i = 1'b0;
wire wb_rdm_we_o;
wire wb_rdm_stb_o;
wire wb_rdm_cab_o;
 
//
// RISC misc
//
//wire [19:0] pic_ints;
 
//
// SRAM controller slave i/f wires
//
wire [31:0] wb_ss_dat_i;
wire [31:0] wb_ss_dat_o;
wire [31:0] wb_ss_adr_i;
wire [3:0] wb_ss_sel_i;
wire wb_ss_we_i;
wire wb_ss_cyc_i;
wire wb_ss_stb_i;
wire wb_ss_ack_o;
wire wb_ss_err_o;
 
 
//
// UART16550 core slave i/f wires
//
wire [31:0] wb_us_dat_i;
wire [31:0] wb_us_dat_o;
wire [31:0] wb_us_adr_i;
wire [3:0] wb_us_sel_i;
wire wb_us_we_i;
wire wb_us_cyc_i;
wire wb_us_stb_i;
wire wb_us_ack_o;
wire wb_us_err_o;
 
//
// UART external i/f wires
//
wire uart_stx;
wire uart_srx;
 
 
//
// Memory controller core slave i/f wires
//
/*
wire [31:0] wb_mem_dat_i;
wire [31:0] wb_mem_dat_o;
wire [31:0] wb_mem_adr_i;
wire [3:0] wb_mem_sel_i;
wire wb_mem_we_i;
wire wb_mem_cyc_i;
wire wb_mem_stb_i;
wire wb_mem_ack_o;
wire wb_mem_err_o;
 
// Internal mem control wires
wire [7:0] mc_cs;
wire [12:0] mc_addr_o;
 
 
// Memory control external wires
wire sdram_clk_i;
wire [11:0] sdram_addr_o;
wire [1:0] sdram_ba_o;
wire [3:0] sdram_dqm_o;
wire sdram_we_o;
wire sdram_cas_o;
wire sdram_ras_o;
wire sdram_cke_o;
wire sdram_cs_o;
wire [31:0] sdram_data_io;
*/
 
//
// JTAG wires
//
wire jtag_tdi;
wire jtag_tms;
wire jtag_tck;
wire jtag_trst;
wire jtag_tdo;
 
 
//
// Reset debounce
//
reg rstn_debounce;
wire rst_r;
reg wb_rst;
reg cpu_rst;
 
//
// Global clock
//
`ifdef OR1200_CLMODE_1TO2
reg wb_clk;
`else
wire wb_clk;
`endif
 
//
// Reset debounce
//
always @(posedge wb_clk or negedge rstn)
if (~rstn)
rstn_debounce <= 1'b0;
else
rstn_debounce <= #1 1'b1;
 
assign rst_r = ~rstn_debounce;
//assign dbg_trst = rstn_debounce & jtag_trst;
 
//
// Reset debounce
//
always @(posedge wb_clk)
wb_rst <= #1 rst_r;
always @ (posedge wb_clk)
cpu_rst <= dbg_cpu0_rst | rst_r;
 
//
// This is purely for testing 1/2 WB clock
// This should never be used when implementing in
// an FPGA. It is used only for simulation regressions.
//
`ifdef OR1200_CLMODE_1TO2
initial wb_clk = 0;
always @(posedge clk)
wb_clk = ~wb_clk;
`else
//
// Some Xilinx P&R tools need this
//
`ifdef TARGET_VIRTEX
IBUFG IBUFG1 (
.O ( wb_clk ),
.I ( clk )
);
`else
assign wb_clk = clk;
`endif
`endif // OR1200_CLMODE_1TO2
 
//
// Unused WISHBONE signals
//
assign wb_us_err_o = 1'b0;
 
 
assign jtag_tvref = 1'b1;
assign jtag_tgnd = 1'b0;
 
// JTAG / adv. debug control testbench
adv_debug_tb tb (
 
.jtag_tck_o(jtag_tck),
.jtag_tms_o(jtag_tms),
.jtag_tdo_o(jtag_tdi),
.jtag_tdi_i(jtag_tdo),
 
.wb_clk_o(clk),
.sys_rstn_o(rstn)
);
 
//
// JTAG TAP controller instantiation
//
tap_top tap (
// JTAG pads
.tms_pad_i(jtag_tms),
.tck_pad_i(jtag_tck),
.trstn_pad_i(1'b1),
.tdi_pad_i(jtag_tdi),
.tdo_pad_o(jtag_tdo),
.tdo_padoe_o(),
 
// TAP states
.test_logic_reset_o(debug_rst),
.run_test_idle_o(),
.shift_dr_o(shift_dr),
.pause_dr_o(),
.update_dr_o(update_dr),
.capture_dr_o(capture_dr),
// Select signals for boundary scan or mbist
.extest_select_o(),
.sample_preload_select_o(),
.mbist_select_o(),
.debug_select_o(debug_select),
// TDO signal that is connected to TDI of sub-modules.
.tdo_o(debug_tdi),
// TDI signals from sub-modules
.debug_tdi_i(debug_tdo), // from debug module
.bs_chain_tdi_i(1'b0), // from Boundary Scan Chain
.mbist_tdi_i(1'b0) // from Mbist Chain
);
 
// This is taken from the xilinx bscan_virtex4.v module
// It simulates the DRCK output of a BSCAN_* block
assign drck = ((debug_select & !shift_dr & !capture_dr) ||
(debug_select & shift_dr & jtag_tck) ||
(debug_select & capture_dr & jtag_tck));
reg xshift;
reg xcapture;
reg xupdate;
reg xselect;
// TAP state outputs are also delayed half a cycle.
always @(negedge jtag_tck)
begin
xshift = shift_dr;
xcapture = capture_dr;
xupdate = update_dr;
xselect = debug_select;
end
 
//////////////////////////////////////////
wire tck2;
assign tck2 = (drck & !xupdate);
 
reg update2;
 
always @ (posedge xupdate or posedge xcapture or negedge xselect)
begin
if(xupdate) update2 <= 1'b1;
else if(xcapture) update2 <= 1'b0;
else if(!xselect) update2 <= 1'b0;
end
 
//
// Instantiation of the development i/f
//
dbg_top dbg_top (
 
// JTAG pins
.tck_i ( tck2 ),
.tdi_i ( debug_tdi ),
.tdo_o ( debug_tdo ),
.rst_i ( debug_rst ),
 
// TAP states
.shift_dr_i( xshift ),
.pause_dr_i( pause_dr ),
.update_dr_i( update2 ),
.capture_dr_i (xcapture),
 
// Instructions
.debug_select_i( xselect ),
 
// RISC signals
.cpu0_clk_i ( wb_clk ),
.cpu0_addr_o ( dbg_adr ),
.cpu0_data_i ( dbg_dat_risc ),
.cpu0_data_o ( dbg_dat_dbg ),
.cpu0_bp_i ( dbg_bp ),
.cpu0_stall_o ( dbg_stall ),
.cpu0_stb_o ( dbg_stb ),
.cpu0_we_o ( dbg_we ),
.cpu0_ack_i ( dbg_ack ),
.cpu0_rst_o ( dbg_cpu0_rst),
 
// WISHBONE common
.wb_clk_i ( wb_clk ),
 
// WISHBONE master interface
.wb_adr_o ( wb_dm_adr_o ),
.wb_dat_o ( wb_dm_dat_o ),
.wb_dat_i ( wb_dm_dat_i ),
.wb_cyc_o ( wb_dm_cyc_o ),
.wb_stb_o ( wb_dm_stb_o ),
.wb_sel_o ( wb_dm_sel_o ),
.wb_we_o ( wb_dm_we_o ),
.wb_ack_i ( wb_dm_ack_i ),
.wb_cab_o ( wb_dm_cab_o ),
.wb_err_i ( wb_dm_err_i ),
.wb_cti_o (),
.wb_bte_o ()
);
 
 
//
// Instantiation of the OR1200 RISC
//
or1200_top or1200_top (
 
// Common
.rst_i ( cpu_rst ),
.clk_i ( clk ),
`ifdef OR1200_CLMODE_1TO2
.clmode_i ( 2'b01 ),
`else
`ifdef OR1200_CLMODE_1TO4
.clmode_i ( 2'b11 ),
`else
.clmode_i ( 2'b00 ),
`endif
`endif
 
// WISHBONE Instruction Master
.iwb_clk_i ( wb_clk ),
.iwb_rst_i ( wb_rst ),
.iwb_cyc_o ( wb_rim_cyc_o ),
.iwb_adr_o ( wb_rim_adr_o ),
.iwb_dat_i ( wb_rim_dat_i ),
.iwb_dat_o ( wb_rim_dat_o ),
.iwb_sel_o ( wb_rim_sel_o ),
.iwb_ack_i ( wb_rim_ack_i ),
.iwb_err_i ( wb_rim_err_i ),
.iwb_rty_i ( wb_rim_rty_i ),
.iwb_we_o ( wb_rim_we_o ),
.iwb_stb_o ( wb_rim_stb_o ),
.iwb_cab_o ( wb_rim_cab_o ),
 
// WISHBONE Data Master
.dwb_clk_i ( wb_clk ),
.dwb_rst_i ( wb_rst ),
.dwb_cyc_o ( wb_rdm_cyc_o ),
.dwb_adr_o ( wb_rdm_adr_o ),
.dwb_dat_i ( wb_rdm_dat_i ),
.dwb_dat_o ( wb_rdm_dat_o ),
.dwb_sel_o ( wb_rdm_sel_o ),
.dwb_ack_i ( wb_rdm_ack_i ),
.dwb_err_i ( wb_rdm_err_i ),
.dwb_rty_i ( wb_rdm_rty_i ),
.dwb_we_o ( wb_rdm_we_o ),
.dwb_stb_o ( wb_rdm_stb_o ),
.dwb_cab_o ( wb_rdm_cab_o ),
 
// Debug
.dbg_stall_i ( dbg_stall ), // Set to 1'b0 if debug is absent / broken
.dbg_dat_i ( dbg_dat_dbg ),
.dbg_adr_i ( dbg_adr ),
.dbg_ewt_i ( 1'b0 ),
.dbg_lss_o ( ),
.dbg_is_o ( ),
.dbg_wp_o ( ),
.dbg_bp_o ( dbg_bp ),
.dbg_dat_o ( dbg_dat_risc ),
.dbg_ack_o ( dbg_ack ),
.dbg_stb_i ( dbg_stb ),
.dbg_we_i ( dbg_we ),
 
// Power Management
.pm_clksd_o ( ),
.pm_cpustall_i ( 1'b0 ),
.pm_dc_gate_o ( ),
.pm_ic_gate_o ( ),
.pm_dmmu_gate_o ( ),
.pm_immu_gate_o ( ),
.pm_tt_gate_o ( ),
.pm_cpu_gate_o ( ),
.pm_wakeup_o ( ),
.pm_lvolt_o ( ),
 
// Interrupts
.pic_ints_i (20'b0)
);
 
 
//
// Instantiation of the On-chip RAM controller
//
onchip_ram_top #(
.dwidth (32),
.size_bytes(16384)
) onchip_ram_top (
 
// WISHBONE common
.wb_clk_i ( wb_clk ),
.wb_rst_i ( wb_rst ),
 
// WISHBONE slave
.wb_dat_i ( wb_ss_dat_i ),
.wb_dat_o ( wb_ss_dat_o ),
.wb_adr_i ( wb_ss_adr_i ),
.wb_sel_i ( wb_ss_sel_i ),
.wb_we_i ( wb_ss_we_i ),
.wb_cyc_i ( wb_ss_cyc_i ),
.wb_stb_i ( wb_ss_stb_i ),
.wb_ack_o ( wb_ss_ack_o ),
.wb_err_o ( wb_ss_err_o )
);
 
//
// Instantiation of the UART16550
//
uart_top uart_top (
 
// WISHBONE common
.wb_clk_i ( wb_clk ),
.wb_rst_i ( wb_rst ),
 
// WISHBONE slave
.wb_adr_i ( wb_us_adr_i[4:0] ),
.wb_dat_i ( wb_us_dat_i ),
.wb_dat_o ( wb_us_dat_o ),
.wb_we_i ( wb_us_we_i ),
.wb_stb_i ( wb_us_stb_i ),
.wb_cyc_i ( wb_us_cyc_i ),
.wb_ack_o ( wb_us_ack_o ),
.wb_sel_i ( wb_us_sel_i ),
 
// Interrupt request
.int_o ( ),
 
// UART signals
// serial input/output
.stx_pad_o ( uart_stx ),
.srx_pad_i ( uart_srx ),
 
// modem signals
.rts_pad_o ( ),
.cts_pad_i ( 1'b0 ),
.dtr_pad_o ( ),
.dsr_pad_i ( 1'b0 ),
.ri_pad_i ( 1'b0 ),
.dcd_pad_i ( 1'b0 )
);
 
/*
mc_wrapper mc_wrapper (
.clk_i ( wb_clk ),
.rst_i ( wb_rst ),
.clk_mem_i ( sdram_clk_i ),
 
.wb_data_i ( wb_mem_dat_i ),
.wb_data_o ( wb_mem_dat_o ),
.wb_addr_i ( wb_mem_adr_i ),
.wb_sel_i ( wb_mem_sel_i ),
.wb_we_i ( wb_mem_we_i ),
.wb_cyc_i ( wb_mem_cyc_i ),
.wb_stb_i ( wb_mem_stb_i ),
.wb_ack_o ( wb_mem_ack_o ),
.wb_err_o ( wb_mem_err_o ),
 
.susp_req_i ( 1'b0 ),
.resume_req_i ( 1'b0 ),
.suspended_o (),
.poc_o ( ), // This is an output so the rest of the system can configure itself
 
.sdram_addr_o ( mc_addr_o ),
.sdram_ba_o ( sdram_ba_o ),
.sdram_cas_n_o ( sdram_cas_o ),
.sdram_ras_n_o ( sdram_ras_o ),
.sdram_cke_n_o ( sdram_cke_o ),
.mc_dqm_o ( sdram_dqm_o ),
.mc_we_n_o ( sdram_we_o ),
.mc_oe_n_o ( ),
.mc_data_io ( sdram_data_io ),
.mc_parity_io ( ),
.mc_cs_n_o ( mc_cs )
);
 
assign sdram_cs_o = mc_cs[0];
assign sdram_addr_o = mc_addr_o[11:0];
*/
 
//
// Instantiation of the Traffic COP
//
wb_conbus_top #(.s0_addr_w (`APP_ADDR_DEC_W),
.s0_addr (`APP_ADDR_SDRAM),
.s1_addr_w (`APP_ADDR_DEC2_W),
.s1_addr (`APP_ADDR_OCRAM),
.s27_addr_w (`APP_ADDR_DECP_W),
.s2_addr (`APP_ADDR_VGA),
.s3_addr (`APP_ADDR_ETH),
.s4_addr (`APP_ADDR_AUDIO),
.s5_addr (`APP_ADDR_UART),
.s6_addr (`APP_ADDR_PS2),
.s7_addr (`APP_ADDR_RES1)
) tc_top (
 
// WISHBONE common
.clk_i ( wb_clk ),
.rst_i ( wb_rst ),
 
// WISHBONE Initiator 0
.m0_cyc_i ( 1'b0 ),
.m0_stb_i ( 1'b0 ),
.m0_cab_i ( 1'b0 ),
.m0_adr_i ( 32'h0000_0000 ),
.m0_sel_i ( 4'b0000 ),
.m0_we_i ( 1'b0 ),
.m0_dat_i ( 32'h0000_0000 ),
.m0_dat_o ( ),
.m0_ack_o ( ),
.m0_err_o ( ),
 
// WISHBONE Initiator 1
.m1_cyc_i ( 1'b0 ),
.m1_stb_i ( 1'b0 ),
.m1_cab_i ( 1'b0 ),
.m1_adr_i ( 32'h0000_0000 ),
.m1_sel_i ( 4'b0000 ),
.m1_we_i ( 1'b0 ),
.m1_dat_i ( 32'h0000_0000 ),
.m1_dat_o ( ),
.m1_ack_o ( ),
.m1_err_o ( ),
 
// WISHBONE Initiator 2
.m2_cyc_i ( 1'b0 ),
.m2_stb_i ( 1'b0 ),
.m2_cab_i ( 1'b0 ),
.m2_adr_i ( 32'h0000_0000 ),
.m2_sel_i ( 4'b0000 ),
.m2_we_i ( 1'b0 ),
.m2_dat_i ( 32'h0000_0000 ),
.m2_dat_o ( ),
.m2_ack_o ( ),
.m2_err_o ( ),
// WISHBONE Initiator 3
.m3_cyc_i ( wb_dm_cyc_o ),
.m3_stb_i ( wb_dm_stb_o ),
.m3_cab_i ( wb_dm_cab_o ),
.m3_adr_i ( wb_dm_adr_o ),
.m3_sel_i ( wb_dm_sel_o ),
.m3_we_i ( wb_dm_we_o ),
.m3_dat_i ( wb_dm_dat_o ),
.m3_dat_o ( wb_dm_dat_i ),
.m3_ack_o ( wb_dm_ack_i ),
.m3_err_o ( wb_dm_err_i ),
 
// WISHBONE Initiator 4
.m4_cyc_i ( wb_rdm_cyc_o ),
.m4_stb_i ( wb_rdm_stb_o ),
.m4_cab_i ( wb_rdm_cab_o ),
.m4_adr_i ( wb_rdm_adr_o ),
.m4_sel_i ( wb_rdm_sel_o ),
.m4_we_i ( wb_rdm_we_o ),
.m4_dat_i ( wb_rdm_dat_o ),
.m4_dat_o ( wb_rdm_dat_i ),
.m4_ack_o ( wb_rdm_ack_i ),
.m4_err_o ( wb_rdm_err_i ),
 
// WISHBONE Initiator 5
.m5_cyc_i ( wb_rim_cyc_o ),
.m5_stb_i ( wb_rim_stb_o ),
.m5_cab_i ( wb_rim_cab_o ),
.m5_adr_i ( wb_rim_adr_o ),
.m5_sel_i ( wb_rim_sel_o ),
.m5_we_i ( wb_rim_we_o ),
.m5_dat_i ( wb_rim_dat_o ),
.m5_dat_o ( wb_rim_dat_i ),
.m5_ack_o ( wb_rim_ack_i ),
.m5_err_o ( wb_rim_err_i ),
 
// WISHBONE Initiator 6
.m6_cyc_i ( 1'b0 ),
.m6_stb_i ( 1'b0 ),
.m6_cab_i ( 1'b0 ),
.m6_adr_i ( 32'h0000_0000 ),
.m6_sel_i ( 4'b0000 ),
.m6_we_i ( 1'b0 ),
.m6_dat_i ( 32'h0000_0000 ),
.m6_dat_o ( ),
.m6_ack_o ( ),
.m6_err_o ( ),
 
// WISHBONE Initiator 7
.m7_cyc_i ( 1'b0 ),
.m7_stb_i ( 1'b0 ),
.m7_cab_i ( 1'b0 ),
.m7_adr_i ( 32'h0000_0000 ),
.m7_sel_i ( 4'b0000 ),
.m7_we_i ( 1'b0 ),
.m7_dat_i ( 32'h0000_0000 ),
.m7_dat_o ( ),
.m7_ack_o ( ),
.m7_err_o ( ),
 
// WISHBONE Target 0
.s0_cyc_o ( ),
.s0_stb_o ( ),
.s0_cab_o ( ),
.s0_adr_o ( ),
.s0_sel_o ( ),
.s0_we_o ( ),
.s0_dat_o ( ),
.s0_dat_i ( 32'h0000_0000 ),
.s0_ack_i ( 1'b0 ),
.s0_err_i ( 1'b0 ),
.s0_rty_i ( 1'b0 ),
/*
.s0_cyc_o ( wb_mem_cyc_i ),
.s0_stb_o ( wb_mem_stb_i ),
.s0_cab_o ( wb_mem_cab_i ),
.s0_adr_o ( wb_mem_adr_i ),
.s0_sel_o ( wb_mem_sel_i ),
.s0_we_o ( wb_mem_we_i ),
.s0_dat_o ( wb_mem_dat_i ),
.s0_dat_i ( wb_mem_dat_o ),
.s0_ack_i ( wb_mem_ack_o ),
.s0_err_i ( wb_mem_err_o ),
.s0_rty_i ( 1'b0),
*/
 
// WISHBONE Target 1
.s1_cyc_o ( wb_ss_cyc_i ),
.s1_stb_o ( wb_ss_stb_i ),
.s1_cab_o ( wb_ss_cab_i ),
.s1_adr_o ( wb_ss_adr_i ),
.s1_sel_o ( wb_ss_sel_i ),
.s1_we_o ( wb_ss_we_i ),
.s1_dat_o ( wb_ss_dat_i ),
.s1_dat_i ( wb_ss_dat_o ),
.s1_ack_i ( wb_ss_ack_o ),
.s1_err_i ( wb_ss_err_o ),
.s1_rty_i ( 1'b0 ),
// WISHBONE Target 2
.s2_cyc_o ( ),
.s2_stb_o ( ),
.s2_cab_o ( ),
.s2_adr_o ( ),
.s2_sel_o ( ),
.s2_we_o ( ),
.s2_dat_o ( ),
.s2_dat_i ( 32'h0000_0000 ),
.s2_ack_i ( 1'b0 ),
.s2_err_i ( 1'b0 ),
.s2_rty_i ( 1'b0 ),
// WISHBONE Target 3
.s3_cyc_o ( ),
.s3_stb_o ( ),
.s3_cab_o ( ),
.s3_adr_o ( ),
.s3_sel_o ( ),
.s3_we_o ( ),
.s3_dat_o ( ),
.s3_dat_i ( 32'h0000_0000 ),
.s3_ack_i ( 1'b0 ),
.s3_err_i ( 1'b0 ),
.s3_rty_i ( 1'b0),
// WISHBONE Target 4
.s4_cyc_o ( ),
.s4_stb_o ( ),
.s4_cab_o ( ),
.s4_adr_o ( ),
.s4_sel_o ( ),
.s4_we_o ( ),
.s4_dat_o ( ),
.s4_dat_i ( 32'h0000_0000 ),
.s4_ack_i ( 1'b0 ),
.s4_err_i ( 1'b0 ),
.s4_rty_i ( 1'b0),
// WISHBONE Target 5
.s5_cyc_o ( wb_us_cyc_i ),
.s5_stb_o ( wb_us_stb_i ),
.s5_cab_o ( wb_us_cab_i ),
.s5_adr_o ( wb_us_adr_i ),
.s5_sel_o ( wb_us_sel_i ),
.s5_we_o ( wb_us_we_i ),
.s5_dat_o ( wb_us_dat_i ),
.s5_dat_i ( wb_us_dat_o ),
.s5_ack_i ( wb_us_ack_o ),
.s5_err_i ( wb_us_err_o ),
.s5_rty_i ( 1'b0 ),
// WISHBONE Target 6
.s6_cyc_o ( ),
.s6_stb_o ( ),
.s6_cab_o ( ),
.s6_adr_o ( ),
.s6_sel_o ( ),
.s6_we_o ( ),
.s6_dat_o ( ),
.s6_dat_i ( 32'h0000_0000 ),
.s6_ack_i ( 1'b0 ),
.s6_err_i ( 1'b0 ),
.s6_rty_i ( 1'b0),
// WISHBONE Target 7
.s7_cyc_o ( ),
.s7_stb_o ( ),
.s7_cab_o ( ),
.s7_adr_o ( ),
.s7_sel_o ( ),
.s7_we_o ( ),
.s7_dat_o ( ),
.s7_dat_i ( 32'h0000_0000 ),
.s7_ack_i ( 1'b0 ),
.s7_err_i ( 1'b0 ),
.s7_rty_i ( 1'b0)
);
 
//initial begin
// $dumpvars(0);
// $dumpfile("dump.vcd");
//end
 
endmodule
/xsv_fpga_defines.v
0,0 → 1,100
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1K test app definitions ////
//// ////
//// This file is part of the OR1K test application ////
//// http://www.opencores.org/cores/or1k/xess/ ////
//// ////
//// Description ////
//// DEfine target technology etc. Right now FIFOs are available ////
//// only for Xilinx Virtex FPGAs. (TARGET_VIRTEX) ////
//// ////
//// To Do: ////
//// - nothing really ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, damjan.lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: xsv_fpga_defines.v,v $
// Revision 1.2 2008/07/11 08:16:01 Nathan
// Ran through dos2unix
//
// Revision 1.1 2008/07/08 19:11:54 Nathan
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
//
// Revision 1.4 2004/04/05 08:44:35 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2 2002/03/29 20:58:51 lampret
// Changed hardcoded address for fake MC to use a define.
//
// Revision 1.1.1.1 2002/03/21 16:55:44 lampret
// First import of the "new" XESS XSV environment.
//
//
//
 
//
// Define to target to Xilinx Virtex
//
//`define TARGET_VIRTEX
 
//
// Interrupts
//
`define APP_INT_RES1 1:0
`define APP_INT_UART 2
`define APP_INT_RES2 3
`define APP_INT_ETH 4
`define APP_INT_PS2 5
`define APP_INT_RES3 19:6
 
//
// Address map
//
`define APP_ADDR_DEC_W 3
`define APP_ADDR_SDRAM `APP_ADDR_DEC_W'b001
`define APP_ADDR_DEC2_W 8
`define APP_ADDR_OCRAM `APP_ADDR_DEC2_W'h00
`define APP_ADDR_DECP_W 8
//`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h99
`define APP_ADDR_VGA `APP_ADDR_DECP_W'h97
`define APP_ADDR_ETH `APP_ADDR_DECP_W'h92
`define APP_ADDR_AUDIO `APP_ADDR_DECP_W'h9d
`define APP_ADDR_UART `APP_ADDR_DECP_W'h90
`define APP_ADDR_PS2 `APP_ADDR_DECP_W'h94
`define APP_ADDR_RES1 `APP_ADDR_DECP_W'h9e
//`define APP_ADDR_RES2 `APP_ADDR_DECP_W'h9f
//`define APP_ADDR_FAKEMC 4'h6
 
// For simulation...
// `define DBG_IF_MODEL 1

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