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Subversion Repositories adv_debug_sys

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  • This comparison shows the changes necessary to convert path 
    /adv_debug_sys/tags/ADS_RELEASE_1_1_0/Hardware/jtag/cells
    from Rev 8 to Rev 18
    ↔ Reverse comparison
  •

Rev 8 → Rev 18

/rtl/verilog/InputCell.v
0,0 → 1,62
/**********************************************************************************
* *
* This verilog file is a part of the Boundary Scan Implementation and comes in *
* a pack with several other files. It is fully IEEE 1149.1 compliant. *
* For details check www.opencores.org (pdf files, bsdl file, etc.) *
* *
* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* See the file COPYING for the full details of the license. *
* *
* OPENCORES.ORG is looking for new open source IP cores and developers that *
* would like to help in our mission. *
* *
**********************************************************************************/
 
 
 
/**********************************************************************************
* *
* Input Cell: *
* *
* InputPin: Value that comes from on-chip logic and goes to pin *
* FromPreviousBSCell: Value from previous boundary scan cell *
* ToNextBSCell: Value for next boundary scan cell *
* CaptureDR, ShiftDR: TAP states *
* TCK: Test Clock *
* *
**********************************************************************************/
 
// This is not a top module
module InputCell( InputPin, FromPreviousBSCell, CaptureDR, ShiftDR, TCK, ToNextBSCell);
input InputPin;
input FromPreviousBSCell;
input CaptureDR;
input ShiftDR;
input TCK;
reg Latch;
output ToNextBSCell;
reg ToNextBSCell;
 
wire SelectedInput = CaptureDR? InputPin : FromPreviousBSCell;
 
always @ (posedge TCK)
begin
if(CaptureDR | ShiftDR)
Latch<=SelectedInput;
end
 
always @ (negedge TCK)
begin
ToNextBSCell<=Latch;
end
 
 
endmodule // InputCell
/rtl/verilog/ControlCell.v
0,0 → 1,77
/**********************************************************************************
* *
* This verilog file is a part of the Boundary Scan Implementation and comes in *
* a pack with several other files. It is fully IEEE 1149.1 compliant. *
* For details check www.opencores.org (pdf files, bsdl file, etc.) *
* *
* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* See the file COPYING for the full details of the license. *
* *
* OPENCORES.ORG is looking for new open source IP cores and developers that *
* would like to help in our mission. *
* *
**********************************************************************************/
 
 
/**********************************************************************************
* *
* I/O Control Cell: *
* *
* OutputControl: Output Control from on-chip logic *
* FromPreviousBSCell: Value from previous boundary scan cell *
* ToNextBSCell: Value for next boundary scan cell *
* CaptureDR, ShiftDR, UpdateDR: TAP states *
* extest: Instruction Register Command *
* TCK: Test Clock *
* *
* Output Enable can be generated by running CaptureDR-UpdateDR sequence or *
* shifting data for the exact number of time *
* *
**********************************************************************************/
 
// This is not a top module
module ControlCell( OutputControl, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, ToOutputEnable);
input OutputControl;
input FromPreviousBSCell;
input CaptureDR;
input ShiftDR;
input UpdateDR;
input extest;
input TCK;
 
reg Latch;
 
output ToNextBSCell;
output ToOutputEnable;
 
reg ToNextBSCell;
reg ShiftedControl;
 
wire SelectedInput = CaptureDR? OutputControl : FromPreviousBSCell;
 
always @ (posedge TCK)
begin
if(CaptureDR | ShiftDR)
Latch<=SelectedInput;
end
 
always @ (negedge TCK)
begin
ToNextBSCell<=Latch;
end
 
always @ (negedge TCK)
begin
if(UpdateDR)
ShiftedControl<=ToNextBSCell;
end
 
assign ToOutputEnable = extest? ShiftedControl : OutputControl;
 
endmodule // ControlCell
/rtl/verilog/OutputCell.v
0,0 → 1,83
/**********************************************************************************
* *
* This verilog file is a part of the Boundary Scan Implementation and comes in *
* a pack with several other files. It is fully IEEE 1149.1 compliant. *
* For details check www.opencores.org (pdf files, bsdl file, etc.) *
* *
* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* See the file COPYING for the full details of the license. *
* *
* OPENCORES.ORG is looking for new open source IP cores and developers that *
* would like to help in our mission. *
* *
**********************************************************************************/
 
 
 
/**********************************************************************************
* *
* Output Cell: *
* *
* FromCore: Value that comes from on-chip logic and goes to pin *
* FromPreviousBSCell: Value from previous boundary scan cell *
* ToNextBSCell: Value for next boundary scan cell *
* CaptureDR, ShiftDR, UpdateDR: TAP states *
* extest: Instruction Register Command *
* TCK: Test Clock *
* TristatedPin: Signal from core is connected to this output pin via BS *
* FromOutputEnable: This pin comes from core or ControlCell *
* *
* Signal that is connected to TristatedPin comes from core or BS chain. *
* Tristate control is generated in core or BS chain (ControlCell). *
* *
**********************************************************************************/
 
// This is not a top module
module OutputCell( FromCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, TristatedPin);
input FromCore;
input FromPreviousBSCell;
input CaptureDR;
input ShiftDR;
input UpdateDR;
input extest;
input TCK;
input FromOutputEnable;
 
reg Latch;
 
output ToNextBSCell;
reg ToNextBSCell;
 
output TristatedPin;
 
reg ShiftedControl;
 
wire SelectedInput = CaptureDR? FromCore : FromPreviousBSCell;
 
always @ (posedge TCK)
begin
if(CaptureDR | ShiftDR)
Latch<=SelectedInput;
end
 
always @ (negedge TCK)
begin
ToNextBSCell<=Latch;
end
 
always @ (negedge TCK)
begin
if(UpdateDR)
ShiftedControl<=ToNextBSCell;
end
 
wire MuxedSignal = extest? ShiftedControl : FromCore;
assign TristatedPin = FromOutputEnable? MuxedSignal : 1'bz;
 
endmodule // OutputCell
/rtl/verilog/BiDirectionalCell.v
0,0 → 1,66
/**********************************************************************************
* *
* BiDirectional Cell: *
* *
* FromCore: Value that comes from on-chip logic and goes to pin *
* ToCore: Value that is read-in from the pin and goes to core *
* FromPreviousBSCell: Value from previous boundary scan cell *
* ToNextBSCell: Value for next boundary scan cell *
* CaptureDR, ShiftDR, UpdateDR: TAP states *
* extest: Instruction Register Command *
* TCK: Test Clock *
* BiDirPin: Bidirectional pin connected to this BS cell *
* FromOutputEnable: This pin comes from core or ControlCell *
* *
* Signal that is connected to BiDirPin comes from core or BS chain. Tristate *
* control is generated in core or BS chain (ControlCell). *
* *
**********************************************************************************/
 
module BiDirectionalCell( FromCore, ToCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, BiDirPin);
input FromCore;
input FromPreviousBSCell;
input CaptureDR;
input ShiftDR;
input UpdateDR;
input extest;
input TCK;
input FromOutputEnable;
 
reg Latch;
 
output ToNextBSCell;
reg ToNextBSCell;
 
output BiDirPin;
output ToCore;
 
reg ShiftedControl;
 
wire SelectedInput = CaptureDR? BiDirPin : FromPreviousBSCell;
 
always @ (posedge TCK)
begin
if(CaptureDR | ShiftDR)
Latch<=SelectedInput;
end
 
always @ (negedge TCK)
begin
ToNextBSCell<=Latch;
end
 
always @ (negedge TCK)
begin
if(UpdateDR)
ShiftedControl<=ToNextBSCell;
end
 
wire MuxedSignal = extest? ShiftedControl : FromCore;
assign BiDirPin = FromOutputEnable? MuxedSignal : 1'bz;
 
//BUF Buffer (.I(BiDirPin), .O(ToCore));
assign ToCore = BiDirPin;
 
 
endmodule // TristateCell

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