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/adv_dbg_tb.v
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//////////////////////////////////////////////////////////////////////
//// ////
//// adv_dbg_tb.v ////
//// ////
//// ////
//// Testbench for the SoC Advanced Debug Interface. ////
//// ////
//// Author(s): ////
//// Nathan Yawn (nathan.yawn@opencored.org) ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: adv_dbg_tb.v,v $
// Revision 1.7 2010-01-13 00:55:45 Nathan
// Created hi-speed mode for burst reads. This will probably be most beneficial to the OR1K module, as GDB does a burst read of all the GPRs each time a microinstruction is single-stepped.
//
// Revision 1.2 2009/05/17 20:54:55 Nathan
// Changed email address to opencores.org
//
// Revision 1.1 2008/07/08 19:11:55 Nathan
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
//
// Revision 1.11 2008/07/08 18:53:47 Nathan
// Fixed wrong include name.
//
// Revision 1.10 2008/06/30 20:09:19 Nathan
// Removed code to select top-level module as active (it served no purpose). Re-numbered modules, requiring changes to testbench and software driver.
//
 
 
`include "tap_defines.v"
`include "adbg_defines.v"
`include "adbg_wb_defines.v"
`include "wb_model_defines.v"
 
// Polynomial for the CRC calculation
// Yes, it's backwards. Yes, this is on purpose.
// To decrease logic + routing, we want to shift the CRC calculation
// in the same direction we use to shift the data out, LSB first.
`define DBG_CRC_POLY 32'hedb88320
 
// These are indicies into an array which hold values for the JTAG outputs
`define JTAG_TMS 0
`define JTAG_TCK 1
`define JTAG_TDO 2
 
`define JTAG_TMS_bit 3'h1
`define JTAG_TCK_bit 3'h2
`define JTAG_TDO_bit 3'h4
 
`define wait_jtag_period #50
 
 
module adv_debug_tb;
 
// Connections to the JTAG TAP
reg jtag_tck_o;
reg jtag_tms_o;
reg jtag_tdo_o;
wire jtag_tdi_i;
 
// Connections between TAP and debug module
wire capture_dr;
wire shift_dr;
wire pause_dr;
wire update_dr;
wire dbg_rst;
wire dbg_tdi;
wire dbg_tdo;
wire dbg_sel;
 
// Connections between the debug module and the wishbone
`ifdef DBG_WISHBONE_SUPPORTED
wire [31:0] wb_adr;
wire [31:0] wb_dat_m;
wire [31:0] wb_dat_s;
wire wb_cyc;
wire wb_stb;
wire [3:0] wb_sel;
wire wb_we;
wire wb_ack;
wire wb_err;
reg wb_clk_i; // the wishbone clock
reg wb_rst_i;
`endif
 
`ifdef DBG_CPU0_SUPPORTED
wire cpu0_clk;
wire [31:0]cpu0_addr;
wire [31:0] cpu0_data_c;
wire [31:0] cpu0_data_d;
wire cpu0_bp;
wire cpu0_stall;
wire cpu0_stb;
wire cpu0_we;
wire cpu0_ack;
wire cpu0_rst;
`endif
 
`ifdef DBG_CPU1_SUPPORTED
reg cpu1_clk;
wire [31:0]cpu1_addr;
wire [31:0] cpu1_data_c;
wire [31:0] cpu1_data_d;
wire cpu1_bp;
wire cpu1_stall;
wire cpu1_stb;
wire cpu1_we;
wire cpu1_ack;
wire cpu1_rst;
`endif // `ifdef DBG_CPU1_SUPPORTED
reg test_enabled;
 
// Data which will be written to the WB interface
reg [31:0] static_data32 [0:15];
reg [15:0] static_data16 [0:15];
reg [7:0] static_data8 [0:15];
 
// Arrays to hold data read back from the WB interface, for comparison
reg [31:0] input_data32 [0:15];
reg [15:0] input_data16 [0:15];
reg [7:0] input_data8 [0:15];
 
reg [32:0] err_data; // holds the contents of the error register from the various modules
 
reg failed;
integer i;
 
initial
begin
jtag_tck_o = 1'b0;
jtag_tms_o = 1'b0;
jtag_tdo_o = 1'b0;
end
 
// Provide the wishbone clock
`ifdef DBG_WISHBONE_SUPPORTED
initial
begin
wb_clk_i = 1'b0;
forever #7 wb_clk_i = ~wb_clk_i; // Odd frequency ratio to test the synchronization
end
`endif
 
// Provide the CPU0 clock
//`ifdef DBG_CPU0_SUPPORTED
//initial
//begin
//cpu0_clk = 1'b0;
//forever #6 cpu0_clk = ~cpu0_clk; // Odd frequency ratio to test the synchronization
//end
//`endif
 
// Start the test (and reset the wishbone)
initial
begin
test_enabled = 1'b0;
wb_rst_i = 1'b0;
#100;
wb_rst_i = 1'b1;
#100;
wb_rst_i = 1'b0;
 
// Init the memory
initialize_memory(32'h0,32'h16);
// Init the WB model
i_wb.cycle_response(`ACK_RESPONSE, 2, 0); // response type, wait cycles, retry_cycles
 
#1 test_enabled<=#1 1'b1;
end
 
// This is the main test procedure
always @ (posedge test_enabled)
begin
 
$display("Starting advanced debug test");
reset_jtag;
#1000;
check_idcode;
#1000;
// Select the debug module in the IR
set_ir(`DEBUG);
#1000;
///////////////////////////////////////////////////////////////////
// Test CPU0 unit
////////////////////////////////////////////////////////////////////
`ifdef DBG_CPU0_SUPPORTED
// Select the CPU0 unit in the debug module
#1000;
$display("Selecting CPU0 module at time %t", $time);
select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
 
// Test reset, stall bits
#1000;
$display("Testing CPU0 intreg select at time %t", $time);
select_module_internal_register(32'h1, 1); // Really just a read, with discarded data
#1000;
select_module_internal_register(32'h0, 1); // Really just a read, with discarded data
#1000;
// Read the stall and reset bits
$display("Testing reset and stall bits at time %t", $time);
read_module_internal_register(8'd2, err_data); // We assume the register is already selected
$display("Reset and stall bits are %x", err_data);
#1000;
// Set rst/stall bits
$display("Setting reset and stall bits at time %t", $time);
write_module_internal_register(32'h0, 8'h1, 32'h3, 8'h2); // idx, idxlen, data, datalen
#1000;
// Read the bits again
$display("Testing reset and stall bits again at time %t", $time);
read_module_internal_register(8'd2, err_data); // We assume the register is already selected
$display("Reset and stall bits are %x", err_data);
#1000;
// Clear the bits
$display("Clearing reset and stall bits at time %t", $time);
write_module_internal_register(32'h0, 8'h1, 32'h0, 8'h2); // idx, idxlen, data, datalen
#1000;
// Read the bits again
$display("Testing reset and stall bits again at time %t", $time);
read_module_internal_register(8'd2, err_data); // We assume the register is already selected
$display("Reset and stall bits are %x", err_data);
#1000;
// Behavioral CPU model must be stalled in order to do SPR access
//$display("Setting reset and stall bits at time %t", $time);
write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h2); // idx, idxlen, data, datalen
#1000;
// Test SPR bus access
$display("Testing CPU0 32-bit burst write at time %t", $time);
do_module_burst_write(3'h4, 16'd16, 32'h10); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
#1000;
$display("Testing CPU0 32-bit burst read at time %t", $time);
do_module_burst_read(3'h4, 16'd16, 32'h0);
#1000;
 
`endif
 
///////////////////////////////////////////////////////////////////
// Test the Wishbone unit
////////////////////////////////////////////////////////////////////
`ifdef DBG_WISHBONE_SUPPORTED
// Select the WB unit in the debug module
#1000;
$display("Selecting Wishbone module at time %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
/*
// Test error conditions
#1000;
$display("Testing error (size 0 WB burst write) at time %t", $time);
do_module_burst_write(3'h1, 16'h0, 32'h0); // 0-word write = error, ignored
#1000;
$display("Testing error (size 0 WB burst read) at time %t", $time);
do_module_burst_read(3'h1, 16'h0, 32'h0); // 0-word read = error, ignored
// Test NOP (a zero in the MSB, then a NOP opcode)
#1000;
$display("Testing NOP at time %t", $time);
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream(5'h0, 8'h5, 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
#1000;
*/
/*
#1000;
$display("Testing WB intreg select at time %t", $time);
select_module_internal_register(32'h1, 1); // Really just a read, with discarded data
#1000;
select_module_internal_register(32'h0, 1); // Really just a read, with discarded data
#1000;
// Reset the error bit
write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h1); // idx, idxlen, data, datalen
#1000;
// Read the error bit
read_module_internal_register(8'd33, err_data); // We assume the register is already selected
#1000;
*/
/////////////////////////////////
// Test 8-bit WB access
failed = 0;
$display("Testing WB 8-bit burst write at time %t: resetting ", $time);
do_module_burst_write(3'h1, 16'd16, 32'h0); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
#1000;
$display("Testing WB 8-bit burst read at time %t", $time);
do_module_burst_read(3'h1, 16'd16, 32'h0);
#1000;
for(i = 0; i < 16; i = i+1) begin
if(static_data8[i] != input_data8[i]) begin
failed = 1;
$display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data8[i], input_data8[i]);
end
end
if(!failed) $display("8-bit read/write OK!");
/* try it unaligned
do_module_burst_write(3'h1, 16'd5, 32'h3); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
#1000;
do_module_burst_read(3'h1, 16'd4, 32'h4);
#1000;
*/
/////////////////////////////////
// Test 16-bit WB access
failed = 0;
$display("Testing WB 16-bit burst write at time %t", $time);
do_module_burst_write(3'h2, 16'd16, 32'h0); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
#1000;
$display("Testing WB 16-bit burst read at time %t", $time);
do_module_burst_read(3'h2, 16'd16, 32'h0);
#1000;
for(i = 0; i < 16; i = i+1) begin
if(static_data16[i] != input_data16[i]) begin
failed = 1;
$display("16-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data16[i], input_data16[i]);
end
end
if(!failed) $display("16-bit read/write OK!");
/* try it unaligned
do_module_burst_write(3'h2, 16'd5, 32'h2); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
#1000;
do_module_burst_read(3'h2, 16'd4, 32'h4);
#1000;
*/
////////////////////////////////////
// Test 32-bit WB access
failed = 0;
$display("Testing WB 32-bit burst write at time %t", $time);
do_module_burst_write(3'h4, 16'd16, 32'h0); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
#1000;
$display("Testing WB 32-bit burst read at time %t", $time);
do_module_burst_read(3'h4, 16'd16, 32'h0);
#1000;
for(i = 0; i < 16; i = i+1) begin
if(static_data32[i] != input_data32[i]) begin
failed = 1;
$display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data32[i], input_data32[i]);
end
end
if(!failed) $display("32-bit read/write OK!");
/* Try another address
do_module_burst_write(3'h4, 16'd16, 32'h200); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
#1000;
do_module_burst_read(3'h4, 16'd15, 32'h204);
#1000;
*/
////////////////////////////////
// Test error register
err_data = 33'h0;
// Select and reset the error register
write_module_internal_register(`DBG_WB_INTREG_ERROR, `DBG_WB_REGSELECT_SIZE, 64'h1, 8'h1); // regidx,idxlen,writedata, datalen;
i_wb.cycle_response(`ERR_RESPONSE, 2, 0); // response type, wait cycles, retry_cycles
do_module_burst_write(3'h4, 16'd4, 32'hdeaddead); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
read_module_internal_register(8'd33, err_data); // get the error register
$display("Error bit is %d, error address is %x", err_data[0], err_data>>1);
 
`endif // WB module supported
end
 
task initialize_memory;
input [31:0] start_addr;
input [31:0] length;
integer i;
reg [31:0] addr;
begin
 
for (i=0; i<length; i=i+1)
begin
static_data32[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
static_data16[i] <= {i[7:0], i[7:0]+ 2'd1};
static_data8[i] <= i[7:0];
end
end
endtask
 
///////////////////////////////////////////////////////////////////////////////
// Declaration and interconnection of components
 
// Top module
tap_top i_tap (
// JTAG pads
.tms_pad_i(jtag_tms_o),
.tck_pad_i(jtag_tck_o),
.trstn_pad_i(1'b1),
.tdi_pad_i(jtag_tdo_o),
.tdo_pad_o(jtag_tdi_i),
.tdo_padoe_o(),
 
// TAP states
.test_logic_reset_o(dbg_rst),
.run_test_idle_o(),
.shift_dr_o(shift_dr),
.pause_dr_o(pause_dr),
.update_dr_o(update_dr),
.capture_dr_o(capture_dr),
// Select signals for boundary scan or mbist
.extest_select_o(),
.sample_preload_select_o(),
.mbist_select_o(),
.debug_select_o(dbg_sel),
// TDO signal that is connected to TDI of sub-modules.
.tdi_o(dbg_tdo),
// TDI signals from sub-modules
.debug_tdo_i(dbg_tdi), // from debug module
.bs_chain_tdo_i(1'b0), // from Boundary Scan Chain
.mbist_tdo_i(1'b0) // from Mbist Chain
);
 
 
// Top module
adbg_top i_dbg_module(
// JTAG signals
.tck_i(jtag_tck_o),
.tdi_i(dbg_tdo),
.tdo_o(dbg_tdi),
.rst_i(dbg_rst),
 
// TAP states
.shift_dr_i(shift_dr),
.pause_dr_i(pause_dr),
.update_dr_i(update_dr),
.capture_dr_i(capture_dr),
 
// Instructions
.debug_select_i(dbg_sel)
 
 
`ifdef DBG_WISHBONE_SUPPORTED
// WISHBONE common signals
,
.wb_clk_i(wb_clk_i),
// WISHBONE master interface
.wb_adr_o(wb_adr),
.wb_dat_o(wb_dat_m),
.wb_dat_i(wb_dat_s),
.wb_cyc_o(wb_cyc),
.wb_stb_o(wb_stb),
.wb_sel_o(wb_sel),
.wb_we_o(wb_we),
.wb_ack_i(wb_ack),
.wb_cab_o(),
.wb_err_i(wb_err),
.wb_cti_o(),
.wb_bte_o()
`endif
 
`ifdef DBG_CPU0_SUPPORTED
// CPU signals
,
.cpu0_clk_i(cpu0_clk),
.cpu0_addr_o(cpu0_addr),
.cpu0_data_i(cpu0_data_c),
.cpu0_data_o(cpu0_data_d),
.cpu0_bp_i(cpu0_bp),
.cpu0_stall_o(cpu0_stall),
.cpu0_stb_o(cpu0_stb),
.cpu0_we_o(cpu0_we),
.cpu0_ack_i(cpu0_ack),
.cpu0_rst_o(cpu0_rst)
`endif
 
`ifdef DBG_CPU1_SUPPORTED
// CPU signals
,
.cpu1_clk_i(cpu1_clk),
.cpu1_addr_o(cpu1_addr),
.cpu1_data_i(cpu1_data_c),
.cpu1_data_o(cpu1_data_d),
.cpu1_bp_i(cpu1_bp),
.cpu1_stall_o(cpu1_stall),
.cpu1_stb_o(cpu1_stb),
.cpu1_we_o(cpu1_we),
.cpu1_ack_i(cpu1_ack),
.cpu1_rst_o(cpu1_rst)
`endif
 
);
 
 
`ifdef DBG_WISHBONE_SUPPORTED
// The 'wishbone' may be just a p2p connection to a simple RAM
/*
onchip_ram_top i_ocram (
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wb_dat_i(wb_dat_m),
.wb_dat_o(wb_dat_s),
.wb_adr_i(wb_adr[11:0]),
.wb_sel_i(wb_sel),
.wb_we_i(wb_we),
.wb_cyc_i(wb_cyc),
.wb_stb_i(wb_stb),
.wb_ack_o(wb_ack),
.wb_err_o(wb_err)
);
*/
 
wb_slave_behavioral i_wb
(
.CLK_I(wb_clk_i),
.RST_I(wb_rst_i),
.ACK_O(wb_ack),
.ADR_I(wb_adr),
.CYC_I(wb_cyc),
.DAT_O(wb_dat_s),
.DAT_I(wb_dat_m),
.ERR_O(wb_err),
.RTY_O(),
.SEL_I(wb_sel),
.STB_I(wb_stb),
.WE_I(wb_we),
.CAB_I(1'b0)
);
`endif
 
 
`ifdef DBG_CPU0_SUPPORTED
// Instantiate a behavioral model of the CPU SPR bus
cpu_behavioral cpu0_i (
.cpu_rst_i(cpu0_rst),
.cpu_clk_o(cpu0_clk),
.cpu_addr_i(cpu0_addr),
.cpu_data_o(cpu0_data_c),
.cpu_data_i(cpu0_data_d),
.cpu_bp_o(cpu0_bp),
.cpu_stall_i(cpu0_stall),
.cpu_stb_i(cpu0_stb),
.cpu_we_i(cpu0_we),
.cpu_ack_o(cpu0_ack),
.cpu_rst_o(cpu0_rst)
);
 
`endif
 
 
`ifdef DBG_CPU1_SUPPORTED
// Instantiate a behavioral model of the CPU SPR bus
cpu_behavioral cpu1_i (
.cpu_rst_i(cpu1_rst),
.cpu_clk_o(cpu1_clk),
.cpu_addr_i(cpu1_addr),
.cpu_data_o(cpu1_data_c),
.cpu_data_i(cpu1_data_d),
.cpu_bp_o(cpu1_bp),
.cpu_stall_i(cpu1_stall),
.cpu_stb_i(cpu1_stb),
.cpu_we_i(cpu1_we),
.cpu_ack_o(cpu1_ack),
.cpu_rst_o(cpu1_rst)
);
`endif
///////////////////////////////////////////////////////////////////////////
// Higher-level chain manipulation functions
 
// calculate the CRC, up to 32 bits at a time
task compute_crc;
input [31:0] crc_in;
input [31:0] data_in;
input [5:0] length_bits;
output [31:0] crc_out;
integer i;
reg [31:0] d;
reg [31:0] c;
begin
crc_out = crc_in;
for(i = 0; i < length_bits; i = i+1) begin
d = (data_in[i]) ? 32'hffffffff : 32'h0;
c = (crc_out[0]) ? 32'hffffffff : 32'h0;
//crc_out = {crc_out[30:0], 1'b0}; // original
crc_out = crc_out >> 1;
crc_out = crc_out ^ ((d ^ c) & `DBG_CRC_POLY);
//$display("CRC Itr %d, inbit = %d, crc = 0x%x", i, data_in[i], crc_out);
end
end
endtask
 
task check_idcode;
reg [63:0] readdata;
reg[31:0] idcode;
begin
set_ir(`IDCODE);
// Read the IDCODE in the DR
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_read_write_stream(64'h0, 8'd32, 1, readdata); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
idcode = readdata[31:0];
$display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);
end
endtask;
 
task select_debug_module;
input [1:0] moduleid;
reg validid;
begin
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream({1'b1,moduleid}, 8'h3, 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
$display("Selecting module (%0x)", moduleid);
// Read back the status to make sure a valid chain is selected
/* Pointless, the newly selected module would respond instead...
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
read_write_bit(`JTAG_TMS_bit, validid); // get data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
if(validid) $display("Selected valid module (%0x)", moduleid);
else $display("Failed to select module (%0x)", moduleid);
*/
end
endtask
 
 
task send_module_burst_command;
input [3:0] opcode;
input [31:0] address;
input [15:0] burstlength;
reg [63:0] streamdata;
begin
streamdata = {11'h0,1'b0,opcode,address,burstlength};
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream(streamdata, 8'd53, 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
end
endtask
 
task select_module_internal_register; // Really just a read, with discarded data
input [31:0] regidx;
input [7:0] len; // the length of the register index data, we assume not more than 32
reg[63:0] streamdata;
begin
streamdata = 64'h0;
streamdata = streamdata | regidx;
streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream(streamdata, (len+5), 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
end
endtask
 
task read_module_internal_register; // We assume the register is already selected
//input [31:0] regidx;
input [7:0] len; // the length of the data desired, we assume a max of 64 bits
output [63:0] instream;
reg [63:0] bitmask;
begin
instream = 64'h0;
// We shift out all 0's, which is a NOP to the debug unit
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
// Shift at least 5 bits, as this is the min, for a valid NOP
jtag_read_write_stream(64'h0, len+4,1,instream); // exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
bitmask = 64'hffffffffffffffff;
bitmask = bitmask << len;
bitmask = ~bitmask;
instream = instream & bitmask; // Cut off any unwanted excess bits
end
endtask
 
task write_module_internal_register;
input [31:0] regidx; // the length of the register index data
input [7:0] idxlen;
input [63:0] writedata;
input [7:0] datalen; // the length of the data to write. We assume the two length combined are 59 or less.
reg[63:0] streamdata;
begin
streamdata = 64'h0; // This will 0 the toplevel/module select bit
streamdata = streamdata | writedata;
streamdata = streamdata | (regidx << datalen);
streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream(streamdata, (idxlen+datalen+5), 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
end
endtask
 
// This includes the sending of the burst command
task do_module_burst_read;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] instream;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o; // temp signal...
reg [31:0] crc_read;
reg [5:0] word_size_bits;
begin
$display("Doing burst read, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
instream = 64'h0;
word_size_bits = word_size_bytes << 3;
crc_calc_i = 32'hffffffff;
// Send the command
case (word_size_bytes)
3'h1: opcode = `DBG_WB_CMD_BREAD8;
3'h2: opcode = `DBG_WB_CMD_BREAD16;
3'h4: opcode = `DBG_WB_CMD_BREAD32;
default:
begin
$display("Tried burst read with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
opcode = `DBG_WB_CMD_BREAD32;
end
endcase
send_module_burst_command(opcode,start_address, word_count); // returns to state idle
// Get us back to shift_dr mode to read a burst
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
 
`ifdef ADBG_USE_HISPEED
// Get 1 status bit, then word_size_bytes*8 bits
status = 1'b0;
j = 0;
while(!status) begin
read_write_bit(3'h0, status);
j = j + 1;
end
if(j > 1) begin
$display("Took %0d tries before good status bit during burst read", j);
end
`endif
// Now, repeat...
for(i = 0; i < word_count; i=i+1) begin
`ifndef ADBG_USE_HISPEED
// Get 1 status bit, then word_size_bytes*8 bits
status = 1'b0;
j = 0;
while(!status) begin
read_write_bit(3'h0, status);
j = j + 1;
end
if(j > 1) begin
$display("Took %0d tries before good status bit during burst read", j);
end
`endif
jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream);
//$display("Read 0x%0x", instream[31:0]);
compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o);
crc_calc_i = crc_calc_o;
if(word_size_bytes == 1) input_data8[i] = instream[7:0];
else if(word_size_bytes == 2) input_data16[i] = instream[15:0];
else input_data32[i] = instream[31:0];
end
// Read the data CRC from the debug module.
jtag_read_write_stream(64'h0, 6'd32, 1, crc_read);
if(crc_calc_o != crc_read) $display("CRC ERROR! Computed 0x%x, read CRC 0x%x", crc_calc_o, crc_read);
else $display("CRC OK!");
// Finally, shift out 5 0's, to make the next command a NOP
// Not necessary, debug unit won't latch a new opcode at the end of a burst
//jtag_write_stream(64'h0, 8'h5, 1);
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
end
endtask
 
 
task do_module_burst_write;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] dataword;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o;
reg crc_match;
reg [5:0] word_size_bits;
begin
$display("Doing burst write, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
word_size_bits = word_size_bytes << 3;
crc_calc_i = 32'hffffffff;
// Send the command
case (word_size_bytes)
3'h1: opcode = `DBG_WB_CMD_BWRITE8;
3'h2: opcode = `DBG_WB_CMD_BWRITE16;
3'h4: opcode = `DBG_WB_CMD_BWRITE32;
default:
begin
$display("Tried burst write with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
opcode = `DBG_WB_CMD_BWRITE32;
end
endcase
send_module_burst_command(opcode, start_address, word_count); // returns to state idle
// Get us back to shift_dr mode to write a burst
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
 
// Write a start bit (a 1) so it knows when to start counting
write_bit(`JTAG_TDO_bit);
 
// Now, repeat...
for(i = 0; i < word_count; i=i+1) begin
// Write word_size_bytes*8 bits, then get 1 status bit
if(word_size_bytes == 4) dataword = {32'h0, static_data32[i]};
else if(word_size_bytes == 2) dataword = {48'h0, static_data16[i]};
else dataword = {56'h0, static_data8[i]};
jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0);
compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o);
crc_calc_i = crc_calc_o;
`ifndef ADBG_USE_HISPEED
// Check if WB bus is ready
// *** THIS WILL NOT WORK IF THERE IS MORE THAN 1 DEVICE IN THE JTAG CHAIN!!!
status = 1'b0;
read_write_bit(3'h0, status);
if(!status) begin
$display("Bad status bit during burst write, index %d", i);
end
`endif
//$display("Wrote 0x%0x", dataword);
end
// Send the CRC we computed
jtag_write_stream(crc_calc_o, 6'd32,0);
// Read the 'CRC match' bit, and go to exit1_dr
read_write_bit(`JTAG_TMS_bit, crc_match);
if(!crc_match) $display("CRC ERROR! match bit after write is %d (computed CRC 0x%x)", crc_match, crc_calc_o);
else $display("CRC OK!");
// Finally, shift out 5 0's, to make the next command a NOP
// Not necessary, module will not latch new opcode during burst
//jtag_write_stream(64'h0, 8'h5, 1);
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
end
 
endtask
 
 
// Puts a value in the TAP IR, assuming we start in IDLE state.
// Returns to IDLE state when finished
task set_ir;
input [3:0] irval;
begin
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(`JTAG_TMS_bit); // select_ir_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream({60'h0,irval}, 8'h4, 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
end
endtask
 
// Resets the TAP and puts it into idle mode
task reset_jtag;
integer i;
begin
for(i = 0; i < 8; i=i+1) begin
write_bit(`JTAG_TMS_bit); // 5 TMS should put us in test_logic_reset mode
end
write_bit(3'h0); // idle
end
endtask
 
 
////////////////////////////////////////////////////////////////////////////
// Tasks to write or read-write a string of data
 
task jtag_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
integer i;
integer databit;
reg [2:0] bits;
begin
for(i = 0; i < (len-1); i=i+1) begin
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
write_bit(bits);
end
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
write_bit(bits);
end
endtask
 
 
task jtag_read_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
output [63:0] instream;
integer i;
integer databit;
reg [2:0] bits;
reg inbit;
begin
instream = 64'h0;
for(i = 0; i < (len-1); i=i+1) begin
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
read_write_bit(bits, inbit);
instream = (instream | (inbit << i));
end
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
read_write_bit(bits, inbit);
instream = (instream | (inbit << (len-1)));
end
endtask
 
/////////////////////////////////////////////////////////////////////////
// Tasks which write or readwrite a single bit (including clocking)
 
task write_bit;
input [2:0] bitvals;
begin
// Set data
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
// Raise clock
jtag_out(bitvals | `JTAG_TCK_bit);
`wait_jtag_period;
// drop clock (making output available in the SHIFT_xR states)
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
end
endtask
 
task read_write_bit;
input [2:0] bitvals;
output l_tdi_val;
begin
// read bit state
l_tdi_val <= jtag_tdi_i;
// Set data
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
// Raise clock
jtag_out(bitvals | `JTAG_TCK_bit);
`wait_jtag_period;
// drop clock (making output available in the SHIFT_xR states)
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
end
endtask
 
/////////////////////////////////////////////////////////////////
// Basic functions to set the state of the JTAG TAP I/F bits
 
task jtag_out;
input [2:0] bitvals;
begin
 
jtag_tck_o <= bitvals[`JTAG_TCK];
jtag_tms_o <= bitvals[`JTAG_TMS];
jtag_tdo_o <= bitvals[`JTAG_TDO];
end
endtask
 
 
task jtag_inout;
input [2:0] bitvals;
output l_tdi_val;
begin
 
jtag_tck_o <= bitvals[`JTAG_TCK];
jtag_tms_o <= bitvals[`JTAG_TMS];
jtag_tdo_o <= bitvals[`JTAG_TDO];
 
l_tdi_val <= jtag_tdi_i;
end
endtask
 
endmodule
/wb_slave_behavioral.v
0,0 → 1,428
//////////////////////////////////////////////////////////////////////
//// ////
//// wb_slave_behavioral.v ////
//// ////
//// ////
//// This file is part of the SoC Debug Interface. ////
//// http://www.opencores.org/projects/DebugInterface/ ////
//// ////
//// Author(s): ////
//// Tadej Markovic, tadej@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: wb_slave_behavioral.v,v $
// Revision 1.2 2010-01-08 01:41:08 Nathan
// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
//
// Revision 1.1 2008/07/08 19:11:57 Nathan
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
//
// Revision 1.2 2008/06/26 20:54:44 Nathan
// Testbench modified to use WB behavioral model instead of an onchip_ram. Added test of WB error register.
//
// Revision 1.1 2008/06/18 18:34:49 Nathan
// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.
//
// Revision 1.1.1.1 2008/05/14 12:07:36 Nathan
// Original from OpenCores
//
// Revision 1.3 2004/03/28 20:27:40 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.2 2004/01/15 10:47:13 mohor
// Working.
//
// Revision 1.1 2003/12/23 14:26:01 mohor
// New version of the debug interface. Not finished, yet.
//
//
//
//
 
//`include "timescale.v"
`include "wb_model_defines.v"
module wb_slave_behavioral
(
CLK_I,
RST_I,
ACK_O,
ADR_I,
CYC_I,
DAT_O,
DAT_I,
ERR_O,
RTY_O,
SEL_I,
STB_I,
WE_I,
CAB_I
);
 
/*------------------------------------------------------------------------------------------------------
WISHBONE signals
------------------------------------------------------------------------------------------------------*/
input CLK_I;
input RST_I;
output ACK_O;
input `WB_ADDR_TYPE ADR_I;
input CYC_I;
output `WB_DATA_TYPE DAT_O;
input `WB_DATA_TYPE DAT_I;
output ERR_O;
output RTY_O;
input `WB_SEL_TYPE SEL_I;
input STB_I;
input WE_I;
input CAB_I;
 
reg `WB_DATA_TYPE DAT_O;
 
/*------------------------------------------------------------------------------------------------------
Asynchronous dual-port RAM signals for storing and fetching the data
------------------------------------------------------------------------------------------------------*/
//reg `WB_DATA_TYPE wb_memory [0:16777215]; // WB memory - 24 addresses connected - 2 LSB not used
reg `WB_DATA_TYPE wb_memory [0:1048575]; // WB memory - 20 addresses connected - 2 LSB not used
reg `WB_DATA_TYPE mem_wr_data_out;
reg `WB_DATA_TYPE mem_rd_data_in;
 
/*------------------------------------------------------------------------------------------------------
Maximum values for WAIT and RETRY counters and which response !!!
------------------------------------------------------------------------------------------------------*/
reg [2:0] a_e_r_resp; // tells with which cycle_termination_signal must wb_slave respond !
reg [8:0] wait_cyc;
reg [7:0] max_retry;
 
// assign registers to default state while in reset
// always@(RST_I)
// begin
// if (RST_I)
// begin
// a_e_r_resp <= 3'b000; // do not respond
// wait_cyc <= 8'b0; // no wait cycles
// max_retry <= 8'h0; // no retries
// end
// end //reset
 
task cycle_response;
input [2:0] ack_err_rty_resp; // acknowledge, error or retry response input flags
input [8:0] wait_cycles; // if wait cycles before each data termination cycle (ack, err or rty)
input [7:0] retry_cycles; // noumber of retry cycles before acknowledge cycle
begin
// assign values
a_e_r_resp <= #1 ack_err_rty_resp;
wait_cyc <= #1 wait_cycles;
max_retry <= #1 retry_cycles;
end
endtask // cycle_response
 
/*------------------------------------------------------------------------------------------------------
Tasks for writing and reading to and from memory !!!
------------------------------------------------------------------------------------------------------*/
reg `WB_ADDR_TYPE task_wr_adr_i;
reg `WB_ADDR_TYPE task_rd_adr_i;
reg `WB_DATA_TYPE task_dat_i;
reg `WB_DATA_TYPE task_dat_o;
reg `WB_SEL_TYPE task_sel_i;
reg task_wr_data;
reg task_data_written;
reg `WB_DATA_TYPE task_mem_wr_data;
 
// write to memory
task wr_mem;
input `WB_ADDR_TYPE adr_i;
input `WB_DATA_TYPE dat_i;
input `WB_SEL_TYPE sel_i;
begin
task_data_written = 0;
task_wr_adr_i = adr_i;
task_dat_i = dat_i;
task_sel_i = sel_i;
task_wr_data = 1;
wait(task_data_written);
task_wr_data = 0;
end
endtask
 
// read from memory
task rd_mem;
input `WB_ADDR_TYPE adr_i;
output `WB_DATA_TYPE dat_o;
input `WB_SEL_TYPE sel_i;
begin
task_rd_adr_i = adr_i;
task_sel_i = sel_i;
#1;
dat_o = task_dat_o;
end
endtask
 
/*------------------------------------------------------------------------------------------------------
Internal signals and logic
------------------------------------------------------------------------------------------------------*/
reg calc_ack;
reg calc_err;
reg calc_rty;
 
reg [7:0] retry_cnt;
reg [7:0] retry_num;
reg retry_expired;
 
// Retry counter
always@(posedge RST_I or posedge CLK_I)
begin
if (RST_I)
retry_cnt <= #1 8'h00;
else
begin
if (calc_ack || calc_err)
retry_cnt <= #1 8'h00;
else if (calc_rty)
retry_cnt <= #1 retry_num;
end
end
 
always@(retry_cnt or max_retry)
begin
if (retry_cnt < max_retry)
begin
retry_num = retry_cnt + 1'b1;
retry_expired = 1'b0;
end
else
begin
retry_num = retry_cnt;
retry_expired = 1'b1;
end
end
 
reg [8:0] wait_cnt;
reg [8:0] wait_num;
reg wait_expired;
 
// Wait counter
always@(posedge RST_I or posedge CLK_I)
begin
if (RST_I)
wait_cnt <= #1 9'h0;
else
begin
if (wait_expired || ~STB_I)
wait_cnt <= #1 9'h0;
else
wait_cnt <= #1 wait_num;
end
end
 
always@(wait_cnt or wait_cyc or STB_I or a_e_r_resp or retry_expired)
begin
if ((wait_cyc > 0) && (STB_I))
begin
if (wait_cnt < wait_cyc)
begin
wait_num = wait_cnt + 1'b1;
wait_expired = 1'b0;
calc_ack = 1'b0;
calc_err = 1'b0;
calc_rty = 1'b0;
end
else
begin
wait_num = wait_cnt;
wait_expired = 1'b1;
if (a_e_r_resp == 3'b100)
begin
calc_ack = 1'b1;
calc_err = 1'b0;
calc_rty = 1'b0;
end
else
if (a_e_r_resp == 3'b010)
begin
calc_ack = 1'b0;
calc_err = 1'b1;
calc_rty = 1'b0;
end
else
if (a_e_r_resp == 3'b001)
begin
calc_err = 1'b0;
if (retry_expired)
begin
calc_ack = 1'b1;
calc_rty = 1'b0;
end
else
begin
calc_ack = 1'b0;
calc_rty = 1'b1;
end
end
else
begin
calc_ack = 1'b0;
calc_err = 1'b0;
calc_rty = 1'b0;
end
end
end
else
if ((wait_cyc == 0) && (STB_I))
begin
wait_num = 9'h0;
wait_expired = 1'b1;
if (a_e_r_resp == 3'b100)
begin
calc_ack = 1'b1;
calc_err = 1'b0;
calc_rty = 1'b0;
end
else if (a_e_r_resp == 3'b010)
begin
calc_ack = 1'b0;
calc_err = 1'b1;
calc_rty = 1'b0;
end
else if (a_e_r_resp == 3'b001)
begin
calc_err = 1'b0;
if (retry_expired)
begin
calc_ack = 1'b1;
calc_rty = 1'b0;
end
else
begin
calc_ack = 1'b0;
calc_rty = 1'b1;
end
end
else
begin
calc_ack = 1'b0;
calc_err = 1'b0;
calc_rty = 1'b0;
end
end
else
begin
wait_num = 9'h0;
wait_expired = 1'b0;
calc_ack = 1'b0;
calc_err = 1'b0;
calc_rty = 1'b0;
end
end
 
wire rd_sel = (CYC_I && STB_I && ~WE_I);
wire wr_sel = (CYC_I && STB_I && WE_I);
 
// Generate cycle termination signals
assign ACK_O = calc_ack && STB_I;
assign ERR_O = calc_err && STB_I;
assign RTY_O = calc_rty && STB_I;
 
// Assign address to asynchronous memory
always@(RST_I or ADR_I)
begin
if (RST_I) // this is added because at start of test bench we need address change in order to get data!
begin
#1 mem_rd_data_in = `WB_DATA_WIDTH'hxxxx_xxxx;
end
else
begin
// #1 mem_rd_data_in = wb_memory[ADR_I[25:2]];
#1 mem_rd_data_in = wb_memory[ADR_I[21:2]];
end
end
 
// Data input/output interface
always@(rd_sel or mem_rd_data_in or RST_I)
begin
if (RST_I)
DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx; // assign outputs to unknown state while in reset
else if (rd_sel)
DAT_O <=#1 mem_rd_data_in;
else
DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx;
end
 
 
always@(RST_I or task_rd_adr_i)
begin
if (RST_I)
task_dat_o = `WB_DATA_WIDTH'hxxxx_xxxx;
else
task_dat_o = wb_memory[task_rd_adr_i[21:2]];
end
always@(CLK_I or wr_sel or task_wr_data or ADR_I or task_wr_adr_i or
mem_wr_data_out or DAT_I or task_mem_wr_data or task_dat_i or
SEL_I or task_sel_i)
begin
if (task_wr_data)
begin
task_mem_wr_data = wb_memory[task_wr_adr_i[21:2]];
 
if (task_sel_i[3])
task_mem_wr_data[31:24] = task_dat_i[31:24];
if (task_sel_i[2])
task_mem_wr_data[23:16] = task_dat_i[23:16];
if (task_sel_i[1])
task_mem_wr_data[15: 8] = task_dat_i[15: 8];
if (task_sel_i[0])
task_mem_wr_data[ 7: 0] = task_dat_i[ 7: 0];
 
wb_memory[task_wr_adr_i[21:2]] = task_mem_wr_data; // write data
task_data_written = 1;
end
else if (wr_sel && CLK_I)
begin
// mem_wr_data_out = wb_memory[ADR_I[25:2]]; // if no SEL_I is active, old value will be written
mem_wr_data_out = wb_memory[ADR_I[21:2]]; // if no SEL_I is active, old value will be written
 
if (SEL_I[3])
mem_wr_data_out[31:24] = DAT_I[31:24];
if (SEL_I[2])
mem_wr_data_out[23:16] = DAT_I[23:16];
if (SEL_I[1])
mem_wr_data_out[15: 8] = DAT_I[15: 8];
if (SEL_I[0])
mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0];
 
// wb_memory[ADR_I[25:2]] <= mem_wr_data_out; // write data
wb_memory[ADR_I[21:2]] = mem_wr_data_out; // write data
end
end
 
endmodule
/wave.do
0,0 → 1,333
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {JTAG top}
add wave -noupdate -format Logic /adv_debug_tb/jtag_tck_o
add wave -noupdate -format Logic /adv_debug_tb/jtag_tms_o
add wave -noupdate -format Logic /adv_debug_tb/jtag_tdo_o
add wave -noupdate -format Logic /adv_debug_tb/jtag_tdi_i
add wave -noupdate -divider {TAP signals}
add wave -noupdate -format Logic /adv_debug_tb/dbg_rst
add wave -noupdate -format Logic /adv_debug_tb/capture_dr
add wave -noupdate -format Logic /adv_debug_tb/shift_dr
add wave -noupdate -format Logic /adv_debug_tb/pause_dr
add wave -noupdate -format Logic /adv_debug_tb/update_dr
add wave -noupdate -format Logic /adv_debug_tb/dbg_sel
add wave -noupdate -format Logic /adv_debug_tb/dbg_tdi
add wave -noupdate -format Logic /adv_debug_tb/dbg_tdo
add wave -noupdate -divider {Wishbone signals}
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/wb_adr
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/wb_dat_m
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/wb_dat_s
add wave -noupdate -format Logic /adv_debug_tb/wb_cyc
add wave -noupdate -format Logic /adv_debug_tb/wb_stb
add wave -noupdate -format Literal /adv_debug_tb/wb_sel
add wave -noupdate -format Logic /adv_debug_tb/wb_we
add wave -noupdate -format Logic /adv_debug_tb/wb_ack
add wave -noupdate -format Logic /adv_debug_tb/wb_err
add wave -noupdate -format Logic /adv_debug_tb/wb_clk_i
add wave -noupdate -format Logic /adv_debug_tb/wb_rst_i
add wave -noupdate -divider {CPU0 signals}
add wave -noupdate -format Logic /adv_debug_tb/cpu0_clk
add wave -noupdate -format Logic /adv_debug_tb/cpu0_rst
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/cpu0_addr
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/cpu0_data_c
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/cpu0_data_d
add wave -noupdate -format Logic /adv_debug_tb/cpu0_we
add wave -noupdate -format Logic /adv_debug_tb/cpu0_stb
add wave -noupdate -format Logic /adv_debug_tb/cpu0_ack
add wave -noupdate -format Logic /adv_debug_tb/cpu0_bp
add wave -noupdate -format Logic /adv_debug_tb/cpu0_stall
add wave -noupdate -divider {Debug top internals}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tck_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdi_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/rst_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/shift_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/pause_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/update_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/capture_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/debug_select_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_clk_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_adr_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_dat_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_dat_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_cyc_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_stb_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_sel_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_we_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_ack_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_cab_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_err_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_cti_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_bte_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_clk_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/cpu0_addr_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/cpu0_data_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/cpu0_data_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_bp_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_stall_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_stb_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_we_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_ack_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_rst_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/input_shift_reg
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/module_id_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/select_cmd
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/module_id_in
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/module_selects
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_wb
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_cpu0
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_cpu1
add wave -noupdate -divider {DBG Wishbone module internals}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/tck_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/module_tdo_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/tdi_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/capture_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/shift_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/update_dr_i
add wave -noupdate -format Literal -radix binary /adv_debug_tb/i_dbg_module/i_dbg_wb/data_register_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/module_select_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/rst_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_clk_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_adr_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_dat_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_dat_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_cyc_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_stb_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_sel_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_we_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_ack_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_cab_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_err_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_cti_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_bte_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/address_counter
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_count
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_wb/word_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/operation
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_out_shift_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/internal_register_select
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/internal_reg_error
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/addr_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/addr_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/op_reg_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_ct_rst
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/word_ct_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/word_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/out_reg_ld_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/out_reg_shift_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/out_reg_data_sel
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/tdo_output_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_strobe
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_clr
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_in_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_shift_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/regsel_ld_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/intreg_ld_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/error_reg_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_clr_err
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/word_count_zero
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_count_max
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/module_cmd
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_ready
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_err
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/burst_instruction
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/intreg_instruction
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/intreg_write
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/rd_op
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_match
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_count_32
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_wb/word_size_bits
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_wb/word_size_bytes
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/incremented_address
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_to_addr_counter
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_to_word_counter
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_wb/decremented_word_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/address_data_in
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_wb/count_data_in
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/operation_in
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_to_biu
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_from_biu
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_data_out
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_data_in
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_serial_out
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/reg_select_data
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/out_reg_data
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_from_internal_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_rst
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/module_state
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/module_next_state
add wave -noupdate -divider {DBG WB module BIU internals}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/tck_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rst_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/data_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/data_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/addr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/strobe_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rd_wrn_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/err_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/word_size_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_clk_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_adr_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_dat_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_dat_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_cyc_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_stb_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_sel_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_we_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_ack_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_cab_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_err_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_cti_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_bte_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/sel_reg
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/addr_reg
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/data_in_reg
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/data_out_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wr_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/str_sync
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_sync
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/err_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_sync_tff1
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_sync_tff2
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_sync_tff2q
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/str_sync_wbff1
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/str_sync_wbff2
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/str_sync_wbff2q
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/data_o_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_sync_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/err_en
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/be_dec
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/start_toggle
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/swapped_data_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/swapped_data_out
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_fsm_state
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/next_fsm_state
add wave -noupdate -divider {DBG CPU0 module signals}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/tck_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/module_tdo_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/tdi_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/capture_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/shift_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/update_dr_i
add wave -noupdate -format Literal -radix binary /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_register_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/module_select_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/rst_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_clk_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_addr_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_data_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_data_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_stb_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_we_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_ack_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_rst_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_bp_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_stall_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/address_counter
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/bit_count
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/word_count
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/operation
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_out_shift_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/internal_register_select
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/internal_reg_status
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/addr_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/addr_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/op_reg_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/bit_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/bit_ct_rst
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/word_ct_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/word_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/out_reg_ld_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/out_reg_shift_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/out_reg_data_sel
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/tdo_output_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/biu_strobe
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_clr
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_in_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_shift_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/regsel_ld_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/intreg_ld_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/word_count_zero
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/bit_count_max
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/module_cmd
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/biu_ready
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/burst_instruction
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/intreg_instruction
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/intreg_write
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/rd_op
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_match
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/bit_count_32
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/word_size_bits
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/incremented_address
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_to_addr_counter
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_to_word_counter
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/decremented_word_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/address_data_in
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/count_data_in
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/operation_in
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_to_biu
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_from_biu
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_data_out
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_data_in
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_serial_out
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/reg_select_data
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/out_reg_data
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_from_internal_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/status_reg_wr
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/module_state
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/module_next_state
add wave -noupdate -divider {CPU0 BIU internals}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/tck_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rst_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/data_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/data_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/addr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/strobe_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rd_wrn_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rdy_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_clk_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_addr_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_data_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_data_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_stb_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_we_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_ack_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/addr_reg
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/data_in_reg
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/data_out_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/wr_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/str_sync
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_tff1
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_tff2
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_tff2q
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/str_sync_wbff1
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/str_sync_wbff2
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/str_sync_wbff2q
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/data_o_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/start_toggle
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_fsm_state
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/next_fsm_state
add wave -noupdate -divider {CPU0 Status register internals}
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {31260960 ps} 0}
configure wave -namecolwidth 409
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {38962 ns} {70222960 ps}
/cpu_behavioral.v
0,0 → 1,155
//////////////////////////////////////////////////////////////////////
//// ////
//// cpu_behavioral.v ////
//// ////
//// ////
//// This file is part of the SoC Debug Interface. ////
//// http://www.opencores.org/projects/DebugInterface/ ////
//// ////
//// Author(s): ////
//// Igor Mohor (igorm@opencores.org) ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: cpu_behavioral.v,v $
// Revision 1.2 2010-01-08 01:41:08 Nathan
// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
//
// Revision 1.1 2008/07/08 19:11:55 Nathan
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
//
// Revision 1.1 2008/06/18 18:34:48 Nathan
// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.
//
// Revision 1.1.1.1 2008/05/14 12:07:35 Nathan
// Original from OpenCores
//
// Revision 1.4 2004/03/28 20:27:40 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.3 2004/01/22 11:07:28 mohor
// test stall_test added.
//
// Revision 1.2 2004/01/17 18:01:31 mohor
// New version.
//
// Revision 1.1 2004/01/17 17:01:25 mohor
// Almost finished.
//
//
//
//
//
`include "timescale.v"
 
 
module cpu_behavioral
(
// CPU signals
cpu_rst_i,
cpu_clk_o,
cpu_addr_i,
cpu_data_o,
cpu_data_i,
cpu_bp_o,
cpu_stall_i,
cpu_stb_i,
cpu_we_i,
cpu_ack_o,
cpu_rst_o
);
 
 
// CPU signals
input cpu_rst_i;
output cpu_clk_o;
input [31:0] cpu_addr_i;
output [31:0] cpu_data_o;
input [31:0] cpu_data_i;
output cpu_bp_o;
input cpu_stall_i;
input cpu_stb_i;
input cpu_we_i;
output cpu_ack_o;
output cpu_rst_o;
 
reg cpu_clk_o;
reg [31:0] cpu_data_o;
reg cpu_bp_o;
reg cpu_ack_o;
reg cpu_ack_q;
wire cpu_ack;
initial
begin
cpu_clk_o = 1'b0;
forever #5 cpu_clk_o = ~cpu_clk_o;
end
 
 
initial
begin
cpu_bp_o = 1'b0;
end
 
assign #200 cpu_ack = cpu_stall_i & cpu_stb_i;
 
 
 
always @ (posedge cpu_clk_o or posedge cpu_rst_i)
begin
if (cpu_rst_i)
begin
cpu_ack_o <= #1 1'b0;
cpu_ack_q <= #1 1'b0;
end
else
begin
cpu_ack_o <= #1 cpu_ack;
cpu_ack_q <= #1 cpu_ack_o;
end
end
 
always @ (posedge cpu_clk_o or posedge cpu_rst_i)
begin
if (cpu_rst_i)
cpu_data_o <= #1 32'h12345678;
else if (cpu_ack_o && (!cpu_ack_q))
cpu_data_o <= #1 cpu_data_o + 32'h11111111;
end
 
 
 
 
endmodule
 
/wb_model_defines.v
0,0 → 1,166
//////////////////////////////////////////////////////////////////////
//// ////
//// wb_model_defines.v ////
//// ////
//// ////
//// This file is part of the SoC Debug Interface. ////
//// http://www.opencores.org/projects/DebugInterface/ ////
//// ////
//// Author(s): ////
//// - Miha Dolenc (mihad@opencores.org) ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: wb_model_defines.v,v $
// Revision 1.2 2010-01-08 01:41:08 Nathan
// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
//
// Revision 1.1 2008/07/08 19:11:57 Nathan
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
//
// Revision 1.1 2008/06/18 18:34:48 Nathan
// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.
//
// Revision 1.1.1.1 2008/05/14 12:07:36 Nathan
// Original from OpenCores
//
// Revision 1.2 2004/03/28 20:27:40 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.1 2003/12/23 14:26:01 mohor
// New version of the debug interface. Not finished, yet.
//
//
//
 
// WISHBONE frequency in GHz
`define WB_FREQ 0.100
 
// memory frequency in GHz
`define MEM_FREQ 0.100
 
// setup and hold time definitions for WISHBONE - used in BFMs for signal generation
`define Tsetup 4
`define Thold 1
 
// how many clock cycles should model wait for design's response - integer 32 bit value
`define WAIT_FOR_RESPONSE 1023
 
// maximum number of transactions allowed in single call to block or cab transfer routines
`define MAX_BLK_SIZE 1024
 
// maximum retry terminations allowed for WISHBONE master to repeat an access
`define WB_TB_MAX_RTY 0
 
 
// some common types and defines
`define WB_ADDR_WIDTH 32
`define WB_DATA_WIDTH 32
`define WB_SEL_WIDTH `WB_DATA_WIDTH/8
`define WB_TAG_WIDTH 5
`define WB_ADDR_TYPE [(`WB_ADDR_WIDTH - 1):0]
`define WB_DATA_TYPE [(`WB_DATA_WIDTH - 1):0]
`define WB_SEL_TYPE [(`WB_SEL_WIDTH - 1):0]
`define WB_TAG_TYPE [(`WB_TAG_WIDTH - 1):0]
 
// read cycle stimulus - consists of:
// - address field - which address read will be performed from
// - sel field - what byte select value should be
// - tag field - what tag values should be put on the bus
`define READ_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
`define READ_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
`define READ_ADDRESS [(`WB_ADDR_WIDTH - 1):0]
`define READ_SEL [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH - 1):`WB_ADDR_WIDTH]
`define READ_TAG_STIM [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_SEL_WIDTH)]
 
// read cycle return type consists of:
// - read data field
// - tag field received from WISHBONE
// - wishbone slave response fields - ACK, ERR and RTY
// - test bench error indicator (when testcase has not used wb master model properly)
// - how much data was actually transfered
`define READ_RETURN_TYPE [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):0]
`define READ_DATA [(32 + `WB_DATA_WIDTH + 4 - 1):32 + 4]
`define READ_TAG_RET [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):(`WB_DATA_WIDTH + 32 + 4)]
`define READ_RETURN_LENGTH (32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1)
 
// write cycle stimulus type consists of
// - address field
// - data field
// - sel field
// - tag field
`define WRITE_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
`define WRITE_ADDRESS [(`WB_ADDR_WIDTH - 1):0]
`define WRITE_DATA [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH - 1):`WB_ADDR_WIDTH]
`define WRITE_SEL [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH)]
`define WRITE_TAG_STIM [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH)]
 
// length of WRITE_STIMULUS
`define WRITE_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
 
// write cycle return type consists of:
// - test bench error indicator (when testcase has not used wb master model properly)
// - wishbone slave response fields - ACK, ERR and RTY
// - tag field received from WISHBONE
// - how much data was actually transfered
`define WRITE_RETURN_TYPE [(32 + 4 + `WB_TAG_WIDTH - 1):0]
`define WRITE_TAG_RET [(32 + 4 + `WB_TAG_WIDTH - 1):32 + 4]
 
// this four fields are common to both read and write routines return values
`define TB_ERROR_BIT [0]
`define CYC_ACK [1]
`define CYC_RTY [2]
`define CYC_ERR [3]
`define CYC_RESPONSE [3:1]
`define CYC_ACTUAL_TRANSFER [35:4]
 
// block transfer flags
`define WB_TRANSFER_FLAGS [41:0]
// consists of:
// - number of transfer cycles to perform
// - flag that enables retry termination handling - if disabled, block transfer routines will return on any termination other than acknowledge
// - flag indicating CAB transfer is to be performed - ignored by all single transfer routines
// - number of initial wait states to insert
// - number of subsequent wait states to insert
`define WB_TRANSFER_SIZE [41:10]
`define WB_TRANSFER_AUTO_RTY [8]
`define WB_TRANSFER_CAB [9]
`define INIT_WAITS [3:0]
`define SUBSEQ_WAITS [7:4]
 
// wb slave response
`define ACK_RESPONSE 3'b100
`define ERR_RESPONSE 3'b010
`define RTY_RESPONSE 3'b001
`define NO_RESPONSE 3'b000
/timescale.v
0,0 → 1,71
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v ////
//// ////
//// ////
//// This file is part of the SoC Debug Interface. ////
//// http://www.opencores.org/projects/DebugInterface/ ////
//// ////
//// Author(s): ////
//// Igor Mohor (igorm@opencores.org) ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: timescale.v,v $
// Revision 1.2 2010-01-08 01:41:08 Nathan
// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
//
// Revision 1.1 2008/07/08 19:11:56 Nathan
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
//
// Revision 1.1 2008/06/18 18:34:48 Nathan
// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.
//
// Revision 1.1.1.1 2008/05/14 12:07:36 Nathan
// Original from OpenCores
//
// Revision 1.4 2004/03/28 20:27:40 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.3 2004/01/17 17:01:25 mohor
// Almost finished.
//
// Revision 1.2 2003/12/23 14:26:01 mohor
// New version of the debug interface. Not finished, yet.
//
//
//
//
`timescale 1ns/10ps
 

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