OpenCores
URL https://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk

Subversion Repositories adv_debug_sys

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /adv_debug_sys/tags/ADS_RELEASE_2_5_0/Hardware/adv_dbg_if/bench
    from Rev 42 to Rev 48
    ↔ Reverse comparison
  •

Rev 42 → Rev 48

/jtag_serial_port/wave.do
0,0 → 1,377
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tck_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdi_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/rst_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/shift_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/pause_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/update_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/capture_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/debug_select_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_clk_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_rst_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_adr_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_dat_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_dat_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_cyc_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_stb_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_sel_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_we_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_ack_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_cab_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_err_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_cti_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_bte_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_jsp_adr_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_jsp_dat_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_jsp_dat_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_jsp_cyc_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_jsp_stb_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_jsp_sel_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_jsp_we_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_jsp_ack_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_jsp_cab_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_jsp_err_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_jsp_cti_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_jsp_bte_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/int_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_wb
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_cpu0
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_cpu1
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_jsp
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/input_shift_reg
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/module_id_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/select_cmd
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/module_id_in
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/module_selects
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/select_inhibit
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/module_inhibit
add wave -noupdate -divider {JSP Module}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/tck_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/module_tdo_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/tdi_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/capture_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/shift_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/update_dr_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/data_register_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/module_select_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/top_inhibit_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/rst_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_clk_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_rst_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_adr_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_dat_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_dat_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_cyc_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_stb_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_sel_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_we_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_ack_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_cab_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_err_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_cti_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_bte_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/int_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/read_bit_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/write_bit_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/input_word_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/output_word_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/user_word_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/data_out_shift_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/rd_bit_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/rd_bit_ct_rst
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wr_bit_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wr_bit_ct_rst
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/in_word_ct_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/out_word_ct_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/in_word_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/out_word_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/user_word_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/user_word_ct_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/out_reg_ld_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/out_reg_shift_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/out_reg_data_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/biu_rd_strobe
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/biu_wr_strobe
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/in_word_count_zero
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/out_word_count_zero
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/user_word_count_zero
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/rd_bit_count_max
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wr_bit_count_max
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/data_to_in_word_counter
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/data_to_out_word_counter
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/data_to_user_word_counter
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/decremented_in_word_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/decremented_out_word_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/decremented_user_word_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/count_data_in
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/data_to_biu
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/data_from_biu
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/biu_space_available
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/biu_bytes_available
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/count_data_from_biu
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/out_reg_data
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/rd_module_state
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/rd_module_next_state
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/wr_module_state
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/wr_module_next_state
add wave -noupdate -divider {JSP BIU}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/tck_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rst_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/data_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/data_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/bytes_free_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/bytes_available_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_strobe_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_strobe_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_clk_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_rst_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_adr_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_dat_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_dat_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_cyc_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_stb_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_sel_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_we_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_ack_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_err_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/int_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/data_in
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rdata
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wen_tff
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/ren_tff
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_fifo_ack
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_bytes_free
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_bytes_avail
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_bytes_avail
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_bytes_avail_not_zero
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/ren_sff_out
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo_data_out
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/data_to_wb
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/data_from_wb
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo_not_empty
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wda_rst
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wpp
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/w_fifo_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/ren_rst
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rdata_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rpp
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/r_fifo_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/r_wb_ack
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/w_wb_ack
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wdata_avail
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_rd
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_wr
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/pop
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rcz
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fsm_state
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/next_rd_fsm_state
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fsm_state
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/next_wr_fsm_state
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/bus_data_lo
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/bus_data_hi
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_reg_ack
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo_not_full
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_dlab_bit
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_ier
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_iir
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/thr_int_arm
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_lsr
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_dlab_bit_wren
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_ier_wren
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_iir_rden
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_lcr
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_fcr_wren
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rcvr_fifo_rst
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/xmit_fifo_rst
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_mcr
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_msr
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_scr
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/iir_gen
add wave -noupdate -divider {WR FIFO}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/CLK
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/RST
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/DATA_IN
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/DATA_OUT
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/PUSH_POPn
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/EN
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/BYTES_AVAIL
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/BYTES_FREE
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/reg0
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/reg1
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/reg2
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/reg3
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/reg4
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/reg5
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/reg6
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/reg7
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/counter
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/push_ok
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/pop_ok
add wave -noupdate -divider {RD FIFO}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/CLK
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/RST
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/DATA_IN
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/DATA_OUT
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/PUSH_POPn
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/EN
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/BYTES_AVAIL
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/BYTES_FREE
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/reg0
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/reg1
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/reg2
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/reg3
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/reg4
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/reg5
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/reg6
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/reg7
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/counter
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/push_ok
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/pop_ok
add wave -noupdate -divider {WB Module}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/tck_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/module_tdo_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/tdi_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/capture_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/shift_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/update_dr_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_register_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/module_select_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/top_inhibit_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/rst_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_clk_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_adr_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_dat_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_dat_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_cyc_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_stb_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_sel_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_we_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_ack_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_cab_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_err_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_cti_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_bte_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/address_counter
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_count
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/word_count
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/operation
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_out_shift_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/internal_register_select
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/internal_reg_error
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/addr_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/addr_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/op_reg_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_ct_rst
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/word_ct_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/word_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/out_reg_ld_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/out_reg_shift_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/out_reg_data_sel
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/tdo_output_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_strobe
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_clr
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_in_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_shift_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/regsel_ld_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/intreg_ld_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/error_reg_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_clr_err
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/word_count_zero
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_count_max
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/module_cmd
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_ready
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_err
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/burst_instruction
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/intreg_instruction
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/intreg_write
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/rd_op
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_match
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_count_32
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/word_size_bits
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/word_size_bytes
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/incremented_address
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_to_addr_counter
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_to_word_counter
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/decremented_word_count
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/address_data_in
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/count_data_in
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/operation_in
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_to_biu
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_from_biu
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_data_out
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_data_in
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_serial_out
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/reg_select_data
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/out_reg_data
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_from_internal_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_rst
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/module_state
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/module_next_state
add wave -noupdate -divider {WB BIU}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/tck_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rst_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/data_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/data_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/addr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/strobe_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rd_wrn_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/err_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/word_size_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_clk_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_adr_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_dat_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_dat_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_cyc_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_stb_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_sel_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_we_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_ack_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_cab_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_err_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_cti_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_bte_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/sel_reg
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/addr_reg
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/data_in_reg
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/data_out_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wr_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/str_sync
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_sync
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/err_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_sync_tff1
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_sync_tff2
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_sync_tff2q
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/str_sync_wbff1
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/str_sync_wbff2
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/str_sync_wbff2q
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/data_o_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_sync_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/err_en
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/be_dec
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/start_toggle
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/swapped_data_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/swapped_data_out
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_fsm_state
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/next_fsm_state
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {553794 ns} 0}
configure wave -namecolwidth 466
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {391982 ns} {400422 ns}
/jtag_serial_port/adv_dbg_jsp_tb.v
0,0 → 1,1461
//////////////////////////////////////////////////////////////////////
//// ////
//// adv_dbg_tb.v ////
//// ////
//// ////
//// Testbench for the SoC Advanced Debug Interface. ////
//// This testbench specifically tests the JTAG serial port ////
//// ////
//// Author(s): ////
//// Nathan Yawn (nathan.yawn@opencored.org) ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
 
`include "tap_defines.v"
`include "adbg_defines.v"
`include "adbg_wb_defines.v"
 
// Polynomial for the CRC calculation
// Yes, it's backwards. Yes, this is on purpose.
// To decrease logic + routing, we want to shift the CRC calculation
// in the same direction we use to shift the data out, LSB first.
`define DBG_CRC_POLY 32'hedb88320
 
// These are indicies into an array which hold values for the JTAG outputs
`define JTAG_TMS 0
`define JTAG_TCK 1
`define JTAG_TDO 2
 
`define JTAG_TMS_bit 3'h1
`define JTAG_TCK_bit 3'h2
`define JTAG_TDO_bit 3'h4
 
`define wait_jtag_period #50
 
 
module adv_debug_tb;
 
// Connections to the JTAG TAP
reg jtag_tck_o;
reg jtag_tms_o;
reg jtag_tdo_o;
wire jtag_tdi_i;
 
// Connections between TAP and debug module
wire capture_dr;
wire shift_dr;
wire pause_dr;
wire update_dr;
wire dbg_rst;
wire dbg_tdi;
wire dbg_tdo;
wire dbg_sel;
 
// Connections between the debug module and the wishbone
`ifdef DBG_WISHBONE_SUPPORTED
wire [31:0] wb_adr;
wire [31:0] wb_dat_m;
wire [31:0] wb_dat_s;
wire wb_cyc;
wire wb_stb;
wire [3:0] wb_sel;
wire wb_we;
wire wb_ack;
wire wb_err;
reg wb_clk_i; // the wishbone clock
reg wb_rst_i;
`endif
 
`ifdef DBG_CPU0_SUPPORTED
wire cpu0_clk;
wire [31:0]cpu0_addr;
wire [31:0] cpu0_data_c;
wire [31:0] cpu0_data_d;
wire cpu0_bp;
wire cpu0_stall;
wire cpu0_stb;
wire cpu0_we;
wire cpu0_ack;
wire cpu0_rst;
`endif
 
wire jsp_int;
reg test_enabled;
 
// Data which will be written to the WB interface
reg [31:0] static_data32 [0:15];
reg [15:0] static_data16 [0:15];
reg [7:0] static_data8 [0:15];
 
// Arrays to hold data read back from the WB interface, for comparison
reg [31:0] input_data32 [0:15];
reg [15:0] input_data16 [0:15];
reg [7:0] input_data8 [0:15];
 
reg [32:0] err_data; // holds the contents of the error register from the various modules
 
reg failed;
integer i;
 
reg [63:0] jsp_data8;
initial
begin
jtag_tck_o = 1'b0;
jtag_tms_o = 1'b0;
jtag_tdo_o = 1'b0;
end
 
// Provide the wishbone clock
`ifdef DBG_WISHBONE_SUPPORTED
initial
begin
wb_clk_i = 1'b0;
forever #7 wb_clk_i = ~wb_clk_i; // Odd frequency ratio to test the synchronization
end
`endif
 
 
 
// Start the test (and reset the wishbone)
initial
begin
test_enabled = 1'b0;
wb_rst_i = 1'b0;
#100;
wb_rst_i = 1'b1;
#100;
wb_rst_i = 1'b0;
 
// Init the memory
initialize_memory(32'h0,32'h16);
 
#1 test_enabled<=#1 1'b1;
end
 
// This is the main test procedure
always @ (posedge test_enabled)
begin
 
$display("Starting advanced debug JTAG serial port test");
reset_jtag;
#1000;
check_idcode;
#1000;
// Select the debug module in the IR
set_ir(`DEBUG);
#1000;
 
///////////////////////////////////////////////////////////////////
// Test the JTAG serial port. We use the debug unit WB interface
// to act as the CPU/WB master.
////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////
// Do an 8 byte transfer, JSP->WB
$display("-------------------------------------------");
$display("--- Test 1: 8 bytes JSP->WB");
// Write 8 bytes from JTAG to WB
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
#200
$display("JTAG putting 8 bytes to JSP module at time %t", $time);
do_jsp_read_write(4'h8,jsp_data8); // 4 bits words to write, 64 bits output data
// data returned in input_data8[]
// Select the WB unit in the debug module, read the data written
#1000;
$display("Selecting Wishbone module at time %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
failed <= 1'b0;
for(i = 0; i < 8; i=i+1) begin
do_module_burst_read(3'h1, 16'd1, 32'h0);
//$display("WB read got 0x%x", input_data8[0]);
if(input_data8[0] != i) begin
failed = 1;
$display("JSP-to-WB data mismatch at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
//$display("JTAG read got 0x%x", input_data8[i]);
end
 
end
if(!failed) $display("WB-to-JSP data: 8 bytes OK! Test 1 passed!");
 
/////////////////////////////////////////////////////
// Do an 8-byte transfer, WB->JSP
$display("-------------------------------------------");
$display("--- Test 2: 8 bytes WB->JSP");
// Put 8 bytes from the WB into the JSP
#1000
$display("WB putting 8 bytes to JSP module at time %t", $time);
for(i = 0; i < 8; i=i+1) begin
static_data8[0] = i;
do_module_burst_write(3'h1, 16'd1, 32'h0);
end
 
// Get 8 bytes from the JSP
#1000
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
#1000
$display("JTAG getting 8 bytes from JSP module at time %t", $time);
do_jsp_read_write(4'h0,jsp_data8); // 4 bits words to write, 64 bits output data
// data returned in input_data8[]
 
failed <= 1'b0;
for(i = 0; i < 8; i=i+1) begin
if(i != input_data8[i]) begin
failed = 1;
$display("WB-to-JSP data mismatch at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
//$display("JTAG read got 0x%x", input_data8[i]);
end
end
if(!failed) $display("WB-to-JSP data: 8 bytes OK! Test 2 passed!");
//////////////////////////////////////
// Write 4 bytes, then 4 more, JSP->WB (read all back at once)
$display("-------------------------------------------");
$display("--- Test 3: 4+4 bytes, JSP->WB");
// Write 4 bytes from JTAG
#1000
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
#200
$display("JTAG putting 4 bytes to JSP module at time %t", $time);
do_jsp_read_write(4'h4,jsp_data8); // 4 bits words to write, 64 bits output data
do_jsp_read_write(4'h4,jsp_data8); // 4 bits words to write, 64 bits output data
// data returned in input_data8[]
// Select the WB unit in the debug module, read the data written
#1000;
$display("Selecting Wishbone module at time %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
failed <= 1'b0;
for(i = 0; i < 4; i=i+1) begin
do_module_burst_read(3'h1, 16'd1, 32'h0);
if(input_data8[0] != i) begin
failed = 1;
$display("JSP-to-WB 4+4 data mismatch at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
end
end
for(i = 0; i < 4; i=i+1) begin
do_module_burst_read(3'h1, 16'd1, 32'h0);
if(input_data8[0] != i) begin
failed = 1;
$display("JSP-to-WB 4+4 data mismatch at index %d, wrote 0x%x, read 0x%x", i+4, i, input_data8[i]);
end
end
if(!failed) $display("WB-to-JSP 4+4 data: 8 bytes OK! Test 3 passed!");
////////////////////////////////////////
// Read 8 from JTAG, put 4 to WB
$display("-------------------------------------------");
$display("--- Test 4: 8 bytes WB->JSP, 4 bytes JSP->WB");
// Put 8 bytes from the WB into the JSP
#1000
$display("Selecting Wishbone module at time %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
$display("WB putting 8 bytes to JSP module for R8W4 read at time %t", $time);
for(i = 0; i < 8; i=i+1) begin
static_data8[0] = i;
do_module_burst_write(3'h1, 16'd1, 32'h0);
end
 
// Get 8 bytes from the JSP, put 4 to WB
#1000
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
#1000
$display("JTAG getting 8 and putting 4 at time %t", $time);
do_jsp_read_write(4'h4,jsp_data8); // 4 bits words to write, 64 bits output data
// data returned in input_data8[]
 
failed <= 1'b0;
for(i = 0; i < 8; i=i+1) begin
if(i != input_data8[i]) begin
failed = 1;
$display("R8W4 data mismatch getting JSP data at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
end
end
if(!failed) $display("R8W4: 8 JSP bytes OK!");
// Remove the 4 bytes via the WB
#1000;
$display("Selecting Wishbone module at time %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
failed <= 1'b0;
for(i = 0; i < 4; i=i+1) begin
do_module_burst_read(3'h1, 16'd1, 32'h0);
if(input_data8[0] != i) begin
failed = 1;
$display("R8W4 data mismatch clearing WB data at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
end
end
if(!failed) $display("R8W4: 4 WB bytes OK!");
///////////////////////////////////////////////////
// Test putting more data than space available
$display("-------------------------------------------");
$display("--- Test 5: Put 6 JSP->WB, then 6 more");
// put 6 to WB
#1000
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
#1000
$display("JTAG putting 6 at time %t", $time);
do_jsp_read_write(4'h6,jsp_data8); // 4 bits words to write, 64 bits output data
// put 6 more
#1000
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
#1000
$display("JTAG putting 6 at time %t", $time);
do_jsp_read_write(4'h6,jsp_data8); // 4 bits words to write, 64 bits output data
// Get the data back from the WB
#1000;
$display("Selecting Wishbone module at time %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
failed <= 1'b0;
for(i = 0; i < 6; i=i+1) begin
do_module_burst_read(3'h1, 16'd1, 32'h0);
if(input_data8[0] != i) begin
failed = 1;
$display("W6W6 data mismatch reading WB data at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
end
end
for(i = 0; i < 2; i=i+1) begin
do_module_burst_read(3'h1, 16'd1, 32'h0);
if(input_data8[0] != i) begin
failed = 1;
$display("W6W6 data mismatch reading WB data at index %d, wrote 0x%x, read 0x%x", i+6, i, input_data8[i]);
end
end
if(!failed) $display("W6W6: 8 WB bytes OK!");
 
//////////////////////////////////////////
// Verify behavior of WB UART 16450-style registers
// Check LSR with both FIFOs empty
$display("-------------------------------------------");
$display("--- Test 6a: Check LSR with both FIFOs empty");
$display("Selecting Wishbone module at time %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
do_module_burst_read(3'h1, 16'd1, 32'h5);
if(input_data8[0] != 8'h60) begin
$display("LSR mismatch with both FIFOs empty, read 0x%x, expected 0x60", input_data8[0]);
end
else $display("LSR with both FIFOs empty OK!");
 
$display("-------------------------------------------");
$display("--- Test 6b: Check LSR with WB read data available");
#1000
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
$display("JTAG putting 1 at time %t", $time);
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
$display("Selecting Wishbone module at time %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
do_module_burst_read(3'h1, 16'd1, 32'h5);
if(input_data8[0] != 8'h61) begin
$display("LSR mismatch with WB read data available, read 0x%x, expected 0x61", input_data8[0]);
end
else $display("LSR with WB read data available OK!");
$display("-------------------------------------------");
$display("--- Test 6c: Check LSR with WB read data available and write FIFO not empty / full");
#1000
$display("Selecting Wishbone module at time %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
$display("WB putting 1 bytes to JSP module for LSR test at time %t", $time);
do_module_burst_write(3'h1, 16'd1, 32'h0);
do_module_burst_read(3'h1, 16'd1, 32'h5);
if(input_data8[0] != 8'h61) begin
$display("LSR mismatch with WB read data available and write FIFO not empty, read 0x%x, expected 0x61", input_data8[0]);
end
else $display("LSR with WB read data available and write FIFO not empty OK!");
// Fill the write FIFO
for(i = 0; i < 7; i = i + 1) begin
do_module_burst_write(3'h1, 16'd1, 32'h0);
end
do_module_burst_read(3'h1, 16'd1, 32'h5);
if(input_data8[0] != 8'h01) begin
$display("LSR mismatch with WB read data available and write FIFO full, read 0x%x, expected 0x01", input_data8[0]);
end
else $display("LSR with WB read data available and write FIFO full OK!");
$display("-------------------------------------------");
$display("--- Test 6d: Check LSR with write FIFO full");
do_module_burst_read(3'h1, 16'd1, 32'h0); // get/clear the read data
do_module_burst_read(3'h1, 16'd1, 32'h5);
if(input_data8[0] != 8'h00) begin
$display("LSR mismatch with WB write FIFO full, read 0x%x, expected 0x00", input_data8[0]);
end
else $display("LSR with WB write FIFO full OK!");
//////////////////////////////////////
// Test DLAB bit
// Now that we've tested the LSR, we can use it to verity the FIFO states
 
$display("-------------------------------------------");
$display("--- Test 7: test DLAB bit");
#1000
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
$display("JTAG putting 1 (and getting 8) at time %t", $time);
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
// Set the DLAB bit. This should prevent reads/writes to the FIFOs from the WB
#1000
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
#1000
$display("Setting DLAB bit it time %t", $time);
static_data8[0] = 8'h80;
do_module_burst_write(3'h1, 16'd1, 32'h00000003);
// Read from 0. This should not get the available byte.
do_module_burst_read(3'h1, 16'd1, 32'h0);
// Try to write the FIFO full. This should not put any bytes to the transmit FIFO
for(i = 0; i < 8; i = i + 1) begin
do_module_burst_write(3'h1, 16'd1, 32'h0);
end
// Check FIFO status in the LSR
$display("Checking LSR");
do_module_burst_read(3'h1, 16'd1, 32'h5);
if(input_data8[0] != 8'h61) begin
$display("LSR mismatch in DLAB inhibit test, read 0x%x, expected 0x61", input_data8[0]);
end
else $display("DLAB inhibit test OK!");
// Now clear the DLAB, and try again.
$display("Clearing DLAB at time %t", $time);
static_data8[0] = 8'h00;
do_module_burst_write(3'h1, 16'd1, 32'h3);
do_module_burst_read(3'h1, 16'd1, 32'h0); // Should empty the read FIFO
for(i = 0; i < 8; i = i + 1) begin
do_module_burst_write(3'h1, 16'd1, 32'h0); // Should un-empty the read FIFO
end
// Check FIFO status in the LSR
do_module_burst_read(3'h1, 16'd1, 32'h5);
if(input_data8[0] != 8'h00) begin
$display("LSR mismatch in DLAB test 2, read 0x%x, expected 0x00", input_data8[0]);
end
else $display("DLAB un-inhibit test OK!");
// Note WB write FIFO is full at this point
///////////////////////////////////////////////////
// Test interrupt functionality.
$display("-------------------------------------------");
$display("--- Test 8a: IER write");
// Write IER to 0
static_data8[0] = 8'h00;
do_module_burst_write(3'h1, 16'd1, 32'h1);
// Make sure it's 0
do_module_burst_read(3'h1, 16'd1, 32'h1);
if(input_data8[0] != 8'h00) begin
$display("Failed to set IER to 0x00, read 0x%x", input_data8[0]);
end
else $display("Set IER to 0: pass");
// Make sure int_o is not set
if(jsp_int) begin
$display("JSP Interrupt set when no interrupts enabled: FAIL");
end
else $display("JSP interrupt not set, interrupts disabled: OK");
// Write IER to 0x0F
static_data8[0] = 8'h0F;
do_module_burst_write(3'h1, 16'd1, 32'h1);
// Make sure it's 0x0F
do_module_burst_read(3'h1, 16'd1, 32'h1);
if(input_data8[0] != 8'h0F) begin
$display("Failed to set IER to 0x0F, read 0x%x", input_data8[0]);
end
else $display("Set IER to 0x0F: pass");
 
// Write IER to 0x03
static_data8[0] = 8'h03;
do_module_burst_write(3'h1, 16'd1, 32'h1);
// Make sure it's 0x03
do_module_burst_read(3'h1, 16'd1, 32'h1);
if(input_data8[0] != 8'h03) begin
$display("Failed to set IER to 0x03, read 0x%x", input_data8[0]);
end
else $display("Set IER to 0x03: pass");
 
////////////////////////////////////
// Test the int_o output
 
$display("-------------------------------------------");
$display("--- Test 8b: int_o output");
// Make sure int_o is (still) not set WB RD FIFO empty, WB WR FIFO is full
if(jsp_int) begin
$display("JSP Interrupt set when no int condition: FAIL");
end
else $display("JSP interrupt not set, no INT condition: OK");
// Check IIR for 'no active interrupt'
do_module_burst_read(3'h1, 16'd1, 32'h2);
if(input_data8[0] != 8'h01) begin
$display("Wrong value for IIR with no active interrupt, read 0x%x, expected 0x01", input_data8[0]);
end
else $display("IIR is 0x01 with no active interrupt: pass");
// Read a byte from the JSP, should trigger the 'THR empty' interrupt
#1000
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
$display("JTAG getting 8 at time %t", $time);
do_jsp_read_write(4'h0,jsp_data8); // 4 bits words to write, 64 bits output data
 
 
// Make sure int_o is (still) not set WB RD FIFO empty, WB WR FIFO is full
if(!jsp_int) begin
$display("JSP Interrupt not set when THR empty: FAIL");
end
else $display("JSP interrupt set for THR empty: OK");
#1000
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
// Check IIR for THR empty
do_module_burst_read(3'h1, 16'd1, 32'h2);
if(input_data8[0] != 8'h02) begin
$display("Wrong value for IIR with no active interrupt, read 0x%x, expected 0x02", input_data8[0]);
end
else $display("IIR is 0x02 with THR empty: pass");
// IIR read should have cleared int_o and changed IIR to 'no active interrupt'
if(jsp_int) begin
$display("JSP Interrupt set after IIR read: FAIL");
end
else $display("JSP interrupt not set after clearing THR INT with IIR read: OK");
// Check IIR for 'no active interrupt'
do_module_burst_read(3'h1, 16'd1, 32'h2);
if(input_data8[0] != 8'h01) begin
$display("Wrong value for IIR after clearing THR INT with IIR read, read 0x%x, expected 0x01", input_data8[0]);
end
else $display("IIR is 0x01 after clearing THR INT with IIR read: pass");
// Write a byte from the WB, should trigger int_o
static_data8[0] = 8'h00;
do_module_burst_write(3'h1, 16'd1, 32'h0);
// check int_o, should be set
if(!jsp_int) begin
$display("JSP Interrupt not set when THR not full: FAIL");
end
else $display("JSP interrupt set for THR not full: OK");
// Write a byte from the JSP, should take precedence in IIR
#1000
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
$display("JTAG putting 1 at time %t", $time);
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
// check int_o, should be set
if(!jsp_int) begin
$display("JSP Interrupt not set when read data available: FAIL");
end
else $display("JSP interrupt set for read data available: OK");
// Check IIR, should show read data available
#1000
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
do_module_burst_read(3'h1, 16'd1, 32'h2);
if(input_data8[0] != 8'h4) begin
$display("Wrong value for IIR after clearing THR INT with IIR read, read 0x%x, expected 0x04", input_data8[0]);
end
else $display("IIR is 0x04 after putting a JSP byte: pass");
// Read the byte from the WB.
do_module_burst_read(3'h1, 16'd1, 32'h0);
// check int_o, should be set
if(!jsp_int) begin
$display("JSP Interrupt not set when THR not full: FAIL");
end
else $display("JSP interrupt set for THR not full: OK");
// Check IIR, should show THRE
#1000
do_module_burst_read(3'h1, 16'd1, 32'h2);
if(input_data8[0] != 8'h02) begin
$display("Wrong value for IIR after clearing RDA INT with WB read (THRE), read 0x%x, expected 0x02", input_data8[0]);
end
else $display("IIR is 0x02 after reading data with THRE: pass");
// check int_o, should be cleared
if(jsp_int) begin
$display("JSP Interrupt set after clearing THRE with IIR read: FAIL");
end
else $display("JSP interrupt not set, THRE cleared with IIR read: OK");
// Check IIR, should no no interrupt
#1000
do_module_burst_read(3'h1, 16'd1, 32'h2);
if(input_data8[0] != 8'h01) begin
$display("Wrong value for IIR after clearing THR INT with IIR read, read 0x%x, expected 0x01", input_data8[0]);
end
else $display("IIR is 0x01 after reading data with THRE: pass");
// Put a byte from the JSP
#1000
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
$display("JTAG putting 1 at time %t", $time);
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
// check int_o, should be set
if(!jsp_int) begin
$display("JSP Interrupt not set when read data available: FAIL");
end
else $display("JSP interrupt set for read data available: OK");
// check IIR, should show receive data available
#1000
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
do_module_burst_read(3'h1, 16'd1, 32'h2);
if(input_data8[0] != 8'h4) begin
$display("Wrong value for IIR with RDA, read 0x%x, expected 0x04", input_data8[0]);
end
else $display("IIR is 0x04 after putting a JSP byte: pass");
// Read the byte over WB
do_module_burst_read(3'h1, 16'd1, 32'h0);
// check int_o, should be cleared
if(jsp_int) begin
$display("JSP Interrupt set when no int condition: FAIL");
end
else $display("JSP interrupt not set, no INT condition: OK");
// check IIR, should show no active interrupt
#1000
do_module_burst_read(3'h1, 16'd1, 32'h2);
if(input_data8[0] != 8'h1) begin
$display("Wrong value for IIR with no active int, read 0x%x, expected 0x01", input_data8[0]);
end
else $display("IIR is 0x01 with no active interrupts: pass");
////////////////////////////////////
// Test the software resets
 
$display("-------------------------------------------");
$display("--- Test 9: Software WB/UART FIFO reset");
// First, test reset only JSP->WB FIFO
// Put a byte from the JSP
#1000
//$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
//$display("JTAG putting 1 at time %t", $time);
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
// Put a byte from the WB
#1000
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
#500
static_data8[0] = 8'h00;
do_module_burst_write(3'h1, 16'd1, 32'h0);
// Reset the JSP->WB FIFO
#500
static_data8[0] = 8'h02;
do_module_burst_write(3'h1, 16'd1, 32'h2);
 
// To test, need to read the output from the transact function:
// Should be 1 byte available, 8 bytes free
#1000
//$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
$display("Next line should show 1 byte available, 8 bytes free:");
do_jsp_read_write(4'h0,jsp_data8); // 4 bits words to write, 64 bits output data
// Second, test reset only WB->JSP FIFO
// Put a byte from the JSP
#1000
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
// Put a byte from the WB
#1000
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
#500
static_data8[0] = 8'h00;
do_module_burst_write(3'h1, 16'd1, 32'h0);
// Reset the WB->JSP FIFO
#500
static_data8[0] = 8'h04;
do_module_burst_write(3'h1, 16'd1, 32'h2);
 
// To test, need to read the output from the transact function:
// Should be 0 byte available, 7 bytes free
#1000
//$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
$display("Next line should show 0 byte available, 7 bytes free:");
do_jsp_read_write(4'h0,jsp_data8); // 4 bits words to write, 64 bits output data
// Finally, test reset both directions
// Put a byte from the JSP
#1000
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
// Put a byte from the WB
#1000
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
#500
static_data8[0] = 8'h00;
do_module_burst_write(3'h1, 16'd1, 32'h0);
// Reset both FIFO
#500
static_data8[0] = 8'h06;
do_module_burst_write(3'h1, 16'd1, 32'h2);
 
// To test, need to read the output from the transact function:
// Should be 0 byte available, 8 bytes free
#1000
//$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
$display("Next line should show 0 byte available, 8 bytes free:");
do_jsp_read_write(4'h0,jsp_data8); // 4 bits words to write, 64 bits output data
//////////////////////////////
// End of tests
$display("----------------------------------");
$display("--- ALL TESTS COMPLETE ---");
end
 
task initialize_memory;
input [31:0] start_addr;
input [31:0] length;
integer i;
reg [31:0] addr;
begin
 
jsp_data8 <= 64'h0706050403020100;
 
for (i=0; i<length; i=i+1)
begin
static_data32[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
static_data16[i] <= {i[7:0], i[7:0]+ 2'd1};
static_data8[i] <= i[7:0];
end
end
endtask
 
///////////////////////////////////////////////////////////////////////////////
// Declaration and interconnection of components
 
// Top module
tap_top i_tap (
// JTAG pads
.tms_pad_i(jtag_tms_o),
.tck_pad_i(jtag_tck_o),
.trstn_pad_i(1'b1),
.tdi_pad_i(jtag_tdo_o),
.tdo_pad_o(jtag_tdi_i),
.tdo_padoe_o(),
 
// TAP states
.test_logic_reset_o(dbg_rst),
.run_test_idle_o(),
.shift_dr_o(shift_dr),
.pause_dr_o(pause_dr),
.update_dr_o(update_dr),
.capture_dr_o(capture_dr),
// Select signals for boundary scan or mbist
.extest_select_o(),
.sample_preload_select_o(),
.mbist_select_o(),
.debug_select_o(dbg_sel),
// TDO signal that is connected to TDI of sub-modules.
.tdi_o(dbg_tdo),
// TDI signals from sub-modules
.debug_tdo_i(dbg_tdi), // from debug module
.bs_chain_tdo_i(1'b0), // from Boundary Scan Chain
.mbist_tdo_i(1'b0) // from Mbist Chain
);
 
 
// Top module
adbg_top i_dbg_module(
// JTAG signals
.tck_i(jtag_tck_o),
.tdi_i(dbg_tdo),
.tdo_o(dbg_tdi),
.rst_i(dbg_rst),
 
// TAP states
.shift_dr_i(shift_dr),
.pause_dr_i(pause_dr),
.update_dr_i(update_dr),
.capture_dr_i(capture_dr),
 
// Instructions
.debug_select_i(dbg_sel)
 
 
`ifdef DBG_WISHBONE_SUPPORTED
// WISHBONE common signals
,
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
// WISHBONE master interface
.wb_adr_o(wb_adr),
.wb_dat_o(wb_dat_m),
.wb_dat_i(wb_dat_s),
.wb_cyc_o(wb_cyc),
.wb_stb_o(wb_stb),
.wb_sel_o(wb_sel),
.wb_we_o(wb_we),
.wb_ack_i(wb_ack),
.wb_cab_o(),
.wb_err_i(wb_err),
.wb_cti_o(),
.wb_bte_o()
`endif
 
`ifdef DBG_JSP_SUPPORTED
// WISHBONE slave, including interrupt output
,
.wb_jsp_adr_i(wb_adr),
.wb_jsp_dat_o(wb_dat_s),
.wb_jsp_dat_i(wb_dat_m),
.wb_jsp_cyc_i(wb_cyc),
.wb_jsp_stb_i(wb_stb),
.wb_jsp_sel_i(wb_sel),
.wb_jsp_we_i(wb_we),
.wb_jsp_ack_o(wb_ack),
.wb_jsp_cab_i(),
.wb_jsp_err_o(wb_err),
.wb_jsp_cti_i(),
.wb_jsp_bte_i(),
.int_o(jsp_int)
`endif
 
);
 
 
///////////////////////////////////////////////////////////////////////////
// Higher-level chain manipulation functions
 
// calculate the CRC, up to 32 bits at a time
task compute_crc;
input [31:0] crc_in;
input [31:0] data_in;
input [5:0] length_bits;
output [31:0] crc_out;
integer i;
reg [31:0] d;
reg [31:0] c;
begin
crc_out = crc_in;
for(i = 0; i < length_bits; i = i+1) begin
d = (data_in[i]) ? 32'hffffffff : 32'h0;
c = (crc_out[0]) ? 32'hffffffff : 32'h0;
//crc_out = {crc_out[30:0], 1'b0}; // original
crc_out = crc_out >> 1;
crc_out = crc_out ^ ((d ^ c) & `DBG_CRC_POLY);
//$display("CRC Itr %d, inbit = %d, crc = 0x%x", i, data_in[i], crc_out);
end
end
endtask
 
task check_idcode;
reg [63:0] readdata;
reg[31:0] idcode;
begin
set_ir(`IDCODE);
// Read the IDCODE in the DR
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_read_write_stream(64'h0, 8'd32, 1, readdata); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
idcode = readdata[31:0];
$display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);
end
endtask;
 
task select_debug_module;
input [1:0] moduleid;
reg validid;
begin
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream({1'b1,moduleid}, 8'h3, 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
$display("Selecting module (%0x)", moduleid);
end
endtask
 
 
task send_module_burst_command;
input [3:0] opcode;
input [31:0] address;
input [15:0] burstlength;
reg [63:0] streamdata;
begin
streamdata = {11'h0,1'b0,opcode,address,burstlength};
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream(streamdata, 8'd53, 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
end
endtask
 
task select_module_internal_register; // Really just a read, with discarded data
input [31:0] regidx;
input [7:0] len; // the length of the register index data, we assume not more than 32
reg[63:0] streamdata;
begin
streamdata = 64'h0;
streamdata = streamdata | regidx;
streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream(streamdata, (len+5), 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
end
endtask
 
task read_module_internal_register; // We assume the register is already selected
//input [31:0] regidx;
input [7:0] len; // the length of the data desired, we assume a max of 64 bits
output [63:0] instream;
reg [63:0] bitmask;
begin
instream = 64'h0;
// We shift out all 0's, which is a NOP to the debug unit
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
// Shift at least 5 bits, as this is the min, for a valid NOP
jtag_read_write_stream(64'h0, len+4,1,instream); // exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
bitmask = 64'hffffffffffffffff;
bitmask = bitmask << len;
bitmask = ~bitmask;
instream = instream & bitmask; // Cut off any unwanted excess bits
end
endtask
 
task write_module_internal_register;
input [31:0] regidx; // the length of the register index data
input [7:0] idxlen;
input [63:0] writedata;
input [7:0] datalen; // the length of the data to write. We assume the two length combined are 59 or less.
reg[63:0] streamdata;
begin
streamdata = 64'h0; // This will 0 the toplevel/module select bit
streamdata = streamdata | writedata;
streamdata = streamdata | (regidx << datalen);
streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream(streamdata, (idxlen+datalen+5), 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
end
endtask
 
// This includes the sending of the burst command
task do_module_burst_read;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] instream;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o; // temp signal...
reg [31:0] crc_read;
reg [5:0] word_size_bits;
begin
//$display("Doing burst read, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
instream = 64'h0;
word_size_bits = word_size_bytes << 3;
crc_calc_i = 32'hffffffff;
// Send the command
case (word_size_bytes)
3'h1: opcode = `DBG_WB_CMD_BREAD8;
3'h2: opcode = `DBG_WB_CMD_BREAD16;
3'h4: opcode = `DBG_WB_CMD_BREAD32;
default:
begin
$display("Tried burst read with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
opcode = `DBG_WB_CMD_BREAD32;
end
endcase
send_module_burst_command(opcode,start_address, word_count); // returns to state idle
// Get us back to shift_dr mode to read a burst
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
 
`ifdef ADBG_USE_HISPEED
// Get 1 status bit, then word_size_bytes*8 bits
status = 1'b0;
j = 0;
while(!status) begin
read_write_bit(3'h0, status);
j = j + 1;
end
//if(j > 1) begin
// $display("Took %0d tries before good status bit during burst read", j);
//end
`endif
// Now, repeat...
for(i = 0; i < word_count; i=i+1) begin
`ifndef ADBG_USE_HISPEED
// Get 1 status bit, then word_size_bytes*8 bits
status = 1'b0;
j = 0;
while(!status) begin
read_write_bit(3'h0, status);
j = j + 1;
end
//if(j > 1) begin
// $display("Took %0d tries before good status bit during burst read", j);
//end
`endif
jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream);
//$display("Read 0x%0x", instream[31:0]);
compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o);
crc_calc_i = crc_calc_o;
if(word_size_bytes == 1) input_data8[i] = instream[7:0];
else if(word_size_bytes == 2) input_data16[i] = instream[15:0];
else input_data32[i] = instream[31:0];
end
// Read the data CRC from the debug module.
jtag_read_write_stream(64'h0, 6'd32, 1, crc_read);
if(crc_calc_o != crc_read) $display("CRC ERROR! Computed 0x%x, read CRC 0x%x", crc_calc_o, crc_read);
//else $display("CRC OK!");
// Finally, shift out 5 0's, to make the next command a NOP
// Not necessary, debug unit won't latch a new opcode at the end of a burst
//jtag_write_stream(64'h0, 8'h5, 1);
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
end
endtask
 
 
task do_module_burst_write;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] dataword;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o;
reg crc_match;
reg [5:0] word_size_bits;
begin
//$display("Doing burst write, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
word_size_bits = word_size_bytes << 3;
crc_calc_i = 32'hffffffff;
// Send the command
case (word_size_bytes)
3'h1: opcode = `DBG_WB_CMD_BWRITE8;
3'h2: opcode = `DBG_WB_CMD_BWRITE16;
3'h4: opcode = `DBG_WB_CMD_BWRITE32;
default:
begin
$display("Tried burst write with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
opcode = `DBG_WB_CMD_BWRITE32;
end
endcase
send_module_burst_command(opcode, start_address, word_count); // returns to state idle
// Get us back to shift_dr mode to write a burst
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
 
// Write a start bit (a 1) so it knows when to start counting
write_bit(`JTAG_TDO_bit);
 
// Now, repeat...
for(i = 0; i < word_count; i=i+1) begin
// Write word_size_bytes*8 bits, then get 1 status bit
if(word_size_bytes == 4) dataword = {32'h0, static_data32[i]};
else if(word_size_bytes == 2) dataword = {48'h0, static_data16[i]};
else dataword = {56'h0, static_data8[i]};
jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0);
compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o);
crc_calc_i = crc_calc_o;
`ifndef ADBG_USE_HISPEED
// Check if WB bus is ready
// *** THIS WILL NOT WORK IF THERE IS MORE THAN 1 DEVICE IN THE JTAG CHAIN!!!
status = 1'b0;
read_write_bit(3'h0, status);
if(!status) begin
$display("Bad status bit during burst write, index %d", i);
end
`endif
//$display("Wrote 0x%0x", dataword);
end
// Send the CRC we computed
jtag_write_stream(crc_calc_o, 6'd32,0);
// Read the 'CRC match' bit, and go to exit1_dr
read_write_bit(`JTAG_TMS_bit, crc_match);
if(!crc_match) $display("CRC ERROR! match bit after write is %d (computed CRC 0x%x)", crc_match, crc_calc_o);
//else $display("CRC OK!");
// Finally, shift out 5 0's, to make the next command a NOP
// Not necessary, module will not latch new opcode during burst
//jtag_write_stream(64'h0, 8'h5, 1);
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
end
 
endtask
 
task do_jsp_read_write;
input [3:0] words_to_put;
input [63:0] outstream;
reg [63:0] instream;
integer i;
integer j;
integer snd;
integer rcv;
integer xfer_size;
reg inbit;
// reg shiftbit;
begin
 
// Put us in shift mode
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
 
`ifdef ADBG_JSP_SUPPORT_MULTI
read_write_bit(`JTAG_TDO_bit,inbit); // Put the start bit
`endif
 
// Put / get lengths
jtag_read_write_stream({56'h0,words_to_put, 4'b0000}, 8'h8,0,instream);
`ifdef ADBG_JSP_SUPPORT_MULTI
//shiftbit = instream[7];
instream = (instream << 1);
instream[0] = inbit;
inbit = instream[8];
`endif
 
$display("JSP got %d bytes available, %d bytes free", instream[7:4], instream[3:0]);
 
// Determine transfer size...
rcv = instream[7:4];
snd = words_to_put;
if(instream[3:0] < words_to_put) snd = instream[3:0];
xfer_size = snd;
if(rcv > snd) xfer_size = rcv;
// *** Always do 8 bytes transfers, for testing
// xfer_size = 8;
// ***
$display("Doing JSP transfer of %d bytes", xfer_size);
// Put / get bytes.
for(i = 0; i < xfer_size; i=i+1) begin
#100
jtag_read_write_stream(outstream>>(i*8), 8'h8,0,instream); // Length is in bits...
`ifdef ADBG_JSP_SUPPORT_MULTI
input_data8[i] = {instream[6:0], inbit};
inbit = instream[7];
`else
input_data8[i] = instream[7:0]; // Move input data to where it can be gotten by main task
`endif
end
 
// JSP does not use the module_inhibit output, so last data bit must be a '0'
// Excess writes are ignored. This will however pop a byte from the receive
// FIFO, so make sure all data bytes have been fetched before this is sent.
write_bit(`JTAG_TMS_bit); // exit_dr
// Put us back in idle mode
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
end
endtask // do_jsp_read_write
 
// Puts a value in the TAP IR, assuming we start in IDLE state.
// Returns to IDLE state when finished
task set_ir;
input [3:0] irval;
begin
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(`JTAG_TMS_bit); // select_ir_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream({60'h0,irval}, 8'h4, 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
end
endtask
 
// Resets the TAP and puts it into idle mode
task reset_jtag;
integer i;
begin
for(i = 0; i < 8; i=i+1) begin
write_bit(`JTAG_TMS_bit); // 5 TMS should put us in test_logic_reset mode
end
write_bit(3'h0); // idle
end
endtask
 
 
////////////////////////////////////////////////////////////////////////////
// Tasks to write or read-write a string of data
 
task jtag_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
integer i;
integer databit;
reg [2:0] bits;
begin
for(i = 0; i < (len-1); i=i+1) begin
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
write_bit(bits);
end
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
write_bit(bits);
end
endtask
 
 
task jtag_read_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
output [63:0] instream;
integer i;
integer databit;
reg [2:0] bits;
reg inbit;
begin
instream = 64'h0;
for(i = 0; i < (len-1); i=i+1) begin
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
read_write_bit(bits, inbit);
instream = (instream | (inbit << i));
end
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
read_write_bit(bits, inbit);
instream = (instream | (inbit << (len-1)));
end
endtask
 
/////////////////////////////////////////////////////////////////////////
// Tasks which write or readwrite a single bit (including clocking)
 
task write_bit;
input [2:0] bitvals;
begin
// Set data
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
// Raise clock
jtag_out(bitvals | `JTAG_TCK_bit);
`wait_jtag_period;
// drop clock (making output available in the SHIFT_xR states)
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
end
endtask
 
task read_write_bit;
input [2:0] bitvals;
output l_tdi_val;
begin
// read bit state
l_tdi_val <= jtag_tdi_i;
// Set data
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
// Raise clock
jtag_out(bitvals | `JTAG_TCK_bit);
`wait_jtag_period;
// drop clock (making output available in the SHIFT_xR states)
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
end
endtask
 
/////////////////////////////////////////////////////////////////
// Basic functions to set the state of the JTAG TAP I/F bits
 
task jtag_out;
input [2:0] bitvals;
begin
 
jtag_tck_o <= bitvals[`JTAG_TCK];
jtag_tms_o <= bitvals[`JTAG_TMS];
jtag_tdo_o <= bitvals[`JTAG_TDO];
end
endtask
 
 
task jtag_inout;
input [2:0] bitvals;
output l_tdi_val;
begin
 
jtag_tck_o <= bitvals[`JTAG_TCK];
jtag_tms_o <= bitvals[`JTAG_TMS];
jtag_tdo_o <= bitvals[`JTAG_TDO];
 
l_tdi_val <= jtag_tdi_i;
end
endtask
 
endmodule
/README_testbench.txt
0,0 → 1,33
README_testbench.txt
Advanced Debug Module (adv_dbg_if)
Nathan Yawn, nathan.yawn@opencores.org
 
Three testbenches are supplied with the advanced debug interface. The first
uses behavioral simulation of a wishbone bus with a memory attached, and
another behavioral simulation of an OR1200 CPU. This testbench performs
and tests bus / memory operations, and performs a few CPU operations, The
top-level module is in adv_dbg_tb.v. Other than the behavioral models, it
instantiates an adv_dbg_if (found in ../rtl/verilog/), and a JTAG TAP
("jtag" module, not included with this module). Note that the TAP
written by Igor Mohor will not work correctly; use the version distributed
with the Advanced Debug System (written by Nathan Yawn).
 
The second testbench includes an actual wishbone/OR1200 system. Its
top-level entity is xsv_fpga_top. It instantiates a wb_conbus, an OR1200,
an onchipram, a jtag TAP, and a UART16550, along with an adv_dbg_if. The
testbench is also instantiated here, and is used to drive the inputs to
the JTAG TAP. This testbench is less polished, but includes a functional
test of the single-step capability of the CPU.
 
The third testbench is used to test the JTAG serial port function. Its
top-level entity is adv_dbg_jsp_tb. This testbench instantiates only
a JTAG TAP and and adv_dbg_if. The CPU module of the adv_dbg_if should
not be enabled for this testbench. The WB initiator output of the WB
module is connected point-to-point to the WB target interface of the JTAG
Serial Port (JSP) module. The WB interface is used to drive the WB side
of the JSP.
 
All testbenches were written for use in ModelSim (version 6.4). A
wave.do file is also included for each testbench, which will display a
useful collection of signals in the ModelSim wave view.
 
/full_system/adv_dbg_tb.v
0,0 → 1,916
//////////////////////////////////////////////////////////////////////
//// ////
//// adv_dbg_tb.v ////
//// ////
//// ////
//// Testbench for the SoC Advanced Debug Interface. ////
//// ////
//// Author(s): ////
//// Nathan Yawn (nathan.yawn@opencores.org) ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: adv_dbg_tb.v,v $
// Revision 1.6 2010-01-16 02:15:22 Nathan
// Updated to match changes in hardware. Added support for hi-speed mode.
//
// Revision 1.5 2010-01-08 01:41:07 Nathan
// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
//
// Revision 1.4 2009/05/17 20:54:55 Nathan
// Changed email address to opencores.org
//
// Revision 1.3 2008/07/11 08:18:47 Nathan
// Added a bit to the CPU test. Added the hack that allows the driver to work with a Xilinx BSCAN device.
//
 
 
`include "tap_defines.v"
`include "adbg_defines.v"
`include "adbg_wb_defines.v"
 
 
// Polynomial for the CRC calculation
// Yes, it's backwards. Yes, this is on purpose.
// To decrease logic + routing, we want to shift the CRC calculation
// in the same direction we use to shift the data out, LSB first.
`define DBG_CRC_POLY 32'hedb88320
 
// These are indicies into an array which hold values for the JTAG outputs
`define JTAG_TMS 0
`define JTAG_TCK 1
`define JTAG_TDO 2
 
`define JTAG_TMS_bit 3'h1
`define JTAG_TCK_bit 3'h2
`define JTAG_TDO_bit 3'h4
 
`define wait_jtag_period #50
 
 
module adv_debug_tb (
 
jtag_tck_o,
jtag_tms_o,
jtag_tdo_o,
jtag_tdi_i,
 
wb_clk_o,
sys_rstn_o
 
 
);
 
output jtag_tck_o;
output jtag_tms_o;
output jtag_tdo_o;
input jtag_tdi_i;
output wb_clk_o;
output sys_rstn_o;
 
// Connections to the JTAG TAP
reg jtag_tck_o;
reg jtag_tms_o;
reg jtag_tdo_o;
wire jtag_tdi_i;
 
reg wb_clk_o;
reg sys_rst_o;
reg sys_rstn_o;
reg test_enabled;
 
// Data which will be written to the WB interface
reg [31:0] static_data32 [0:15];
reg [15:0] static_data16 [0:15];
reg [7:0] static_data8 [0:15];
 
// Arrays to hold data read back from the WB interface, for comparison
reg [31:0] input_data32 [0:15];
reg [15:0] input_data16 [0:15];
reg [7:0] input_data8 [0:15];
 
reg [32:0] err_data; // holds the contents of the error register from the various modules
 
reg failed;
integer i;
 
initial
begin
jtag_tck_o = 1'b0;
jtag_tms_o = 1'b0;
jtag_tdo_o = 1'b0;
end
 
// Provide the wishbone / CPU / system clock
initial
begin
wb_clk_o = 1'b0;
forever #5 wb_clk_o = ~wb_clk_o;
end
 
initial
begin
sys_rstn_o = 1'b1;
#200 sys_rstn_o = 1'b0;
#5000 sys_rstn_o = 1'b1;
end
 
 
// Start the test (and reset the wishbone)
initial
begin
test_enabled = 1'b0;
 
// Init the memory
initialize_memory(32'h0,32'h16);
 
#5 test_enabled<= 1'b1;
end
 
// This is the main test procedure
always @ (posedge test_enabled)
begin
 
$display("Starting advanced debug test");
reset_jtag;
#6000;
check_idcode;
#1000;
// Select the debug module in the IR
set_ir(`DEBUG);
#1000;
`ifdef DBG_CPU0_SUPPORTED
// STALL the CPU, so it won't interfere with WB tests
// Select the CPU0 unit in the debug module
#1000;
$display("Selecting CPU0 module at time %t", $time);
select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
 
// Set the stall bit...holding the CPU in reset prevents WB access (?)
$display("Setting reset and stall bits at time %t", $time);
write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h2); // idx, idxlen, data, datalen
#1000;
`endif
///////////////////////////////////////////////////////////////////
// Test the Wishbone unit
////////////////////////////////////////////////////////////////////
`ifdef DBG_WISHBONE_SUPPORTED
// Select the WB unit in the debug module
#1000;
$display("Selecting Wishbone module at time %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
// Reset the error bit
write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h1); // idx, idxlen, data, datalen
#1000;
/////////////////////////////////
// Test 8-bit WB access
failed = 0;
$display("Testing WB 8-bit burst write at time %t: resetting ", $time);
do_module_burst_write(3'h1, 16'd16, 32'h87); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
#1000;
$display("Testing WB 8-bit burst read at time %t", $time);
do_module_burst_read(3'h1, 16'd16, 32'h87);
#1000;
for(i = 0; i < 16; i = i+1) begin
if(static_data8[i] != input_data8[i]) begin
failed = 1;
$display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data8[i], input_data8[i]);
end
end
if(!failed) $display("8-bit read/write OK!");
/////////////////////////////////
// Test 16-bit WB access
failed = 0;
$display("Testing WB 16-bit burst write at time %t", $time);
do_module_burst_write(3'h2, 16'd16, 32'h22); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
#1000;
$display("Testing WB 16-bit burst read at time %t", $time);
do_module_burst_read(3'h2, 16'd16, 32'h22);
#1000;
for(i = 0; i < 16; i = i+1) begin
if(static_data16[i] != input_data16[i]) begin
failed = 1;
$display("16-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data16[i], input_data16[i]);
end
end
if(!failed) $display("16-bit read/write OK!");
////////////////////////////////////
// Test 32-bit WB access
failed = 0;
$display("Testing WB 32-bit burst write at time %t", $time);
do_module_burst_write(3'h4, 16'd16, 32'h100); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
#1000;
$display("Testing WB 32-bit burst read at time %t", $time);
do_module_burst_read(3'h4, 16'd16, 32'h100);
#1000;
for(i = 0; i < 16; i = i+1) begin
if(static_data32[i] != input_data32[i]) begin
failed = 1;
$display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data32[i], input_data32[i]);
end
end
if(!failed) $display("32-bit read/write OK!");
////////////////////////////////
// Test error register
err_data = 33'h0;
// Select and reset the error register
write_module_internal_register(`DBG_WB_INTREG_ERROR, `DBG_WB_REGSELECT_SIZE, 64'h1, 8'h1); // regidx,idxlen,writedata, datalen;
//i_wb.cycle_response(`ERR_RESPONSE, 2, 0); // response type, wait cycles, retry_cycles
do_module_burst_write(3'h4, 16'd4, 32'hdeaddead); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
read_module_internal_register(8'd33, err_data); // get the error register
$display("Error bit is %d, error address is %x", err_data[0], err_data>>1);
 
`endif // WB module supported
///////////////////////////////////////////////////////////////////
// Test CPU0 unit
////////////////////////////////////////////////////////////////////
`ifdef DBG_CPU0_SUPPORTED
// Select the CPU0 unit in the debug module
#1000;
$display("Selecting CPU0 module at time %t", $time);
select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
 
// Set the stall bit (clear the reset bit)
$display("Setting reset and stall bits at time %t", $time);
write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h2); // idx, idxlen, data, datalen
#1000;
// Make sure CPU stalled
$display("Testing reset and stall bits at time %t", $time);
read_module_internal_register(8'd2, err_data); // We assume the register is already selected
$display("Reset and stall bits are %x", err_data);
#1000;
 
// Write some opcodes into the memory
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
 
static_data32[0] = 32'hE0000005;/* l.xor r0,r0,r0 */
static_data32[1] = 32'h9C200000; /* l.addi r1,r0,0x0 */
static_data32[2] = 32'h18400000;/* l.movhi r2,0x4000 */
static_data32[3] = 32'hA8420030;/* l.ori r2,r2,0x30 */
static_data32[4] = 32'h9C210001;/* l.addi r1,r1,1 */
static_data32[5] = 32'h9C210001; /* l.addi r1,r1,1 */
static_data32[6] = 32'hD4020800;/* l.sw 0(r2),r1 */
static_data32[7] = 32'h9C210001;/* l.addi r1,r1,1 */
static_data32[8] = 32'h84620000;/* l.lwz r3,0(r2) */
static_data32[9] = 32'h03FFFFFB;/* l.j loop2 */
static_data32[10] = 32'hE0211800;/* l.add r1,r1,r3 */
 
do_module_burst_write(3'h4, 16'd11, 32'h0); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
 
#1000;
select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
 
#1000;
$display("Enabling CPU exceptions at time %t", $time);
static_data32[0] = 32'h1; // enable exceptions
do_module_burst_write(3'h4, 16'd1, 32'd17); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
 
#1000;
$display("Set \'trap causes stall\' at time %t", $time);
static_data32[0] = 32'h00002000; // Trap causes stall
do_module_burst_write(3'h4, 16'd1, (6 << 11)+20); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
 
#1000;
$display("Set PC at time %t", $time);
static_data32[0] = 32'h0; // Set PC
do_module_burst_write(3'h4, 16'd1, 32'd16); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
 
#1000;
$display("Set step bit at time %t", $time);
static_data32[0] = (1 << 22); // set step bit
do_module_burst_write(3'h4, 16'd1, (6<<11) + 16); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
 
// Unstall x11
for(i = 0; i < 11; i = i + 1)
begin
#1000;
$display("Unstall (%d/11) at time %t", i, $time);
write_module_internal_register(32'h0, 8'h1, 32'h0, 8'h2); // idx, idxlen, data, datalen
end
 
#1000;
#1000;
#1000;
 
$display("Getting NPC at time %t", $time);
do_module_burst_read(3'h4, 16'd1, 32'd16);
$display("NPC = %x, expected 0x00000010", input_data32[0]);
$display("Getting PPC at time %t", $time);
do_module_burst_read(3'h4, 16'd1, 32'd18);
$display("PPC = %x, expected 0x00000028", input_data32[0]);
#1000;
$display("Getting R1 at time %t", $time);
do_module_burst_read(3'h4, 16'd1, 32'h401); // Word size, count, addr; save old instr
$display("R1 = %d, expected 5", input_data32[0]);
#1000;
$display("Un-set step bit at %t", $time);
static_data32[0] = 32'h0; // Trap causes stall
do_module_burst_write(3'h4, 16'd1, (6 << 11)+16);
// Put a trap instr at 0x20
#1000;
$display("Select WB at %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
#1000;
$display("Save old instr at %t", $time);
do_module_burst_read(3'h4, 16'd1, 32'h20); // Save old instr
#1000;
$display("Put trap instr at %t", $time);
static_data32[0] = 32'h21000001; /* l.trap */
do_module_burst_write(3'h4, 16'd1, 32'h20); // put new instr
#1000;
$display("Select CPU0 at %t", $time);
select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
#1000;
$display("Set PC to 0x24 at %t", $time);
static_data32[0] = 32'h24;
do_module_burst_write(3'h4, 16'd1, 32'd16); // Set PC to 0x24
#1000;
$display("Unstall at time %t", $time);
write_module_internal_register(32'h0, 8'h1, 32'h0, 8'h2); // idx, idxlen, data, datalen
 
// We assume it stalls again here...
#1000;
 
err_data = 1;
while(err_data != 0)
begin
$display("Testing for stall at %t", $time);
read_module_internal_register(8'd2, err_data); // We assume the register is already selected
#1000;
end
 
 
// *** The software self-test does 2 separate reads here...
$display("Getting NPC at time %t", $time);
do_module_burst_read(3'h4, 16'd3, 32'd16);
$display("NPC = %x, expected 0x00000024", input_data32[0]);
$display("PPC = %x, expected 0x00000020", input_data32[2]);
 
 
 
`endif
 
end
 
task initialize_memory;
input [31:0] start_addr;
input [31:0] length;
integer i;
reg [31:0] addr;
begin
 
for (i=0; i<length; i=i+1)
begin
static_data32[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
static_data16[i] <= {i[7:0], i[7:0]+ 2'd1};
static_data8[i] <= i[7:0];
end
end
endtask
 
 
///////////////////////////////////////////////////////////////////////////
// Higher-level chain manipulation functions
 
// calculate the CRC, up to 32 bits at a time
task compute_crc;
input [31:0] crc_in;
input [31:0] data_in;
input [5:0] length_bits;
output [31:0] crc_out;
integer i;
reg [31:0] d;
reg [31:0] c;
begin
crc_out = crc_in;
for(i = 0; i < length_bits; i = i+1) begin
d = (data_in[i]) ? 32'hffffffff : 32'h0;
c = (crc_out[0]) ? 32'hffffffff : 32'h0;
//crc_out = {crc_out[30:0], 1'b0}; // original
crc_out = crc_out >> 1;
crc_out = crc_out ^ ((d ^ c) & `DBG_CRC_POLY);
//$display("CRC Itr %d, inbit = %d, crc = 0x%x", i, data_in[i], crc_out);
end
end
endtask
 
task check_idcode;
reg [63:0] readdata;
reg[31:0] idcode;
begin
set_ir(`IDCODE);
// Read the IDCODE in the DR
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_read_write_stream(64'h0, 8'd32, 1, readdata); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
idcode = readdata[31:0];
$display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);
end
endtask;
 
task select_debug_module;
input [1:0] moduleid;
reg validid;
begin
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream({1'b1,moduleid}, 8'h3, 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
$display("Selecting module (%0x)", moduleid);
// Read back the status to make sure a valid chain is selected
/* Pointless, the newly selected module would respond instead...
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
read_write_bit(`JTAG_TMS_bit, validid); // get data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
if(validid) $display("Selected valid module (%0x)", moduleid);
else $display("Failed to select module (%0x)", moduleid);
*/
end
endtask
 
 
task send_module_burst_command;
input [3:0] opcode;
input [31:0] address;
input [15:0] burstlength;
reg [63:0] streamdata;
begin
streamdata = {11'h0,1'b0,opcode,address,burstlength};
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream(streamdata, 8'd53, 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
end
endtask
 
task select_module_internal_register; // Really just a read, with discarded data
input [31:0] regidx;
input [7:0] len; // the length of the register index data, we assume not more than 32
reg[63:0] streamdata;
begin
streamdata = 64'h0;
streamdata = streamdata | regidx;
streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream(streamdata, (len+5), 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
end
endtask
 
task read_module_internal_register; // We assume the register is already selected
//input [31:0] regidx;
input [7:0] len; // the length of the data desired, we assume a max of 64 bits
output [63:0] instream;
reg [63:0] bitmask;
begin
instream = 64'h0;
// We shift out all 0's, which is a NOP to the debug unit
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
// Shift at least 5 bits, as this is the min, for a valid NOP
jtag_read_write_stream(64'h0, len+4,1,instream); // exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
bitmask = 64'hffffffffffffffff;
bitmask = bitmask << len;
bitmask = ~bitmask;
instream = instream & bitmask; // Cut off any unwanted excess bits
end
endtask
 
task write_module_internal_register;
input [31:0] regidx; // the length of the register index data
input [7:0] idxlen;
input [63:0] writedata;
input [7:0] datalen; // the length of the data to write. We assume the two length combined are 59 or less.
reg[63:0] streamdata;
begin
streamdata = 64'h0; // This will 0 the toplevel/module select bit
streamdata = streamdata | writedata;
streamdata = streamdata | (regidx << datalen);
streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream(streamdata, (idxlen+datalen+5), 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
end
endtask
 
// This includes the sending of the burst command
task do_module_burst_read;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] instream;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o; // temp signal...
reg [31:0] crc_read;
reg [5:0] word_size_bits;
begin
$display("Doing burst read, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
instream = 64'h0;
word_size_bits = word_size_bytes << 3;
crc_calc_i = 32'hffffffff;
// Send the command
case (word_size_bytes)
3'h1: opcode = `DBG_WB_CMD_BREAD8;
3'h2: opcode = `DBG_WB_CMD_BREAD16;
3'h4: opcode = `DBG_WB_CMD_BREAD32;
default:
begin
$display("Tried burst read with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
opcode = `DBG_WB_CMD_BREAD32;
end
endcase
send_module_burst_command(opcode,start_address, word_count); // returns to state idle
// This charming kludge provides ONE TCK, in case a xilinx BSCAN TAP is used,
// because the FSM needs it between the read burst command and the actual
// read burst. Blech.
#500;
set_ir(`IDCODE);
#500;
set_ir(`DEBUG);
#500;
// Get us back to shift_dr mode to read a burst
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
`ifdef ADBG_USE_HISPEED
// Get 1 status bit, then word_size_bytes*8 bits
status = 1'b0;
j = 0;
while(!status) begin
read_write_bit(3'h0, status);
j = j + 1;
end
if(j > 1) begin
$display("Took %0d tries before good status bit during burst read", j);
end
`endif
// Now, repeat...
for(i = 0; i < word_count; i=i+1) begin
`ifndef ADBG_USE_HISPEED
// Get 1 status bit, then word_size_bytes*8 bits
status = 1'b0;
j = 0;
while(!status) begin
read_write_bit(3'h0, status);
j = j + 1;
end
if(j > 1) begin
$display("Took %0d tries before good status bit during burst read", j);
end
`endif
jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream);
//$display("Read 0x%0x", instream[31:0]);
compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o);
crc_calc_i = crc_calc_o;
if(word_size_bytes == 1) input_data8[i] = instream[7:0];
else if(word_size_bytes == 2) input_data16[i] = instream[15:0];
else input_data32[i] = instream[31:0];
end
// Read the data CRC from the debug module.
jtag_read_write_stream(64'h0, 6'd32, 1, crc_read);
if(crc_calc_o != crc_read) $display("CRC ERROR! Computed 0x%x, read CRC 0x%x", crc_calc_o, crc_read);
else $display("CRC OK!");
// Finally, shift out 5 0's, to make the next command a NOP
// Not necessary, debug unit won't latch a new opcode at the end of a burst
//jtag_write_stream(64'h0, 8'h5, 1);
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
end
endtask
 
 
task do_module_burst_write;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] dataword;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o;
reg crc_match;
reg [5:0] word_size_bits;
begin
$display("Doing burst write, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
word_size_bits = word_size_bytes << 3;
crc_calc_i = 32'hffffffff;
// Send the command
case (word_size_bytes)
3'h1: opcode = `DBG_WB_CMD_BWRITE8;
3'h2: opcode = `DBG_WB_CMD_BWRITE16;
3'h4: opcode = `DBG_WB_CMD_BWRITE32;
default:
begin
$display("Tried burst write with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
opcode = `DBG_WB_CMD_BWRITE32;
end
endcase
send_module_burst_command(opcode, start_address, word_count); // returns to state idle
// Get us back to shift_dr mode to write a burst
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
 
// Write a start bit (a 1) so it knows when to start counting
write_bit(`JTAG_TDO_bit);
 
// Now, repeat...
for(i = 0; i < word_count; i=i+1) begin
// Write word_size_bytes*8 bits, then get 1 status bit
if(word_size_bytes == 4) dataword = {32'h0, static_data32[i]};
else if(word_size_bytes == 2) dataword = {48'h0, static_data16[i]};
else dataword = {56'h0, static_data8[i]};
jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0);
compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o);
crc_calc_i = crc_calc_o;
`ifndef ADBG_USE_HISPEED
// Check if WB bus is ready
// *** THIS WILL NOT WORK IF THERE IS MORE THAN 1 DEVICE IN THE JTAG CHAIN!!!
status = 1'b0;
read_write_bit(3'h0, status);
if(!status) begin
$display("Bad status bit during burst write, index %d", i);
end
`endif
//$display("Wrote 0x%0x", dataword);
end
// Send the CRC we computed
jtag_write_stream(crc_calc_o, 6'd32,0);
// Read the 'CRC match' bit, and go to exit1_dr
read_write_bit(`JTAG_TMS_bit, crc_match);
if(!crc_match) $display("CRC ERROR! match bit after write is %d (computed CRC 0x%x)", crc_match, crc_calc_o);
else $display("CRC OK!");
// Finally, shift out 5 0's, to make the next command a NOP
// Not necessary, module will not latch new opcode during burst
//jtag_write_stream(64'h0, 8'h5, 1);
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
end
 
endtask
 
 
// Puts a value in the TAP IR, assuming we start in IDLE state.
// Returns to IDLE state when finished
task set_ir;
input [3:0] irval;
begin
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(`JTAG_TMS_bit); // select_ir_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream({60'h0,irval}, 8'h4, 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
end
endtask
 
// Resets the TAP and puts it into idle mode
task reset_jtag;
integer i;
begin
for(i = 0; i < 8; i=i+1) begin
write_bit(`JTAG_TMS_bit); // 5 TMS should put us in test_logic_reset mode
end
write_bit(3'h0); // idle
end
endtask
 
 
////////////////////////////////////////////////////////////////////////////
// Tasks to write or read-write a string of data
 
task jtag_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
integer i;
integer databit;
reg [2:0] bits;
begin
for(i = 0; i < (len-1); i=i+1) begin
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
write_bit(bits);
end
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
write_bit(bits);
end
endtask
 
 
task jtag_read_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
output [63:0] instream;
integer i;
integer databit;
reg [2:0] bits;
reg inbit;
begin
instream = 64'h0;
for(i = 0; i < (len-1); i=i+1) begin
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
read_write_bit(bits, inbit);
instream = (instream | (inbit << i));
end
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
read_write_bit(bits, inbit);
instream = (instream | (inbit << (len-1)));
end
endtask
 
/////////////////////////////////////////////////////////////////////////
// Tasks which write or readwrite a single bit (including clocking)
 
task write_bit;
input [2:0] bitvals;
begin
// Set data
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
// Raise clock
jtag_out(bitvals | `JTAG_TCK_bit);
`wait_jtag_period;
// drop clock (making output available in the SHIFT_xR states)
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
end
endtask
 
task read_write_bit;
input [2:0] bitvals;
output l_tdi_val;
begin
// read bit state
l_tdi_val <= jtag_tdi_i;
// Set data
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
// Raise clock
jtag_out(bitvals | `JTAG_TCK_bit);
`wait_jtag_period;
// drop clock (making output available in the SHIFT_xR states)
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
end
endtask
 
/////////////////////////////////////////////////////////////////
// Basic functions to set the state of the JTAG TAP I/F bits
 
task jtag_out;
input [2:0] bitvals;
begin
 
jtag_tck_o <= bitvals[`JTAG_TCK];
jtag_tms_o <= bitvals[`JTAG_TMS];
jtag_tdo_o <= bitvals[`JTAG_TDO];
end
endtask
 
 
task jtag_inout;
input [2:0] bitvals;
output l_tdi_val;
begin
 
jtag_tck_o <= bitvals[`JTAG_TCK];
jtag_tms_o <= bitvals[`JTAG_TMS];
jtag_tdo_o <= bitvals[`JTAG_TDO];
 
l_tdi_val <= jtag_tdi_i;
end
endtask
 
endmodule
/full_system/wave.do
0,0 → 1,500
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /xsv_fpga_top/jtag_tdi
add wave -noupdate -format Logic /xsv_fpga_top/jtag_tms
add wave -noupdate -format Logic /xsv_fpga_top/jtag_tck
add wave -noupdate -format Logic /xsv_fpga_top/jtag_tdo
add wave -noupdate -format Logic /xsv_fpga_top/debug_select
add wave -noupdate -divider {Top level signals}
add wave -noupdate -format Logic /xsv_fpga_top/clk
add wave -noupdate -format Logic /xsv_fpga_top/rstn
add wave -noupdate -format Logic /xsv_fpga_top/rst_r
add wave -noupdate -format Logic /xsv_fpga_top/wb_rst
add wave -noupdate -format Logic /xsv_fpga_top/cpu_rst
add wave -noupdate -divider {Top-level CPU dbg}
add wave -noupdate -format Literal /xsv_fpga_top/dbg_lss
add wave -noupdate -format Literal /xsv_fpga_top/dbg_is
add wave -noupdate -format Literal /xsv_fpga_top/dbg_wp
add wave -noupdate -format Logic /xsv_fpga_top/dbg_bp
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_dat_dbg
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_dat_risc
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_adr
add wave -noupdate -format Logic /xsv_fpga_top/dbg_ewt
add wave -noupdate -format Logic /xsv_fpga_top/dbg_stall
add wave -noupdate -format Logic /xsv_fpga_top/dbg_we
add wave -noupdate -format Logic /xsv_fpga_top/dbg_stb
add wave -noupdate -format Logic /xsv_fpga_top/dbg_ack
add wave -noupdate -divider {CPU IWB}
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_clk_i
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_rst_i
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_ack_i
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_err_i
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_rty_i
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/iwb_dat_i
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_cyc_o
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/iwb_adr_o
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_stb_o
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_we_o
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/iwb_sel_o
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/iwb_dat_o
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_cab_o
add wave -noupdate -divider {DBG WB signals}
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/wb_dm_adr_o
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/wb_dm_dat_i
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/wb_dm_dat_o
add wave -noupdate -format Literal /xsv_fpga_top/wb_dm_sel_o
add wave -noupdate -format Logic /xsv_fpga_top/wb_dm_we_o
add wave -noupdate -format Logic /xsv_fpga_top/wb_dm_stb_o
add wave -noupdate -format Logic /xsv_fpga_top/wb_dm_cyc_o
add wave -noupdate -format Logic /xsv_fpga_top/wb_dm_cab_o
add wave -noupdate -format Logic /xsv_fpga_top/wb_dm_ack_i
add wave -noupdate -format Logic /xsv_fpga_top/wb_dm_err_i
add wave -noupdate -divider {DBG WB BIU}
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/tck_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/rst_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/data_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/data_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/addr_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/strobe_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/rd_wrn_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/rdy_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/err_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/word_size_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/wb_clk_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/wb_adr_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/wb_dat_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/wb_dat_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/wb_cyc_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/wb_stb_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/wb_sel_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/wb_we_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/wb_ack_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/wb_cab_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/wb_err_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/wb_cti_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/wb_bte_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/sel_reg
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/addr_reg
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/data_in_reg
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/data_out_reg
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/wr_reg
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/str_sync
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/rdy_sync
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/err_reg
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/rdy_sync_tff1
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/rdy_sync_tff2
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/rdy_sync_tff2q
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/str_sync_wbff1
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/str_sync_wbff2
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/str_sync_wbff2q
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/data_o_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/rdy_sync_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/err_en
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/be_dec
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/start_toggle
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/swapped_data_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/swapped_data_out
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/wb_fsm_state
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_biu_i/next_fsm_state
add wave -noupdate -divider {DBG WB Module}
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/tck_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/module_tdo_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/tdi_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/capture_dr_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/shift_dr_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/update_dr_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_register_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/module_select_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/top_inhibit_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/rst_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_clk_i
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_adr_o
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_dat_o
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_dat_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_cyc_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_stb_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_sel_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_we_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_ack_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_cab_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_err_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_cti_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_bte_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/address_counter
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/bit_count
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/word_count
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/operation
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_out_shift_reg
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/internal_register_select
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/internal_reg_error
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/addr_sel
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/addr_ct_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/op_reg_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/bit_ct_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/bit_ct_rst
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/word_ct_sel
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/word_ct_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/out_reg_ld_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/out_reg_shift_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/out_reg_data_sel
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/tdo_output_sel
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu_strobe
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_clr
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_in_sel
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_shift_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/regsel_ld_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/intreg_ld_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/error_reg_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu_clr_err
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/word_count_zero
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/bit_count_max
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/module_cmd
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu_ready
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu_err
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/burst_instruction
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/intreg_instruction
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/intreg_write
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/rd_op
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_match
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/bit_count_32
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/word_size_bits
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/word_size_bytes
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/incremented_address
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_to_addr_counter
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_to_word_counter
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/decremented_word_count
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/address_data_in
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/count_data_in
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/operation_in
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_to_biu
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_from_biu
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/crc_data_out
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_data_in
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_serial_out
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/reg_select_data
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/out_reg_data
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_from_internal_reg
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu_rst
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/module_state
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/module_next_state
add wave -noupdate -divider {DBG Top}
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/tck_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/tdi_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/tdo_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/rst_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/shift_dr_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/pause_dr_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/update_dr_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/capture_dr_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/debug_select_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_clk_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/wb_adr_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/wb_dat_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/wb_dat_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_cyc_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_stb_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/wb_sel_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_we_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_ack_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_cab_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_err_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/wb_cti_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/wb_bte_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_clk_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/cpu0_addr_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/cpu0_data_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/cpu0_data_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_bp_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_stall_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_stb_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_we_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_ack_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_rst_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/tdo_wb
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/tdo_cpu0
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/tdo_cpu1
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/input_shift_reg
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/module_id_reg
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/select_inhibit
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/module_inhibit
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/select_cmd
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/module_id_in
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/module_selects
add wave -noupdate -divider {DBG CPU0 Module}
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/tck_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/module_tdo_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/tdi_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/capture_dr_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/shift_dr_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/update_dr_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_register_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/module_select_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/top_inhibit_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/rst_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_clk_i
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_addr_o
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_data_i
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_data_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_stb_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_we_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_ack_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_rst_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_bp_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_stall_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/address_counter
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/bit_count
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/word_count
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/operation
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_out_shift_reg
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/internal_register_select
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/internal_reg_status
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/addr_sel
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/addr_ct_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/op_reg_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/bit_ct_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/bit_ct_rst
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/word_ct_sel
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/word_ct_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/out_reg_ld_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/out_reg_shift_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/out_reg_data_sel
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/tdo_output_sel
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/biu_strobe
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_clr
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_in_sel
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_shift_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/regsel_ld_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/intreg_ld_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/word_count_zero
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/bit_count_max
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/module_cmd
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/biu_ready
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/burst_instruction
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/intreg_instruction
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/intreg_write
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/rd_op
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_match
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/bit_count_32
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/word_size_bits
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/address_increment
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/incremented_address
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_to_addr_counter
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_to_word_counter
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/decremented_word_count
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/address_data_in
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/count_data_in
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/operation_in
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_to_biu
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_from_biu
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_data_out
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_data_in
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_serial_out
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/reg_select_data
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/out_reg_data
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_from_internal_reg
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/status_reg_wr
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/module_state
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/module_next_state
add wave -noupdate -divider {DBG CPU0 BIU}
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/tck_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rst_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/data_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/data_o
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/addr_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/strobe_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rd_wrn_i
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rdy_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_clk_i
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_addr_o
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_data_i
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_data_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_stb_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_we_o
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_ack_i
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/addr_reg
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/data_in_reg
add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/data_out_reg
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/wr_reg
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/str_sync
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_tff1
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_tff2
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_tff2q
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/str_sync_wbff1
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/str_sync_wbff2
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/str_sync_wbff2q
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/data_o_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_en
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/start_toggle
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_fsm_state
add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/next_fsm_state
add wave -noupdate -divider {CPU debug unit}
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/clk
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/rst
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcpu_cycstb_i
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcpu_we_i
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcpu_adr_i
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcpu_dat_lsu
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcpu_dat_dc
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/icpu_cycstb_i
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/ex_freeze
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/branch_op
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/ex_insn
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/id_pc
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/spr_dat_npc
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/rf_dataw
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/du_dsr
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/du_stall
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/du_addr
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/du_dat_i
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/du_dat_o
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/du_read
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/du_write
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/du_except
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/du_hwbkpt
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/spr_cs
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/spr_write
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/spr_addr
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/spr_dat_i
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/spr_dat_o
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_stall_i
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_ewt_i
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dbg_lss_o
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dbg_is_o
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dbg_wp_o
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_bp_o
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_stb_i
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_we_i
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dbg_adr_i
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dbg_dat_i
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dbg_dat_o
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_ack_o
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dmr1
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dmr2
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dsr
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/drr
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr0
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr1
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr2
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr3
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr4
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr5
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr6
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr7
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr0
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr1
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr2
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr3
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr4
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr5
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr6
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr7
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dwcr0
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dwcr1
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dmr1_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dmr2_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dsr_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/drr_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr0_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr1_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr2_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr3_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr4_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr5_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr6_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr7_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr0_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr1_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr2_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr3_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr4_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr5_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr6_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr7_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dwcr0_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dwcr1_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_bp_r
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/except_stop
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/tbia_dat_o
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/tbim_dat_o
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/tbar_dat_o
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/tbts_dat_o
add wave -noupdate -divider {CPU SPRs}
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/clk
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/rst
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/flagforw
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/flag_we
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/flag
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/cyforw
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/cy_we
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/carry
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/addrbase
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/addrofs
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/dat_i
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/alu_op
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/branch_op
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/epcr
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/eear
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/esr
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/except_started
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/to_wbmux
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/epcr_we
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/eear_we
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/esr_we
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/pc_we
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/sr_we
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/to_sr
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/sr
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_cfgr
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_rf
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_npc
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_ppc
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_mac
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_pic
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_tt
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_pm
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_dmmu
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_immu
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_du
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_addr
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_o
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_cs
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_we
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/du_addr
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/du_dat_du
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/du_read
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/du_write
add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/du_dat_cpu
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/write_spr
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/read_spr
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/cfgr_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/rf_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/npc_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/ppc_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/sr_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/epcr_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/eear_sel
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/esr_sel
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/sys_data
add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/du_access
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/sprs_op
add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/unqualified_cs
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {4278 ps} 0}
configure wave -namecolwidth 391
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {6180 ps}
/full_system/xsv_fpga_top.v
0,0 → 1,917
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1K test application for XESS XSV board, Top Level ////
//// ////
//// This file is part of the OR1K test application ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Top level instantiating all the blocks. ////
//// ////
//// To Do: ////
//// - nothing really ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: xsv_fpga_top.v,v $
// Revision 1.5 2010-01-16 02:15:22 Nathan
// Updated to match changes in hardware. Added support for hi-speed mode.
//
// Revision 1.4 2010-01-08 01:41:07 Nathan
// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
//
// Revision 1.3 2008/07/11 08:22:17 Nathan
// Added code to make the native TAP simulate a Xilinx BSCAN device, and code to simulate the behavior of the xilinx_internal_jtag module. The adv_dbg_module should get inputs that emulate the xilinx_internal_jtag device outputs.
//
// Revision 1.10 2004/04/05 08:44:35 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.8 2003/04/07 21:05:58 lampret
// WB = 1/2 RISC clock test code enabled.
//
// Revision 1.7 2003/04/07 01:28:17 lampret
// Adding OR1200_CLMODE_1TO2 test code.
//
// Revision 1.6 2002/08/12 05:35:12 lampret
// rty_i are unused - tied to zero.
//
// Revision 1.5 2002/03/29 20:58:51 lampret
// Changed hardcoded address for fake MC to use a define.
//
// Revision 1.4 2002/03/29 16:30:47 lampret
// Fixed port names that changed.
//
// Revision 1.3 2002/03/29 15:50:03 lampret
// Added response from memory controller (addr 0x60000000)
//
// Revision 1.2 2002/03/21 17:39:16 lampret
// Fixed some typos
//
//
 
`include "xsv_fpga_defines.v"
//`include "bench_defines.v"
 
module xsv_fpga_top (
 
//
// Global signals
//
//clk,
//rstn,
 
// UART signals
uart_stx, uart_srx
// SDRAM signals
/*
sdram_clk_i, sdram_addr_o, sdram_ba_o, sdram_dqm_o,
sdram_we_o, sdram_cas_o, sdram_ras_o,
sdram_cke_o, sdram_cs_o, sdram_data_io
*/
);
 
//
// I/O Ports
//
 
//
// Global
//
//input clk;
//input rstn;
 
// UART
input uart_srx;
output uart_stx;
 
// SDRAM
/*
input sdram_clk_i;
output [11:0] sdram_addr_o;
output [1:0] sdram_ba_o;
output [3:0] sdram_dqm_o;
output sdram_we_o;
output sdram_cas_o;
output sdram_ras_o;
output sdram_cke_o;
output sdram_cs_o;
inout [31:0] sdram_data_io;
*/
 
//
// Internal wires
//
 
wire clk;
wire rstn;
 
//
// Debug core master i/f wires
//
wire [31:0] wb_dm_adr_o;
wire [31:0] wb_dm_dat_i;
wire [31:0] wb_dm_dat_o;
wire [3:0] wb_dm_sel_o;
wire wb_dm_we_o;
wire wb_dm_stb_o;
wire wb_dm_cyc_o;
wire wb_dm_cab_o;
wire wb_dm_ack_i;
wire wb_dm_err_i;
 
//
// Debug <-> RISC wires
//
wire [3:0] dbg_lss;
wire [1:0] dbg_is;
wire [10:0] dbg_wp;
wire dbg_bp;
wire [31:0] dbg_dat_dbg;
wire [31:0] dbg_dat_risc;
wire [31:0] dbg_adr;
wire dbg_ewt;
wire dbg_stall;
wire dbg_we;
wire dbg_stb;
wire dbg_ack;
wire dbg_cpu0_rst;
 
//
// TAP<->dbg_interface
//
wire debug_rst;
wire debug_select;
wire debug_tdi;
wire debug_tdo;
wire shift_dr;
wire pause_dr;
wire update_dr;
wire capture_dr;
wire drck; // To emulate the BSCAN_VIRTEX/SPARTAN devices
 
//
// RISC instruction master i/f wires
//
wire [31:0] wb_rim_adr_o;
wire wb_rim_cyc_o;
wire [31:0] wb_rim_dat_i;
wire [31:0] wb_rim_dat_o;
wire [3:0] wb_rim_sel_o;
wire wb_rim_ack_i;
wire wb_rim_err_i;
wire wb_rim_rty_i = 1'b0;
wire wb_rim_we_o;
wire wb_rim_stb_o;
wire wb_rim_cab_o;
//wire [31:0] wb_rif_adr;
//reg prefix_flash;
 
//
// RISC data master i/f wires
//
wire [31:0] wb_rdm_adr_o;
wire wb_rdm_cyc_o;
wire [31:0] wb_rdm_dat_i;
wire [31:0] wb_rdm_dat_o;
wire [3:0] wb_rdm_sel_o;
wire wb_rdm_ack_i;
wire wb_rdm_err_i;
wire wb_rdm_rty_i = 1'b0;
wire wb_rdm_we_o;
wire wb_rdm_stb_o;
wire wb_rdm_cab_o;
 
//
// RISC misc
//
//wire [19:0] pic_ints;
 
//
// SRAM controller slave i/f wires
//
wire [31:0] wb_ss_dat_i;
wire [31:0] wb_ss_dat_o;
wire [31:0] wb_ss_adr_i;
wire [3:0] wb_ss_sel_i;
wire wb_ss_we_i;
wire wb_ss_cyc_i;
wire wb_ss_stb_i;
wire wb_ss_ack_o;
wire wb_ss_err_o;
 
 
//
// UART16550 core slave i/f wires
//
wire [31:0] wb_us_dat_i;
wire [31:0] wb_us_dat_o;
wire [31:0] wb_us_adr_i;
wire [3:0] wb_us_sel_i;
wire wb_us_we_i;
wire wb_us_cyc_i;
wire wb_us_stb_i;
wire wb_us_ack_o;
wire wb_us_err_o;
 
//
// UART external i/f wires
//
wire uart_stx;
wire uart_srx;
 
 
//
// Memory controller core slave i/f wires
//
/*
wire [31:0] wb_mem_dat_i;
wire [31:0] wb_mem_dat_o;
wire [31:0] wb_mem_adr_i;
wire [3:0] wb_mem_sel_i;
wire wb_mem_we_i;
wire wb_mem_cyc_i;
wire wb_mem_stb_i;
wire wb_mem_ack_o;
wire wb_mem_err_o;
 
// Internal mem control wires
wire [7:0] mc_cs;
wire [12:0] mc_addr_o;
 
 
// Memory control external wires
wire sdram_clk_i;
wire [11:0] sdram_addr_o;
wire [1:0] sdram_ba_o;
wire [3:0] sdram_dqm_o;
wire sdram_we_o;
wire sdram_cas_o;
wire sdram_ras_o;
wire sdram_cke_o;
wire sdram_cs_o;
wire [31:0] sdram_data_io;
*/
 
//
// JTAG wires
//
wire jtag_tdi;
wire jtag_tms;
wire jtag_tck;
wire jtag_trst;
wire jtag_tdo;
 
 
//
// Reset debounce
//
reg rstn_debounce;
wire rst_r;
reg wb_rst;
reg cpu_rst;
 
//
// Global clock
//
`ifdef OR1200_CLMODE_1TO2
reg wb_clk;
`else
wire wb_clk;
`endif
 
//
// Reset debounce
//
always @(posedge wb_clk or negedge rstn)
if (~rstn)
rstn_debounce <= 1'b0;
else
rstn_debounce <= #1 1'b1;
 
assign rst_r = ~rstn_debounce;
//assign dbg_trst = rstn_debounce & jtag_trst;
 
//
// Reset debounce
//
always @(posedge wb_clk)
wb_rst <= #1 rst_r;
always @ (posedge wb_clk)
cpu_rst <= dbg_cpu0_rst | rst_r;
 
//
// This is purely for testing 1/2 WB clock
// This should never be used when implementing in
// an FPGA. It is used only for simulation regressions.
//
`ifdef OR1200_CLMODE_1TO2
initial wb_clk = 0;
always @(posedge clk)
wb_clk = ~wb_clk;
`else
//
// Some Xilinx P&R tools need this
//
`ifdef TARGET_VIRTEX
IBUFG IBUFG1 (
.O ( wb_clk ),
.I ( clk )
);
`else
assign wb_clk = clk;
`endif
`endif // OR1200_CLMODE_1TO2
 
//
// Unused WISHBONE signals
//
assign wb_us_err_o = 1'b0;
 
 
assign jtag_tvref = 1'b1;
assign jtag_tgnd = 1'b0;
 
// JTAG / adv. debug control testbench
adv_debug_tb tb (
 
.jtag_tck_o(jtag_tck),
.jtag_tms_o(jtag_tms),
.jtag_tdo_o(jtag_tdi),
.jtag_tdi_i(jtag_tdo),
 
.wb_clk_o(clk),
.sys_rstn_o(rstn)
);
 
//
// JTAG TAP controller instantiation
//
tap_top tap (
// JTAG pads
.tms_pad_i(jtag_tms),
.tck_pad_i(jtag_tck),
.trstn_pad_i(1'b1),
.tdi_pad_i(jtag_tdi),
.tdo_pad_o(jtag_tdo),
.tdo_padoe_o(),
 
// TAP states
.test_logic_reset_o(debug_rst),
.run_test_idle_o(),
.shift_dr_o(shift_dr),
.pause_dr_o(),
.update_dr_o(update_dr),
.capture_dr_o(capture_dr),
// Select signals for boundary scan or mbist
.extest_select_o(),
.sample_preload_select_o(),
.mbist_select_o(),
.debug_select_o(debug_select),
// TDO signal that is connected to TDI of sub-modules.
.tdi_o(debug_tdi),
// TDI signals from sub-modules
.debug_tdo_i(debug_tdo), // from debug module
.bs_chain_tdo_i(1'b0), // from Boundary Scan Chain
.mbist_tdo_i(1'b0) // from Mbist Chain
);
 
// This is taken from the xilinx bscan_virtex4.v module
// It simulates the DRCK output of a BSCAN_* block
assign drck = ((debug_select & !shift_dr & !capture_dr) ||
(debug_select & shift_dr & jtag_tck) ||
(debug_select & capture_dr & jtag_tck));
reg xshift;
reg xcapture;
reg xupdate;
reg xselect;
// TAP state outputs are also delayed half a cycle.
always @(negedge jtag_tck)
begin
xshift = shift_dr;
xcapture = capture_dr;
xupdate = update_dr;
xselect = debug_select;
end
 
//////////////////////////////////////////
wire tck2;
assign tck2 = (drck & !xupdate);
 
reg update2;
 
always @ (posedge xupdate or posedge xcapture or negedge xselect)
begin
if(xupdate) update2 <= 1'b1;
else if(xcapture) update2 <= 1'b0;
else if(!xselect) update2 <= 1'b0;
end
 
//
// Instantiation of the development i/f
//
adbg_top dbg_top (
 
// JTAG pins
.tck_i ( tck2 ),
.tdi_i ( debug_tdi ),
.tdo_o ( debug_tdo ),
.rst_i ( debug_rst ),
 
// TAP states
.shift_dr_i( xshift ),
.pause_dr_i( pause_dr ),
.update_dr_i( update2 ),
.capture_dr_i (xcapture),
 
// Instructions
.debug_select_i( xselect ),
 
// RISC signals
.cpu0_clk_i ( wb_clk ),
.cpu0_addr_o ( dbg_adr ),
.cpu0_data_i ( dbg_dat_risc ),
.cpu0_data_o ( dbg_dat_dbg ),
.cpu0_bp_i ( dbg_bp ),
.cpu0_stall_o ( dbg_stall ),
.cpu0_stb_o ( dbg_stb ),
.cpu0_we_o ( dbg_we ),
.cpu0_ack_i ( dbg_ack ),
.cpu0_rst_o ( dbg_cpu0_rst),
 
// WISHBONE common
.wb_clk_i ( wb_clk ),
 
// WISHBONE master interface
.wb_adr_o ( wb_dm_adr_o ),
.wb_dat_o ( wb_dm_dat_o ),
.wb_dat_i ( wb_dm_dat_i ),
.wb_cyc_o ( wb_dm_cyc_o ),
.wb_stb_o ( wb_dm_stb_o ),
.wb_sel_o ( wb_dm_sel_o ),
.wb_we_o ( wb_dm_we_o ),
.wb_ack_i ( wb_dm_ack_i ),
.wb_cab_o ( wb_dm_cab_o ),
.wb_err_i ( wb_dm_err_i ),
.wb_cti_o (),
.wb_bte_o ()
);
 
 
//
// Instantiation of the OR1200 RISC
//
or1200_top or1200_top (
 
// Common
.rst_i ( cpu_rst ),
.clk_i ( clk ),
`ifdef OR1200_CLMODE_1TO2
.clmode_i ( 2'b01 ),
`else
`ifdef OR1200_CLMODE_1TO4
.clmode_i ( 2'b11 ),
`else
.clmode_i ( 2'b00 ),
`endif
`endif
 
// WISHBONE Instruction Master
.iwb_clk_i ( wb_clk ),
.iwb_rst_i ( wb_rst ),
.iwb_cyc_o ( wb_rim_cyc_o ),
.iwb_adr_o ( wb_rim_adr_o ),
.iwb_dat_i ( wb_rim_dat_i ),
.iwb_dat_o ( wb_rim_dat_o ),
.iwb_sel_o ( wb_rim_sel_o ),
.iwb_ack_i ( wb_rim_ack_i ),
.iwb_err_i ( wb_rim_err_i ),
.iwb_rty_i ( wb_rim_rty_i ),
.iwb_we_o ( wb_rim_we_o ),
.iwb_stb_o ( wb_rim_stb_o ),
.iwb_cab_o ( wb_rim_cab_o ),
 
// WISHBONE Data Master
.dwb_clk_i ( wb_clk ),
.dwb_rst_i ( wb_rst ),
.dwb_cyc_o ( wb_rdm_cyc_o ),
.dwb_adr_o ( wb_rdm_adr_o ),
.dwb_dat_i ( wb_rdm_dat_i ),
.dwb_dat_o ( wb_rdm_dat_o ),
.dwb_sel_o ( wb_rdm_sel_o ),
.dwb_ack_i ( wb_rdm_ack_i ),
.dwb_err_i ( wb_rdm_err_i ),
.dwb_rty_i ( wb_rdm_rty_i ),
.dwb_we_o ( wb_rdm_we_o ),
.dwb_stb_o ( wb_rdm_stb_o ),
.dwb_cab_o ( wb_rdm_cab_o ),
 
// Debug
.dbg_stall_i ( dbg_stall ), // Set to 1'b0 if debug is absent / broken
.dbg_dat_i ( dbg_dat_dbg ),
.dbg_adr_i ( dbg_adr ),
.dbg_ewt_i ( 1'b0 ),
.dbg_lss_o ( ),
.dbg_is_o ( ),
.dbg_wp_o ( ),
.dbg_bp_o ( dbg_bp ),
.dbg_dat_o ( dbg_dat_risc ),
.dbg_ack_o ( dbg_ack ),
.dbg_stb_i ( dbg_stb ),
.dbg_we_i ( dbg_we ),
 
// Power Management
.pm_clksd_o ( ),
.pm_cpustall_i ( 1'b0 ),
.pm_dc_gate_o ( ),
.pm_ic_gate_o ( ),
.pm_dmmu_gate_o ( ),
.pm_immu_gate_o ( ),
.pm_tt_gate_o ( ),
.pm_cpu_gate_o ( ),
.pm_wakeup_o ( ),
.pm_lvolt_o ( ),
 
// Interrupts
.pic_ints_i (20'b0)
);
 
 
//
// Instantiation of the On-chip RAM controller
//
onchip_ram_top #(
.dwidth (32),
.size_bytes(16384)
) onchip_ram_top (
 
// WISHBONE common
.wb_clk_i ( wb_clk ),
.wb_rst_i ( wb_rst ),
 
// WISHBONE slave
.wb_dat_i ( wb_ss_dat_i ),
.wb_dat_o ( wb_ss_dat_o ),
.wb_adr_i ( wb_ss_adr_i ),
.wb_sel_i ( wb_ss_sel_i ),
.wb_we_i ( wb_ss_we_i ),
.wb_cyc_i ( wb_ss_cyc_i ),
.wb_stb_i ( wb_ss_stb_i ),
.wb_ack_o ( wb_ss_ack_o ),
.wb_err_o ( wb_ss_err_o )
);
 
//
// Instantiation of the UART16550
//
uart_top uart_top (
 
// WISHBONE common
.wb_clk_i ( wb_clk ),
.wb_rst_i ( wb_rst ),
 
// WISHBONE slave
.wb_adr_i ( wb_us_adr_i[4:0] ),
.wb_dat_i ( wb_us_dat_i ),
.wb_dat_o ( wb_us_dat_o ),
.wb_we_i ( wb_us_we_i ),
.wb_stb_i ( wb_us_stb_i ),
.wb_cyc_i ( wb_us_cyc_i ),
.wb_ack_o ( wb_us_ack_o ),
.wb_sel_i ( wb_us_sel_i ),
 
// Interrupt request
.int_o ( ),
 
// UART signals
// serial input/output
.stx_pad_o ( uart_stx ),
.srx_pad_i ( uart_srx ),
 
// modem signals
.rts_pad_o ( ),
.cts_pad_i ( 1'b0 ),
.dtr_pad_o ( ),
.dsr_pad_i ( 1'b0 ),
.ri_pad_i ( 1'b0 ),
.dcd_pad_i ( 1'b0 )
);
 
/*
mc_wrapper mc_wrapper (
.clk_i ( wb_clk ),
.rst_i ( wb_rst ),
.clk_mem_i ( sdram_clk_i ),
 
.wb_data_i ( wb_mem_dat_i ),
.wb_data_o ( wb_mem_dat_o ),
.wb_addr_i ( wb_mem_adr_i ),
.wb_sel_i ( wb_mem_sel_i ),
.wb_we_i ( wb_mem_we_i ),
.wb_cyc_i ( wb_mem_cyc_i ),
.wb_stb_i ( wb_mem_stb_i ),
.wb_ack_o ( wb_mem_ack_o ),
.wb_err_o ( wb_mem_err_o ),
 
.susp_req_i ( 1'b0 ),
.resume_req_i ( 1'b0 ),
.suspended_o (),
.poc_o ( ), // This is an output so the rest of the system can configure itself
 
.sdram_addr_o ( mc_addr_o ),
.sdram_ba_o ( sdram_ba_o ),
.sdram_cas_n_o ( sdram_cas_o ),
.sdram_ras_n_o ( sdram_ras_o ),
.sdram_cke_n_o ( sdram_cke_o ),
.mc_dqm_o ( sdram_dqm_o ),
.mc_we_n_o ( sdram_we_o ),
.mc_oe_n_o ( ),
.mc_data_io ( sdram_data_io ),
.mc_parity_io ( ),
.mc_cs_n_o ( mc_cs )
);
 
assign sdram_cs_o = mc_cs[0];
assign sdram_addr_o = mc_addr_o[11:0];
*/
 
//
// Instantiation of the Traffic COP
//
wb_conbus_top #(.s0_addr_w (`APP_ADDR_DEC_W),
.s0_addr (`APP_ADDR_SDRAM),
.s1_addr_w (`APP_ADDR_DEC2_W),
.s1_addr (`APP_ADDR_OCRAM),
.s27_addr_w (`APP_ADDR_DECP_W),
.s2_addr (`APP_ADDR_VGA),
.s3_addr (`APP_ADDR_ETH),
.s4_addr (`APP_ADDR_AUDIO),
.s5_addr (`APP_ADDR_UART),
.s6_addr (`APP_ADDR_PS2),
.s7_addr (`APP_ADDR_RES1)
) tc_top (
 
// WISHBONE common
.clk_i ( wb_clk ),
.rst_i ( wb_rst ),
 
// WISHBONE Initiator 0
.m0_cyc_i ( 1'b0 ),
.m0_stb_i ( 1'b0 ),
.m0_cab_i ( 1'b0 ),
.m0_adr_i ( 32'h0000_0000 ),
.m0_sel_i ( 4'b0000 ),
.m0_we_i ( 1'b0 ),
.m0_dat_i ( 32'h0000_0000 ),
.m0_dat_o ( ),
.m0_ack_o ( ),
.m0_err_o ( ),
 
// WISHBONE Initiator 1
.m1_cyc_i ( 1'b0 ),
.m1_stb_i ( 1'b0 ),
.m1_cab_i ( 1'b0 ),
.m1_adr_i ( 32'h0000_0000 ),
.m1_sel_i ( 4'b0000 ),
.m1_we_i ( 1'b0 ),
.m1_dat_i ( 32'h0000_0000 ),
.m1_dat_o ( ),
.m1_ack_o ( ),
.m1_err_o ( ),
 
// WISHBONE Initiator 2
.m2_cyc_i ( 1'b0 ),
.m2_stb_i ( 1'b0 ),
.m2_cab_i ( 1'b0 ),
.m2_adr_i ( 32'h0000_0000 ),
.m2_sel_i ( 4'b0000 ),
.m2_we_i ( 1'b0 ),
.m2_dat_i ( 32'h0000_0000 ),
.m2_dat_o ( ),
.m2_ack_o ( ),
.m2_err_o ( ),
// WISHBONE Initiator 3
.m3_cyc_i ( wb_dm_cyc_o ),
.m3_stb_i ( wb_dm_stb_o ),
.m3_cab_i ( wb_dm_cab_o ),
.m3_adr_i ( wb_dm_adr_o ),
.m3_sel_i ( wb_dm_sel_o ),
.m3_we_i ( wb_dm_we_o ),
.m3_dat_i ( wb_dm_dat_o ),
.m3_dat_o ( wb_dm_dat_i ),
.m3_ack_o ( wb_dm_ack_i ),
.m3_err_o ( wb_dm_err_i ),
 
// WISHBONE Initiator 4
.m4_cyc_i ( wb_rdm_cyc_o ),
.m4_stb_i ( wb_rdm_stb_o ),
.m4_cab_i ( wb_rdm_cab_o ),
.m4_adr_i ( wb_rdm_adr_o ),
.m4_sel_i ( wb_rdm_sel_o ),
.m4_we_i ( wb_rdm_we_o ),
.m4_dat_i ( wb_rdm_dat_o ),
.m4_dat_o ( wb_rdm_dat_i ),
.m4_ack_o ( wb_rdm_ack_i ),
.m4_err_o ( wb_rdm_err_i ),
 
// WISHBONE Initiator 5
.m5_cyc_i ( wb_rim_cyc_o ),
.m5_stb_i ( wb_rim_stb_o ),
.m5_cab_i ( wb_rim_cab_o ),
.m5_adr_i ( wb_rim_adr_o ),
.m5_sel_i ( wb_rim_sel_o ),
.m5_we_i ( wb_rim_we_o ),
.m5_dat_i ( wb_rim_dat_o ),
.m5_dat_o ( wb_rim_dat_i ),
.m5_ack_o ( wb_rim_ack_i ),
.m5_err_o ( wb_rim_err_i ),
 
// WISHBONE Initiator 6
.m6_cyc_i ( 1'b0 ),
.m6_stb_i ( 1'b0 ),
.m6_cab_i ( 1'b0 ),
.m6_adr_i ( 32'h0000_0000 ),
.m6_sel_i ( 4'b0000 ),
.m6_we_i ( 1'b0 ),
.m6_dat_i ( 32'h0000_0000 ),
.m6_dat_o ( ),
.m6_ack_o ( ),
.m6_err_o ( ),
 
// WISHBONE Initiator 7
.m7_cyc_i ( 1'b0 ),
.m7_stb_i ( 1'b0 ),
.m7_cab_i ( 1'b0 ),
.m7_adr_i ( 32'h0000_0000 ),
.m7_sel_i ( 4'b0000 ),
.m7_we_i ( 1'b0 ),
.m7_dat_i ( 32'h0000_0000 ),
.m7_dat_o ( ),
.m7_ack_o ( ),
.m7_err_o ( ),
 
// WISHBONE Target 0
.s0_cyc_o ( ),
.s0_stb_o ( ),
.s0_cab_o ( ),
.s0_adr_o ( ),
.s0_sel_o ( ),
.s0_we_o ( ),
.s0_dat_o ( ),
.s0_dat_i ( 32'h0000_0000 ),
.s0_ack_i ( 1'b0 ),
.s0_err_i ( 1'b0 ),
.s0_rty_i ( 1'b0 ),
/*
.s0_cyc_o ( wb_mem_cyc_i ),
.s0_stb_o ( wb_mem_stb_i ),
.s0_cab_o ( wb_mem_cab_i ),
.s0_adr_o ( wb_mem_adr_i ),
.s0_sel_o ( wb_mem_sel_i ),
.s0_we_o ( wb_mem_we_i ),
.s0_dat_o ( wb_mem_dat_i ),
.s0_dat_i ( wb_mem_dat_o ),
.s0_ack_i ( wb_mem_ack_o ),
.s0_err_i ( wb_mem_err_o ),
.s0_rty_i ( 1'b0),
*/
 
// WISHBONE Target 1
.s1_cyc_o ( wb_ss_cyc_i ),
.s1_stb_o ( wb_ss_stb_i ),
.s1_cab_o ( wb_ss_cab_i ),
.s1_adr_o ( wb_ss_adr_i ),
.s1_sel_o ( wb_ss_sel_i ),
.s1_we_o ( wb_ss_we_i ),
.s1_dat_o ( wb_ss_dat_i ),
.s1_dat_i ( wb_ss_dat_o ),
.s1_ack_i ( wb_ss_ack_o ),
.s1_err_i ( wb_ss_err_o ),
.s1_rty_i ( 1'b0 ),
// WISHBONE Target 2
.s2_cyc_o ( ),
.s2_stb_o ( ),
.s2_cab_o ( ),
.s2_adr_o ( ),
.s2_sel_o ( ),
.s2_we_o ( ),
.s2_dat_o ( ),
.s2_dat_i ( 32'h0000_0000 ),
.s2_ack_i ( 1'b0 ),
.s2_err_i ( 1'b0 ),
.s2_rty_i ( 1'b0 ),
// WISHBONE Target 3
.s3_cyc_o ( ),
.s3_stb_o ( ),
.s3_cab_o ( ),
.s3_adr_o ( ),
.s3_sel_o ( ),
.s3_we_o ( ),
.s3_dat_o ( ),
.s3_dat_i ( 32'h0000_0000 ),
.s3_ack_i ( 1'b0 ),
.s3_err_i ( 1'b0 ),
.s3_rty_i ( 1'b0),
// WISHBONE Target 4
.s4_cyc_o ( ),
.s4_stb_o ( ),
.s4_cab_o ( ),
.s4_adr_o ( ),
.s4_sel_o ( ),
.s4_we_o ( ),
.s4_dat_o ( ),
.s4_dat_i ( 32'h0000_0000 ),
.s4_ack_i ( 1'b0 ),
.s4_err_i ( 1'b0 ),
.s4_rty_i ( 1'b0),
// WISHBONE Target 5
.s5_cyc_o ( wb_us_cyc_i ),
.s5_stb_o ( wb_us_stb_i ),
.s5_cab_o ( wb_us_cab_i ),
.s5_adr_o ( wb_us_adr_i ),
.s5_sel_o ( wb_us_sel_i ),
.s5_we_o ( wb_us_we_i ),
.s5_dat_o ( wb_us_dat_i ),
.s5_dat_i ( wb_us_dat_o ),
.s5_ack_i ( wb_us_ack_o ),
.s5_err_i ( wb_us_err_o ),
.s5_rty_i ( 1'b0 ),
// WISHBONE Target 6
.s6_cyc_o ( ),
.s6_stb_o ( ),
.s6_cab_o ( ),
.s6_adr_o ( ),
.s6_sel_o ( ),
.s6_we_o ( ),
.s6_dat_o ( ),
.s6_dat_i ( 32'h0000_0000 ),
.s6_ack_i ( 1'b0 ),
.s6_err_i ( 1'b0 ),
.s6_rty_i ( 1'b0),
// WISHBONE Target 7
.s7_cyc_o ( ),
.s7_stb_o ( ),
.s7_cab_o ( ),
.s7_adr_o ( ),
.s7_sel_o ( ),
.s7_we_o ( ),
.s7_dat_o ( ),
.s7_dat_i ( 32'h0000_0000 ),
.s7_ack_i ( 1'b0 ),
.s7_err_i ( 1'b0 ),
.s7_rty_i ( 1'b0)
);
 
//initial begin
// $dumpvars(0);
// $dumpfile("dump.vcd");
//end
 
endmodule
/full_system/xsv_fpga_defines.v
0,0 → 1,103
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1K test app definitions ////
//// ////
//// This file is part of the OR1K test application ////
//// http://www.opencores.org/cores/or1k/xess/ ////
//// ////
//// Description ////
//// DEfine target technology etc. Right now FIFOs are available ////
//// only for Xilinx Virtex FPGAs. (TARGET_VIRTEX) ////
//// ////
//// To Do: ////
//// - nothing really ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, damjan.lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: xsv_fpga_defines.v,v $
// Revision 1.3 2010-01-08 01:41:07 Nathan
// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
//
// Revision 1.2 2008/07/11 08:16:01 Nathan
// Ran through dos2unix
//
// Revision 1.1 2008/07/08 19:11:54 Nathan
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
//
// Revision 1.4 2004/04/05 08:44:35 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2 2002/03/29 20:58:51 lampret
// Changed hardcoded address for fake MC to use a define.
//
// Revision 1.1.1.1 2002/03/21 16:55:44 lampret
// First import of the "new" XESS XSV environment.
//
//
//
 
//
// Define to target to Xilinx Virtex
//
//`define TARGET_VIRTEX
 
//
// Interrupts
//
`define APP_INT_RES1 1:0
`define APP_INT_UART 2
`define APP_INT_RES2 3
`define APP_INT_ETH 4
`define APP_INT_PS2 5
`define APP_INT_RES3 19:6
 
//
// Address map
//
`define APP_ADDR_DEC_W 3
`define APP_ADDR_SDRAM `APP_ADDR_DEC_W'b001
`define APP_ADDR_DEC2_W 8
`define APP_ADDR_OCRAM `APP_ADDR_DEC2_W'h00
`define APP_ADDR_DECP_W 8
//`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h99
`define APP_ADDR_VGA `APP_ADDR_DECP_W'h97
`define APP_ADDR_ETH `APP_ADDR_DECP_W'h92
`define APP_ADDR_AUDIO `APP_ADDR_DECP_W'h9d
`define APP_ADDR_UART `APP_ADDR_DECP_W'h90
`define APP_ADDR_PS2 `APP_ADDR_DECP_W'h94
`define APP_ADDR_RES1 `APP_ADDR_DECP_W'h9e
//`define APP_ADDR_RES2 `APP_ADDR_DECP_W'h9f
//`define APP_ADDR_FAKEMC 4'h6
 
// For simulation...
// `define DBG_IF_MODEL 1
/simulated_system/adv_dbg_tb.v
0,0 → 1,1088
//////////////////////////////////////////////////////////////////////
//// ////
//// adv_dbg_tb.v ////
//// ////
//// ////
//// Testbench for the SoC Advanced Debug Interface. ////
//// ////
//// Author(s): ////
//// Nathan Yawn (nathan.yawn@opencored.org) ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: adv_dbg_tb.v,v $
// Revision 1.7 2010-01-13 00:55:45 Nathan
// Created hi-speed mode for burst reads. This will probably be most beneficial to the OR1K module, as GDB does a burst read of all the GPRs each time a microinstruction is single-stepped.
//
// Revision 1.2 2009/05/17 20:54:55 Nathan
// Changed email address to opencores.org
//
// Revision 1.1 2008/07/08 19:11:55 Nathan
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
//
// Revision 1.11 2008/07/08 18:53:47 Nathan
// Fixed wrong include name.
//
// Revision 1.10 2008/06/30 20:09:19 Nathan
// Removed code to select top-level module as active (it served no purpose). Re-numbered modules, requiring changes to testbench and software driver.
//
 
 
`include "tap_defines.v"
`include "adbg_defines.v"
`include "adbg_wb_defines.v"
`include "wb_model_defines.v"
 
// Polynomial for the CRC calculation
// Yes, it's backwards. Yes, this is on purpose.
// To decrease logic + routing, we want to shift the CRC calculation
// in the same direction we use to shift the data out, LSB first.
`define DBG_CRC_POLY 32'hedb88320
 
// These are indicies into an array which hold values for the JTAG outputs
`define JTAG_TMS 0
`define JTAG_TCK 1
`define JTAG_TDO 2
 
`define JTAG_TMS_bit 3'h1
`define JTAG_TCK_bit 3'h2
`define JTAG_TDO_bit 3'h4
 
`define wait_jtag_period #50
 
 
module adv_debug_tb;
 
// Connections to the JTAG TAP
reg jtag_tck_o;
reg jtag_tms_o;
reg jtag_tdo_o;
wire jtag_tdi_i;
 
// Connections between TAP and debug module
wire capture_dr;
wire shift_dr;
wire pause_dr;
wire update_dr;
wire dbg_rst;
wire dbg_tdi;
wire dbg_tdo;
wire dbg_sel;
 
// Connections between the debug module and the wishbone
`ifdef DBG_WISHBONE_SUPPORTED
wire [31:0] wb_adr;
wire [31:0] wb_dat_m;
wire [31:0] wb_dat_s;
wire wb_cyc;
wire wb_stb;
wire [3:0] wb_sel;
wire wb_we;
wire wb_ack;
wire wb_err;
reg wb_clk_i; // the wishbone clock
reg wb_rst_i;
`endif
 
`ifdef DBG_CPU0_SUPPORTED
wire cpu0_clk;
wire [31:0]cpu0_addr;
wire [31:0] cpu0_data_c;
wire [31:0] cpu0_data_d;
wire cpu0_bp;
wire cpu0_stall;
wire cpu0_stb;
wire cpu0_we;
wire cpu0_ack;
wire cpu0_rst;
`endif
 
`ifdef DBG_CPU1_SUPPORTED
reg cpu1_clk;
wire [31:0]cpu1_addr;
wire [31:0] cpu1_data_c;
wire [31:0] cpu1_data_d;
wire cpu1_bp;
wire cpu1_stall;
wire cpu1_stb;
wire cpu1_we;
wire cpu1_ack;
wire cpu1_rst;
`endif // `ifdef DBG_CPU1_SUPPORTED
reg test_enabled;
 
// Data which will be written to the WB interface
reg [31:0] static_data32 [0:15];
reg [15:0] static_data16 [0:15];
reg [7:0] static_data8 [0:15];
 
// Arrays to hold data read back from the WB interface, for comparison
reg [31:0] input_data32 [0:15];
reg [15:0] input_data16 [0:15];
reg [7:0] input_data8 [0:15];
 
reg [32:0] err_data; // holds the contents of the error register from the various modules
 
reg failed;
integer i;
 
initial
begin
jtag_tck_o = 1'b0;
jtag_tms_o = 1'b0;
jtag_tdo_o = 1'b0;
end
 
// Provide the wishbone clock
`ifdef DBG_WISHBONE_SUPPORTED
initial
begin
wb_clk_i = 1'b0;
forever #7 wb_clk_i = ~wb_clk_i; // Odd frequency ratio to test the synchronization
end
`endif
 
// Provide the CPU0 clock
//`ifdef DBG_CPU0_SUPPORTED
//initial
//begin
//cpu0_clk = 1'b0;
//forever #6 cpu0_clk = ~cpu0_clk; // Odd frequency ratio to test the synchronization
//end
//`endif
 
// Start the test (and reset the wishbone)
initial
begin
test_enabled = 1'b0;
wb_rst_i = 1'b0;
#100;
wb_rst_i = 1'b1;
#100;
wb_rst_i = 1'b0;
 
// Init the memory
initialize_memory(32'h0,32'h16);
// Init the WB model
i_wb.cycle_response(`ACK_RESPONSE, 2, 0); // response type, wait cycles, retry_cycles
 
#1 test_enabled<=#1 1'b1;
end
 
// This is the main test procedure
always @ (posedge test_enabled)
begin
 
$display("Starting advanced debug test");
reset_jtag;
#1000;
check_idcode;
#1000;
// Select the debug module in the IR
set_ir(`DEBUG);
#1000;
///////////////////////////////////////////////////////////////////
// Test CPU0 unit
////////////////////////////////////////////////////////////////////
`ifdef DBG_CPU0_SUPPORTED
// Select the CPU0 unit in the debug module
#1000;
$display("Selecting CPU0 module at time %t", $time);
select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
 
// Test reset, stall bits
#1000;
$display("Testing CPU0 intreg select at time %t", $time);
select_module_internal_register(32'h1, 1); // Really just a read, with discarded data
#1000;
select_module_internal_register(32'h0, 1); // Really just a read, with discarded data
#1000;
// Read the stall and reset bits
$display("Testing reset and stall bits at time %t", $time);
read_module_internal_register(8'd2, err_data); // We assume the register is already selected
$display("Reset and stall bits are %x", err_data);
#1000;
// Set rst/stall bits
$display("Setting reset and stall bits at time %t", $time);
write_module_internal_register(32'h0, 8'h1, 32'h3, 8'h2); // idx, idxlen, data, datalen
#1000;
// Read the bits again
$display("Testing reset and stall bits again at time %t", $time);
read_module_internal_register(8'd2, err_data); // We assume the register is already selected
$display("Reset and stall bits are %x", err_data);
#1000;
// Clear the bits
$display("Clearing reset and stall bits at time %t", $time);
write_module_internal_register(32'h0, 8'h1, 32'h0, 8'h2); // idx, idxlen, data, datalen
#1000;
// Read the bits again
$display("Testing reset and stall bits again at time %t", $time);
read_module_internal_register(8'd2, err_data); // We assume the register is already selected
$display("Reset and stall bits are %x", err_data);
#1000;
// Behavioral CPU model must be stalled in order to do SPR access
//$display("Setting reset and stall bits at time %t", $time);
write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h2); // idx, idxlen, data, datalen
#1000;
// Test SPR bus access
$display("Testing CPU0 32-bit burst write at time %t", $time);
do_module_burst_write(3'h4, 16'd16, 32'h10); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
#1000;
$display("Testing CPU0 32-bit burst read at time %t", $time);
do_module_burst_read(3'h4, 16'd16, 32'h0);
#1000;
 
`endif
 
///////////////////////////////////////////////////////////////////
// Test the Wishbone unit
////////////////////////////////////////////////////////////////////
`ifdef DBG_WISHBONE_SUPPORTED
// Select the WB unit in the debug module
#1000;
$display("Selecting Wishbone module at time %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
/*
// Test error conditions
#1000;
$display("Testing error (size 0 WB burst write) at time %t", $time);
do_module_burst_write(3'h1, 16'h0, 32'h0); // 0-word write = error, ignored
#1000;
$display("Testing error (size 0 WB burst read) at time %t", $time);
do_module_burst_read(3'h1, 16'h0, 32'h0); // 0-word read = error, ignored
// Test NOP (a zero in the MSB, then a NOP opcode)
#1000;
$display("Testing NOP at time %t", $time);
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream(5'h0, 8'h5, 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
#1000;
*/
/*
#1000;
$display("Testing WB intreg select at time %t", $time);
select_module_internal_register(32'h1, 1); // Really just a read, with discarded data
#1000;
select_module_internal_register(32'h0, 1); // Really just a read, with discarded data
#1000;
// Reset the error bit
write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h1); // idx, idxlen, data, datalen
#1000;
// Read the error bit
read_module_internal_register(8'd33, err_data); // We assume the register is already selected
#1000;
*/
/////////////////////////////////
// Test 8-bit WB access
failed = 0;
$display("Testing WB 8-bit burst write at time %t: resetting ", $time);
do_module_burst_write(3'h1, 16'd16, 32'h0); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
#1000;
$display("Testing WB 8-bit burst read at time %t", $time);
do_module_burst_read(3'h1, 16'd16, 32'h0);
#1000;
for(i = 0; i < 16; i = i+1) begin
if(static_data8[i] != input_data8[i]) begin
failed = 1;
$display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data8[i], input_data8[i]);
end
end
if(!failed) $display("8-bit read/write OK!");
/* try it unaligned
do_module_burst_write(3'h1, 16'd5, 32'h3); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
#1000;
do_module_burst_read(3'h1, 16'd4, 32'h4);
#1000;
*/
/////////////////////////////////
// Test 16-bit WB access
failed = 0;
$display("Testing WB 16-bit burst write at time %t", $time);
do_module_burst_write(3'h2, 16'd16, 32'h0); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
#1000;
$display("Testing WB 16-bit burst read at time %t", $time);
do_module_burst_read(3'h2, 16'd16, 32'h0);
#1000;
for(i = 0; i < 16; i = i+1) begin
if(static_data16[i] != input_data16[i]) begin
failed = 1;
$display("16-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data16[i], input_data16[i]);
end
end
if(!failed) $display("16-bit read/write OK!");
/* try it unaligned
do_module_burst_write(3'h2, 16'd5, 32'h2); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
#1000;
do_module_burst_read(3'h2, 16'd4, 32'h4);
#1000;
*/
////////////////////////////////////
// Test 32-bit WB access
failed = 0;
$display("Testing WB 32-bit burst write at time %t", $time);
do_module_burst_write(3'h4, 16'd16, 32'h0); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
#1000;
$display("Testing WB 32-bit burst read at time %t", $time);
do_module_burst_read(3'h4, 16'd16, 32'h0);
#1000;
for(i = 0; i < 16; i = i+1) begin
if(static_data32[i] != input_data32[i]) begin
failed = 1;
$display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data32[i], input_data32[i]);
end
end
if(!failed) $display("32-bit read/write OK!");
/* Try another address
do_module_burst_write(3'h4, 16'd16, 32'h200); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
#1000;
do_module_burst_read(3'h4, 16'd15, 32'h204);
#1000;
*/
////////////////////////////////
// Test error register
err_data = 33'h0;
// Select and reset the error register
write_module_internal_register(`DBG_WB_INTREG_ERROR, `DBG_WB_REGSELECT_SIZE, 64'h1, 8'h1); // regidx,idxlen,writedata, datalen;
i_wb.cycle_response(`ERR_RESPONSE, 2, 0); // response type, wait cycles, retry_cycles
do_module_burst_write(3'h4, 16'd4, 32'hdeaddead); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
read_module_internal_register(8'd33, err_data); // get the error register
$display("Error bit is %d, error address is %x", err_data[0], err_data>>1);
 
`endif // WB module supported
end
 
task initialize_memory;
input [31:0] start_addr;
input [31:0] length;
integer i;
reg [31:0] addr;
begin
 
for (i=0; i<length; i=i+1)
begin
static_data32[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
static_data16[i] <= {i[7:0], i[7:0]+ 2'd1};
static_data8[i] <= i[7:0];
end
end
endtask
 
///////////////////////////////////////////////////////////////////////////////
// Declaration and interconnection of components
 
// Top module
tap_top i_tap (
// JTAG pads
.tms_pad_i(jtag_tms_o),
.tck_pad_i(jtag_tck_o),
.trstn_pad_i(1'b1),
.tdi_pad_i(jtag_tdo_o),
.tdo_pad_o(jtag_tdi_i),
.tdo_padoe_o(),
 
// TAP states
.test_logic_reset_o(dbg_rst),
.run_test_idle_o(),
.shift_dr_o(shift_dr),
.pause_dr_o(pause_dr),
.update_dr_o(update_dr),
.capture_dr_o(capture_dr),
// Select signals for boundary scan or mbist
.extest_select_o(),
.sample_preload_select_o(),
.mbist_select_o(),
.debug_select_o(dbg_sel),
// TDO signal that is connected to TDI of sub-modules.
.tdi_o(dbg_tdo),
// TDI signals from sub-modules
.debug_tdo_i(dbg_tdi), // from debug module
.bs_chain_tdo_i(1'b0), // from Boundary Scan Chain
.mbist_tdo_i(1'b0) // from Mbist Chain
);
 
 
// Top module
adbg_top i_dbg_module(
// JTAG signals
.tck_i(jtag_tck_o),
.tdi_i(dbg_tdo),
.tdo_o(dbg_tdi),
.rst_i(dbg_rst),
 
// TAP states
.shift_dr_i(shift_dr),
.pause_dr_i(pause_dr),
.update_dr_i(update_dr),
.capture_dr_i(capture_dr),
 
// Instructions
.debug_select_i(dbg_sel)
 
 
`ifdef DBG_WISHBONE_SUPPORTED
// WISHBONE common signals
,
.wb_clk_i(wb_clk_i),
// WISHBONE master interface
.wb_adr_o(wb_adr),
.wb_dat_o(wb_dat_m),
.wb_dat_i(wb_dat_s),
.wb_cyc_o(wb_cyc),
.wb_stb_o(wb_stb),
.wb_sel_o(wb_sel),
.wb_we_o(wb_we),
.wb_ack_i(wb_ack),
.wb_cab_o(),
.wb_err_i(wb_err),
.wb_cti_o(),
.wb_bte_o()
`endif
 
`ifdef DBG_CPU0_SUPPORTED
// CPU signals
,
.cpu0_clk_i(cpu0_clk),
.cpu0_addr_o(cpu0_addr),
.cpu0_data_i(cpu0_data_c),
.cpu0_data_o(cpu0_data_d),
.cpu0_bp_i(cpu0_bp),
.cpu0_stall_o(cpu0_stall),
.cpu0_stb_o(cpu0_stb),
.cpu0_we_o(cpu0_we),
.cpu0_ack_i(cpu0_ack),
.cpu0_rst_o(cpu0_rst)
`endif
 
`ifdef DBG_CPU1_SUPPORTED
// CPU signals
,
.cpu1_clk_i(cpu1_clk),
.cpu1_addr_o(cpu1_addr),
.cpu1_data_i(cpu1_data_c),
.cpu1_data_o(cpu1_data_d),
.cpu1_bp_i(cpu1_bp),
.cpu1_stall_o(cpu1_stall),
.cpu1_stb_o(cpu1_stb),
.cpu1_we_o(cpu1_we),
.cpu1_ack_i(cpu1_ack),
.cpu1_rst_o(cpu1_rst)
`endif
 
);
 
 
`ifdef DBG_WISHBONE_SUPPORTED
// The 'wishbone' may be just a p2p connection to a simple RAM
/*
onchip_ram_top i_ocram (
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wb_dat_i(wb_dat_m),
.wb_dat_o(wb_dat_s),
.wb_adr_i(wb_adr[11:0]),
.wb_sel_i(wb_sel),
.wb_we_i(wb_we),
.wb_cyc_i(wb_cyc),
.wb_stb_i(wb_stb),
.wb_ack_o(wb_ack),
.wb_err_o(wb_err)
);
*/
 
wb_slave_behavioral i_wb
(
.CLK_I(wb_clk_i),
.RST_I(wb_rst_i),
.ACK_O(wb_ack),
.ADR_I(wb_adr),
.CYC_I(wb_cyc),
.DAT_O(wb_dat_s),
.DAT_I(wb_dat_m),
.ERR_O(wb_err),
.RTY_O(),
.SEL_I(wb_sel),
.STB_I(wb_stb),
.WE_I(wb_we),
.CAB_I(1'b0)
);
`endif
 
 
`ifdef DBG_CPU0_SUPPORTED
// Instantiate a behavioral model of the CPU SPR bus
cpu_behavioral cpu0_i (
.cpu_rst_i(cpu0_rst),
.cpu_clk_o(cpu0_clk),
.cpu_addr_i(cpu0_addr),
.cpu_data_o(cpu0_data_c),
.cpu_data_i(cpu0_data_d),
.cpu_bp_o(cpu0_bp),
.cpu_stall_i(cpu0_stall),
.cpu_stb_i(cpu0_stb),
.cpu_we_i(cpu0_we),
.cpu_ack_o(cpu0_ack),
.cpu_rst_o(cpu0_rst)
);
 
`endif
 
 
`ifdef DBG_CPU1_SUPPORTED
// Instantiate a behavioral model of the CPU SPR bus
cpu_behavioral cpu1_i (
.cpu_rst_i(cpu1_rst),
.cpu_clk_o(cpu1_clk),
.cpu_addr_i(cpu1_addr),
.cpu_data_o(cpu1_data_c),
.cpu_data_i(cpu1_data_d),
.cpu_bp_o(cpu1_bp),
.cpu_stall_i(cpu1_stall),
.cpu_stb_i(cpu1_stb),
.cpu_we_i(cpu1_we),
.cpu_ack_o(cpu1_ack),
.cpu_rst_o(cpu1_rst)
);
`endif
///////////////////////////////////////////////////////////////////////////
// Higher-level chain manipulation functions
 
// calculate the CRC, up to 32 bits at a time
task compute_crc;
input [31:0] crc_in;
input [31:0] data_in;
input [5:0] length_bits;
output [31:0] crc_out;
integer i;
reg [31:0] d;
reg [31:0] c;
begin
crc_out = crc_in;
for(i = 0; i < length_bits; i = i+1) begin
d = (data_in[i]) ? 32'hffffffff : 32'h0;
c = (crc_out[0]) ? 32'hffffffff : 32'h0;
//crc_out = {crc_out[30:0], 1'b0}; // original
crc_out = crc_out >> 1;
crc_out = crc_out ^ ((d ^ c) & `DBG_CRC_POLY);
//$display("CRC Itr %d, inbit = %d, crc = 0x%x", i, data_in[i], crc_out);
end
end
endtask
 
task check_idcode;
reg [63:0] readdata;
reg[31:0] idcode;
begin
set_ir(`IDCODE);
// Read the IDCODE in the DR
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_read_write_stream(64'h0, 8'd32, 1, readdata); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
idcode = readdata[31:0];
$display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);
end
endtask;
 
task select_debug_module;
input [1:0] moduleid;
reg validid;
begin
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream({1'b1,moduleid}, 8'h3, 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
$display("Selecting module (%0x)", moduleid);
// Read back the status to make sure a valid chain is selected
/* Pointless, the newly selected module would respond instead...
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
read_write_bit(`JTAG_TMS_bit, validid); // get data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
if(validid) $display("Selected valid module (%0x)", moduleid);
else $display("Failed to select module (%0x)", moduleid);
*/
end
endtask
 
 
task send_module_burst_command;
input [3:0] opcode;
input [31:0] address;
input [15:0] burstlength;
reg [63:0] streamdata;
begin
streamdata = {11'h0,1'b0,opcode,address,burstlength};
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream(streamdata, 8'd53, 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
end
endtask
 
task select_module_internal_register; // Really just a read, with discarded data
input [31:0] regidx;
input [7:0] len; // the length of the register index data, we assume not more than 32
reg[63:0] streamdata;
begin
streamdata = 64'h0;
streamdata = streamdata | regidx;
streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream(streamdata, (len+5), 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
end
endtask
 
task read_module_internal_register; // We assume the register is already selected
//input [31:0] regidx;
input [7:0] len; // the length of the data desired, we assume a max of 64 bits
output [63:0] instream;
reg [63:0] bitmask;
begin
instream = 64'h0;
// We shift out all 0's, which is a NOP to the debug unit
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
// Shift at least 5 bits, as this is the min, for a valid NOP
jtag_read_write_stream(64'h0, len+4,1,instream); // exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
bitmask = 64'hffffffffffffffff;
bitmask = bitmask << len;
bitmask = ~bitmask;
instream = instream & bitmask; // Cut off any unwanted excess bits
end
endtask
 
task write_module_internal_register;
input [31:0] regidx; // the length of the register index data
input [7:0] idxlen;
input [63:0] writedata;
input [7:0] datalen; // the length of the data to write. We assume the two length combined are 59 or less.
reg[63:0] streamdata;
begin
streamdata = 64'h0; // This will 0 the toplevel/module select bit
streamdata = streamdata | writedata;
streamdata = streamdata | (regidx << datalen);
streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream(streamdata, (idxlen+datalen+5), 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
end
endtask
 
// This includes the sending of the burst command
task do_module_burst_read;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] instream;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o; // temp signal...
reg [31:0] crc_read;
reg [5:0] word_size_bits;
begin
$display("Doing burst read, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
instream = 64'h0;
word_size_bits = word_size_bytes << 3;
crc_calc_i = 32'hffffffff;
// Send the command
case (word_size_bytes)
3'h1: opcode = `DBG_WB_CMD_BREAD8;
3'h2: opcode = `DBG_WB_CMD_BREAD16;
3'h4: opcode = `DBG_WB_CMD_BREAD32;
default:
begin
$display("Tried burst read with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
opcode = `DBG_WB_CMD_BREAD32;
end
endcase
send_module_burst_command(opcode,start_address, word_count); // returns to state idle
// Get us back to shift_dr mode to read a burst
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
 
`ifdef ADBG_USE_HISPEED
// Get 1 status bit, then word_size_bytes*8 bits
status = 1'b0;
j = 0;
while(!status) begin
read_write_bit(3'h0, status);
j = j + 1;
end
if(j > 1) begin
$display("Took %0d tries before good status bit during burst read", j);
end
`endif
// Now, repeat...
for(i = 0; i < word_count; i=i+1) begin
`ifndef ADBG_USE_HISPEED
// Get 1 status bit, then word_size_bytes*8 bits
status = 1'b0;
j = 0;
while(!status) begin
read_write_bit(3'h0, status);
j = j + 1;
end
if(j > 1) begin
$display("Took %0d tries before good status bit during burst read", j);
end
`endif
jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream);
//$display("Read 0x%0x", instream[31:0]);
compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o);
crc_calc_i = crc_calc_o;
if(word_size_bytes == 1) input_data8[i] = instream[7:0];
else if(word_size_bytes == 2) input_data16[i] = instream[15:0];
else input_data32[i] = instream[31:0];
end
// Read the data CRC from the debug module.
jtag_read_write_stream(64'h0, 6'd32, 1, crc_read);
if(crc_calc_o != crc_read) $display("CRC ERROR! Computed 0x%x, read CRC 0x%x", crc_calc_o, crc_read);
else $display("CRC OK!");
// Finally, shift out 5 0's, to make the next command a NOP
// Not necessary, debug unit won't latch a new opcode at the end of a burst
//jtag_write_stream(64'h0, 8'h5, 1);
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
end
endtask
 
 
task do_module_burst_write;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] dataword;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o;
reg crc_match;
reg [5:0] word_size_bits;
begin
$display("Doing burst write, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
word_size_bits = word_size_bytes << 3;
crc_calc_i = 32'hffffffff;
// Send the command
case (word_size_bytes)
3'h1: opcode = `DBG_WB_CMD_BWRITE8;
3'h2: opcode = `DBG_WB_CMD_BWRITE16;
3'h4: opcode = `DBG_WB_CMD_BWRITE32;
default:
begin
$display("Tried burst write with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
opcode = `DBG_WB_CMD_BWRITE32;
end
endcase
send_module_burst_command(opcode, start_address, word_count); // returns to state idle
// Get us back to shift_dr mode to write a burst
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
 
// Write a start bit (a 1) so it knows when to start counting
write_bit(`JTAG_TDO_bit);
 
// Now, repeat...
for(i = 0; i < word_count; i=i+1) begin
// Write word_size_bytes*8 bits, then get 1 status bit
if(word_size_bytes == 4) dataword = {32'h0, static_data32[i]};
else if(word_size_bytes == 2) dataword = {48'h0, static_data16[i]};
else dataword = {56'h0, static_data8[i]};
jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0);
compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o);
crc_calc_i = crc_calc_o;
`ifndef ADBG_USE_HISPEED
// Check if WB bus is ready
// *** THIS WILL NOT WORK IF THERE IS MORE THAN 1 DEVICE IN THE JTAG CHAIN!!!
status = 1'b0;
read_write_bit(3'h0, status);
if(!status) begin
$display("Bad status bit during burst write, index %d", i);
end
`endif
//$display("Wrote 0x%0x", dataword);
end
// Send the CRC we computed
jtag_write_stream(crc_calc_o, 6'd32,0);
// Read the 'CRC match' bit, and go to exit1_dr
read_write_bit(`JTAG_TMS_bit, crc_match);
if(!crc_match) $display("CRC ERROR! match bit after write is %d (computed CRC 0x%x)", crc_match, crc_calc_o);
else $display("CRC OK!");
// Finally, shift out 5 0's, to make the next command a NOP
// Not necessary, module will not latch new opcode during burst
//jtag_write_stream(64'h0, 8'h5, 1);
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
end
 
endtask
 
 
// Puts a value in the TAP IR, assuming we start in IDLE state.
// Returns to IDLE state when finished
task set_ir;
input [3:0] irval;
begin
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(`JTAG_TMS_bit); // select_ir_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream({60'h0,irval}, 8'h4, 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
end
endtask
 
// Resets the TAP and puts it into idle mode
task reset_jtag;
integer i;
begin
for(i = 0; i < 8; i=i+1) begin
write_bit(`JTAG_TMS_bit); // 5 TMS should put us in test_logic_reset mode
end
write_bit(3'h0); // idle
end
endtask
 
 
////////////////////////////////////////////////////////////////////////////
// Tasks to write or read-write a string of data
 
task jtag_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
integer i;
integer databit;
reg [2:0] bits;
begin
for(i = 0; i < (len-1); i=i+1) begin
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
write_bit(bits);
end
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
write_bit(bits);
end
endtask
 
 
task jtag_read_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
output [63:0] instream;
integer i;
integer databit;
reg [2:0] bits;
reg inbit;
begin
instream = 64'h0;
for(i = 0; i < (len-1); i=i+1) begin
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
read_write_bit(bits, inbit);
instream = (instream | (inbit << i));
end
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
read_write_bit(bits, inbit);
instream = (instream | (inbit << (len-1)));
end
endtask
 
/////////////////////////////////////////////////////////////////////////
// Tasks which write or readwrite a single bit (including clocking)
 
task write_bit;
input [2:0] bitvals;
begin
// Set data
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
// Raise clock
jtag_out(bitvals | `JTAG_TCK_bit);
`wait_jtag_period;
// drop clock (making output available in the SHIFT_xR states)
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
end
endtask
 
task read_write_bit;
input [2:0] bitvals;
output l_tdi_val;
begin
// read bit state
l_tdi_val <= jtag_tdi_i;
// Set data
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
// Raise clock
jtag_out(bitvals | `JTAG_TCK_bit);
`wait_jtag_period;
// drop clock (making output available in the SHIFT_xR states)
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
end
endtask
 
/////////////////////////////////////////////////////////////////
// Basic functions to set the state of the JTAG TAP I/F bits
 
task jtag_out;
input [2:0] bitvals;
begin
 
jtag_tck_o <= bitvals[`JTAG_TCK];
jtag_tms_o <= bitvals[`JTAG_TMS];
jtag_tdo_o <= bitvals[`JTAG_TDO];
end
endtask
 
 
task jtag_inout;
input [2:0] bitvals;
output l_tdi_val;
begin
 
jtag_tck_o <= bitvals[`JTAG_TCK];
jtag_tms_o <= bitvals[`JTAG_TMS];
jtag_tdo_o <= bitvals[`JTAG_TDO];
 
l_tdi_val <= jtag_tdi_i;
end
endtask
 
endmodule
/simulated_system/wb_slave_behavioral.v
0,0 → 1,428
//////////////////////////////////////////////////////////////////////
//// ////
//// wb_slave_behavioral.v ////
//// ////
//// ////
//// This file is part of the SoC Debug Interface. ////
//// http://www.opencores.org/projects/DebugInterface/ ////
//// ////
//// Author(s): ////
//// Tadej Markovic, tadej@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: wb_slave_behavioral.v,v $
// Revision 1.2 2010-01-08 01:41:08 Nathan
// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
//
// Revision 1.1 2008/07/08 19:11:57 Nathan
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
//
// Revision 1.2 2008/06/26 20:54:44 Nathan
// Testbench modified to use WB behavioral model instead of an onchip_ram. Added test of WB error register.
//
// Revision 1.1 2008/06/18 18:34:49 Nathan
// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.
//
// Revision 1.1.1.1 2008/05/14 12:07:36 Nathan
// Original from OpenCores
//
// Revision 1.3 2004/03/28 20:27:40 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.2 2004/01/15 10:47:13 mohor
// Working.
//
// Revision 1.1 2003/12/23 14:26:01 mohor
// New version of the debug interface. Not finished, yet.
//
//
//
//
 
//`include "timescale.v"
`include "wb_model_defines.v"
module wb_slave_behavioral
(
CLK_I,
RST_I,
ACK_O,
ADR_I,
CYC_I,
DAT_O,
DAT_I,
ERR_O,
RTY_O,
SEL_I,
STB_I,
WE_I,
CAB_I
);
 
/*------------------------------------------------------------------------------------------------------
WISHBONE signals
------------------------------------------------------------------------------------------------------*/
input CLK_I;
input RST_I;
output ACK_O;
input `WB_ADDR_TYPE ADR_I;
input CYC_I;
output `WB_DATA_TYPE DAT_O;
input `WB_DATA_TYPE DAT_I;
output ERR_O;
output RTY_O;
input `WB_SEL_TYPE SEL_I;
input STB_I;
input WE_I;
input CAB_I;
 
reg `WB_DATA_TYPE DAT_O;
 
/*------------------------------------------------------------------------------------------------------
Asynchronous dual-port RAM signals for storing and fetching the data
------------------------------------------------------------------------------------------------------*/
//reg `WB_DATA_TYPE wb_memory [0:16777215]; // WB memory - 24 addresses connected - 2 LSB not used
reg `WB_DATA_TYPE wb_memory [0:1048575]; // WB memory - 20 addresses connected - 2 LSB not used
reg `WB_DATA_TYPE mem_wr_data_out;
reg `WB_DATA_TYPE mem_rd_data_in;
 
/*------------------------------------------------------------------------------------------------------
Maximum values for WAIT and RETRY counters and which response !!!
------------------------------------------------------------------------------------------------------*/
reg [2:0] a_e_r_resp; // tells with which cycle_termination_signal must wb_slave respond !
reg [8:0] wait_cyc;
reg [7:0] max_retry;
 
// assign registers to default state while in reset
// always@(RST_I)
// begin
// if (RST_I)
// begin
// a_e_r_resp <= 3'b000; // do not respond
// wait_cyc <= 8'b0; // no wait cycles
// max_retry <= 8'h0; // no retries
// end
// end //reset
 
task cycle_response;
input [2:0] ack_err_rty_resp; // acknowledge, error or retry response input flags
input [8:0] wait_cycles; // if wait cycles before each data termination cycle (ack, err or rty)
input [7:0] retry_cycles; // noumber of retry cycles before acknowledge cycle
begin
// assign values
a_e_r_resp <= #1 ack_err_rty_resp;
wait_cyc <= #1 wait_cycles;
max_retry <= #1 retry_cycles;
end
endtask // cycle_response
 
/*------------------------------------------------------------------------------------------------------
Tasks for writing and reading to and from memory !!!
------------------------------------------------------------------------------------------------------*/
reg `WB_ADDR_TYPE task_wr_adr_i;
reg `WB_ADDR_TYPE task_rd_adr_i;
reg `WB_DATA_TYPE task_dat_i;
reg `WB_DATA_TYPE task_dat_o;
reg `WB_SEL_TYPE task_sel_i;
reg task_wr_data;
reg task_data_written;
reg `WB_DATA_TYPE task_mem_wr_data;
 
// write to memory
task wr_mem;
input `WB_ADDR_TYPE adr_i;
input `WB_DATA_TYPE dat_i;
input `WB_SEL_TYPE sel_i;
begin
task_data_written = 0;
task_wr_adr_i = adr_i;
task_dat_i = dat_i;
task_sel_i = sel_i;
task_wr_data = 1;
wait(task_data_written);
task_wr_data = 0;
end
endtask
 
// read from memory
task rd_mem;
input `WB_ADDR_TYPE adr_i;
output `WB_DATA_TYPE dat_o;
input `WB_SEL_TYPE sel_i;
begin
task_rd_adr_i = adr_i;
task_sel_i = sel_i;
#1;
dat_o = task_dat_o;
end
endtask
 
/*------------------------------------------------------------------------------------------------------
Internal signals and logic
------------------------------------------------------------------------------------------------------*/
reg calc_ack;
reg calc_err;
reg calc_rty;
 
reg [7:0] retry_cnt;
reg [7:0] retry_num;
reg retry_expired;
 
// Retry counter
always@(posedge RST_I or posedge CLK_I)
begin
if (RST_I)
retry_cnt <= #1 8'h00;
else
begin
if (calc_ack || calc_err)
retry_cnt <= #1 8'h00;
else if (calc_rty)
retry_cnt <= #1 retry_num;
end
end
 
always@(retry_cnt or max_retry)
begin
if (retry_cnt < max_retry)
begin
retry_num = retry_cnt + 1'b1;
retry_expired = 1'b0;
end
else
begin
retry_num = retry_cnt;
retry_expired = 1'b1;
end
end
 
reg [8:0] wait_cnt;
reg [8:0] wait_num;
reg wait_expired;
 
// Wait counter
always@(posedge RST_I or posedge CLK_I)
begin
if (RST_I)
wait_cnt <= #1 9'h0;
else
begin
if (wait_expired || ~STB_I)
wait_cnt <= #1 9'h0;
else
wait_cnt <= #1 wait_num;
end
end
 
always@(wait_cnt or wait_cyc or STB_I or a_e_r_resp or retry_expired)
begin
if ((wait_cyc > 0) && (STB_I))
begin
if (wait_cnt < wait_cyc)
begin
wait_num = wait_cnt + 1'b1;
wait_expired = 1'b0;
calc_ack = 1'b0;
calc_err = 1'b0;
calc_rty = 1'b0;
end
else
begin
wait_num = wait_cnt;
wait_expired = 1'b1;
if (a_e_r_resp == 3'b100)
begin
calc_ack = 1'b1;
calc_err = 1'b0;
calc_rty = 1'b0;
end
else
if (a_e_r_resp == 3'b010)
begin
calc_ack = 1'b0;
calc_err = 1'b1;
calc_rty = 1'b0;
end
else
if (a_e_r_resp == 3'b001)
begin
calc_err = 1'b0;
if (retry_expired)
begin
calc_ack = 1'b1;
calc_rty = 1'b0;
end
else
begin
calc_ack = 1'b0;
calc_rty = 1'b1;
end
end
else
begin
calc_ack = 1'b0;
calc_err = 1'b0;
calc_rty = 1'b0;
end
end
end
else
if ((wait_cyc == 0) && (STB_I))
begin
wait_num = 9'h0;
wait_expired = 1'b1;
if (a_e_r_resp == 3'b100)
begin
calc_ack = 1'b1;
calc_err = 1'b0;
calc_rty = 1'b0;
end
else if (a_e_r_resp == 3'b010)
begin
calc_ack = 1'b0;
calc_err = 1'b1;
calc_rty = 1'b0;
end
else if (a_e_r_resp == 3'b001)
begin
calc_err = 1'b0;
if (retry_expired)
begin
calc_ack = 1'b1;
calc_rty = 1'b0;
end
else
begin
calc_ack = 1'b0;
calc_rty = 1'b1;
end
end
else
begin
calc_ack = 1'b0;
calc_err = 1'b0;
calc_rty = 1'b0;
end
end
else
begin
wait_num = 9'h0;
wait_expired = 1'b0;
calc_ack = 1'b0;
calc_err = 1'b0;
calc_rty = 1'b0;
end
end
 
wire rd_sel = (CYC_I && STB_I && ~WE_I);
wire wr_sel = (CYC_I && STB_I && WE_I);
 
// Generate cycle termination signals
assign ACK_O = calc_ack && STB_I;
assign ERR_O = calc_err && STB_I;
assign RTY_O = calc_rty && STB_I;
 
// Assign address to asynchronous memory
always@(RST_I or ADR_I)
begin
if (RST_I) // this is added because at start of test bench we need address change in order to get data!
begin
#1 mem_rd_data_in = `WB_DATA_WIDTH'hxxxx_xxxx;
end
else
begin
// #1 mem_rd_data_in = wb_memory[ADR_I[25:2]];
#1 mem_rd_data_in = wb_memory[ADR_I[21:2]];
end
end
 
// Data input/output interface
always@(rd_sel or mem_rd_data_in or RST_I)
begin
if (RST_I)
DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx; // assign outputs to unknown state while in reset
else if (rd_sel)
DAT_O <=#1 mem_rd_data_in;
else
DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx;
end
 
 
always@(RST_I or task_rd_adr_i)
begin
if (RST_I)
task_dat_o = `WB_DATA_WIDTH'hxxxx_xxxx;
else
task_dat_o = wb_memory[task_rd_adr_i[21:2]];
end
always@(CLK_I or wr_sel or task_wr_data or ADR_I or task_wr_adr_i or
mem_wr_data_out or DAT_I or task_mem_wr_data or task_dat_i or
SEL_I or task_sel_i)
begin
if (task_wr_data)
begin
task_mem_wr_data = wb_memory[task_wr_adr_i[21:2]];
 
if (task_sel_i[3])
task_mem_wr_data[31:24] = task_dat_i[31:24];
if (task_sel_i[2])
task_mem_wr_data[23:16] = task_dat_i[23:16];
if (task_sel_i[1])
task_mem_wr_data[15: 8] = task_dat_i[15: 8];
if (task_sel_i[0])
task_mem_wr_data[ 7: 0] = task_dat_i[ 7: 0];
 
wb_memory[task_wr_adr_i[21:2]] = task_mem_wr_data; // write data
task_data_written = 1;
end
else if (wr_sel && CLK_I)
begin
// mem_wr_data_out = wb_memory[ADR_I[25:2]]; // if no SEL_I is active, old value will be written
mem_wr_data_out = wb_memory[ADR_I[21:2]]; // if no SEL_I is active, old value will be written
 
if (SEL_I[3])
mem_wr_data_out[31:24] = DAT_I[31:24];
if (SEL_I[2])
mem_wr_data_out[23:16] = DAT_I[23:16];
if (SEL_I[1])
mem_wr_data_out[15: 8] = DAT_I[15: 8];
if (SEL_I[0])
mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0];
 
// wb_memory[ADR_I[25:2]] <= mem_wr_data_out; // write data
wb_memory[ADR_I[21:2]] = mem_wr_data_out; // write data
end
end
 
endmodule
/simulated_system/wave.do
0,0 → 1,333
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {JTAG top}
add wave -noupdate -format Logic /adv_debug_tb/jtag_tck_o
add wave -noupdate -format Logic /adv_debug_tb/jtag_tms_o
add wave -noupdate -format Logic /adv_debug_tb/jtag_tdo_o
add wave -noupdate -format Logic /adv_debug_tb/jtag_tdi_i
add wave -noupdate -divider {TAP signals}
add wave -noupdate -format Logic /adv_debug_tb/dbg_rst
add wave -noupdate -format Logic /adv_debug_tb/capture_dr
add wave -noupdate -format Logic /adv_debug_tb/shift_dr
add wave -noupdate -format Logic /adv_debug_tb/pause_dr
add wave -noupdate -format Logic /adv_debug_tb/update_dr
add wave -noupdate -format Logic /adv_debug_tb/dbg_sel
add wave -noupdate -format Logic /adv_debug_tb/dbg_tdi
add wave -noupdate -format Logic /adv_debug_tb/dbg_tdo
add wave -noupdate -divider {Wishbone signals}
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/wb_adr
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/wb_dat_m
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/wb_dat_s
add wave -noupdate -format Logic /adv_debug_tb/wb_cyc
add wave -noupdate -format Logic /adv_debug_tb/wb_stb
add wave -noupdate -format Literal /adv_debug_tb/wb_sel
add wave -noupdate -format Logic /adv_debug_tb/wb_we
add wave -noupdate -format Logic /adv_debug_tb/wb_ack
add wave -noupdate -format Logic /adv_debug_tb/wb_err
add wave -noupdate -format Logic /adv_debug_tb/wb_clk_i
add wave -noupdate -format Logic /adv_debug_tb/wb_rst_i
add wave -noupdate -divider {CPU0 signals}
add wave -noupdate -format Logic /adv_debug_tb/cpu0_clk
add wave -noupdate -format Logic /adv_debug_tb/cpu0_rst
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/cpu0_addr
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/cpu0_data_c
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/cpu0_data_d
add wave -noupdate -format Logic /adv_debug_tb/cpu0_we
add wave -noupdate -format Logic /adv_debug_tb/cpu0_stb
add wave -noupdate -format Logic /adv_debug_tb/cpu0_ack
add wave -noupdate -format Logic /adv_debug_tb/cpu0_bp
add wave -noupdate -format Logic /adv_debug_tb/cpu0_stall
add wave -noupdate -divider {Debug top internals}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tck_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdi_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/rst_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/shift_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/pause_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/update_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/capture_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/debug_select_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_clk_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_adr_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_dat_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_dat_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_cyc_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_stb_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_sel_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_we_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_ack_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_cab_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_err_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_cti_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_bte_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_clk_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/cpu0_addr_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/cpu0_data_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/cpu0_data_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_bp_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_stall_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_stb_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_we_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_ack_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_rst_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/input_shift_reg
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/module_id_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/select_cmd
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/module_id_in
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/module_selects
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_wb
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_cpu0
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_cpu1
add wave -noupdate -divider {DBG Wishbone module internals}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/tck_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/module_tdo_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/tdi_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/capture_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/shift_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/update_dr_i
add wave -noupdate -format Literal -radix binary /adv_debug_tb/i_dbg_module/i_dbg_wb/data_register_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/module_select_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/rst_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_clk_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_adr_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_dat_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_dat_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_cyc_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_stb_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_sel_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_we_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_ack_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_cab_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_err_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_cti_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_bte_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/address_counter
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_count
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_wb/word_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/operation
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_out_shift_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/internal_register_select
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/internal_reg_error
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/addr_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/addr_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/op_reg_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_ct_rst
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/word_ct_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/word_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/out_reg_ld_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/out_reg_shift_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/out_reg_data_sel
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/tdo_output_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_strobe
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_clr
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_in_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_shift_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/regsel_ld_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/intreg_ld_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/error_reg_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_clr_err
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/word_count_zero
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_count_max
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/module_cmd
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_ready
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_err
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/burst_instruction
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/intreg_instruction
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/intreg_write
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/rd_op
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_match
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_count_32
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_wb/word_size_bits
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_wb/word_size_bytes
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/incremented_address
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_to_addr_counter
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_to_word_counter
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_wb/decremented_word_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/address_data_in
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_wb/count_data_in
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/operation_in
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_to_biu
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_from_biu
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_data_out
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_data_in
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_serial_out
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/reg_select_data
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/out_reg_data
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_from_internal_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_rst
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/module_state
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/module_next_state
add wave -noupdate -divider {DBG WB module BIU internals}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/tck_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rst_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/data_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/data_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/addr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/strobe_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rd_wrn_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/err_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/word_size_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_clk_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_adr_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_dat_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_dat_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_cyc_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_stb_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_sel_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_we_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_ack_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_cab_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_err_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_cti_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_bte_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/sel_reg
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/addr_reg
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/data_in_reg
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/data_out_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wr_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/str_sync
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_sync
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/err_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_sync_tff1
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_sync_tff2
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_sync_tff2q
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/str_sync_wbff1
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/str_sync_wbff2
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/str_sync_wbff2q
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/data_o_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_sync_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/err_en
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/be_dec
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/start_toggle
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/swapped_data_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/swapped_data_out
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_fsm_state
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/next_fsm_state
add wave -noupdate -divider {DBG CPU0 module signals}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/tck_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/module_tdo_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/tdi_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/capture_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/shift_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/update_dr_i
add wave -noupdate -format Literal -radix binary /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_register_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/module_select_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/rst_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_clk_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_addr_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_data_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_data_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_stb_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_we_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_ack_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_rst_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_bp_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_stall_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/address_counter
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/bit_count
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/word_count
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/operation
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_out_shift_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/internal_register_select
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/internal_reg_status
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/addr_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/addr_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/op_reg_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/bit_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/bit_ct_rst
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/word_ct_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/word_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/out_reg_ld_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/out_reg_shift_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/out_reg_data_sel
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/tdo_output_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/biu_strobe
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_clr
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_in_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_shift_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/regsel_ld_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/intreg_ld_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/word_count_zero
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/bit_count_max
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/module_cmd
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/biu_ready
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/burst_instruction
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/intreg_instruction
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/intreg_write
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/rd_op
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_match
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/bit_count_32
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/word_size_bits
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/incremented_address
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_to_addr_counter
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_to_word_counter
add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/decremented_word_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/address_data_in
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/count_data_in
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/operation_in
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_to_biu
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_from_biu
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_data_out
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_data_in
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_serial_out
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/reg_select_data
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/out_reg_data
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_from_internal_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/status_reg_wr
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/module_state
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/module_next_state
add wave -noupdate -divider {CPU0 BIU internals}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/tck_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rst_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/data_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/data_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/addr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/strobe_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rd_wrn_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rdy_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_clk_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_addr_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_data_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_data_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_stb_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_we_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_ack_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/addr_reg
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/data_in_reg
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/data_out_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/wr_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/str_sync
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_tff1
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_tff2
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_tff2q
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/str_sync_wbff1
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/str_sync_wbff2
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/str_sync_wbff2q
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/data_o_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/start_toggle
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_fsm_state
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/next_fsm_state
add wave -noupdate -divider {CPU0 Status register internals}
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {31260960 ps} 0}
configure wave -namecolwidth 409
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {38962 ns} {70222960 ps}
/simulated_system/cpu_behavioral.v
0,0 → 1,155
//////////////////////////////////////////////////////////////////////
//// ////
//// cpu_behavioral.v ////
//// ////
//// ////
//// This file is part of the SoC Debug Interface. ////
//// http://www.opencores.org/projects/DebugInterface/ ////
//// ////
//// Author(s): ////
//// Igor Mohor (igorm@opencores.org) ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: cpu_behavioral.v,v $
// Revision 1.2 2010-01-08 01:41:08 Nathan
// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
//
// Revision 1.1 2008/07/08 19:11:55 Nathan
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
//
// Revision 1.1 2008/06/18 18:34:48 Nathan
// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.
//
// Revision 1.1.1.1 2008/05/14 12:07:35 Nathan
// Original from OpenCores
//
// Revision 1.4 2004/03/28 20:27:40 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.3 2004/01/22 11:07:28 mohor
// test stall_test added.
//
// Revision 1.2 2004/01/17 18:01:31 mohor
// New version.
//
// Revision 1.1 2004/01/17 17:01:25 mohor
// Almost finished.
//
//
//
//
//
`include "timescale.v"
 
 
module cpu_behavioral
(
// CPU signals
cpu_rst_i,
cpu_clk_o,
cpu_addr_i,
cpu_data_o,
cpu_data_i,
cpu_bp_o,
cpu_stall_i,
cpu_stb_i,
cpu_we_i,
cpu_ack_o,
cpu_rst_o
);
 
 
// CPU signals
input cpu_rst_i;
output cpu_clk_o;
input [31:0] cpu_addr_i;
output [31:0] cpu_data_o;
input [31:0] cpu_data_i;
output cpu_bp_o;
input cpu_stall_i;
input cpu_stb_i;
input cpu_we_i;
output cpu_ack_o;
output cpu_rst_o;
 
reg cpu_clk_o;
reg [31:0] cpu_data_o;
reg cpu_bp_o;
reg cpu_ack_o;
reg cpu_ack_q;
wire cpu_ack;
initial
begin
cpu_clk_o = 1'b0;
forever #5 cpu_clk_o = ~cpu_clk_o;
end
 
 
initial
begin
cpu_bp_o = 1'b0;
end
 
assign #200 cpu_ack = cpu_stall_i & cpu_stb_i;
 
 
 
always @ (posedge cpu_clk_o or posedge cpu_rst_i)
begin
if (cpu_rst_i)
begin
cpu_ack_o <= #1 1'b0;
cpu_ack_q <= #1 1'b0;
end
else
begin
cpu_ack_o <= #1 cpu_ack;
cpu_ack_q <= #1 cpu_ack_o;
end
end
 
always @ (posedge cpu_clk_o or posedge cpu_rst_i)
begin
if (cpu_rst_i)
cpu_data_o <= #1 32'h12345678;
else if (cpu_ack_o && (!cpu_ack_q))
cpu_data_o <= #1 cpu_data_o + 32'h11111111;
end
 
 
 
 
endmodule
 
/simulated_system/wb_model_defines.v
0,0 → 1,166
//////////////////////////////////////////////////////////////////////
//// ////
//// wb_model_defines.v ////
//// ////
//// ////
//// This file is part of the SoC Debug Interface. ////
//// http://www.opencores.org/projects/DebugInterface/ ////
//// ////
//// Author(s): ////
//// - Miha Dolenc (mihad@opencores.org) ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: wb_model_defines.v,v $
// Revision 1.2 2010-01-08 01:41:08 Nathan
// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
//
// Revision 1.1 2008/07/08 19:11:57 Nathan
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
//
// Revision 1.1 2008/06/18 18:34:48 Nathan
// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.
//
// Revision 1.1.1.1 2008/05/14 12:07:36 Nathan
// Original from OpenCores
//
// Revision 1.2 2004/03/28 20:27:40 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.1 2003/12/23 14:26:01 mohor
// New version of the debug interface. Not finished, yet.
//
//
//
 
// WISHBONE frequency in GHz
`define WB_FREQ 0.100
 
// memory frequency in GHz
`define MEM_FREQ 0.100
 
// setup and hold time definitions for WISHBONE - used in BFMs for signal generation
`define Tsetup 4
`define Thold 1
 
// how many clock cycles should model wait for design's response - integer 32 bit value
`define WAIT_FOR_RESPONSE 1023
 
// maximum number of transactions allowed in single call to block or cab transfer routines
`define MAX_BLK_SIZE 1024
 
// maximum retry terminations allowed for WISHBONE master to repeat an access
`define WB_TB_MAX_RTY 0
 
 
// some common types and defines
`define WB_ADDR_WIDTH 32
`define WB_DATA_WIDTH 32
`define WB_SEL_WIDTH `WB_DATA_WIDTH/8
`define WB_TAG_WIDTH 5
`define WB_ADDR_TYPE [(`WB_ADDR_WIDTH - 1):0]
`define WB_DATA_TYPE [(`WB_DATA_WIDTH - 1):0]
`define WB_SEL_TYPE [(`WB_SEL_WIDTH - 1):0]
`define WB_TAG_TYPE [(`WB_TAG_WIDTH - 1):0]
 
// read cycle stimulus - consists of:
// - address field - which address read will be performed from
// - sel field - what byte select value should be
// - tag field - what tag values should be put on the bus
`define READ_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
`define READ_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
`define READ_ADDRESS [(`WB_ADDR_WIDTH - 1):0]
`define READ_SEL [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH - 1):`WB_ADDR_WIDTH]
`define READ_TAG_STIM [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_SEL_WIDTH)]
 
// read cycle return type consists of:
// - read data field
// - tag field received from WISHBONE
// - wishbone slave response fields - ACK, ERR and RTY
// - test bench error indicator (when testcase has not used wb master model properly)
// - how much data was actually transfered
`define READ_RETURN_TYPE [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):0]
`define READ_DATA [(32 + `WB_DATA_WIDTH + 4 - 1):32 + 4]
`define READ_TAG_RET [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):(`WB_DATA_WIDTH + 32 + 4)]
`define READ_RETURN_LENGTH (32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1)
 
// write cycle stimulus type consists of
// - address field
// - data field
// - sel field
// - tag field
`define WRITE_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
`define WRITE_ADDRESS [(`WB_ADDR_WIDTH - 1):0]
`define WRITE_DATA [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH - 1):`WB_ADDR_WIDTH]
`define WRITE_SEL [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH)]
`define WRITE_TAG_STIM [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH)]
 
// length of WRITE_STIMULUS
`define WRITE_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
 
// write cycle return type consists of:
// - test bench error indicator (when testcase has not used wb master model properly)
// - wishbone slave response fields - ACK, ERR and RTY
// - tag field received from WISHBONE
// - how much data was actually transfered
`define WRITE_RETURN_TYPE [(32 + 4 + `WB_TAG_WIDTH - 1):0]
`define WRITE_TAG_RET [(32 + 4 + `WB_TAG_WIDTH - 1):32 + 4]
 
// this four fields are common to both read and write routines return values
`define TB_ERROR_BIT [0]
`define CYC_ACK [1]
`define CYC_RTY [2]
`define CYC_ERR [3]
`define CYC_RESPONSE [3:1]
`define CYC_ACTUAL_TRANSFER [35:4]
 
// block transfer flags
`define WB_TRANSFER_FLAGS [41:0]
// consists of:
// - number of transfer cycles to perform
// - flag that enables retry termination handling - if disabled, block transfer routines will return on any termination other than acknowledge
// - flag indicating CAB transfer is to be performed - ignored by all single transfer routines
// - number of initial wait states to insert
// - number of subsequent wait states to insert
`define WB_TRANSFER_SIZE [41:10]
`define WB_TRANSFER_AUTO_RTY [8]
`define WB_TRANSFER_CAB [9]
`define INIT_WAITS [3:0]
`define SUBSEQ_WAITS [7:4]
 
// wb slave response
`define ACK_RESPONSE 3'b100
`define ERR_RESPONSE 3'b010
`define RTY_RESPONSE 3'b001
`define NO_RESPONSE 3'b000
/simulated_system/timescale.v
0,0 → 1,71
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v ////
//// ////
//// ////
//// This file is part of the SoC Debug Interface. ////
//// http://www.opencores.org/projects/DebugInterface/ ////
//// ////
//// Author(s): ////
//// Igor Mohor (igorm@opencores.org) ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: timescale.v,v $
// Revision 1.2 2010-01-08 01:41:08 Nathan
// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
//
// Revision 1.1 2008/07/08 19:11:56 Nathan
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
//
// Revision 1.1 2008/06/18 18:34:48 Nathan
// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.
//
// Revision 1.1.1.1 2008/05/14 12:07:36 Nathan
// Original from OpenCores
//
// Revision 1.4 2004/03/28 20:27:40 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.3 2004/01/17 17:01:25 mohor
// Almost finished.
//
// Revision 1.2 2003/12/23 14:26:01 mohor
// New version of the debug interface. Not finished, yet.
//
//
//
//
`timescale 1ns/10ps
 

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