URL
https://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk
Subversion Repositories adv_debug_sys
Compare Revisions
- This comparison shows the changes necessary to convert path
/adv_debug_sys/trunk/Hardware/adv_dbg_if/rtl
- from Rev 51 to Rev 69
- ↔ Reverse comparison
Rev 51 → Rev 69
/verilog/adbg_crc32.v
26,6 → 26,10
// CVS Revision History |
// |
// $Log: adbg_crc32.v,v $ |
// Revision 1.3 2011-10-24 02:25:11 natey |
// Removed extraneous '#1' delays, which were a holdover from the original |
// versions in the previous dbg_if core. |
// |
// Revision 1.2 2010-01-10 22:54:10 Nathan |
// Update copyright dates |
// |
100,13 → 104,13
always @ (posedge clk or posedge rst) |
begin |
if(rst) |
crc[31:0] <= #1 32'hffffffff; |
crc[31:0] <= 32'hffffffff; |
else if(clr) |
crc[31:0] <= #1 32'hffffffff; |
crc[31:0] <= 32'hffffffff; |
else if(enable) |
crc[31:0] <= #1 new_crc; |
crc[31:0] <= new_crc; |
else if (shift) |
crc[31:0] <= #1 {1'b0, crc[31:1]}; |
crc[31:0] <= {1'b0, crc[31:1]}; |
end |
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|
/verilog/adbg_or1k_status_reg.v
7,12 → 7,13
//// //// |
//// Author(s): //// |
//// Igor Mohor (igorm@opencores.org) //// |
//// Nathan Yawn (nyawn@opencores.org) //// |
//// //// |
//// //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 - 2010 Authors //// |
//// Copyright (C) 2000 - 2011 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
40,6 → 41,10
// CVS Revision History |
// |
// $Log: adbg_or1k_status_reg.v,v $ |
// Revision 1.3 2011-10-24 02:25:11 natey |
// Removed extraneous '#1' delays, which were a holdover from the original |
// versions in the previous dbg_if core. |
// |
// Revision 1.2 2010-01-10 22:54:10 Nathan |
// Update copyright dates |
// |
102,11 → 107,11
always @ (posedge cpu_clk_i or posedge rst_i) |
begin |
if(rst_i) |
stall_bp <= #1 1'b0; |
stall_bp <= 1'b0; |
else if(bp_i) |
stall_bp <= #1 1'b1; |
stall_bp <= 1'b1; |
else if(stall_reg_cpu) |
stall_bp <= #1 1'b0; |
stall_bp <= 1'b0; |
end |
|
|
115,13 → 120,13
begin |
if (rst_i) |
begin |
stall_bp_csff <= #1 1'b0; |
stall_bp_tck <= #1 1'b0; |
stall_bp_csff <= 1'b0; |
stall_bp_tck <= 1'b0; |
end |
else |
begin |
stall_bp_csff <= #1 stall_bp; |
stall_bp_tck <= #1 stall_bp_csff; |
stall_bp_csff <= stall_bp; |
stall_bp_tck <= stall_bp_csff; |
end |
end |
|
130,13 → 135,13
begin |
if (rst_i) |
begin |
stall_reg_csff <= #1 1'b0; |
stall_reg_cpu <= #1 1'b0; |
stall_reg_csff <= 1'b0; |
stall_reg_cpu <= 1'b0; |
end |
else |
begin |
stall_reg_csff <= #1 stall_reg; |
stall_reg_cpu <= #1 stall_reg_csff; |
stall_reg_csff <= stall_reg; |
stall_reg_cpu <= stall_reg_csff; |
end |
end |
|
152,11 → 157,11
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
stall_reg <= #1 1'b0; |
stall_reg <= 1'b0; |
else if (stall_bp_tck) |
stall_reg <= #1 1'b1; |
stall_reg <= 1'b1; |
else if (we_i) |
stall_reg <= #1 data_i[0]; |
stall_reg <= data_i[0]; |
end |
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164,9 → 169,9
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
cpu_reset <= #1 1'b0; |
cpu_reset <= 1'b0; |
else if(we_i) |
cpu_reset <= #1 data_i[1]; |
cpu_reset <= data_i[1]; |
end |
|
|
175,13 → 180,13
begin |
if (rst_i) |
begin |
cpu_reset_csff <= #1 1'b0; |
cpu_rst_o <= #1 1'b0; |
cpu_reset_csff <= 1'b0; |
cpu_rst_o <= 1'b0; |
end |
else |
begin |
cpu_reset_csff <= #1 cpu_reset; |
cpu_rst_o <= #1 cpu_reset_csff; |
cpu_reset_csff <= cpu_reset; |
cpu_rst_o <= cpu_reset_csff; |
end |
end |
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