OpenCores
URL https://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk

Subversion Repositories adv_debug_sys

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /adv_debug_sys/trunk/Hardware/adv_dbg_if
    from Rev 32 to Rev 42
    Reverse comparison

Rev 32 → Rev 42

/bench/jtag_serial_port/wave.do
0,0 → 1,377
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tck_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdi_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/rst_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/shift_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/pause_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/update_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/capture_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/debug_select_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_clk_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_rst_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_adr_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_dat_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_dat_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_cyc_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_stb_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_sel_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_we_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_ack_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_cab_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_err_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_cti_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_bte_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_jsp_adr_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_jsp_dat_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_jsp_dat_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_jsp_cyc_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_jsp_stb_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_jsp_sel_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_jsp_we_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_jsp_ack_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_jsp_cab_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_jsp_err_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_jsp_cti_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_jsp_bte_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/int_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_wb
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_cpu0
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_cpu1
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_jsp
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/input_shift_reg
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/module_id_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/select_cmd
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/module_id_in
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/module_selects
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/select_inhibit
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/module_inhibit
add wave -noupdate -divider {JSP Module}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/tck_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/module_tdo_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/tdi_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/capture_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/shift_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/update_dr_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/data_register_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/module_select_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/top_inhibit_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/rst_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_clk_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_rst_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_adr_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_dat_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_dat_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_cyc_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_stb_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_sel_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_we_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_ack_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_cab_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_err_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_cti_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/wb_bte_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/int_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/read_bit_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/write_bit_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/input_word_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/output_word_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/user_word_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/data_out_shift_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/rd_bit_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/rd_bit_ct_rst
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wr_bit_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wr_bit_ct_rst
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/in_word_ct_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/out_word_ct_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/in_word_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/out_word_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/user_word_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/user_word_ct_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/out_reg_ld_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/out_reg_shift_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/out_reg_data_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/biu_rd_strobe
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/biu_wr_strobe
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/in_word_count_zero
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/out_word_count_zero
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/user_word_count_zero
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/rd_bit_count_max
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/wr_bit_count_max
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/data_to_in_word_counter
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/data_to_out_word_counter
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/data_to_user_word_counter
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/decremented_in_word_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/decremented_out_word_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/decremented_user_word_count
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/count_data_in
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/data_to_biu
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/data_from_biu
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/biu_space_available
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/biu_bytes_available
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/count_data_from_biu
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/out_reg_data
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/rd_module_state
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/rd_module_next_state
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/wr_module_state
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/wr_module_next_state
add wave -noupdate -divider {JSP BIU}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/tck_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rst_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/data_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/data_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/bytes_free_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/bytes_available_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_strobe_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_strobe_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_clk_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_rst_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_adr_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_dat_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_dat_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_cyc_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_stb_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_sel_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_we_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_ack_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_err_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/int_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/data_in
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rdata
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wen_tff
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/ren_tff
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_fifo_ack
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_bytes_free
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_bytes_avail
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_bytes_avail
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_bytes_avail_not_zero
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/ren_sff_out
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo_data_out
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/data_to_wb
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/data_from_wb
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo_not_empty
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wda_rst
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wpp
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/w_fifo_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/ren_rst
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rdata_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rpp
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/r_fifo_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/r_wb_ack
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/w_wb_ack
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wdata_avail
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_rd
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_wr
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/pop
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rcz
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fsm_state
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/next_rd_fsm_state
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fsm_state
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/next_wr_fsm_state
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/bus_data_lo
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/bus_data_hi
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wb_reg_ack
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo_not_full
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_dlab_bit
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_ier
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_iir
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/thr_int_arm
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_lsr
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_dlab_bit_wren
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_ier_wren
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_iir_rden
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_lcr
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_fcr_wren
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rcvr_fifo_rst
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/xmit_fifo_rst
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_mcr
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_msr
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/reg_scr
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/iir_gen
add wave -noupdate -divider {WR FIFO}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/CLK
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/RST
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/DATA_IN
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/DATA_OUT
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/PUSH_POPn
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/EN
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/BYTES_AVAIL
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/BYTES_FREE
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/reg0
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/reg1
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/reg2
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/reg3
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/reg4
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/reg5
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/reg6
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/reg7
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/counter
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/push_ok
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/wr_fifo/pop_ok
add wave -noupdate -divider {RD FIFO}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/CLK
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/RST
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/DATA_IN
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/DATA_OUT
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/PUSH_POPn
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/EN
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/BYTES_AVAIL
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/BYTES_FREE
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/reg0
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/reg1
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/reg2
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/reg3
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/reg4
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/reg5
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/reg6
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/reg7
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/counter
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/push_ok
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_jsp/jsp_biu_i/rd_fifo/pop_ok
add wave -noupdate -divider {WB Module}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/tck_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/module_tdo_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/tdi_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/capture_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/shift_dr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/update_dr_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_register_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/module_select_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/top_inhibit_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/rst_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_clk_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_adr_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_dat_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_dat_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_cyc_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_stb_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_sel_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_we_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_ack_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_cab_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_err_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_cti_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_bte_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/address_counter
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_count
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/word_count
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/operation
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_out_shift_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/internal_register_select
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/internal_reg_error
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/addr_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/addr_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/op_reg_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_ct_rst
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/word_ct_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/word_ct_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/out_reg_ld_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/out_reg_shift_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/out_reg_data_sel
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/tdo_output_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_strobe
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_clr
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_in_sel
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_shift_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/regsel_ld_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/intreg_ld_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/error_reg_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_clr_err
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/word_count_zero
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_count_max
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/module_cmd
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_ready
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_err
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/burst_instruction
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/intreg_instruction
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/intreg_write
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/rd_op
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_match
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_count_32
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/word_size_bits
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/word_size_bytes
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/incremented_address
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_to_addr_counter
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_to_word_counter
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/decremented_word_count
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/address_data_in
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/count_data_in
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/operation_in
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_to_biu
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_from_biu
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_data_out
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_data_in
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_serial_out
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/reg_select_data
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/out_reg_data
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_from_internal_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_rst
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/module_state
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/module_next_state
add wave -noupdate -divider {WB BIU}
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/tck_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rst_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/data_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/data_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/addr_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/strobe_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rd_wrn_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/err_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/word_size_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_clk_i
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_adr_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_dat_o
add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_dat_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_cyc_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_stb_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_sel_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_we_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_ack_i
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_cab_o
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_err_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_cti_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_bte_o
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/sel_reg
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/addr_reg
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/data_in_reg
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/data_out_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wr_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/str_sync
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_sync
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/err_reg
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_sync_tff1
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_sync_tff2
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_sync_tff2q
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/str_sync_wbff1
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/str_sync_wbff2
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/str_sync_wbff2q
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/data_o_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/rdy_sync_en
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/err_en
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/be_dec
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/start_toggle
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/swapped_data_i
add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/swapped_data_out
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/wb_fsm_state
add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_biu_i/next_fsm_state
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {553794 ns} 0}
configure wave -namecolwidth 466
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {391982 ns} {400422 ns}
/bench/jtag_serial_port/adv_dbg_jsp_tb.v
0,0 → 1,1461
//////////////////////////////////////////////////////////////////////
//// ////
//// adv_dbg_tb.v ////
//// ////
//// ////
//// Testbench for the SoC Advanced Debug Interface. ////
//// This testbench specifically tests the JTAG serial port ////
//// ////
//// Author(s): ////
//// Nathan Yawn (nathan.yawn@opencored.org) ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
 
`include "tap_defines.v"
`include "adbg_defines.v"
`include "adbg_wb_defines.v"
 
// Polynomial for the CRC calculation
// Yes, it's backwards. Yes, this is on purpose.
// To decrease logic + routing, we want to shift the CRC calculation
// in the same direction we use to shift the data out, LSB first.
`define DBG_CRC_POLY 32'hedb88320
 
// These are indicies into an array which hold values for the JTAG outputs
`define JTAG_TMS 0
`define JTAG_TCK 1
`define JTAG_TDO 2
 
`define JTAG_TMS_bit 3'h1
`define JTAG_TCK_bit 3'h2
`define JTAG_TDO_bit 3'h4
 
`define wait_jtag_period #50
 
 
module adv_debug_tb;
 
// Connections to the JTAG TAP
reg jtag_tck_o;
reg jtag_tms_o;
reg jtag_tdo_o;
wire jtag_tdi_i;
 
// Connections between TAP and debug module
wire capture_dr;
wire shift_dr;
wire pause_dr;
wire update_dr;
wire dbg_rst;
wire dbg_tdi;
wire dbg_tdo;
wire dbg_sel;
 
// Connections between the debug module and the wishbone
`ifdef DBG_WISHBONE_SUPPORTED
wire [31:0] wb_adr;
wire [31:0] wb_dat_m;
wire [31:0] wb_dat_s;
wire wb_cyc;
wire wb_stb;
wire [3:0] wb_sel;
wire wb_we;
wire wb_ack;
wire wb_err;
reg wb_clk_i; // the wishbone clock
reg wb_rst_i;
`endif
 
`ifdef DBG_CPU0_SUPPORTED
wire cpu0_clk;
wire [31:0]cpu0_addr;
wire [31:0] cpu0_data_c;
wire [31:0] cpu0_data_d;
wire cpu0_bp;
wire cpu0_stall;
wire cpu0_stb;
wire cpu0_we;
wire cpu0_ack;
wire cpu0_rst;
`endif
 
wire jsp_int;
reg test_enabled;
 
// Data which will be written to the WB interface
reg [31:0] static_data32 [0:15];
reg [15:0] static_data16 [0:15];
reg [7:0] static_data8 [0:15];
 
// Arrays to hold data read back from the WB interface, for comparison
reg [31:0] input_data32 [0:15];
reg [15:0] input_data16 [0:15];
reg [7:0] input_data8 [0:15];
 
reg [32:0] err_data; // holds the contents of the error register from the various modules
 
reg failed;
integer i;
 
reg [63:0] jsp_data8;
initial
begin
jtag_tck_o = 1'b0;
jtag_tms_o = 1'b0;
jtag_tdo_o = 1'b0;
end
 
// Provide the wishbone clock
`ifdef DBG_WISHBONE_SUPPORTED
initial
begin
wb_clk_i = 1'b0;
forever #7 wb_clk_i = ~wb_clk_i; // Odd frequency ratio to test the synchronization
end
`endif
 
 
 
// Start the test (and reset the wishbone)
initial
begin
test_enabled = 1'b0;
wb_rst_i = 1'b0;
#100;
wb_rst_i = 1'b1;
#100;
wb_rst_i = 1'b0;
 
// Init the memory
initialize_memory(32'h0,32'h16);
 
#1 test_enabled<=#1 1'b1;
end
 
// This is the main test procedure
always @ (posedge test_enabled)
begin
 
$display("Starting advanced debug JTAG serial port test");
reset_jtag;
#1000;
check_idcode;
#1000;
// Select the debug module in the IR
set_ir(`DEBUG);
#1000;
 
///////////////////////////////////////////////////////////////////
// Test the JTAG serial port. We use the debug unit WB interface
// to act as the CPU/WB master.
////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////
// Do an 8 byte transfer, JSP->WB
$display("-------------------------------------------");
$display("--- Test 1: 8 bytes JSP->WB");
// Write 8 bytes from JTAG to WB
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
#200
$display("JTAG putting 8 bytes to JSP module at time %t", $time);
do_jsp_read_write(4'h8,jsp_data8); // 4 bits words to write, 64 bits output data
// data returned in input_data8[]
// Select the WB unit in the debug module, read the data written
#1000;
$display("Selecting Wishbone module at time %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
failed <= 1'b0;
for(i = 0; i < 8; i=i+1) begin
do_module_burst_read(3'h1, 16'd1, 32'h0);
//$display("WB read got 0x%x", input_data8[0]);
if(input_data8[0] != i) begin
failed = 1;
$display("JSP-to-WB data mismatch at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
//$display("JTAG read got 0x%x", input_data8[i]);
end
 
end
if(!failed) $display("WB-to-JSP data: 8 bytes OK! Test 1 passed!");
 
/////////////////////////////////////////////////////
// Do an 8-byte transfer, WB->JSP
$display("-------------------------------------------");
$display("--- Test 2: 8 bytes WB->JSP");
// Put 8 bytes from the WB into the JSP
#1000
$display("WB putting 8 bytes to JSP module at time %t", $time);
for(i = 0; i < 8; i=i+1) begin
static_data8[0] = i;
do_module_burst_write(3'h1, 16'd1, 32'h0);
end
 
// Get 8 bytes from the JSP
#1000
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
#1000
$display("JTAG getting 8 bytes from JSP module at time %t", $time);
do_jsp_read_write(4'h0,jsp_data8); // 4 bits words to write, 64 bits output data
// data returned in input_data8[]
 
failed <= 1'b0;
for(i = 0; i < 8; i=i+1) begin
if(i != input_data8[i]) begin
failed = 1;
$display("WB-to-JSP data mismatch at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
//$display("JTAG read got 0x%x", input_data8[i]);
end
end
if(!failed) $display("WB-to-JSP data: 8 bytes OK! Test 2 passed!");
//////////////////////////////////////
// Write 4 bytes, then 4 more, JSP->WB (read all back at once)
$display("-------------------------------------------");
$display("--- Test 3: 4+4 bytes, JSP->WB");
// Write 4 bytes from JTAG
#1000
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
#200
$display("JTAG putting 4 bytes to JSP module at time %t", $time);
do_jsp_read_write(4'h4,jsp_data8); // 4 bits words to write, 64 bits output data
do_jsp_read_write(4'h4,jsp_data8); // 4 bits words to write, 64 bits output data
// data returned in input_data8[]
// Select the WB unit in the debug module, read the data written
#1000;
$display("Selecting Wishbone module at time %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
failed <= 1'b0;
for(i = 0; i < 4; i=i+1) begin
do_module_burst_read(3'h1, 16'd1, 32'h0);
if(input_data8[0] != i) begin
failed = 1;
$display("JSP-to-WB 4+4 data mismatch at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
end
end
for(i = 0; i < 4; i=i+1) begin
do_module_burst_read(3'h1, 16'd1, 32'h0);
if(input_data8[0] != i) begin
failed = 1;
$display("JSP-to-WB 4+4 data mismatch at index %d, wrote 0x%x, read 0x%x", i+4, i, input_data8[i]);
end
end
if(!failed) $display("WB-to-JSP 4+4 data: 8 bytes OK! Test 3 passed!");
////////////////////////////////////////
// Read 8 from JTAG, put 4 to WB
$display("-------------------------------------------");
$display("--- Test 4: 8 bytes WB->JSP, 4 bytes JSP->WB");
// Put 8 bytes from the WB into the JSP
#1000
$display("Selecting Wishbone module at time %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
$display("WB putting 8 bytes to JSP module for R8W4 read at time %t", $time);
for(i = 0; i < 8; i=i+1) begin
static_data8[0] = i;
do_module_burst_write(3'h1, 16'd1, 32'h0);
end
 
// Get 8 bytes from the JSP, put 4 to WB
#1000
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
#1000
$display("JTAG getting 8 and putting 4 at time %t", $time);
do_jsp_read_write(4'h4,jsp_data8); // 4 bits words to write, 64 bits output data
// data returned in input_data8[]
 
failed <= 1'b0;
for(i = 0; i < 8; i=i+1) begin
if(i != input_data8[i]) begin
failed = 1;
$display("R8W4 data mismatch getting JSP data at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
end
end
if(!failed) $display("R8W4: 8 JSP bytes OK!");
// Remove the 4 bytes via the WB
#1000;
$display("Selecting Wishbone module at time %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
failed <= 1'b0;
for(i = 0; i < 4; i=i+1) begin
do_module_burst_read(3'h1, 16'd1, 32'h0);
if(input_data8[0] != i) begin
failed = 1;
$display("R8W4 data mismatch clearing WB data at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
end
end
if(!failed) $display("R8W4: 4 WB bytes OK!");
///////////////////////////////////////////////////
// Test putting more data than space available
$display("-------------------------------------------");
$display("--- Test 5: Put 6 JSP->WB, then 6 more");
// put 6 to WB
#1000
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
#1000
$display("JTAG putting 6 at time %t", $time);
do_jsp_read_write(4'h6,jsp_data8); // 4 bits words to write, 64 bits output data
// put 6 more
#1000
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
#1000
$display("JTAG putting 6 at time %t", $time);
do_jsp_read_write(4'h6,jsp_data8); // 4 bits words to write, 64 bits output data
// Get the data back from the WB
#1000;
$display("Selecting Wishbone module at time %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
failed <= 1'b0;
for(i = 0; i < 6; i=i+1) begin
do_module_burst_read(3'h1, 16'd1, 32'h0);
if(input_data8[0] != i) begin
failed = 1;
$display("W6W6 data mismatch reading WB data at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
end
end
for(i = 0; i < 2; i=i+1) begin
do_module_burst_read(3'h1, 16'd1, 32'h0);
if(input_data8[0] != i) begin
failed = 1;
$display("W6W6 data mismatch reading WB data at index %d, wrote 0x%x, read 0x%x", i+6, i, input_data8[i]);
end
end
if(!failed) $display("W6W6: 8 WB bytes OK!");
 
//////////////////////////////////////////
// Verify behavior of WB UART 16450-style registers
// Check LSR with both FIFOs empty
$display("-------------------------------------------");
$display("--- Test 6a: Check LSR with both FIFOs empty");
$display("Selecting Wishbone module at time %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
do_module_burst_read(3'h1, 16'd1, 32'h5);
if(input_data8[0] != 8'h60) begin
$display("LSR mismatch with both FIFOs empty, read 0x%x, expected 0x60", input_data8[0]);
end
else $display("LSR with both FIFOs empty OK!");
 
$display("-------------------------------------------");
$display("--- Test 6b: Check LSR with WB read data available");
#1000
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
$display("JTAG putting 1 at time %t", $time);
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
$display("Selecting Wishbone module at time %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
do_module_burst_read(3'h1, 16'd1, 32'h5);
if(input_data8[0] != 8'h61) begin
$display("LSR mismatch with WB read data available, read 0x%x, expected 0x61", input_data8[0]);
end
else $display("LSR with WB read data available OK!");
$display("-------------------------------------------");
$display("--- Test 6c: Check LSR with WB read data available and write FIFO not empty / full");
#1000
$display("Selecting Wishbone module at time %t", $time);
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
$display("WB putting 1 bytes to JSP module for LSR test at time %t", $time);
do_module_burst_write(3'h1, 16'd1, 32'h0);
do_module_burst_read(3'h1, 16'd1, 32'h5);
if(input_data8[0] != 8'h61) begin
$display("LSR mismatch with WB read data available and write FIFO not empty, read 0x%x, expected 0x61", input_data8[0]);
end
else $display("LSR with WB read data available and write FIFO not empty OK!");
// Fill the write FIFO
for(i = 0; i < 7; i = i + 1) begin
do_module_burst_write(3'h1, 16'd1, 32'h0);
end
do_module_burst_read(3'h1, 16'd1, 32'h5);
if(input_data8[0] != 8'h01) begin
$display("LSR mismatch with WB read data available and write FIFO full, read 0x%x, expected 0x01", input_data8[0]);
end
else $display("LSR with WB read data available and write FIFO full OK!");
$display("-------------------------------------------");
$display("--- Test 6d: Check LSR with write FIFO full");
do_module_burst_read(3'h1, 16'd1, 32'h0); // get/clear the read data
do_module_burst_read(3'h1, 16'd1, 32'h5);
if(input_data8[0] != 8'h00) begin
$display("LSR mismatch with WB write FIFO full, read 0x%x, expected 0x00", input_data8[0]);
end
else $display("LSR with WB write FIFO full OK!");
//////////////////////////////////////
// Test DLAB bit
// Now that we've tested the LSR, we can use it to verity the FIFO states
 
$display("-------------------------------------------");
$display("--- Test 7: test DLAB bit");
#1000
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
$display("JTAG putting 1 (and getting 8) at time %t", $time);
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
// Set the DLAB bit. This should prevent reads/writes to the FIFOs from the WB
#1000
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
#1000
$display("Setting DLAB bit it time %t", $time);
static_data8[0] = 8'h80;
do_module_burst_write(3'h1, 16'd1, 32'h00000003);
// Read from 0. This should not get the available byte.
do_module_burst_read(3'h1, 16'd1, 32'h0);
// Try to write the FIFO full. This should not put any bytes to the transmit FIFO
for(i = 0; i < 8; i = i + 1) begin
do_module_burst_write(3'h1, 16'd1, 32'h0);
end
// Check FIFO status in the LSR
$display("Checking LSR");
do_module_burst_read(3'h1, 16'd1, 32'h5);
if(input_data8[0] != 8'h61) begin
$display("LSR mismatch in DLAB inhibit test, read 0x%x, expected 0x61", input_data8[0]);
end
else $display("DLAB inhibit test OK!");
// Now clear the DLAB, and try again.
$display("Clearing DLAB at time %t", $time);
static_data8[0] = 8'h00;
do_module_burst_write(3'h1, 16'd1, 32'h3);
do_module_burst_read(3'h1, 16'd1, 32'h0); // Should empty the read FIFO
for(i = 0; i < 8; i = i + 1) begin
do_module_burst_write(3'h1, 16'd1, 32'h0); // Should un-empty the read FIFO
end
// Check FIFO status in the LSR
do_module_burst_read(3'h1, 16'd1, 32'h5);
if(input_data8[0] != 8'h00) begin
$display("LSR mismatch in DLAB test 2, read 0x%x, expected 0x00", input_data8[0]);
end
else $display("DLAB un-inhibit test OK!");
// Note WB write FIFO is full at this point
///////////////////////////////////////////////////
// Test interrupt functionality.
$display("-------------------------------------------");
$display("--- Test 8a: IER write");
// Write IER to 0
static_data8[0] = 8'h00;
do_module_burst_write(3'h1, 16'd1, 32'h1);
// Make sure it's 0
do_module_burst_read(3'h1, 16'd1, 32'h1);
if(input_data8[0] != 8'h00) begin
$display("Failed to set IER to 0x00, read 0x%x", input_data8[0]);
end
else $display("Set IER to 0: pass");
// Make sure int_o is not set
if(jsp_int) begin
$display("JSP Interrupt set when no interrupts enabled: FAIL");
end
else $display("JSP interrupt not set, interrupts disabled: OK");
// Write IER to 0x0F
static_data8[0] = 8'h0F;
do_module_burst_write(3'h1, 16'd1, 32'h1);
// Make sure it's 0x0F
do_module_burst_read(3'h1, 16'd1, 32'h1);
if(input_data8[0] != 8'h0F) begin
$display("Failed to set IER to 0x0F, read 0x%x", input_data8[0]);
end
else $display("Set IER to 0x0F: pass");
 
// Write IER to 0x03
static_data8[0] = 8'h03;
do_module_burst_write(3'h1, 16'd1, 32'h1);
// Make sure it's 0x03
do_module_burst_read(3'h1, 16'd1, 32'h1);
if(input_data8[0] != 8'h03) begin
$display("Failed to set IER to 0x03, read 0x%x", input_data8[0]);
end
else $display("Set IER to 0x03: pass");
 
////////////////////////////////////
// Test the int_o output
 
$display("-------------------------------------------");
$display("--- Test 8b: int_o output");
// Make sure int_o is (still) not set WB RD FIFO empty, WB WR FIFO is full
if(jsp_int) begin
$display("JSP Interrupt set when no int condition: FAIL");
end
else $display("JSP interrupt not set, no INT condition: OK");
// Check IIR for 'no active interrupt'
do_module_burst_read(3'h1, 16'd1, 32'h2);
if(input_data8[0] != 8'h01) begin
$display("Wrong value for IIR with no active interrupt, read 0x%x, expected 0x01", input_data8[0]);
end
else $display("IIR is 0x01 with no active interrupt: pass");
// Read a byte from the JSP, should trigger the 'THR empty' interrupt
#1000
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
$display("JTAG getting 8 at time %t", $time);
do_jsp_read_write(4'h0,jsp_data8); // 4 bits words to write, 64 bits output data
 
 
// Make sure int_o is (still) not set WB RD FIFO empty, WB WR FIFO is full
if(!jsp_int) begin
$display("JSP Interrupt not set when THR empty: FAIL");
end
else $display("JSP interrupt set for THR empty: OK");
#1000
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
// Check IIR for THR empty
do_module_burst_read(3'h1, 16'd1, 32'h2);
if(input_data8[0] != 8'h02) begin
$display("Wrong value for IIR with no active interrupt, read 0x%x, expected 0x02", input_data8[0]);
end
else $display("IIR is 0x02 with THR empty: pass");
// IIR read should have cleared int_o and changed IIR to 'no active interrupt'
if(jsp_int) begin
$display("JSP Interrupt set after IIR read: FAIL");
end
else $display("JSP interrupt not set after clearing THR INT with IIR read: OK");
// Check IIR for 'no active interrupt'
do_module_burst_read(3'h1, 16'd1, 32'h2);
if(input_data8[0] != 8'h01) begin
$display("Wrong value for IIR after clearing THR INT with IIR read, read 0x%x, expected 0x01", input_data8[0]);
end
else $display("IIR is 0x01 after clearing THR INT with IIR read: pass");
// Write a byte from the WB, should trigger int_o
static_data8[0] = 8'h00;
do_module_burst_write(3'h1, 16'd1, 32'h0);
// check int_o, should be set
if(!jsp_int) begin
$display("JSP Interrupt not set when THR not full: FAIL");
end
else $display("JSP interrupt set for THR not full: OK");
// Write a byte from the JSP, should take precedence in IIR
#1000
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
$display("JTAG putting 1 at time %t", $time);
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
// check int_o, should be set
if(!jsp_int) begin
$display("JSP Interrupt not set when read data available: FAIL");
end
else $display("JSP interrupt set for read data available: OK");
// Check IIR, should show read data available
#1000
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
do_module_burst_read(3'h1, 16'd1, 32'h2);
if(input_data8[0] != 8'h4) begin
$display("Wrong value for IIR after clearing THR INT with IIR read, read 0x%x, expected 0x04", input_data8[0]);
end
else $display("IIR is 0x04 after putting a JSP byte: pass");
// Read the byte from the WB.
do_module_burst_read(3'h1, 16'd1, 32'h0);
// check int_o, should be set
if(!jsp_int) begin
$display("JSP Interrupt not set when THR not full: FAIL");
end
else $display("JSP interrupt set for THR not full: OK");
// Check IIR, should show THRE
#1000
do_module_burst_read(3'h1, 16'd1, 32'h2);
if(input_data8[0] != 8'h02) begin
$display("Wrong value for IIR after clearing RDA INT with WB read (THRE), read 0x%x, expected 0x02", input_data8[0]);
end
else $display("IIR is 0x02 after reading data with THRE: pass");
// check int_o, should be cleared
if(jsp_int) begin
$display("JSP Interrupt set after clearing THRE with IIR read: FAIL");
end
else $display("JSP interrupt not set, THRE cleared with IIR read: OK");
// Check IIR, should no no interrupt
#1000
do_module_burst_read(3'h1, 16'd1, 32'h2);
if(input_data8[0] != 8'h01) begin
$display("Wrong value for IIR after clearing THR INT with IIR read, read 0x%x, expected 0x01", input_data8[0]);
end
else $display("IIR is 0x01 after reading data with THRE: pass");
// Put a byte from the JSP
#1000
$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
$display("JTAG putting 1 at time %t", $time);
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
// check int_o, should be set
if(!jsp_int) begin
$display("JSP Interrupt not set when read data available: FAIL");
end
else $display("JSP interrupt set for read data available: OK");
// check IIR, should show receive data available
#1000
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
do_module_burst_read(3'h1, 16'd1, 32'h2);
if(input_data8[0] != 8'h4) begin
$display("Wrong value for IIR with RDA, read 0x%x, expected 0x04", input_data8[0]);
end
else $display("IIR is 0x04 after putting a JSP byte: pass");
// Read the byte over WB
do_module_burst_read(3'h1, 16'd1, 32'h0);
// check int_o, should be cleared
if(jsp_int) begin
$display("JSP Interrupt set when no int condition: FAIL");
end
else $display("JSP interrupt not set, no INT condition: OK");
// check IIR, should show no active interrupt
#1000
do_module_burst_read(3'h1, 16'd1, 32'h2);
if(input_data8[0] != 8'h1) begin
$display("Wrong value for IIR with no active int, read 0x%x, expected 0x01", input_data8[0]);
end
else $display("IIR is 0x01 with no active interrupts: pass");
////////////////////////////////////
// Test the software resets
 
$display("-------------------------------------------");
$display("--- Test 9: Software WB/UART FIFO reset");
// First, test reset only JSP->WB FIFO
// Put a byte from the JSP
#1000
//$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
//$display("JTAG putting 1 at time %t", $time);
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
// Put a byte from the WB
#1000
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
#500
static_data8[0] = 8'h00;
do_module_burst_write(3'h1, 16'd1, 32'h0);
// Reset the JSP->WB FIFO
#500
static_data8[0] = 8'h02;
do_module_burst_write(3'h1, 16'd1, 32'h2);
 
// To test, need to read the output from the transact function:
// Should be 1 byte available, 8 bytes free
#1000
//$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
$display("Next line should show 1 byte available, 8 bytes free:");
do_jsp_read_write(4'h0,jsp_data8); // 4 bits words to write, 64 bits output data
// Second, test reset only WB->JSP FIFO
// Put a byte from the JSP
#1000
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
// Put a byte from the WB
#1000
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
#500
static_data8[0] = 8'h00;
do_module_burst_write(3'h1, 16'd1, 32'h0);
// Reset the WB->JSP FIFO
#500
static_data8[0] = 8'h04;
do_module_burst_write(3'h1, 16'd1, 32'h2);
 
// To test, need to read the output from the transact function:
// Should be 0 byte available, 7 bytes free
#1000
//$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
$display("Next line should show 0 byte available, 7 bytes free:");
do_jsp_read_write(4'h0,jsp_data8); // 4 bits words to write, 64 bits output data
// Finally, test reset both directions
// Put a byte from the JSP
#1000
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
// Put a byte from the WB
#1000
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
#500
static_data8[0] = 8'h00;
do_module_burst_write(3'h1, 16'd1, 32'h0);
// Reset both FIFO
#500
static_data8[0] = 8'h06;
do_module_burst_write(3'h1, 16'd1, 32'h2);
 
// To test, need to read the output from the transact function:
// Should be 0 byte available, 8 bytes free
#1000
//$display("Selecting JSP module at time %t", $time);
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
$display("Next line should show 0 byte available, 8 bytes free:");
do_jsp_read_write(4'h0,jsp_data8); // 4 bits words to write, 64 bits output data
//////////////////////////////
// End of tests
$display("----------------------------------");
$display("--- ALL TESTS COMPLETE ---");
end
 
task initialize_memory;
input [31:0] start_addr;
input [31:0] length;
integer i;
reg [31:0] addr;
begin
 
jsp_data8 <= 64'h0706050403020100;
 
for (i=0; i<length; i=i+1)
begin
static_data32[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
static_data16[i] <= {i[7:0], i[7:0]+ 2'd1};
static_data8[i] <= i[7:0];
end
end
endtask
 
///////////////////////////////////////////////////////////////////////////////
// Declaration and interconnection of components
 
// Top module
tap_top i_tap (
// JTAG pads
.tms_pad_i(jtag_tms_o),
.tck_pad_i(jtag_tck_o),
.trstn_pad_i(1'b1),
.tdi_pad_i(jtag_tdo_o),
.tdo_pad_o(jtag_tdi_i),
.tdo_padoe_o(),
 
// TAP states
.test_logic_reset_o(dbg_rst),
.run_test_idle_o(),
.shift_dr_o(shift_dr),
.pause_dr_o(pause_dr),
.update_dr_o(update_dr),
.capture_dr_o(capture_dr),
// Select signals for boundary scan or mbist
.extest_select_o(),
.sample_preload_select_o(),
.mbist_select_o(),
.debug_select_o(dbg_sel),
// TDO signal that is connected to TDI of sub-modules.
.tdi_o(dbg_tdo),
// TDI signals from sub-modules
.debug_tdo_i(dbg_tdi), // from debug module
.bs_chain_tdo_i(1'b0), // from Boundary Scan Chain
.mbist_tdo_i(1'b0) // from Mbist Chain
);
 
 
// Top module
adbg_top i_dbg_module(
// JTAG signals
.tck_i(jtag_tck_o),
.tdi_i(dbg_tdo),
.tdo_o(dbg_tdi),
.rst_i(dbg_rst),
 
// TAP states
.shift_dr_i(shift_dr),
.pause_dr_i(pause_dr),
.update_dr_i(update_dr),
.capture_dr_i(capture_dr),
 
// Instructions
.debug_select_i(dbg_sel)
 
 
`ifdef DBG_WISHBONE_SUPPORTED
// WISHBONE common signals
,
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
// WISHBONE master interface
.wb_adr_o(wb_adr),
.wb_dat_o(wb_dat_m),
.wb_dat_i(wb_dat_s),
.wb_cyc_o(wb_cyc),
.wb_stb_o(wb_stb),
.wb_sel_o(wb_sel),
.wb_we_o(wb_we),
.wb_ack_i(wb_ack),
.wb_cab_o(),
.wb_err_i(wb_err),
.wb_cti_o(),
.wb_bte_o()
`endif
 
`ifdef DBG_JSP_SUPPORTED
// WISHBONE slave, including interrupt output
,
.wb_jsp_adr_i(wb_adr),
.wb_jsp_dat_o(wb_dat_s),
.wb_jsp_dat_i(wb_dat_m),
.wb_jsp_cyc_i(wb_cyc),
.wb_jsp_stb_i(wb_stb),
.wb_jsp_sel_i(wb_sel),
.wb_jsp_we_i(wb_we),
.wb_jsp_ack_o(wb_ack),
.wb_jsp_cab_i(),
.wb_jsp_err_o(wb_err),
.wb_jsp_cti_i(),
.wb_jsp_bte_i(),
.int_o(jsp_int)
`endif
 
);
 
 
///////////////////////////////////////////////////////////////////////////
// Higher-level chain manipulation functions
 
// calculate the CRC, up to 32 bits at a time
task compute_crc;
input [31:0] crc_in;
input [31:0] data_in;
input [5:0] length_bits;
output [31:0] crc_out;
integer i;
reg [31:0] d;
reg [31:0] c;
begin
crc_out = crc_in;
for(i = 0; i < length_bits; i = i+1) begin
d = (data_in[i]) ? 32'hffffffff : 32'h0;
c = (crc_out[0]) ? 32'hffffffff : 32'h0;
//crc_out = {crc_out[30:0], 1'b0}; // original
crc_out = crc_out >> 1;
crc_out = crc_out ^ ((d ^ c) & `DBG_CRC_POLY);
//$display("CRC Itr %d, inbit = %d, crc = 0x%x", i, data_in[i], crc_out);
end
end
endtask
 
task check_idcode;
reg [63:0] readdata;
reg[31:0] idcode;
begin
set_ir(`IDCODE);
// Read the IDCODE in the DR
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_read_write_stream(64'h0, 8'd32, 1, readdata); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
idcode = readdata[31:0];
$display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);
end
endtask;
 
task select_debug_module;
input [1:0] moduleid;
reg validid;
begin
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream({1'b1,moduleid}, 8'h3, 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
$display("Selecting module (%0x)", moduleid);
end
endtask
 
 
task send_module_burst_command;
input [3:0] opcode;
input [31:0] address;
input [15:0] burstlength;
reg [63:0] streamdata;
begin
streamdata = {11'h0,1'b0,opcode,address,burstlength};
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream(streamdata, 8'd53, 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
end
endtask
 
task select_module_internal_register; // Really just a read, with discarded data
input [31:0] regidx;
input [7:0] len; // the length of the register index data, we assume not more than 32
reg[63:0] streamdata;
begin
streamdata = 64'h0;
streamdata = streamdata | regidx;
streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream(streamdata, (len+5), 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
end
endtask
 
task read_module_internal_register; // We assume the register is already selected
//input [31:0] regidx;
input [7:0] len; // the length of the data desired, we assume a max of 64 bits
output [63:0] instream;
reg [63:0] bitmask;
begin
instream = 64'h0;
// We shift out all 0's, which is a NOP to the debug unit
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
// Shift at least 5 bits, as this is the min, for a valid NOP
jtag_read_write_stream(64'h0, len+4,1,instream); // exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
bitmask = 64'hffffffffffffffff;
bitmask = bitmask << len;
bitmask = ~bitmask;
instream = instream & bitmask; // Cut off any unwanted excess bits
end
endtask
 
task write_module_internal_register;
input [31:0] regidx; // the length of the register index data
input [7:0] idxlen;
input [63:0] writedata;
input [7:0] datalen; // the length of the data to write. We assume the two length combined are 59 or less.
reg[63:0] streamdata;
begin
streamdata = 64'h0; // This will 0 the toplevel/module select bit
streamdata = streamdata | writedata;
streamdata = streamdata | (regidx << datalen);
streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream(streamdata, (idxlen+datalen+5), 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
end
endtask
 
// This includes the sending of the burst command
task do_module_burst_read;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] instream;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o; // temp signal...
reg [31:0] crc_read;
reg [5:0] word_size_bits;
begin
//$display("Doing burst read, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
instream = 64'h0;
word_size_bits = word_size_bytes << 3;
crc_calc_i = 32'hffffffff;
// Send the command
case (word_size_bytes)
3'h1: opcode = `DBG_WB_CMD_BREAD8;
3'h2: opcode = `DBG_WB_CMD_BREAD16;
3'h4: opcode = `DBG_WB_CMD_BREAD32;
default:
begin
$display("Tried burst read with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
opcode = `DBG_WB_CMD_BREAD32;
end
endcase
send_module_burst_command(opcode,start_address, word_count); // returns to state idle
// Get us back to shift_dr mode to read a burst
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
 
`ifdef ADBG_USE_HISPEED
// Get 1 status bit, then word_size_bytes*8 bits
status = 1'b0;
j = 0;
while(!status) begin
read_write_bit(3'h0, status);
j = j + 1;
end
//if(j > 1) begin
// $display("Took %0d tries before good status bit during burst read", j);
//end
`endif
// Now, repeat...
for(i = 0; i < word_count; i=i+1) begin
`ifndef ADBG_USE_HISPEED
// Get 1 status bit, then word_size_bytes*8 bits
status = 1'b0;
j = 0;
while(!status) begin
read_write_bit(3'h0, status);
j = j + 1;
end
//if(j > 1) begin
// $display("Took %0d tries before good status bit during burst read", j);
//end
`endif
jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream);
//$display("Read 0x%0x", instream[31:0]);
compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o);
crc_calc_i = crc_calc_o;
if(word_size_bytes == 1) input_data8[i] = instream[7:0];
else if(word_size_bytes == 2) input_data16[i] = instream[15:0];
else input_data32[i] = instream[31:0];
end
// Read the data CRC from the debug module.
jtag_read_write_stream(64'h0, 6'd32, 1, crc_read);
if(crc_calc_o != crc_read) $display("CRC ERROR! Computed 0x%x, read CRC 0x%x", crc_calc_o, crc_read);
//else $display("CRC OK!");
// Finally, shift out 5 0's, to make the next command a NOP
// Not necessary, debug unit won't latch a new opcode at the end of a burst
//jtag_write_stream(64'h0, 8'h5, 1);
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
end
endtask
 
 
task do_module_burst_write;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] dataword;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o;
reg crc_match;
reg [5:0] word_size_bits;
begin
//$display("Doing burst write, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
word_size_bits = word_size_bytes << 3;
crc_calc_i = 32'hffffffff;
// Send the command
case (word_size_bytes)
3'h1: opcode = `DBG_WB_CMD_BWRITE8;
3'h2: opcode = `DBG_WB_CMD_BWRITE16;
3'h4: opcode = `DBG_WB_CMD_BWRITE32;
default:
begin
$display("Tried burst write with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
opcode = `DBG_WB_CMD_BWRITE32;
end
endcase
send_module_burst_command(opcode, start_address, word_count); // returns to state idle
// Get us back to shift_dr mode to write a burst
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
 
// Write a start bit (a 1) so it knows when to start counting
write_bit(`JTAG_TDO_bit);
 
// Now, repeat...
for(i = 0; i < word_count; i=i+1) begin
// Write word_size_bytes*8 bits, then get 1 status bit
if(word_size_bytes == 4) dataword = {32'h0, static_data32[i]};
else if(word_size_bytes == 2) dataword = {48'h0, static_data16[i]};
else dataword = {56'h0, static_data8[i]};
jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0);
compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o);
crc_calc_i = crc_calc_o;
`ifndef ADBG_USE_HISPEED
// Check if WB bus is ready
// *** THIS WILL NOT WORK IF THERE IS MORE THAN 1 DEVICE IN THE JTAG CHAIN!!!
status = 1'b0;
read_write_bit(3'h0, status);
if(!status) begin
$display("Bad status bit during burst write, index %d", i);
end
`endif
//$display("Wrote 0x%0x", dataword);
end
// Send the CRC we computed
jtag_write_stream(crc_calc_o, 6'd32,0);
// Read the 'CRC match' bit, and go to exit1_dr
read_write_bit(`JTAG_TMS_bit, crc_match);
if(!crc_match) $display("CRC ERROR! match bit after write is %d (computed CRC 0x%x)", crc_match, crc_calc_o);
//else $display("CRC OK!");
// Finally, shift out 5 0's, to make the next command a NOP
// Not necessary, module will not latch new opcode during burst
//jtag_write_stream(64'h0, 8'h5, 1);
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
end
 
endtask
 
task do_jsp_read_write;
input [3:0] words_to_put;
input [63:0] outstream;
reg [63:0] instream;
integer i;
integer j;
integer snd;
integer rcv;
integer xfer_size;
reg inbit;
// reg shiftbit;
begin
 
// Put us in shift mode
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
 
`ifdef ADBG_JSP_SUPPORT_MULTI
read_write_bit(`JTAG_TDO_bit,inbit); // Put the start bit
`endif
 
// Put / get lengths
jtag_read_write_stream({56'h0,words_to_put, 4'b0000}, 8'h8,0,instream);
`ifdef ADBG_JSP_SUPPORT_MULTI
//shiftbit = instream[7];
instream = (instream << 1);
instream[0] = inbit;
inbit = instream[8];
`endif
 
$display("JSP got %d bytes available, %d bytes free", instream[7:4], instream[3:0]);
 
// Determine transfer size...
rcv = instream[7:4];
snd = words_to_put;
if(instream[3:0] < words_to_put) snd = instream[3:0];
xfer_size = snd;
if(rcv > snd) xfer_size = rcv;
// *** Always do 8 bytes transfers, for testing
// xfer_size = 8;
// ***
$display("Doing JSP transfer of %d bytes", xfer_size);
// Put / get bytes.
for(i = 0; i < xfer_size; i=i+1) begin
#100
jtag_read_write_stream(outstream>>(i*8), 8'h8,0,instream); // Length is in bits...
`ifdef ADBG_JSP_SUPPORT_MULTI
input_data8[i] = {instream[6:0], inbit};
inbit = instream[7];
`else
input_data8[i] = instream[7:0]; // Move input data to where it can be gotten by main task
`endif
end
 
// JSP does not use the module_inhibit output, so last data bit must be a '0'
// Excess writes are ignored. This will however pop a byte from the receive
// FIFO, so make sure all data bytes have been fetched before this is sent.
write_bit(`JTAG_TMS_bit); // exit_dr
// Put us back in idle mode
write_bit(`JTAG_TMS_bit); // update_dr
write_bit(3'h0); // idle
end
endtask // do_jsp_read_write
 
// Puts a value in the TAP IR, assuming we start in IDLE state.
// Returns to IDLE state when finished
task set_ir;
input [3:0] irval;
begin
write_bit(`JTAG_TMS_bit); // select_dr_scan
write_bit(`JTAG_TMS_bit); // select_ir_scan
write_bit(3'h0); // capture_ir
write_bit(3'h0); // shift_ir
jtag_write_stream({60'h0,irval}, 8'h4, 1); // write data, exit_1
write_bit(`JTAG_TMS_bit); // update_ir
write_bit(3'h0); // idle
end
endtask
 
// Resets the TAP and puts it into idle mode
task reset_jtag;
integer i;
begin
for(i = 0; i < 8; i=i+1) begin
write_bit(`JTAG_TMS_bit); // 5 TMS should put us in test_logic_reset mode
end
write_bit(3'h0); // idle
end
endtask
 
 
////////////////////////////////////////////////////////////////////////////
// Tasks to write or read-write a string of data
 
task jtag_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
integer i;
integer databit;
reg [2:0] bits;
begin
for(i = 0; i < (len-1); i=i+1) begin
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
write_bit(bits);
end
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
write_bit(bits);
end
endtask
 
 
task jtag_read_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
output [63:0] instream;
integer i;
integer databit;
reg [2:0] bits;
reg inbit;
begin
instream = 64'h0;
for(i = 0; i < (len-1); i=i+1) begin
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
read_write_bit(bits, inbit);
instream = (instream | (inbit << i));
end
databit = (stream >> i) & 1'h1;
bits = databit << `JTAG_TDO;
if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
read_write_bit(bits, inbit);
instream = (instream | (inbit << (len-1)));
end
endtask
 
/////////////////////////////////////////////////////////////////////////
// Tasks which write or readwrite a single bit (including clocking)
 
task write_bit;
input [2:0] bitvals;
begin
// Set data
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
// Raise clock
jtag_out(bitvals | `JTAG_TCK_bit);
`wait_jtag_period;
// drop clock (making output available in the SHIFT_xR states)
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
end
endtask
 
task read_write_bit;
input [2:0] bitvals;
output l_tdi_val;
begin
// read bit state
l_tdi_val <= jtag_tdi_i;
// Set data
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
// Raise clock
jtag_out(bitvals | `JTAG_TCK_bit);
`wait_jtag_period;
// drop clock (making output available in the SHIFT_xR states)
jtag_out(bitvals & ~(`JTAG_TCK_bit));
`wait_jtag_period;
end
endtask
 
/////////////////////////////////////////////////////////////////
// Basic functions to set the state of the JTAG TAP I/F bits
 
task jtag_out;
input [2:0] bitvals;
begin
 
jtag_tck_o <= bitvals[`JTAG_TCK];
jtag_tms_o <= bitvals[`JTAG_TMS];
jtag_tdo_o <= bitvals[`JTAG_TDO];
end
endtask
 
 
task jtag_inout;
input [2:0] bitvals;
output l_tdi_val;
begin
 
jtag_tck_o <= bitvals[`JTAG_TCK];
jtag_tms_o <= bitvals[`JTAG_TMS];
jtag_tdo_o <= bitvals[`JTAG_TDO];
 
l_tdi_val <= jtag_tdi_i;
end
endtask
 
endmodule
/bench/README_testbench.txt
2,17 → 2,17
Advanced Debug Module (adv_dbg_if)
Nathan Yawn, nathan.yawn@opencores.org
 
Two testbenches are supplied with the advanced debug interface. The first
Three testbenches are supplied with the advanced debug interface. The first
uses behavioral simulation of a wishbone bus with a memory attached, and
another behavioral simulation of an OR1200 CPU. This testbench performs
and tests bus / memory operations, and performs a few CPU operations, The
top-level module is in adv_dbg_tb.v. Other than the beavioral models, it
top-level module is in adv_dbg_tb.v. Other than the behavioral models, it
instantiates an adv_dbg_if (found in ../rtl/verilog/), and a JTAG TAP
("jtag" module, not included with this module). Note that the TAP
distributed by OpenCores will not work correctly; use the version modified
by Nathan Yawn.
written by Igor Mohor will not work correctly; use the version distributed
with the Advanced Debug System (written by Nathan Yawn).
 
The second testbench includes an actuall wishbone/OR1200 system. Its
The second testbench includes an actual wishbone/OR1200 system. Its
top-level entity is xsv_fpga_top. It instantiates a wb_conbus, an OR1200,
an onchipram, a jtag TAP, and a UART16550, along with an adv_dbg_if. The
testbench is also instantiated here, and is used to drive the inputs to
19,7 → 19,15
the JTAG TAP. This testbench is less polished, but includes a functional
test of the single-step capability of the CPU.
 
Both testbenches were written for use in ModelSim (version 6.3). A
The third testbench is used to test the JTAG serial port function. Its
top-level entity is adv_dbg_jsp_tb. This testbench instantiates only
a JTAG TAP and and adv_dbg_if. The CPU module of the adv_dbg_if should
not be enabled for this testbench. The WB initiator output of the WB
module is connected point-to-point to the WB target interface of the JTAG
Serial Port (JSP) module. The WB interface is used to drive the WB side
of the JSP.
 
All testbenches were written for use in ModelSim (version 6.4). A
wave.do file is also included for each testbench, which will display a
useful collection of signals in the ModelSim wave view.
 
/rtl/verilog/syncflop.v
0,0 → 1,126
//////////////////////////////////////////////////////////////////////
//// ////
//// syncflop.v ////
//// ////
//// ////
//// A generic synchronization device between two clock domains ////
//// ////
//// Author(s): ////
//// Nathan Yawn (nathan.yawn@opencores.org) ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// This is a synchronization element between two clock domains. It
// uses toggle signaling - that is, clock domain 1 changes the state
// of TOGGLE_IN to indicate a change, rather than setting the level
// high. When TOGGLE_IN changes state, the output on D_OUT will be
// set to level '1', and will hold that value until D_RST is held
// high during a rising edge of DEST_CLK. D_OUT will be updated
// on the second rising edge of DEST_CLK after the state of
// TOGGLE_IN has changed.
// RESET is asynchronous. This is necessary to coordinate the reset
// between different clock domains with potentially different reset
// signals.
//
// Ports:
// DEST_CLK: Clock for the target clock domain
// D_SET: Synchronously set the output to '1'
// D_CLR: Synchronously reset the output to '0'
// RESET: Set all FF's to '0' (asynchronous)
// TOGGLE_IN: Toggle data signal from source clock domain
// D_OUT: Output to clock domain 2
 
 
// Top module
module syncflop(
DEST_CLK,
D_SET,
D_RST,
RESET,
TOGGLE_IN,
D_OUT
);
 
 
input DEST_CLK;
input D_SET;
input D_RST;
input RESET;
input TOGGLE_IN;
output D_OUT;
 
reg sync1;
reg sync2;
reg syncprev;
reg srflop;
wire syncxor;
wire srinput;
wire D_OUT;
 
// Combinatorial assignments
assign syncxor = sync2 ^ syncprev;
assign srinput = syncxor | D_SET;
assign D_OUT = srflop | syncxor;
// First DFF (always enabled)
always @ (posedge DEST_CLK or posedge RESET)
begin
if(RESET) sync1 <= 1'b0;
else sync1 <= TOGGLE_IN;
end
 
// Second DFF (always enabled)
always @ (posedge DEST_CLK or posedge RESET)
begin
if(RESET) sync2 <= 1'b0;
else sync2 <= sync1;
end
 
// Third DFF (always enabled, used to detect toggles)
always @ (posedge DEST_CLK or posedge RESET)
begin
if(RESET) syncprev <= 1'b0;
else syncprev <= sync2;
end
 
// Set/Reset FF (holds detected toggles)
always @ (posedge DEST_CLK or posedge RESET)
begin
if(RESET) srflop <= 1'b0;
else if(D_RST) srflop <= 1'b0;
else if (srinput) srflop <= 1'b1;
end
 
endmodule
/rtl/verilog/adbg_or1k_module.v
40,6 → 40,9
// CVS Revision History
//
// $Log: adbg_or1k_module.v,v $
// Revision 1.6 2010-03-08 21:04:18 Nathan
// Changes for the JTAG serial port module. Uncompiled, untestede. Removed CVS logs, minor fixes in comments.
//
// Revision 1.5 2010-01-13 00:55:45 Nathan
// Created hi-speed mode for burst reads. This will probably be most beneficial to the OR1K module, as GDB does a burst read of all the GPRs each time a microinstruction is single-stepped.
//
107,7 → 110,7
output top_inhibit_o;
input rst_i;
 
// WISHBONE master interface
// Interface to OR1200 debug unit
input cpu_clk_i; // 'bus' style interface to SPRs
output [31:0] cpu_addr_o;
input [31:0] cpu_data_i;
/rtl/verilog/adbg_jsp_module.v
0,0 → 1,574
//////////////////////////////////////////////////////////////////////
//// ////
//// adbg_jsp_module.v ////
//// ////
//// ////
//// This file is part of the SoC Advanced Debug Interface. ////
//// ////
//// Author(s): ////
//// Nathan Yawn (nathan.yawn@opencores.org) ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
`include "adbg_defines.v"
 
// Module interface
module adbg_jsp_module (
// JTAG signals
tck_i,
module_tdo_o,
tdi_i,
 
// TAP states
capture_dr_i,
shift_dr_i,
update_dr_i,
 
data_register_i, // the data register is at top level, shared between all modules
module_select_i,
top_inhibit_o,
rst_i,
 
// WISHBONE common signals
wb_clk_i, wb_rst_i,
 
// WISHBONE slave interface
wb_adr_i, wb_dat_o, wb_dat_i, wb_cyc_i, wb_stb_i, wb_sel_i,
wb_we_i, wb_ack_o, wb_cab_i, wb_err_o, wb_cti_i, wb_bte_i, int_o
);
 
// JTAG signals
input tck_i;
output module_tdo_o;
input tdi_i; // This is only used by the CRC module - data_register_i[MSB] is delayed a cycle
 
// TAP states
input capture_dr_i;
input shift_dr_i;
input update_dr_i;
 
input [52:0] data_register_i;
input module_select_i;
output top_inhibit_o;
input rst_i;
// WISHBONE slave interface
input wb_clk_i;
input wb_rst_i;
input [31:0] wb_adr_i;
output [31:0] wb_dat_o;
input [31:0] wb_dat_i;
input wb_cyc_i;
input wb_stb_i;
input [3:0] wb_sel_i;
input wb_we_i;
output wb_ack_o;
input wb_cab_i;
output wb_err_o;
input [2:0] wb_cti_i;
input [1:0] wb_bte_i;
output int_o;
// Declare inputs / outputs as wires / registers
wire module_tdo_o;
wire top_inhibit_o;
 
// NOTE: For the rest of this file, "input" and the "in" direction refer to bytes being transferred
// from the PC, through the JTAG, and into the BIU FIFO. The "output" direction refers to data being
// transferred from the BIU FIFO, through the JTAG to the PC.
// The read and write bit counts are separated to allow for JTAG chains with multiple devices.
// The read bit count starts right away (after a single throwaway bit), but the write count
// waits to receive a '1' start bit.
 
// Registers to hold state etc.
reg [3:0] read_bit_count; // How many bits have been shifted out
reg [3:0] write_bit_count; // How many bits have been shifted in
reg [3:0] input_word_count; // space (bytes) remaining in input FIFO (from JTAG)
reg [3:0] output_word_count; // bytes remaining in output FIFO (to JTAG)
reg [3:0] user_word_count; // bytes user intends to send from PC
reg [7:0] data_out_shift_reg; // parallel-load output shift register
 
 
// Control signals for the various counters / registers / state machines
reg rd_bit_ct_en; // enable bit counter
reg rd_bit_ct_rst; // reset (zero) bit count register
reg wr_bit_ct_en; // enable bit counter
reg wr_bit_ct_rst; // reset (zero) bit count register
reg in_word_ct_sel; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count
reg out_word_ct_sel; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count
reg in_word_ct_en; // Enable input byte counter register
reg out_word_ct_en; // Enable output byte count register
reg user_word_ct_en; // Enable user byte count registere
reg user_word_ct_sel; // selects data for user byte counter. 0 = user data, 1 = decremented byte count
reg out_reg_ld_en; // Enable parallel load of data_out_shift_reg
reg out_reg_shift_en; // Enable shift of data_out_shift_reg
reg out_reg_data_sel; // 0 = BIU data, 1 = byte count data (also from BIU)
reg biu_rd_strobe; // Indicates that the bus unit should ACK the last read operation + start another
reg biu_wr_strobe; // Indicates BIU should latch input + begin a write operation
 
 
// Status signals
wire in_word_count_zero; // true when input byte counter is zero
wire out_word_count_zero; // true when output byte counter is zero
wire user_word_count_zero; // true when user byte counter is zero
wire rd_bit_count_max; // true when bit counter is equal to current word size
wire wr_bit_count_max; // true when bit counter is equal to current word size
// Intermediate signals
wire [3:0] data_to_in_word_counter; // output of the mux in front of the input byte counter reg
wire [3:0] data_to_out_word_counter; // output of the mux in front of the output byte counter reg
wire [3:0] data_to_user_word_counter; // output of mux in front of user word counter
wire [3:0] decremented_in_word_count;
wire [3:0] decremented_out_word_count;
wire [3:0] decremented_user_word_count;
wire [3:0] count_data_in; // from data_register_i
wire [7:0] data_to_biu; // from data_register_i
wire [7:0] data_from_biu; // to data_out_shift_register
wire [3:0] biu_space_available;
wire [3:0] biu_bytes_available;
wire [7:0] count_data_from_biu; // combined space avail / bytes avail
wire [7:0] out_reg_data; // parallel input to the output shift register
 
 
/////////////////////////////////////////////////
// Combinatorial assignments
 
assign count_data_from_biu = {biu_bytes_available, biu_space_available};
assign count_data_in = {tdi_i, data_register_i[52:50]}; // Second nibble of user data
assign data_to_biu = {tdi_i,data_register_i[52:46]};
assign top_inhibit_o = 1'b0;
 
//////////////////////////////////////
// Input bit counter
 
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i) write_bit_count <= 4'h0;
else if(wr_bit_ct_rst) write_bit_count <= 4'h0;
else if(wr_bit_ct_en) write_bit_count <= write_bit_count + 4'h1;
end
 
assign wr_bit_count_max = (write_bit_count == 4'h7) ? 1'b1 : 1'b0;
 
//////////////////////////////////////
// Output bit counter
 
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i) read_bit_count <= 4'h0;
else if(rd_bit_ct_rst) read_bit_count <= 4'h0;
else if(rd_bit_ct_en) read_bit_count <= read_bit_count + 4'h1;
end
 
assign rd_bit_count_max = (read_bit_count == 4'h7) ? 1'b1 : 1'b0;
 
////////////////////////////////////////
// Input word counter
 
assign data_to_in_word_counter = (in_word_ct_sel) ? decremented_in_word_count : biu_space_available;
assign decremented_in_word_count = input_word_count - 4'h1;
 
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i)
input_word_count <= 4'h0;
else if(in_word_ct_en)
input_word_count <= data_to_in_word_counter;
end
 
assign in_word_count_zero = (input_word_count == 4'h0);
////////////////////////////////////////
// Output word counter
 
assign data_to_out_word_counter = (out_word_ct_sel) ? decremented_out_word_count : biu_bytes_available;
assign decremented_out_word_count = output_word_count - 4'h1;
 
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i)
output_word_count <= 4'h0;
else if(out_word_ct_en)
output_word_count <= data_to_out_word_counter;
end
 
assign out_word_count_zero = (output_word_count == 4'h0);
 
////////////////////////////////////////
// User word counter
 
assign data_to_user_word_counter = (user_word_ct_sel) ? decremented_user_word_count : count_data_in;
assign decremented_user_word_count = user_word_count - 4'h1;
 
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i) user_word_count <= 4'h0;
else if(user_word_ct_en) user_word_count <= data_to_user_word_counter;
end
 
assign user_word_count_zero = (user_word_count == 4'h0);
/////////////////////////////////////////////////////
// Output register and TDO output MUX
 
assign out_reg_data = (out_reg_data_sel) ? count_data_from_biu : data_from_biu;
 
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i) data_out_shift_reg <= 8'h0;
else if(out_reg_ld_en) data_out_shift_reg <= out_reg_data;
else if(out_reg_shift_en) data_out_shift_reg <= {1'b0, data_out_shift_reg[7:1]};
end
 
assign module_tdo_o = data_out_shift_reg[0];
////////////////////////////////////////
// Bus Interface Unit (to JTAG / WB UART)
// It is assumed that the BIU has internal registers, and will
// latch write data (and ack read data) on rising clock edge
// when strobe is asserted
 
adbg_jsp_biu jsp_biu_i (
// Debug interface signals
.tck_i (tck_i),
.rst_i (rst_i),
.data_i (data_to_biu),
.data_o (data_from_biu),
.bytes_available_o (biu_bytes_available),
.bytes_free_o (biu_space_available),
.rd_strobe_i (biu_rd_strobe),
.wr_strobe_i (biu_wr_strobe),
// Wishbone slave signals
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_i (wb_adr_i),
.wb_dat_o (wb_dat_o),
.wb_dat_i (wb_dat_i),
.wb_cyc_i (wb_cyc_i),
.wb_stb_i (wb_stb_i),
.wb_sel_i (wb_sel_i),
.wb_we_i (wb_we_i),
.wb_ack_o (wb_ack_o),
.wb_cab_i (wb_cab_i),
.wb_err_o (wb_err_o),
.wb_cti_i (wb_cti_i),
.wb_bte_i (wb_bte_i),
.int_o (int_o)
);
 
 
////////////////////////////////////////
// Input Control FSM
 
// Definition of machine state values.
// Don't worry too much about the state encoding, the synthesis tool
// will probably re-encode it anyway.
 
`define STATE_wr_idle 3'h0
`define STATE_wr_wait 3'h1
`define STATE_wr_counts 3'h2
`define STATE_wr_xfer 3'h3
 
reg [2:0] wr_module_state; // FSM state
reg [2:0] wr_module_next_state; // combinatorial signal, not actually a register
 
 
// sequential part of the FSM
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i)
wr_module_state <= `STATE_wr_idle;
else
wr_module_state <= wr_module_next_state;
end
 
 
// Determination of next state; purely combinatorial
always @ (wr_module_state or module_select_i or update_dr_i or capture_dr_i
or shift_dr_i or wr_bit_count_max or tdi_i)
begin
case(wr_module_state)
`STATE_wr_idle:
begin
`ifdef ADBG_JSP_SUPPORT_MULTI
if(module_select_i && capture_dr_i) wr_module_next_state <= `STATE_wr_wait;
`else
if(module_select_i && capture_dr_i) wr_module_next_state <= `STATE_wr_counts;
`endif
else wr_module_next_state <= `STATE_wr_idle;
end
`STATE_wr_wait:
begin
if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
else if(module_select_i && tdi_i) wr_module_next_state <= `STATE_wr_counts; // got start bit
else wr_module_next_state <= `STATE_wr_wait;
end
`STATE_wr_counts:
begin
if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
else if(wr_bit_count_max) wr_module_next_state <= `STATE_wr_xfer;
else wr_module_next_state <= `STATE_wr_counts;
end
 
`STATE_wr_xfer:
begin
if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
else wr_module_next_state <= `STATE_wr_xfer;
end
default: wr_module_next_state <= `STATE_wr_idle; // shouldn't actually happen...
endcase
end
 
// Outputs of state machine, pure combinatorial
always @ (wr_module_state or wr_module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i
or in_word_count_zero or out_word_count_zero or wr_bit_count_max or decremented_in_word_count
or decremented_out_word_count)
begin
// Default everything to 0, keeps the case statement simple
wr_bit_ct_en <= 1'b0; // enable bit counter
wr_bit_ct_rst <= 1'b0; // reset (zero) bit count register
in_word_ct_sel <= 1'b0; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count
user_word_ct_sel <= 1'b0; // selects data for user byte counter, 0 = user data, 1 = decremented count
in_word_ct_en <= 1'b0; // Enable input byte counter register
user_word_ct_en <= 1'b0; // enable user byte count register
biu_wr_strobe <= 1'b0; // Indicates BIU should latch input + begin a write operation
case(wr_module_state)
`STATE_wr_idle:
begin
in_word_ct_sel <= 1'b0;
// Going to transfer; enable count registers and output register
if(wr_module_next_state != `STATE_wr_idle) begin
wr_bit_ct_rst <= 1'b1;
in_word_ct_en <= 1'b1;
end
end
 
// This state is only used when support for multi-device JTAG chains is enabled.
`STATE_wr_wait:
begin
wr_bit_ct_en <= 1'b0; // Don't do anything, just wait for the start bit.
end
 
`STATE_wr_counts:
begin
if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states...
wr_bit_ct_en <= 1'b1;
user_word_ct_sel <= 1'b0;
if(wr_bit_count_max) begin
wr_bit_ct_rst <= 1'b1;
user_word_ct_en <= 1'b1;
end
end
end
`STATE_wr_xfer:
begin
if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states
wr_bit_ct_en <= 1'b1;
in_word_ct_sel <= 1'b1;
user_word_ct_sel <= 1'b1;
if(wr_bit_count_max) begin // Start biu transactions, if word counts allow
wr_bit_ct_rst <= 1'b1;
if(!(in_word_count_zero || user_word_count_zero)) begin
biu_wr_strobe <= 1'b1;
in_word_ct_en <= 1'b1;
user_word_ct_en <= 1'b1;
end
 
end
end
end
 
default: ;
endcase
end
 
////////////////////////////////////////
// Output Control FSM
 
// Definition of machine state values.
// Don't worry too much about the state encoding, the synthesis tool
// will probably re-encode it anyway.
 
`define STATE_rd_idle 4'h0
`define STATE_rd_counts 4'h1
`define STATE_rd_rdack 4'h2
`define STATE_rd_xfer 4'h3
 
// We do not send the equivalent of a 'start bit' (like the one the input FSM
// waits for when support for multi-device JTAG chains is enabled). Since the
// input and output are going to be offset anyway, why bother...
 
reg [2:0] rd_module_state; // FSM state
reg [2:0] rd_module_next_state; // combinatorial signal, not actually a register
 
 
// sequential part of the FSM
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i)
rd_module_state <= `STATE_rd_idle;
else
rd_module_state <= rd_module_next_state;
end
 
 
// Determination of next state; purely combinatorial
always @ (rd_module_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i or rd_bit_count_max)
begin
case(rd_module_state)
`STATE_rd_idle:
begin
if(module_select_i && capture_dr_i) rd_module_next_state <= `STATE_rd_counts;
else rd_module_next_state <= `STATE_rd_idle;
end
`STATE_rd_counts:
begin
if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
else if(rd_bit_count_max) rd_module_next_state <= `STATE_rd_rdack;
else rd_module_next_state <= `STATE_rd_counts;
end
`STATE_rd_rdack:
begin
if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
else rd_module_next_state <= `STATE_rd_xfer;
end
`STATE_rd_xfer:
begin
if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
else if(rd_bit_count_max) rd_module_next_state <= `STATE_rd_rdack;
else rd_module_next_state <= `STATE_rd_xfer;
end
default: rd_module_next_state <= `STATE_rd_idle; // shouldn't actually happen...
endcase
end
 
// Outputs of state machine, pure combinatorial
always @ (rd_module_state or rd_module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i
or in_word_count_zero or out_word_count_zero or rd_bit_count_max or decremented_in_word_count
or decremented_out_word_count)
begin
// Default everything to 0, keeps the case statement simple
rd_bit_ct_en <= 1'b0; // enable bit counter
rd_bit_ct_rst <= 1'b0; // reset (zero) bit count register
out_word_ct_sel <= 1'b0; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count
out_word_ct_en <= 1'b0; // Enable output byte count register
out_reg_ld_en <= 1'b0; // Enable parallel load of data_out_shift_reg
out_reg_shift_en <= 1'b0; // Enable shift of data_out_shift_reg
out_reg_data_sel <= 1'b0; // 0 = BIU data, 1 = byte count data (also from BIU)
biu_rd_strobe <= 1'b0; // Indicates that the bus unit should ACK the last read operation + start another
case(rd_module_state)
`STATE_rd_idle:
begin
out_reg_data_sel <= 1'b1;
out_word_ct_sel <= 1'b0;
// Going to transfer; enable count registers and output register
if(rd_module_next_state != `STATE_rd_idle) begin
out_reg_ld_en <= 1'b1;
rd_bit_ct_rst <= 1'b1;
out_word_ct_en <= 1'b1;
end
end
 
`STATE_rd_counts:
begin
if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states...
rd_bit_ct_en <= 1'b1;
out_reg_shift_en <= 1'b1;
if(rd_bit_count_max) begin
rd_bit_ct_rst <= 1'b1;
// Latch the next output word, but don't ack until STATE_rd_rdack
if(!out_word_count_zero) begin
out_reg_ld_en <= 1'b1;
out_reg_shift_en <= 1'b0;
end
end
end
end
`STATE_rd_rdack:
begin
if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states
rd_bit_ct_en <= 1'b1;
out_reg_shift_en <= 1'b1;
out_reg_data_sel <= 1'b0;
// Never have to worry about bit_count_max here.
if(!out_word_count_zero) begin
biu_rd_strobe <= 1'b1;
end
end
end
`STATE_rd_xfer:
begin
if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states
rd_bit_ct_en <= 1'b1;
out_word_ct_sel <= 1'b1;
out_reg_shift_en <= 1'b1;
out_reg_data_sel <= 1'b0;
if(rd_bit_count_max) begin // Start biu transaction, if word count allows
rd_bit_ct_rst <= 1'b1;
 
// Don't ack the read byte here, we do it in STATE_rdack
if(!out_word_count_zero) begin
out_reg_ld_en <= 1'b1;
out_reg_shift_en <= 1'b0;
out_word_ct_en <= 1'b1;
end
end
end
end
 
default: ;
endcase
end
 
 
endmodule
 
/rtl/verilog/adbg_top.v
36,32 → 36,6
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: adbg_top.v,v $
// Revision 1.3 2010-01-10 22:54:11 Nathan
// Update copyright dates
//
// Revision 1.2 2009/05/17 20:54:56 Nathan
// Changed email address to opencores.org
//
// Revision 1.1 2008/07/22 20:28:32 Nathan
// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
//
// Revision 1.10 2008/07/11 08:13:29 Nathan
// Latch opcode on posedge, like other signals. This fixes a problem
// when the module is used with a Xilinx BSCAN TAP. Added signals to
// allow modules to inhibit latching of a new active module by the top
// module. This allows the sub-modules to force the top level module
// to ignore the command present in the input shift register after e.g.
// a burst read.
//
// Revision 1.7 2008/06/30 20:09:20 Nathan
// Removed code to select top-level module as active (it served no
// purpose). Re-numbered modules, requiring changes to testbench and
// software driver.
//
 
 
`include "adbg_defines.v"
90,7 → 64,8
// WISHBONE common signals
,
wb_clk_i,
 
wb_rst_i,
// WISHBONE master interface
wb_adr_o,
wb_dat_o,
135,7 → 110,30
cpu1_ack_i,
cpu1_rst_o
`endif
 
`ifdef DBG_JSP_SUPPORTED
,
`ifndef DBG_WISHBONE_SUPPORTED
wb_clk_i,
wb_rst_i,
`endif
// WISHBONE target interface
wb_jsp_adr_i,
wb_jsp_dat_o,
wb_jsp_dat_i,
wb_jsp_cyc_i,
wb_jsp_stb_i,
wb_jsp_sel_i,
wb_jsp_we_i,
wb_jsp_ack_o,
wb_jsp_cab_i,
wb_jsp_err_o,
wb_jsp_cti_i,
wb_jsp_bte_i,
int_o
`endif
);
 
 
154,8 → 152,9
// Module select from TAP
input debug_select_i;
 
`ifdef DBG_WISHBONE_SUPPORTED
`ifdef DBG_WISHBONE_SUPPORTED
input wb_clk_i;
input wb_rst_i;
output [31:0] wb_adr_o;
output [31:0] wb_dat_o;
input [31:0] wb_dat_i;
168,9 → 167,9
input wb_err_i;
output [2:0] wb_cti_o;
output [1:0] wb_bte_o;
`endif
`endif
 
`ifdef DBG_CPU0_SUPPORTED
`ifdef DBG_CPU0_SUPPORTED
// CPU signals
input cpu0_clk_i;
output [31:0] cpu0_addr_o;
182,9 → 181,9
output cpu0_we_o;
input cpu0_ack_i;
output cpu0_rst_o;
`endif
`endif
 
`ifdef DBG_CPU1_SUPPORTED
`ifdef DBG_CPU1_SUPPORTED
input cpu1_clk_i;
output [31:0] cpu1_addr_o;
input [31:0] cpu1_data_i;
195,15 → 194,34
output cpu1_we_o;
input cpu1_ack_i;
output cpu1_rst_o;
`endif
`endif
 
 
`ifdef DBG_JSP_SUPPORTED
`ifndef DBG_WISHBONE_SUPPORTED
input wb_clk_i;
input wb_rst_i;
`endif
input [31:0] wb_jsp_adr_i;
output [31:0] wb_jsp_dat_o;
input [31:0] wb_jsp_dat_i;
input wb_jsp_cyc_i;
input wb_jsp_stb_i;
input [3:0] wb_jsp_sel_i;
input wb_jsp_we_i;
output wb_jsp_ack_o;
input wb_jsp_cab_i;
output wb_jsp_err_o;
input [2:0] wb_jsp_cti_i;
input [1:0] wb_jsp_bte_i;
output int_o;
`endif
reg tdo_o;
wire tdo_wb;
wire tdo_cpu0;
wire tdo_cpu1;
wire tdo_jsp;
 
 
// Registers
reg [`DBG_TOP_MODULE_DATA_LEN-1:0] input_shift_reg; // 1 bit sel/cmd, 4 bit opcode, 32 bit address, 16 bit length = 53 bits
//reg output_shift_reg; // Just 1 bit for status (valid module selected)
215,7 → 233,7
wire [(`DBG_TOP_MODULE_ID_LENGTH - 1) : 0] module_id_in; // The part of the input_shift_register to be used as the module select data
reg [(`DBG_TOP_MAX_MODULES - 1) : 0] module_selects; // Select signals for the individual modules
wire select_inhibit; // OR of inhibit signals from sub-modules, prevents latching of a new module ID
wire [2:0] module_inhibit; // signals to allow submodules to prevent top level from latching new module ID
wire [3:0] module_inhibit; // signals to allow submodules to prevent top level from latching new module ID
 
///////////////////////////////////////
// Combinatorial assignments
336,7 → 354,7
 
`ifdef DBG_CPU1_SUPPORTED
// Connecting cpu module
adbg_or1k_module i_dbg_cpu_8051 (
adbg_or1k_module i_dbg_cpu_2 (
// JTAG signals
.tck_i (tck_i),
.module_tdo_o (tdo_cpu1),
369,20 → 387,62
assign module_inhibit[`DBG_TOP_CPU1_DEBUG_MODULE] = 1'b0;
`endif
 
`ifdef DBG_JSP_SUPPORTED
adbg_jsp_module i_dbg_jsp (
// JTAG signals
.tck_i (tck_i),
.module_tdo_o (tdo_jsp),
.tdi_i (tdi_i),
 
// TAP states
.capture_dr_i (capture_dr_i),
.shift_dr_i (shift_dr_i),
.update_dr_i (update_dr_i),
 
.data_register_i (input_shift_reg),
.module_select_i (module_selects[`DBG_TOP_JSP_DEBUG_MODULE]),
.top_inhibit_o (module_inhibit[`DBG_TOP_JSP_DEBUG_MODULE]),
.rst_i (rst_i),
 
// WISHBONE common signals
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
// WISHBONE master interface
.wb_adr_i (wb_jsp_adr_i),
.wb_dat_o (wb_jsp_dat_o),
.wb_dat_i (wb_jsp_dat_i),
.wb_cyc_i (wb_jsp_cyc_i),
.wb_stb_i (wb_jsp_stb_i),
.wb_sel_i (wb_jsp_sel_i),
.wb_we_i (wb_jsp_we_i),
.wb_ack_o (wb_jsp_ack_o),
.wb_cab_i (wb_jsp_cab_i),
.wb_err_o (wb_jsp_err_o),
.wb_cti_i (wb_jsp_cti_i),
.wb_bte_i (wb_jsp_bte_i),
.int_o (int_o)
);
`else
assign tdo_jsp = 1'b0;
assign module_inhibit[`DBG_TOP_JSP_DEBUG_MODULE] = 1'b0;
`endif
assign select_inhibit = |module_inhibit;
 
/////////////////////////////////////////////////
// TDO output MUX
 
always @ (module_id_reg or tdo_wb or tdo_cpu0 or tdo_cpu1)
always @ (module_id_reg or tdo_wb or tdo_cpu0 or tdo_cpu1 or tdo_jsp)
begin
case (module_id_reg)
`DBG_TOP_WISHBONE_DEBUG_MODULE: tdo_o <= tdo_wb;
`DBG_TOP_CPU0_DEBUG_MODULE: tdo_o <= tdo_cpu0;
`DBG_TOP_CPU1_DEBUG_MODULE: tdo_o <= tdo_cpu1;
default: tdo_o <= 1'b0;
endcase
 
case (module_id_reg)
`DBG_TOP_WISHBONE_DEBUG_MODULE: tdo_o <= tdo_wb;
`DBG_TOP_CPU0_DEBUG_MODULE: tdo_o <= tdo_cpu0;
`DBG_TOP_CPU1_DEBUG_MODULE: tdo_o <= tdo_cpu1;
`DBG_TOP_JSP_DEBUG_MODULE: tdo_o <= tdo_jsp;
default: tdo_o <= 1'b0;
endcase
end
 
 
/rtl/verilog/adbg_wb_biu.v
40,6 → 40,9
// CVS Revision History
//
// $Log: adbg_wb_biu.v,v $
// Revision 1.5 2010-03-21 01:05:10 Nathan
// Use all 32 address bits - WishBone slaves may use the 2 least-significant address bits instead of the four wb_sel lines, or in addition to them.
//
// Revision 1.4 2010-01-10 22:54:11 Nathan
// Update copyright dates
//
135,7 → 138,7
 
// Registers
reg [3:0] sel_reg;
reg [29:0] addr_reg; // Don't need the two LSB, this info is in the SEL bits
reg [31:0] addr_reg; // Don't really need the two LSB, this info is in the SEL bits
reg [31:0] data_in_reg; // dbg->WB
reg [31:0] data_out_reg; // WB->dbg
reg wr_reg;
239,7 → 242,7
begin
if(rst_i) begin
sel_reg <= 4'h0;
addr_reg <= 30'h0;
addr_reg <= 32'h0;
data_in_reg <= 32'h0;
wr_reg <= 1'b0;
end
246,7 → 249,7
else
if(strobe_i && rdy_o) begin
sel_reg <= be_dec;
addr_reg <= addr_i[31:2];
addr_reg <= addr_i;
if(!rd_wrn_i) data_in_reg <= swapped_data_i;
wr_reg <= ~rd_wrn_i;
end
285,7 → 288,7
 
assign wb_dat_o = data_in_reg;
assign wb_we_o = wr_reg;
assign wb_adr_o = {addr_reg, 2'h0};
assign wb_adr_o = addr_reg;
assign wb_sel_o = sel_reg;
 
assign data_o = data_out_reg;
/rtl/verilog/bytefifo.v
0,0 → 1,225
//////////////////////////////////////////////////////////////////////
//// ////
//// bytefifo.v ////
//// ////
//// ////
//// A simple byte-wide FIFO with byte and free space counts ////
//// ////
//// Author(s): ////
//// Nathan Yawn (nathan.yawn@opencores.org) ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// This is an 8-entry, byte-wide, single-port FIFO. It can either
// push or pop a byte each clock cycle (but not both). It includes
// outputs indicating the number of bytes in the FIFO, and the number
// of bytes free - if you don't connect BYTES_FREE, the synthesis
// tool should eliminate the hardware to generate it.
//
// This attempts to use few resources. There is only 1 counter,
// and only 1 decoder. The FIFO works like a big shift register:
// bytes are always written to entry '0' of the FIFO, and older
// bytes are shifted toward entry '7' as newer bytes are added.
// The counter determines which entry the output reads.
//
// One caveat is that the DATA_OUT will glitch during a 'push'
// operation. If the output is being sent to another clock
// domain, you should register it first.
//
// Ports:
// CLK: Clock for all synchronous elements
// RST: Zeros the counter and all registers asynchronously
// DATA_IN: Data to be pushed into the FIFO
// DATA_OUT: Always shows the data at the head of the FIFO, 'XX' if empty
// PUSH_POPn: When high (and EN is high), DATA_IN will be pushed onto the
// FIFO and the count will be incremented at the next posedge
// of CLK (assuming the FIFO is not full). When low (and EN
// is high), the count will be decremented and the output changed
// to the next value in the FIFO (assuming FIFO not empty).
// EN: When high at posedege CLK, a push or pop operation will be performed,
// based on the value of PUSH_POPn, assuming sufficient data or space.
// BYTES_AVAIL: Number of bytes in the FIFO. May be in the range 0 to 8.
// BYTES_FREE: Free space in the FIFO. May be in the range 0 to 8.
 
 
// Top module
module bytefifo (
CLK,
RST,
DATA_IN,
DATA_OUT,
PUSH_POPn,
EN,
BYTES_AVAIL,
BYTES_FREE
);
 
 
input CLK;
input RST;
input [7:0] DATA_IN;
output [7:0] DATA_OUT;
input PUSH_POPn;
input EN;
output [3:0] BYTES_AVAIL;
output [3:0] BYTES_FREE;
 
reg [7:0] reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7;
reg [3:0] counter;
reg [7:0] DATA_OUT;
wire [3:0] BYTES_AVAIL;
wire [3:0] BYTES_FREE;
wire push_ok;
wire pop_ok;
///////////////////////////////////
// Combinatorial assignments
assign BYTES_AVAIL = counter;
assign BYTES_FREE = 4'h8 - BYTES_AVAIL;
assign push_ok = !(counter == 4'h8);
assign pop_ok = !(counter == 4'h0);
///////////////////////////////////
// FIFO memory / shift registers
// Reg 0 - takes input from DATA_IN
always @ (posedge CLK or posedge RST)
begin
if(RST)
reg0 <= 8'h0;
else if(EN & PUSH_POPn & push_ok)
reg0 <= DATA_IN;
end
 
 
// Reg 1 - takes input from reg0
always @ (posedge CLK or posedge RST)
begin
if(RST)
reg1 <= 8'h0;
else if(EN & PUSH_POPn & push_ok)
reg1 <= reg0;
end
 
// Reg 2 - takes input from reg1
always @ (posedge CLK or posedge RST)
begin
if(RST)
reg2 <= 8'h0;
else if(EN & PUSH_POPn & push_ok)
reg2 <= reg1;
end
 
// Reg 3 - takes input from reg2
always @ (posedge CLK or posedge RST)
begin
if(RST)
reg3 <= 8'h0;
else if(EN & PUSH_POPn & push_ok)
reg3 <= reg2;
end
 
// Reg 4 - takes input from reg3
always @ (posedge CLK or posedge RST)
begin
if(RST)
reg4 <= 8'h0;
else if(EN & PUSH_POPn & push_ok)
reg4 <= reg3;
end
 
// Reg 5 - takes input from reg4
always @ (posedge CLK or posedge RST)
begin
if(RST)
reg5 <= 8'h0;
else if(EN & PUSH_POPn & push_ok)
reg5 <= reg4;
end
 
// Reg 6 - takes input from reg5
always @ (posedge CLK or posedge RST)
begin
if(RST)
reg6 <= 8'h0;
else if(EN & PUSH_POPn & push_ok)
reg6 <= reg5;
end
 
// Reg 7 - takes input from reg6
always @ (posedge CLK or posedge RST)
begin
if(RST)
reg7 <= 8'h0;
else if(EN & PUSH_POPn & push_ok)
reg7 <= reg6;
end
 
///////////////////////////////////////////////////
// Read counter
// This is a 4-bit saturating up/down counter
// The 'saturating' is done via push_ok and pop_ok
always @ (posedge CLK or posedge RST)
begin
if(RST) counter <= 4'h0;
else if(EN & PUSH_POPn & push_ok) counter <= counter + 4'h1;
else if(EN & (~PUSH_POPn) & pop_ok) counter <= counter - 4'h1;
end
 
/////////////////////////////////////////////////
// Output decoder
always @ (counter or reg0 or reg1 or reg2 or reg3 or reg4 or reg5
or reg6 or reg7)
begin
case (counter)
4'h1: DATA_OUT <= reg0;
4'h2: DATA_OUT <= reg1;
4'h3: DATA_OUT <= reg2;
4'h4: DATA_OUT <= reg3;
4'h5: DATA_OUT <= reg4;
4'h6: DATA_OUT <= reg5;
4'h7: DATA_OUT <= reg6;
4'h8: DATA_OUT <= reg7;
default: DATA_OUT <= 8'hXX;
endcase
end
 
endmodule
/rtl/verilog/adbg_jsp_biu.v
0,0 → 1,530
//////////////////////////////////////////////////////////////////////
//// ////
//// adbg_jsp_biu.v ////
//// ////
//// ////
//// This file is part of the SoC Debug Interface. ////
//// ////
//// Author(s): ////
//// Nathan Yawn (nathan.yawn@opencores.org) ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// This is where the magic happens in the JTAG Serial Port. The serial
// port FIFOs and counters are kept in the WishBone clock domain.
// 'Syncflop' elements are used to synchronize strobe lines across
// clock domains, and 'syncreg' elements keep the byte and free count
// as current as possible in the JTAG clock domain. Also in the WB
// clock domain is a WishBone target interface, which more or less
// tries to emulate a 16550 without FIFOs (despite the fact that
// FIFOs are actually present, they are opaque to the WB interface.)
//
 
 
// Top module
module adbg_jsp_biu
(
// Debug interface signals
tck_i,
rst_i,
data_i,
data_o,
bytes_available_o,
bytes_free_o,
rd_strobe_i,
wr_strobe_i,
 
// Wishbone signals
wb_clk_i,
wb_rst_i,
wb_adr_i,
wb_dat_o,
wb_dat_i,
wb_cyc_i,
wb_stb_i,
wb_sel_i,
wb_we_i,
wb_ack_o,
wb_cab_i,
wb_err_o,
wb_cti_i,
wb_bte_i,
int_o
);
 
// Debug interface signals
input tck_i;
input rst_i;
input [7:0] data_i; // Assume short words are in UPPER order bits!
output [7:0] data_o;
output [3:0] bytes_free_o;
output [3:0] bytes_available_o;
input rd_strobe_i;
input wr_strobe_i;
 
// Wishbone signals
input wb_clk_i;
input wb_rst_i;
input [31:0] wb_adr_i;
output [31:0] wb_dat_o;
input [31:0] wb_dat_i;
input wb_cyc_i;
input wb_stb_i;
input [3:0] wb_sel_i;
input wb_we_i;
output wb_ack_o;
input wb_cab_i;
output wb_err_o;
input [2:0] wb_cti_i;
input [1:0] wb_bte_i;
output int_o;
wire wb_ack_o;
wire [31:0] wb_dat_o;
wire wb_err_o;
wire int_o;
 
wire [7:0] data_o;
wire [3:0] bytes_free_o;
wire [3:0] bytes_available_o;
// Registers
reg [7:0] data_in;
reg [7:0] rdata;
reg wen_tff;
reg ren_tff;
// Wires
wire wb_fifo_ack;
wire [3:0] wr_bytes_free;
wire [3:0] rd_bytes_avail;
wire [3:0] wr_bytes_avail; // used to generate wr_fifo_not_empty
wire rd_bytes_avail_not_zero;
wire ren_sff_out;
wire [7:0] rd_fifo_data_out;
wire [7:0] data_to_wb;
wire [7:0] data_from_wb;
wire wr_fifo_not_empty; // this is for the WishBone interface LSR register
wire rcvr_fifo_rst; // rcvr in the WB sense, opposite most of the rest of this file
wire xmit_fifo_rst; // ditto
// Control Signals (FSM outputs)
reg wda_rst; // reset wdata_avail SFF
reg wpp; // Write FIFO PUSH (1) or POP (0)
reg w_fifo_en; // Enable write FIFO
reg ren_rst; // reset 'pop' SFF
reg rdata_en; // enable 'rdata' register
reg rpp; // read FIFO PUSH (1) or POP (0)
reg r_fifo_en; // enable read FIFO
reg r_wb_ack; // read FSM acks WB transaction
reg w_wb_ack; // write FSM acks WB transaction
 
// Indicators to FSMs
wire wdata_avail; // JTAG side has data available
wire wb_rd; // WishBone requests read
wire wb_wr; // WishBone requests write
wire pop; // JTAG side received a byte, pop and get next
wire rcz; // zero bytes available in read FIFO
 
//////////////////////////////////////////////////////
// TCK clock domain
// There is no FSM here, just signal latching and clock
// domain synchronization
 
assign data_o = rdata;
 
// Write enable (WEN) toggle FF
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i) wen_tff <= 1'b0;
else if(wr_strobe_i) wen_tff <= ~wen_tff;
end
 
 
// Read enable (REN) toggle FF
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i) ren_tff <= 1'b0;
else if(rd_strobe_i) ren_tff <= ~ren_tff;
end
 
// Write data register
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i) data_in <= 8'h0;
else if(wr_strobe_i) data_in <= data_i;
end
 
///////////////////////////////////////////////////////
// Wishbone clock domain
 
// Combinatorial assignments
assign rd_bytes_avail_not_zero = !(rd_bytes_avail == 4'h0);
assign pop = ren_sff_out & rd_bytes_avail_not_zero;
assign rcz = ~rd_bytes_avail_not_zero;
assign wb_fifo_ack = r_wb_ack | w_wb_ack;
assign wr_fifo_not_empty = !(wr_bytes_avail == 4'h0);
// rdata register
always @ (posedge wb_clk_i or posedge rst_i)
begin
if(rst_i) rdata <= 8'h0;
else if(rdata_en) rdata <= rd_fifo_data_out;
end
// WEN SFF
syncflop wen_sff (
.DEST_CLK(wb_clk_i),
.D_SET(1'b0),
.D_RST(wda_rst),
.RESET(rst_i),
.TOGGLE_IN(wen_tff),
.D_OUT(wdata_avail)
);
// REN SFF
syncflop ren_sff (
.DEST_CLK(wb_clk_i),
.D_SET(1'b0),
.D_RST(ren_rst),
.RESET(rst_i),
.TOGGLE_IN(ren_tff),
.D_OUT(ren_sff_out)
);
// 'free space available' syncreg
syncreg freespace_syncreg (
.CLKA(wb_clk_i),
.CLKB(tck_i),
.RST(rst_i),
.DATA_IN(wr_bytes_free),
.DATA_OUT(bytes_free_o)
);
// 'bytes available' syncreg
syncreg bytesavail_syncreg (
.CLKA(wb_clk_i),
.CLKB(tck_i),
.RST(rst_i),
.DATA_IN(rd_bytes_avail),
.DATA_OUT(bytes_available_o)
);
// write FIFO
bytefifo wr_fifo (
.CLK(wb_clk_i),
.RST(rst_i | rcvr_fifo_rst), // rst_i from JTAG clk domain, rcvr_fifo_rst from WB, RST is async reset
.DATA_IN(data_in),
.DATA_OUT(data_to_wb),
.PUSH_POPn(wpp),
.EN(w_fifo_en),
.BYTES_AVAIL(wr_bytes_avail),
.BYTES_FREE(wr_bytes_free)
);
// read FIFO
bytefifo rd_fifo (
.CLK(wb_clk_i),
.RST(rst_i | xmit_fifo_rst), // rst_i from JTAG clk domain, xmit_fifo_rst from WB, RST is async reset
.DATA_IN(data_from_wb),
.DATA_OUT(rd_fifo_data_out),
.PUSH_POPn(rpp),
.EN(r_fifo_en),
.BYTES_AVAIL(rd_bytes_avail),
.BYTES_FREE()
);
 
/////////////////////////////////////////////////////
// State machine for the read FIFO
 
reg [1:0] rd_fsm_state;
reg [1:0] next_rd_fsm_state;
 
`define STATE_RD_IDLE 2'h0
`define STATE_RD_PUSH 2'h1
`define STATE_RD_POP 2'h2
`define STATE_RD_LATCH 2'h3
// Sequential bit
always @ (posedge wb_clk_i or posedge rst_i)
begin
if(rst_i) rd_fsm_state <= `STATE_RD_IDLE;
else rd_fsm_state <= next_rd_fsm_state;
end
 
// Determination of next state (combinatorial)
always @ (rd_fsm_state or wb_wr or pop or rcz)
begin
case (rd_fsm_state)
`STATE_RD_IDLE:
begin
if(wb_wr) next_rd_fsm_state <= `STATE_RD_PUSH;
else if (pop) next_rd_fsm_state <= `STATE_RD_POP;
else next_rd_fsm_state <= `STATE_RD_IDLE;
end
`STATE_RD_PUSH:
begin
if(rcz) next_rd_fsm_state <= `STATE_RD_LATCH; // putting first item in fifo, move to rdata in state LATCH
else if(pop) next_rd_fsm_state <= `STATE_RD_POP;
else next_rd_fsm_state <= `STATE_RD_IDLE;
end
`STATE_RD_POP:
begin
next_rd_fsm_state <= `STATE_RD_LATCH; // new data at FIFO head, move to rdata in state LATCH
end
`STATE_RD_LATCH:
begin
if(wb_wr) next_rd_fsm_state <= `STATE_RD_PUSH;
else if(pop) next_rd_fsm_state <= `STATE_RD_POP;
else next_rd_fsm_state <= `STATE_RD_IDLE;
end
default:
begin
next_rd_fsm_state <= `STATE_RD_IDLE;
end
endcase
end
 
// Outputs of state machine (combinatorial)
always @ (rd_fsm_state)
begin
ren_rst <= 1'b0;
rpp <= 1'b0;
r_fifo_en <= 1'b0;
rdata_en <= 1'b0;
r_wb_ack <= 1'b0;
case (rd_fsm_state)
`STATE_RD_IDLE:;
 
`STATE_RD_PUSH:
begin
rpp <= 1'b1;
r_fifo_en <= 1'b1;
r_wb_ack <= 1'b1;
end
`STATE_RD_POP:
begin
ren_rst <= 1'b1;
r_fifo_en <= 1'b1;
end
`STATE_RD_LATCH:
begin
rdata_en <= 1'b1;
end
endcase
end
 
 
/////////////////////////////////////////////////////
// State machine for the write FIFO
 
reg [1:0] wr_fsm_state;
reg [1:0] next_wr_fsm_state;
 
`define STATE_WR_IDLE 2'h0
`define STATE_WR_PUSH 2'h1
`define STATE_WR_POP 2'h2
 
// Sequential bit
always @ (posedge wb_clk_i or posedge rst_i)
begin
if(rst_i) wr_fsm_state <= `STATE_WR_IDLE;
else wr_fsm_state <= next_wr_fsm_state;
end
 
// Determination of next state (combinatorial)
always @ (wr_fsm_state or wb_rd or wdata_avail)
begin
case (wr_fsm_state)
 
`STATE_WR_IDLE:
begin
if(wb_rd) next_wr_fsm_state <= `STATE_WR_POP;
else if (wdata_avail) next_wr_fsm_state <= `STATE_WR_PUSH;
else next_wr_fsm_state <= `STATE_WR_IDLE;
end
 
`STATE_WR_PUSH:
begin
if(wb_rd) next_wr_fsm_state <= `STATE_WR_POP;
else next_wr_fsm_state <= `STATE_WR_IDLE;
end
 
`STATE_WR_POP:
begin
if(wdata_avail) next_wr_fsm_state <= `STATE_WR_PUSH;
else next_wr_fsm_state <= `STATE_WR_IDLE;
end
 
default:
begin
next_wr_fsm_state <= `STATE_WR_IDLE;
end
endcase
end
 
// Outputs of state machine (combinatorial)
always @ (wr_fsm_state)
begin
wda_rst <= 1'b0;
wpp <= 1'b0;
w_fifo_en <= 1'b0;
w_wb_ack <= 1'b0;
case (wr_fsm_state)
`STATE_WR_IDLE:;
 
`STATE_WR_PUSH:
begin
wda_rst <= 1'b1;
wpp <= 1'b1;
w_fifo_en <= 1'b1;
end
`STATE_WR_POP:
begin
w_wb_ack <= 1'b1;
w_fifo_en <= 1'b1;
end
endcase
 
end
 
////////////////////////////////////////////////////////////
// WishBone interface hardware
// Interface signals to read and write fifos:
// wb_rd: read strobe
// wb_wr: write strobe
// wb_fifo_ack: fifo has completed operation
 
wire [31:0] bus_data_lo;
wire [31:0] bus_data_hi;
wire wb_reg_ack;
wire rd_fifo_not_full; // "rd fifo" is the one the WB writes to
reg [2:0] iir_gen; // actually combinatorial
wire rd_fifo_becoming_empty;
// These 16550 registers are at least partly implemented
reg reg_dlab_bit; // part of the LCR
reg [3:0] reg_ier;
wire [2:0] reg_iir;
reg thr_int_arm; // used so that an IIR read can clear a transmit interrupt
wire [7:0] reg_lsr;
wire reg_dlab_bit_wren;
wire reg_ier_wren;
wire reg_iir_rden;
wire [7:0] reg_lcr; // the DLAB bit above is the 8th bit
wire reg_fcr_wren; // FCR is WR-only, at the same address as the IIR (contains SW reset bits)
// These 16550 registers are not implemented here
wire [7:0] reg_mcr;
wire [7:0] reg_msr;
wire [7:0] reg_scr;
 
// Create handshake signals to/from the FIFOs
assign wb_rd = wb_cyc_i & wb_stb_i & (~wb_we_i) & wb_sel_i[3] & (wb_adr_i[1:0] == 2'b00) & (~reg_dlab_bit);
assign wb_wr = wb_cyc_i & wb_stb_i & wb_we_i & wb_sel_i[3] & (wb_adr_i[1:0] == 2'b00) & (~reg_dlab_bit);
assign wb_ack_o = wb_fifo_ack | wb_reg_ack;
assign wb_err_o = 1'b0;
// Assign the unimplemented registers
assign reg_mcr = 8'h00; // These bits control modem control lines, unused here
assign reg_msr = 8'hB0; // CD, DSR, CTS true, RI false, no changes indicated
assign reg_scr = 8'h00; // scratch register.
// Create the simple / combinatorial registers
assign rd_fifo_not_full = !(rd_bytes_avail == 4'h8);
assign reg_lcr = {reg_dlab_bit, 7'h03}; // Always set for 8n1
assign reg_lsr = {1'b0, rd_fifo_not_full, rd_fifo_not_full, 4'b0000, wr_fifo_not_empty};
// Create enable bits for the 16550 registers that we actually implement
assign reg_dlab_bit_wren = wb_cyc_i & wb_stb_i & wb_we_i & wb_sel_i[0] & (wb_adr_i[2:0] == 3'b011);
assign reg_ier_wren = wb_cyc_i & wb_stb_i & wb_we_i & wb_sel_i[2] & (wb_adr_i[2:0] == 3'b001) & (~reg_dlab_bit);
assign reg_iir_rden = wb_cyc_i & wb_stb_i & (~wb_we_i) & wb_sel_i[1] & (wb_adr_i[2:0] == 3'b010);
assign wb_reg_ack = wb_cyc_i & wb_stb_i & (|wb_sel_i[3:0]) & (reg_dlab_bit | (wb_adr_i[2:0] != 3'b000));
assign reg_fcr_wren = wb_cyc_i & wb_stb_i & wb_we_i & wb_sel_i[1] & (wb_adr_i[2:0] == 3'b010);
assign rcvr_fifo_rst = reg_fcr_wren & wb_dat_i[9];
assign xmit_fifo_rst = reg_fcr_wren & wb_dat_i[10];
// Create DLAB bit
always @ (posedge wb_clk_i)
begin
if(wb_rst_i) reg_dlab_bit <= 1'b0;
else if(reg_dlab_bit_wren) reg_dlab_bit <= wb_dat_i[7];
end
 
// Create IER. We only use the two LS bits...
always @ (posedge wb_clk_i)
begin
if(wb_rst_i) reg_ier <= 4'h0;
else if(reg_ier_wren) reg_ier <= wb_dat_i[19:16];
end
 
// Create IIR (and THR INT arm bit)
assign rd_fifo_becoming_empty = r_fifo_en & (~rpp) & (rd_bytes_avail == 4'h1); // "rd fifo" is the WB write FIFO...
always @ (posedge wb_clk_i)
begin
if(wb_rst_i) thr_int_arm <= 1'b0;
else if(wb_wr | rd_fifo_becoming_empty) thr_int_arm <= 1'b1; // Set when WB write fifo becomes empty, or on a write to it
else if(reg_iir_rden & (~wr_fifo_not_empty)) thr_int_arm <= 1'b0;
end
always @ (thr_int_arm or rd_fifo_not_full or wr_fifo_not_empty)
begin
if(wr_fifo_not_empty) iir_gen <= 3'b100;
else if(thr_int_arm & rd_fifo_not_full) iir_gen <= 3'b010;
else iir_gen <= 3'b001;
end
assign reg_iir = {5'b00000, iir_gen};
// Create the data lines out to the WB.
// Always put all 4 bytes on the WB data lines, let the master pick out what it
// wants.
assign bus_data_lo = {data_to_wb, {4'b0000, reg_ier}, {5'b00000, reg_iir}, reg_lcr};
assign bus_data_hi = {reg_mcr, reg_lsr, reg_msr, reg_scr};
assign wb_dat_o = (wb_adr_i[2]) ? bus_data_hi : bus_data_lo;
 
assign data_from_wb = wb_dat_i[31:24]; // Data to the FIFO
 
// Generate interrupt output
assign int_o = (rd_fifo_not_full & thr_int_arm & reg_ier[1]) | (wr_fifo_not_empty & reg_ier[0]);
endmodule
 
/rtl/verilog/adbg_defines.v
36,31 → 36,8
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: adbg_defines.v,v $
// Revision 1.4 2010-01-14 02:03:40 Nathan
// Make hi-speed mode the default
//
// Revision 1.3 2010-01-10 22:53:48 Nathan
// Added define for hi-speed mode
//
// Revision 1.2 2009/05/17 20:54:56 Nathan
// Changed email address to opencores.org
//
// Revision 1.1 2008/07/22 20:28:30 Nathan
// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
//
// Revision 1.5 2008/07/06 20:02:53 Nathan
// Fixes for synthesis with Xilinx ISE (also synthesizable with
// Quartus II 7.0). Ran through dos2unix.
//
// Revision 1.4 2008/06/30 20:09:20 Nathan
// Removed code to select top-level module as active (it served no
// purpose). Re-numbered modules, requiring changes to testbench and software driver.
//
 
 
// Length of the MODULE ID register
`define DBG_TOP_MODULE_ID_LENGTH 2
 
71,20 → 48,28
`define DBG_TOP_WISHBONE_DEBUG_MODULE 2'h0
`define DBG_TOP_CPU0_DEBUG_MODULE 2'h1
`define DBG_TOP_CPU1_DEBUG_MODULE 2'h2
`define DBG_TOP_JSP_DEBUG_MODULE 2'h3
 
// Length of data
`define DBG_TOP_MODULE_DATA_LEN 53
 
 
// If WISHBONE sub-module is supported uncomment the folowing line
// If WISHBONE sub-module is supported uncomment the following line
`define DBG_WISHBONE_SUPPORTED
 
// If CPU_0 sub-module is supported uncomment the folowing line
// If CPU_0 sub-module is supported uncomment the following line
`define DBG_CPU0_SUPPORTED
 
// If CPU_1 sub-module is supported uncomment the folowing line
// If CPU_1 sub-module is supported uncomment the following line
//`define DBG_CPU1_SUPPORTED
 
// To include the JTAG Serial Port (JSP), uncomment the following line
`define DBG_JSP_SUPPORTED
 
// Define this if you intend to use the JSP in a system with multiple
// devices on the JTAG chain
`define ADBG_JSP_SUPPORT_MULTI
 
// If this is defined, status bits will be skipped on burst
// writes to improve download speeds.
// reads and writes to improve download speeds.
`define ADBG_USE_HISPEED
/rtl/verilog/syncreg.v
0,0 → 1,158
//////////////////////////////////////////////////////////////////////
//// ////
//// syncreg.v ////
//// ////
//// ////
//// Synchronizes a register between two clock domains ////
//// ////
//// Author(s): ////
//// Nathan Yawn (nathan.yawn@opencores.org) ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// This is a synchronization element between two clock domains. Domain A
// is considered the 'source' domain (produces the data), and Domain B
// is considered the 'destination' domain (consumes the data). It is assumed
// that clock A is faster than clock B, but this element will work
// regardless. The idea here is NOT to insure that domain B sees every
// change to the value generated by domain A. Rather, this device
// attempts to keep the value seen by domain B as current as possible,
// always updating to the latest value of the input in domain A.
// Thus, there may be dozens or hundreds of changes to register A
// which are not seen by domain B. There is no external acknowledge
// of receipt from domain B. Domain B simply wants the most current
// value of register A possible at any given time.
// Note the reset is asynchronous; this is necessary to coordinate between
// two clock domains which may have separate reset signals. I could find
// no other way to insure correct initialization with two separate
// reset signals.
//
// Ports:
// CLKA: Clock for the source domain
// CLKB: Clock for the destination domain
// RST: Asynchronously resets all sync elements, prepares
// unit for operation.
// DATA_IN: Data input from clock domain A
// DATA_OUT: Data output to clock domain B
//
 
 
// Top module
module syncreg (
CLKA,
CLKB,
RST,
DATA_IN,
DATA_OUT
);
 
 
input CLKA;
input CLKB;
input RST;
input [3:0] DATA_IN;
output [3:0] DATA_OUT;
 
reg [3:0] regA;
reg [3:0] regB;
reg strobe_toggle;
reg ack_toggle;
wire A_not_equal;
wire A_enable;
wire strobe_sff_out;
wire ack_sff_out;
wire [3:0] DATA_OUT;
 
// Combinatorial assignments
assign A_enable = A_not_equal & ack_sff_out;
assign A_not_equal = !(DATA_IN == regA);
assign DATA_OUT = regB;
// register A (latches input any time it changes)
always @ (posedge CLKA or posedge RST)
begin
if(RST)
regA <= 4'b0;
else if(A_enable)
regA <= DATA_IN;
end
 
// register B (latches data from regA when enabled by the strobe SFF)
always @ (posedge CLKB or posedge RST)
begin
if(RST)
regB <= 4'b0;
else if(strobe_sff_out)
regB <= regA;
end
 
// 'strobe' toggle FF
always @ (posedge CLKA or posedge RST)
begin
if(RST)
strobe_toggle <= 1'b0;
else if(A_enable)
strobe_toggle <= ~strobe_toggle;
end
 
// 'ack' toggle FF
// This is set to '1' at reset, to initialize the unit.
always @ (posedge CLKB or posedge RST)
begin
if(RST)
ack_toggle <= 1'b1;
else if (strobe_sff_out)
ack_toggle <= ~ack_toggle;
end
// 'strobe' sync element
syncflop strobe_sff (
.DEST_CLK (CLKB),
.D_SET (1'b0),
.D_RST (strobe_sff_out),
.RESET (RST),
.TOGGLE_IN (strobe_toggle),
.D_OUT (strobe_sff_out)
);
// 'ack' sync element
syncflop ack_sff (
.DEST_CLK (CLKA),
.D_SET (1'b0),
.D_RST (A_enable),
.RESET (RST),
.TOGGLE_IN (ack_toggle),
.D_OUT (ack_sff_out)
);
endmodule
/doc/AdvancedDebugInterface.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/doc/src/AdvancedDebugInterface.odt Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/doc/src/jsp_submodule.odg Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
doc/src/jsp_submodule.odg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.