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https://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk
Subversion Repositories adv_debug_sys
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- This comparison shows the changes necessary to convert path
/adv_debug_sys/trunk/Hardware
- from Rev 42 to Rev 51
- ↔ Reverse comparison
Rev 42 → Rev 51
/adv_dbg_if/rtl/verilog/adbg_jsp_module.v
354,7 → 354,7
// Outputs of state machine, pure combinatorial |
always @ (wr_module_state or wr_module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i |
or in_word_count_zero or out_word_count_zero or wr_bit_count_max or decremented_in_word_count |
or decremented_out_word_count) |
or decremented_out_word_count or user_word_count_zero) |
begin |
// Default everything to 0, keeps the case statement simple |
wr_bit_ct_en <= 1'b0; // enable bit counter |
/adv_dbg_if/rtl/verilog/adbg_jsp_biu.v
512,7 → 512,7
else iir_gen <= 3'b001; |
end |
|
assign reg_iir = {5'b00000, iir_gen}; |
assign reg_iir = iir_gen; |
|
// Create the data lines out to the WB. |
// Always put all 4 bytes on the WB data lines, let the master pick out what it |