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/altera_virtual_jtag/rtl/vhdl/altera_virtual_jtag.vhd
0,0 → 1,172
//////////////////////////////////////////////////////////////////////
//// ////
//// altera_virtual_jtag.vhd ////
//// ////
//// ////
//// ////
//// Author(s): ////
//// Nathan Yawn (nathan.yawn@opencores.org) ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2003-2008 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// //
// This file is a wrapper for the Altera Virtual JTAG device. //
// It is designed to take the place of a separate TAP //
// controller in Altera systems, to allow a user to access a CPU //
// debug module (such as that of the OR1200) through the FPGA's //
// dedicated JTAG / configuration port. //
// //
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: altera_virtual_jtag.vhd,v $
// Revision 1.2 2009/05/17 20:54:47 Nathan
// Changed email address to opencores.org
//
// Revision 1.1 2008/07/18 20:09:31 Nathan
// Changed directory structure to match existing projects.
//
// Revision 1.2 2008/05/22 19:55:20 Nathan
// Added added copyright, CVS log, and brief description.
//
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
ENTITY altera_virtual_jtag IS
PORT
(
tck_o : OUT STD_LOGIC;
debug_tdi_i : IN STD_LOGIC;
tdo_o : OUT STD_LOGIC;
test_logic_reset_o : OUT STD_LOGIC;
run_test_idle_o : OUT STD_LOGIC;
shift_dr_o : OUT STD_LOGIC;
capture_dr_o : OUT STD_LOGIC;
pause_dr_o : OUT STD_LOGIC;
update_dr_o : OUT STD_LOGIC;
debug_select_o : OUT STD_LOGIC
);
END altera_virtual_jtag;
 
 
ARCHITECTURE OC OF altera_virtual_jtag IS
 
CONSTANT CMD_DEBUG : STD_LOGIC_VECTOR (3 downto 0) := "1000";
 
SIGNAL ir_value : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL exit1_dr : STD_LOGIC;
SIGNAL exit2_dr : STD_LOGIC;
SIGNAL capture_ir : STD_LOGIC;
SIGNAL update_ir : STD_LOGIC;
 
COMPONENT sld_virtual_jtag
GENERIC (
sld_auto_instance_index : STRING;
sld_instance_index : NATURAL;
sld_ir_width : NATURAL;
sld_sim_action : STRING;
sld_sim_n_scan : NATURAL;
sld_sim_total_length : NATURAL;
lpm_type : STRING
);
PORT (
tdi : OUT STD_LOGIC ;
jtag_state_rti : OUT STD_LOGIC ;
jtag_state_e1dr : OUT STD_LOGIC ;
jtag_state_e2dr : OUT STD_LOGIC ;
tms : OUT STD_LOGIC ;
jtag_state_pir : OUT STD_LOGIC ;
jtag_state_tlr : OUT STD_LOGIC ;
tck : OUT STD_LOGIC ;
jtag_state_sir : OUT STD_LOGIC ;
ir_in : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
virtual_state_cir : OUT STD_LOGIC ;
virtual_state_pdr : OUT STD_LOGIC ;
ir_out : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
virtual_state_uir : OUT STD_LOGIC ;
jtag_state_cir : OUT STD_LOGIC ;
jtag_state_uir : OUT STD_LOGIC ;
jtag_state_pdr : OUT STD_LOGIC ;
tdo : IN STD_LOGIC ;
jtag_state_sdrs : OUT STD_LOGIC ;
virtual_state_sdr : OUT STD_LOGIC ;
virtual_state_cdr : OUT STD_LOGIC ;
jtag_state_sdr : OUT STD_LOGIC ;
jtag_state_cdr : OUT STD_LOGIC ;
virtual_state_udr : OUT STD_LOGIC ;
jtag_state_udr : OUT STD_LOGIC ;
jtag_state_sirs : OUT STD_LOGIC ;
jtag_state_e1ir : OUT STD_LOGIC ;
jtag_state_e2ir : OUT STD_LOGIC ;
virtual_state_e1dr : OUT STD_LOGIC ;
virtual_state_e2dr : OUT STD_LOGIC
);
END COMPONENT;
 
BEGIN
 
 
 
sld_virtual_jtag_component : sld_virtual_jtag
GENERIC MAP (
sld_auto_instance_index => "YES",
sld_instance_index => 0,
sld_ir_width => 4,
sld_sim_action => "",
sld_sim_n_scan => 0,
sld_sim_total_length => 0,
lpm_type => "sld_virtual_jtag"
)
PORT MAP (
ir_out => ir_value,
tdo => debug_tdi_i,
tdi => tdo_o,
jtag_state_rti => run_test_idle_o,
tck => tck_o,
ir_in => ir_value,
jtag_state_tlr => test_logic_reset_o,
virtual_state_cir => capture_ir,
virtual_state_pdr => pause_dr_o,
virtual_state_uir => update_ir,
virtual_state_sdr => shift_dr_o,
virtual_state_cdr => capture_dr_o,
virtual_state_udr => update_dr_o,
virtual_state_e1dr => exit1_dr,
virtual_state_e2dr => exit2_dr
);
 
debug_select_o <= '1' when (ir_value = CMD_DEBUG) else '0';
 
END OC;
/altera_virtual_jtag/doc/License_FDL-1.2.txt
0,0 → 1,397
GNU Free Documentation License
Version 1.2, November 2002
 
 
Copyright (C) 2000,2001,2002 Free Software Foundation, Inc.
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/altera_virtual_jtag/doc/src/altera_virtual_jtag.odt Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/altera_virtual_jtag/doc/src/altera_virtual_jtag.odt
altera_virtual_jtag/doc/src/altera_virtual_jtag.odt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: altera_virtual_jtag/doc/altera_virtual_jtag.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: altera_virtual_jtag/doc/altera_virtual_jtag.pdf =================================================================== --- altera_virtual_jtag/doc/altera_virtual_jtag.pdf (nonexistent) +++ altera_virtual_jtag/doc/altera_virtual_jtag.pdf (revision 3)
altera_virtual_jtag/doc/altera_virtual_jtag.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: altera_virtual_jtag/doc/gpl-2.0.txt =================================================================== --- altera_virtual_jtag/doc/gpl-2.0.txt (nonexistent) +++ altera_virtual_jtag/doc/gpl-2.0.txt (revision 3) @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. 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Index: adv_dbg_if/bench/full_system/adv_dbg_tb.v =================================================================== --- adv_dbg_if/bench/full_system/adv_dbg_tb.v (nonexistent) +++ adv_dbg_if/bench/full_system/adv_dbg_tb.v (revision 3) @@ -0,0 +1,892 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// adv_dbg_tb.v //// +//// //// +//// //// +//// Testbench for the SoC Advanced Debug Interface. //// +//// //// +//// Author(s): //// +//// Nathan Yawn (nathan.yawn@opencores.org) //// +//// //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: adv_dbg_tb.v,v $ +// Revision 1.4 2009/05/17 20:54:55 Nathan +// Changed email address to opencores.org +// +// Revision 1.3 2008/07/11 08:18:47 Nathan +// Added a bit to the CPU test. Added the hack that allows the driver to work with a Xilinx BSCAN device. +// + + +`include "tap_defines.v" +`include "dbg_defines.v" +`include "dbg_wb_defines.v" + + +// Polynomial for the CRC calculation +// Yes, it's backwards. Yes, this is on purpose. +// To decrease logic + routing, we want to shift the CRC calculation +// in the same direction we use to shift the data out, LSB first. +`define DBG_CRC_POLY 32'hedb88320 + +// These are indicies into an array which hold values for the JTAG outputs +`define JTAG_TMS 0 +`define JTAG_TCK 1 +`define JTAG_TDO 2 + +`define JTAG_TMS_bit 3'h1 +`define JTAG_TCK_bit 3'h2 +`define JTAG_TDO_bit 3'h4 + +`define wait_jtag_period #50 + + +module adv_debug_tb ( + +jtag_tck_o, +jtag_tms_o, +jtag_tdo_o, +jtag_tdi_i, + +wb_clk_o, +sys_rstn_o + + +); + +output jtag_tck_o; +output jtag_tms_o; +output jtag_tdo_o; +input jtag_tdi_i; +output wb_clk_o; +output sys_rstn_o; + +// Connections to the JTAG TAP +reg jtag_tck_o; +reg jtag_tms_o; +reg jtag_tdo_o; +wire jtag_tdi_i; + +reg wb_clk_o; +reg sys_rst_o; +reg sys_rstn_o; + +reg test_enabled; + +// Data which will be written to the WB interface +reg [31:0] static_data32 [0:15]; +reg [15:0] static_data16 [0:15]; +reg [7:0] static_data8 [0:15]; + +// Arrays to hold data read back from the WB interface, for comparison +reg [31:0] input_data32 [0:15]; +reg [15:0] input_data16 [0:15]; +reg [7:0] input_data8 [0:15]; + +reg [32:0] err_data; // holds the contents of the error register from the various modules + +reg failed; +integer i; + +initial +begin + jtag_tck_o = 1'b0; + jtag_tms_o = 1'b0; + jtag_tdo_o = 1'b0; +end + +// Provide the wishbone / CPU / system clock +initial +begin + wb_clk_o = 1'b0; + forever #5 wb_clk_o = ~wb_clk_o; +end + +initial +begin + sys_rstn_o = 1'b1; + #200 sys_rstn_o = 1'b0; + #5000 sys_rstn_o = 1'b1; +end + + +// Start the test (and reset the wishbone) +initial +begin + test_enabled = 1'b0; + + // Init the memory + initialize_memory(32'h0,32'h16); + + #5 test_enabled<= 1'b1; +end + +// This is the main test procedure +always @ (posedge test_enabled) +begin + + $display("Starting advanced debug test"); + + reset_jtag; + #6000; + check_idcode; + #1000; + + // Select the debug module in the IR + set_ir(`DEBUG); + #1000; + + + `ifdef DBG_CPU0_SUPPORTED + // STALL the CPU, so it won't interfere with WB tests + // Select the CPU0 unit in the debug module + #1000; + $display("Selecting CPU0 module at time %t", $time); + select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE); + + + // Set the stall bit...holding the CPU in reset prevents WB access (?) + $display("Setting reset and stall bits at time %t", $time); + write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h2); // idx, idxlen, data, datalen + #1000; + `endif + + + /////////////////////////////////////////////////////////////////// + // Test the Wishbone unit + //////////////////////////////////////////////////////////////////// + +`ifdef DBG_WISHBONE_SUPPORTED + // Select the WB unit in the debug module + #1000; + $display("Selecting Wishbone module at time %t", $time); + select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE); + + // Reset the error bit + write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h1); // idx, idxlen, data, datalen + #1000; + + ///////////////////////////////// + // Test 8-bit WB access + failed = 0; + $display("Testing WB 8-bit burst write at time %t: resetting ", $time); + do_module_burst_write(3'h1, 16'd16, 32'h87); // 3-bit word size (bytes), 16-bit word count, 32-bit start address + #1000; + $display("Testing WB 8-bit burst read at time %t", $time); + do_module_burst_read(3'h1, 16'd16, 32'h87); + #1000; + for(i = 0; i < 16; i = i+1) begin + if(static_data8[i] != input_data8[i]) begin + failed = 1; + $display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data8[i], input_data8[i]); + end + end + if(!failed) $display("8-bit read/write OK!"); + + + ///////////////////////////////// + // Test 16-bit WB access + failed = 0; + $display("Testing WB 16-bit burst write at time %t", $time); + do_module_burst_write(3'h2, 16'd16, 32'h22); // 3-bit word size (bytes), 16-bit word count, 32-bit start address + #1000; + $display("Testing WB 16-bit burst read at time %t", $time); + do_module_burst_read(3'h2, 16'd16, 32'h22); + #1000; + for(i = 0; i < 16; i = i+1) begin + if(static_data16[i] != input_data16[i]) begin + failed = 1; + $display("16-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data16[i], input_data16[i]); + end + end + if(!failed) $display("16-bit read/write OK!"); + + + //////////////////////////////////// + // Test 32-bit WB access + failed = 0; + $display("Testing WB 32-bit burst write at time %t", $time); + do_module_burst_write(3'h4, 16'd16, 32'h100); // 3-bit word size (bytes), 16-bit word count, 32-bit start address + #1000; + $display("Testing WB 32-bit burst read at time %t", $time); + do_module_burst_read(3'h4, 16'd16, 32'h100); + #1000; + for(i = 0; i < 16; i = i+1) begin + if(static_data32[i] != input_data32[i]) begin + failed = 1; + $display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data32[i], input_data32[i]); + end + end + if(!failed) $display("32-bit read/write OK!"); + + + //////////////////////////////// + // Test error register + err_data = 33'h0; + // Select and reset the error register + write_module_internal_register(`DBG_WB_INTREG_ERROR, `DBG_WB_REGSELECT_SIZE, 64'h1, 8'h1); // regidx,idxlen,writedata, datalen; + //i_wb.cycle_response(`ERR_RESPONSE, 2, 0); // response type, wait cycles, retry_cycles + do_module_burst_write(3'h4, 16'd4, 32'hdeaddead); // 3-bit word size (bytes), 16-bit word count, 32-bit start address + read_module_internal_register(8'd33, err_data); // get the error register + $display("Error bit is %d, error address is %x", err_data[0], err_data>>1); + +`endif // WB module supported + + + /////////////////////////////////////////////////////////////////// + // Test CPU0 unit + //////////////////////////////////////////////////////////////////// +`ifdef DBG_CPU0_SUPPORTED + // Select the CPU0 unit in the debug module + #1000; + $display("Selecting CPU0 module at time %t", $time); + select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE); + + + // Set the stall bit (clear the reset bit) + $display("Setting reset and stall bits at time %t", $time); + write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h2); // idx, idxlen, data, datalen + #1000; + + // Make sure CPU stalled + $display("Testing reset and stall bits at time %t", $time); + read_module_internal_register(8'd2, err_data); // We assume the register is already selected + $display("Reset and stall bits are %x", err_data); + #1000; + + +// Write some opcodes into the memory +select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE); + +static_data32[0] = 32'hE0000005;/* l.xor r0,r0,r0 */ +static_data32[1] = 32'h9C200000; /* l.addi r1,r0,0x0 */ +static_data32[2] = 32'h18400000;/* l.movhi r2,0x4000 */ +static_data32[3] = 32'hA8420030;/* l.ori r2,r2,0x30 */ +static_data32[4] = 32'h9C210001;/* l.addi r1,r1,1 */ +static_data32[5] = 32'h9C210001; /* l.addi r1,r1,1 */ +static_data32[6] = 32'hD4020800;/* l.sw 0(r2),r1 */ +static_data32[7] = 32'h9C210001;/* l.addi r1,r1,1 */ +static_data32[8] = 32'h84620000;/* l.lwz r3,0(r2) */ +static_data32[9] = 32'h03FFFFFB;/* l.j loop2 */ +static_data32[10] = 32'hE0211800;/* l.add r1,r1,r3 */ + +do_module_burst_write(3'h4, 16'd11, 32'h0); // 3-bit word size (bytes), 16-bit word count, 32-bit start address + + #1000; +select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE); + +#1000; +$display("Enabling CPU exceptions at time %t", $time); +static_data32[0] = 32'h1; // enable exceptions +do_module_burst_write(3'h4, 16'd1, 32'd17); // 3-bit word size (bytes), 16-bit word count, 32-bit start address + +#1000; +$display("Set \'trap causes stall\' at time %t", $time); +static_data32[0] = 32'h00002000; // Trap causes stall +do_module_burst_write(3'h4, 16'd1, (6 << 11)+20); // 3-bit word size (bytes), 16-bit word count, 32-bit start address + +#1000; +$display("Set PC at time %t", $time); +static_data32[0] = 32'h0; // Set PC +do_module_burst_write(3'h4, 16'd1, 32'd16); // 3-bit word size (bytes), 16-bit word count, 32-bit start address + +#1000; +$display("Set step bit at time %t", $time); +static_data32[0] = (1 << 22); // set step bit +do_module_burst_write(3'h4, 16'd1, (6<<11) + 16); // 3-bit word size (bytes), 16-bit word count, 32-bit start address + +// Unstall x11 +for(i = 0; i < 11; i = i + 1) +begin + #1000; + $display("Unstall (%d/11) at time %t", i, $time); + write_module_internal_register(32'h0, 8'h1, 32'h0, 8'h2); // idx, idxlen, data, datalen +end + +#1000; +#1000; +#1000; + + $display("Getting NPC at time %t", $time); + do_module_burst_read(3'h4, 16'd1, 32'd16); + + $display("NPC = %x, expected 0x00000010", input_data32[0]); + + $display("Getting PPC at time %t", $time); + do_module_burst_read(3'h4, 16'd1, 32'd18); + $display("PPC = %x, expected 0x00000028", input_data32[0]); + + #1000; + $display("Getting R1 at time %t", $time); + do_module_burst_read(3'h4, 16'd1, 32'h401); // Word size, count, addr; save old instr + $display("R1 = %d, expected 5", input_data32[0]); + + #1000; +$display("Un-set step bit at %t", $time); +static_data32[0] = 32'h0; // Trap causes stall +do_module_burst_write(3'h4, 16'd1, (6 << 11)+16); + +// Put a trap instr at 0x20 +#1000; +$display("Select WB at %t", $time); +select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE); +#1000; +$display("Save old instr at %t", $time); +do_module_burst_read(3'h4, 16'd1, 32'h20); // Save old instr +#1000; +$display("Put trap instr at %t", $time); +static_data32[0] = 32'h21000001; /* l.trap */ +do_module_burst_write(3'h4, 16'd1, 32'h20); // put new instr +#1000; +$display("Select CPU0 at %t", $time); +select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE); +#1000; +$display("Set PC to 0x24 at %t", $time); +static_data32[0] = 32'h24; +do_module_burst_write(3'h4, 16'd1, 32'd16); // Set PC to 0x24 +#1000; +$display("Unstall at time %t", $time); +write_module_internal_register(32'h0, 8'h1, 32'h0, 8'h2); // idx, idxlen, data, datalen + +// We assume it stalls again here... +#1000; + +err_data = 1; +while(err_data != 0) +begin + $display("Testing for stall at %t", $time); + read_module_internal_register(8'd2, err_data); // We assume the register is already selected + #1000; +end + + +// *** The software self-test does 2 separate reads here... + $display("Getting NPC at time %t", $time); + do_module_burst_read(3'h4, 16'd3, 32'd16); + + $display("NPC = %x, expected 0x00000024", input_data32[0]); + $display("PPC = %x, expected 0x00000020", input_data32[2]); + + + +`endif + + +end + +task initialize_memory; + input [31:0] start_addr; + input [31:0] length; + integer i; + reg [31:0] addr; + begin + + for (i=0; i> 1; + crc_out = crc_out ^ ((d ^ c) & `DBG_CRC_POLY); + //$display("CRC Itr %d, inbit = %d, crc = 0x%x", i, data_in[i], crc_out); + end + end +endtask + +task check_idcode; +reg [63:0] readdata; +reg[31:0] idcode; +begin + set_ir(`IDCODE); + + // Read the IDCODE in the DR + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + jtag_read_write_stream(64'h0, 8'd32, 1, readdata); // write data, exit_1 + write_bit(`JTAG_TMS_bit); // update_ir + write_bit(3'h0); // idle + idcode = readdata[31:0]; + $display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE); +end +endtask; + +task select_debug_module; +input [1:0] moduleid; +reg validid; +begin + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + jtag_write_stream({1'b1,moduleid}, 8'h3, 1); // write data, exit_1 + write_bit(`JTAG_TMS_bit); // update_dr + write_bit(3'h0); // idle + + $display("Selecting module (%0x)", moduleid); + + // Read back the status to make sure a valid chain is selected + /* Pointless, the newly selected module would respond instead... + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + read_write_bit(`JTAG_TMS_bit, validid); // get data, exit_1 + write_bit(`JTAG_TMS_bit); // update_dr + write_bit(3'h0); // idle + + if(validid) $display("Selected valid module (%0x)", moduleid); + else $display("Failed to select module (%0x)", moduleid); + */ +end +endtask + + +task send_module_burst_command; +input [3:0] opcode; +input [31:0] address; +input [15:0] burstlength; +reg [63:0] streamdata; +begin + streamdata = {11'h0,1'b0,opcode,address,burstlength}; + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + jtag_write_stream(streamdata, 8'd53, 1); // write data, exit_1 + write_bit(`JTAG_TMS_bit); // update_dr + write_bit(3'h0); // idle +end +endtask + +task select_module_internal_register; // Really just a read, with discarded data + input [31:0] regidx; + input [7:0] len; // the length of the register index data, we assume not more than 32 + reg[63:0] streamdata; +begin + streamdata = 64'h0; + streamdata = streamdata | regidx; + streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len); + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + jtag_write_stream(streamdata, (len+5), 1); // write data, exit_1 + write_bit(`JTAG_TMS_bit); // update_dr + write_bit(3'h0); // idle +end +endtask + + +task read_module_internal_register; // We assume the register is already selected + //input [31:0] regidx; + input [7:0] len; // the length of the data desired, we assume a max of 64 bits + output [63:0] instream; + reg [63:0] bitmask; +begin + instream = 64'h0; + // We shift out all 0's, which is a NOP to the debug unit + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + // Shift at least 5 bits, as this is the min, for a valid NOP + jtag_read_write_stream(64'h0, len+4,1,instream); // exit_1 + write_bit(`JTAG_TMS_bit); // update_dr + write_bit(3'h0); // idle + bitmask = 64'hffffffffffffffff; + bitmask = bitmask << len; + bitmask = ~bitmask; + instream = instream & bitmask; // Cut off any unwanted excess bits +end +endtask + +task write_module_internal_register; + input [31:0] regidx; // the length of the register index data + input [7:0] idxlen; + input [63:0] writedata; + input [7:0] datalen; // the length of the data to write. We assume the two length combined are 59 or less. + reg[63:0] streamdata; +begin + streamdata = 64'h0; // This will 0 the toplevel/module select bit + streamdata = streamdata | writedata; + streamdata = streamdata | (regidx << datalen); + streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen)); + + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + jtag_write_stream(streamdata, (idxlen+datalen+5), 1); // write data, exit_1 + write_bit(`JTAG_TMS_bit); // update_dr + write_bit(3'h0); // idle +end +endtask + +// This includes the sending of the burst command +task do_module_burst_read; +input [5:0] word_size_bytes; +input [15:0] word_count; +input [31:0] start_address; +reg [3:0] opcode; +reg status; +reg [63:0] instream; +integer i; +integer j; +reg [31:0] crc_calc_i; +reg [31:0] crc_calc_o; // temp signal... +reg [31:0] crc_read; +reg [5:0] word_size_bits; +begin + $display("Doing burst read, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address); + instream = 64'h0; + word_size_bits = word_size_bytes << 3; + crc_calc_i = 32'hffffffff; + + // Send the command + case (word_size_bytes) + 3'h1: opcode = `DBG_WB_CMD_BREAD8; + 3'h2: opcode = `DBG_WB_CMD_BREAD16; + 3'h4: opcode = `DBG_WB_CMD_BREAD32; + default: + begin + $display("Tried burst read with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes); + opcode = `DBG_WB_CMD_BREAD32; + end + endcase + + send_module_burst_command(opcode,start_address, word_count); // returns to state idle + + // This charming kludge provides ONE TCK, in case a xilinx BSCAN TAP is used, + // because the FSM needs it between the read burst command and the actual + // read burst. Blech. + #500; + set_ir(`IDCODE); + #500; + set_ir(`DEBUG); + #500; + + // Get us back to shift_dr mode to read a burst + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + + // Now, repeat... + for(i = 0; i < word_count; i=i+1) begin + // Get 1 status bit, then word_size_bytes*8 bits + status = 1'b0; + j = 0; + while(!status) begin + read_write_bit(3'h0, status); + j = j + 1; + end + + if(j > 1) begin + $display("Took %0d tries before good status bit during burst read", j); + end + + jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream); + //$display("Read 0x%0x", instream[31:0]); + compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o); + crc_calc_i = crc_calc_o; + if(word_size_bytes == 1) input_data8[i] = instream[7:0]; + else if(word_size_bytes == 2) input_data16[i] = instream[15:0]; + else input_data32[i] = instream[31:0]; + end + + // Read the data CRC from the debug module. + jtag_read_write_stream(64'h0, 6'd32, 1, crc_read); + if(crc_calc_o != crc_read) $display("CRC ERROR! Computed 0x%x, read CRC 0x%x", crc_calc_o, crc_read); + else $display("CRC OK!"); + + // Finally, shift out 5 0's, to make the next command a NOP + // Not necessary, debug unit won't latch a new opcode at the end of a burst + //jtag_write_stream(64'h0, 8'h5, 1); + write_bit(`JTAG_TMS_bit); // update_ir + write_bit(3'h0); // idle +end +endtask + + +task do_module_burst_write; +input [5:0] word_size_bytes; +input [15:0] word_count; +input [31:0] start_address; +reg [3:0] opcode; +reg status; +reg [63:0] dataword; +integer i; +integer j; +reg [31:0] crc_calc_i; +reg [31:0] crc_calc_o; +reg crc_match; +reg [5:0] word_size_bits; +begin + $display("Doing burst write, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address); + word_size_bits = word_size_bytes << 3; + crc_calc_i = 32'hffffffff; + + // Send the command + case (word_size_bytes) + 3'h1: opcode = `DBG_WB_CMD_BWRITE8; + 3'h2: opcode = `DBG_WB_CMD_BWRITE16; + 3'h4: opcode = `DBG_WB_CMD_BWRITE32; + default: + begin + $display("Tried burst write with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes); + opcode = `DBG_WB_CMD_BWRITE32; + end + endcase + + send_module_burst_command(opcode, start_address, word_count); // returns to state idle + + // Get us back to shift_dr mode to write a burst + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + + + // Write a start bit (a 1) so it knows when to start counting + write_bit(`JTAG_TDO_bit); + + // Now, repeat... + for(i = 0; i < word_count; i=i+1) begin + // Write word_size_bytes*8 bits, then get 1 status bit + if(word_size_bytes == 4) dataword = {32'h0, static_data32[i]}; + else if(word_size_bytes == 2) dataword = {48'h0, static_data16[i]}; + else dataword = {56'h0, static_data8[i]}; + + + jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0); + compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o); + crc_calc_i = crc_calc_o; + + // Check if WB bus is ready + // *** THIS WILL NOT WORK IF THERE IS MORE THAN 1 DEVICE IN THE JTAG CHAIN!!! + status = 1'b0; + read_write_bit(3'h0, status); + + if(!status) begin + $display("Bad status bit during burst write, index %d", i); + end + + + //$display("Wrote 0x%0x", dataword); + end + + // Send the CRC we computed + jtag_write_stream(crc_calc_o, 6'd32,0); + + // Read the 'CRC match' bit, and go to exit1_dr + read_write_bit(`JTAG_TMS_bit, crc_match); + if(!crc_match) $display("CRC ERROR! match bit after write is %d (computed CRC 0x%x)", crc_match, crc_calc_o); + else $display("CRC OK!"); + + // Finally, shift out 5 0's, to make the next command a NOP + // Not necessary, module will not latch new opcode during burst + //jtag_write_stream(64'h0, 8'h5, 1); + write_bit(`JTAG_TMS_bit); // update_ir + write_bit(3'h0); // idle +end + +endtask + + +// Puts a value in the TAP IR, assuming we start in IDLE state. +// Returns to IDLE state when finished +task set_ir; +input [3:0] irval; +begin + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(`JTAG_TMS_bit); // select_ir_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + jtag_write_stream({60'h0,irval}, 8'h4, 1); // write data, exit_1 + write_bit(`JTAG_TMS_bit); // update_ir + write_bit(3'h0); // idle +end +endtask + +// Resets the TAP and puts it into idle mode +task reset_jtag; +integer i; +begin + for(i = 0; i < 8; i=i+1) begin + write_bit(`JTAG_TMS_bit); // 5 TMS should put us in test_logic_reset mode + end + write_bit(3'h0); // idle +end +endtask + + +//////////////////////////////////////////////////////////////////////////// +// Tasks to write or read-write a string of data + +task jtag_write_stream; +input [63:0] stream; +input [7:0] len; +input set_last_bit; +integer i; +integer databit; +reg [2:0] bits; +begin + for(i = 0; i < (len-1); i=i+1) begin + databit = (stream >> i) & 1'h1; + bits = databit << `JTAG_TDO; + write_bit(bits); + end + + databit = (stream >> i) & 1'h1; + bits = databit << `JTAG_TDO; + if(set_last_bit) bits = (bits | `JTAG_TMS_bit); + write_bit(bits); + +end +endtask + + +task jtag_read_write_stream; +input [63:0] stream; +input [7:0] len; +input set_last_bit; +output [63:0] instream; +integer i; +integer databit; +reg [2:0] bits; +reg inbit; +begin + instream = 64'h0; + for(i = 0; i < (len-1); i=i+1) begin + databit = (stream >> i) & 1'h1; + bits = databit << `JTAG_TDO; + read_write_bit(bits, inbit); + instream = (instream | (inbit << i)); + end + + databit = (stream >> i) & 1'h1; + bits = databit << `JTAG_TDO; + if(set_last_bit) bits = (bits | `JTAG_TMS_bit); + read_write_bit(bits, inbit); + instream = (instream | (inbit << (len-1))); +end +endtask + +///////////////////////////////////////////////////////////////////////// +// Tasks which write or readwrite a single bit (including clocking) + +task write_bit; + input [2:0] bitvals; + begin + + // Set data + jtag_out(bitvals & ~(`JTAG_TCK_bit)); + `wait_jtag_period; + + // Raise clock + jtag_out(bitvals | `JTAG_TCK_bit); + `wait_jtag_period; + + // drop clock (making output available in the SHIFT_xR states) + jtag_out(bitvals & ~(`JTAG_TCK_bit)); + `wait_jtag_period; + end +endtask + +task read_write_bit; + input [2:0] bitvals; + output l_tdi_val; + begin + + // read bit state + l_tdi_val <= jtag_tdi_i; + + // Set data + jtag_out(bitvals & ~(`JTAG_TCK_bit)); + `wait_jtag_period; + + // Raise clock + jtag_out(bitvals | `JTAG_TCK_bit); + `wait_jtag_period; + + // drop clock (making output available in the SHIFT_xR states) + jtag_out(bitvals & ~(`JTAG_TCK_bit)); + `wait_jtag_period; + end +endtask + +///////////////////////////////////////////////////////////////// +// Basic functions to set the state of the JTAG TAP I/F bits + +task jtag_out; + input [2:0] bitvals; + begin + + jtag_tck_o <= bitvals[`JTAG_TCK]; + jtag_tms_o <= bitvals[`JTAG_TMS]; + jtag_tdo_o <= bitvals[`JTAG_TDO]; + end +endtask + + +task jtag_inout; + input [2:0] bitvals; + output l_tdi_val; + begin + + jtag_tck_o <= bitvals[`JTAG_TCK]; + jtag_tms_o <= bitvals[`JTAG_TMS]; + jtag_tdo_o <= bitvals[`JTAG_TDO]; + + l_tdi_val <= jtag_tdi_i; + end +endtask + +endmodule \ No newline at end of file Index: adv_dbg_if/bench/full_system/wave.do =================================================================== --- adv_dbg_if/bench/full_system/wave.do (nonexistent) +++ adv_dbg_if/bench/full_system/wave.do (revision 3) @@ -0,0 +1,499 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /xsv_fpga_top/jtag_tdi +add wave -noupdate -format Logic /xsv_fpga_top/jtag_tms +add wave -noupdate -format Logic /xsv_fpga_top/jtag_tck +add wave -noupdate -format Logic /xsv_fpga_top/jtag_tdo +add wave -noupdate -format Logic /xsv_fpga_top/debug_select +add wave -noupdate -divider {Top level signals} +add wave -noupdate -format Logic /xsv_fpga_top/clk +add wave -noupdate -format Logic /xsv_fpga_top/rstn +add wave -noupdate -format Logic /xsv_fpga_top/rst_r +add wave -noupdate -format Logic /xsv_fpga_top/wb_rst +add wave -noupdate -format Logic /xsv_fpga_top/cpu_rst +add wave -noupdate -divider {Top-level CPU dbg} +add wave -noupdate -format Literal /xsv_fpga_top/dbg_lss +add wave -noupdate -format Literal /xsv_fpga_top/dbg_is +add wave -noupdate -format Literal /xsv_fpga_top/dbg_wp +add wave -noupdate -format Logic /xsv_fpga_top/dbg_bp +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_dat_dbg +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_dat_risc +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_adr +add wave -noupdate -format Logic /xsv_fpga_top/dbg_ewt +add wave -noupdate -format Logic /xsv_fpga_top/dbg_stall +add wave -noupdate -format Logic /xsv_fpga_top/dbg_we +add wave -noupdate -format Logic /xsv_fpga_top/dbg_stb +add wave -noupdate -format Logic /xsv_fpga_top/dbg_ack +add wave -noupdate -divider {CPU IWB} +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_clk_i +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_rst_i +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_ack_i +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_err_i +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_rty_i +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/iwb_dat_i +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_cyc_o +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/iwb_adr_o +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_stb_o +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_we_o +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/iwb_sel_o +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/iwb_dat_o +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/iwb_cab_o +add wave -noupdate -divider {DBG WB signals} +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/wb_dm_adr_o +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/wb_dm_dat_i +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/wb_dm_dat_o +add wave -noupdate -format Literal /xsv_fpga_top/wb_dm_sel_o +add wave -noupdate -format Logic /xsv_fpga_top/wb_dm_we_o +add wave -noupdate -format Logic /xsv_fpga_top/wb_dm_stb_o +add wave -noupdate -format Logic /xsv_fpga_top/wb_dm_cyc_o +add wave -noupdate -format Logic /xsv_fpga_top/wb_dm_cab_o +add wave -noupdate -format Logic /xsv_fpga_top/wb_dm_ack_i +add wave -noupdate -format Logic /xsv_fpga_top/wb_dm_err_i +add wave -noupdate -divider {DBG WB BIU} +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/tck_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/rst_i +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/data_i +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/data_o +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/addr_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/strobe_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/rd_wrn_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/rdy_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/err_o +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/word_size_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_clk_i +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_adr_o +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_dat_o +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_dat_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_cyc_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_stb_o +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_sel_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_we_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_ack_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_cab_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_err_i +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_cti_o +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_bte_o +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/sel_reg +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/addr_reg +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/data_in_reg +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/data_out_reg +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wr_reg +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/str_sync +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/rdy_sync +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/err_reg +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/rdy_sync_tff1 +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/rdy_sync_tff2 +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/rdy_sync_tff2q +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/str_sync_wbff1 +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/str_sync_wbff2 +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/str_sync_wbff2q +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/data_o_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/rdy_sync_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/err_en +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/be_dec +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/start_toggle +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/swapped_data_i +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/biu/swapped_data_out +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/wb_fsm_state +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu/next_fsm_state +add wave -noupdate -divider {DBG WB Module} +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/tck_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/module_tdo_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/tdi_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/capture_dr_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/shift_dr_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/update_dr_i +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_register_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/module_select_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/top_inhibit_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/rst_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_clk_i +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_adr_o +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_dat_o +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_dat_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_cyc_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_stb_o +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_sel_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_we_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_ack_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_cab_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/wb_err_i +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_cti_o +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/wb_bte_o +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/address_counter +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/bit_count +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/word_count +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/operation +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_out_shift_reg +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/internal_register_select +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/internal_reg_error +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/addr_sel +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/addr_ct_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/op_reg_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/bit_ct_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/bit_ct_rst +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/word_ct_sel +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/word_ct_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/out_reg_ld_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/out_reg_shift_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/out_reg_data_sel +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/tdo_output_sel +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu_strobe +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_clr +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_in_sel +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_shift_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/regsel_ld_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/intreg_ld_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/error_reg_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu_clr_err +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/word_count_zero +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/bit_count_max +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/module_cmd +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu_ready +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu_err +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/burst_instruction +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/intreg_instruction +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/intreg_write +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/rd_op +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_match +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/bit_count_32 +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/word_size_bits +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/word_size_bytes +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/incremented_address +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_to_addr_counter +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_to_word_counter +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/decremented_word_count +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/address_data_in +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/count_data_in +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/operation_in +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_to_biu +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_from_biu +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/crc_data_out +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_data_in +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/crc_serial_out +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/reg_select_data +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/out_reg_data +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/data_from_internal_reg +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_wb/biu_rst +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/module_state +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_wb/module_next_state +add wave -noupdate -divider {DBG Top} +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/tck_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/tdi_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/tdo_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/rst_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/shift_dr_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/pause_dr_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/update_dr_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/capture_dr_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/debug_select_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_clk_i +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/wb_adr_o +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/wb_dat_o +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/wb_dat_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_cyc_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_stb_o +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/wb_sel_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_we_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_ack_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_cab_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/wb_err_i +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/wb_cti_o +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/wb_bte_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_clk_i +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/cpu0_addr_o +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/cpu0_data_i +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/cpu0_data_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_bp_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_stall_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_stb_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_we_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_ack_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/cpu0_rst_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/tdo_wb +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/tdo_cpu0 +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/tdo_cpu1 +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/input_shift_reg +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/module_id_reg +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/select_inhibit +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/module_inhibit +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/select_cmd +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/module_id_in +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/module_selects +add wave -noupdate -divider {DBG CPU0 Module} +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/tck_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/module_tdo_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/tdi_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/capture_dr_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/shift_dr_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/update_dr_i +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_register_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/module_select_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/top_inhibit_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/rst_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_clk_i +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_addr_o +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_data_i +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_data_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_stb_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_we_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_ack_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_rst_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_bp_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/cpu_stall_o +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/address_counter +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/bit_count +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/word_count +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/operation +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_out_shift_reg +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/internal_register_select +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/internal_reg_status +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/addr_sel +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/addr_ct_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/op_reg_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/bit_ct_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/bit_ct_rst +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/word_ct_sel +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/word_ct_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/out_reg_ld_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/out_reg_shift_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/out_reg_data_sel +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/tdo_output_sel +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/biu_strobe +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_clr +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_in_sel +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_shift_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/regsel_ld_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/intreg_ld_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/word_count_zero +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/bit_count_max +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/module_cmd +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/biu_ready +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/burst_instruction +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/intreg_instruction +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/intreg_write +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/rd_op +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_match +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/bit_count_32 +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/word_size_bits +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/address_increment +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/incremented_address +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_to_addr_counter +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_to_word_counter +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/decremented_word_count +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/address_data_in +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/count_data_in +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/operation_in +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_to_biu +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_from_biu +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_data_out +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_data_in +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/crc_serial_out +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/reg_select_data +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/out_reg_data +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/data_from_internal_reg +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/status_reg_wr +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/module_state +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/module_next_state +add wave -noupdate -divider {DBG CPU0 BIU} +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/tck_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rst_i +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/data_i +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/data_o +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/addr_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/strobe_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rd_wrn_i +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rdy_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_clk_i +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_addr_o +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_data_i +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_data_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_stb_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_we_o +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_ack_i +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/addr_reg +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/data_in_reg +add wave -noupdate -format Literal /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/data_out_reg +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/wr_reg +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/str_sync +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_tff1 +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_tff2 +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_tff2q +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/str_sync_wbff1 +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/str_sync_wbff2 +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/str_sync_wbff2q +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/data_o_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_en +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/start_toggle +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/cpu_fsm_state +add wave -noupdate -format Logic /xsv_fpga_top/dbg_top/i_dbg_cpu_or1k/or1k_biu_i/next_fsm_state +add wave -noupdate -divider {CPU debug unit} +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/clk +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/rst +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcpu_cycstb_i +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcpu_we_i +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcpu_adr_i +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcpu_dat_lsu +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcpu_dat_dc +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/icpu_cycstb_i +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/ex_freeze +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/branch_op +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/ex_insn +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/id_pc +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/spr_dat_npc +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/rf_dataw +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/du_dsr +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/du_stall +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/du_addr +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/du_dat_i +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/du_dat_o +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/du_read +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/du_write +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/du_except +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/du_hwbkpt +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/spr_cs +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/spr_write +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/spr_addr +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/spr_dat_i +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/spr_dat_o +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_stall_i +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_ewt_i +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dbg_lss_o +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dbg_is_o +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dbg_wp_o +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_bp_o +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_stb_i +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_we_i +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dbg_adr_i +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dbg_dat_i +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dbg_dat_o +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_ack_o +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dmr1 +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dmr2 +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dsr +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/drr +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr0 +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr1 +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr2 +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr3 +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr4 +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr5 +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr6 +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dvr7 +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr0 +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr1 +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr2 +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr3 +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr4 +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr5 +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr6 +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dcr7 +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dwcr0 +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/dwcr1 +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dmr1_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dmr2_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dsr_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/drr_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr0_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr1_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr2_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr3_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr4_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr5_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr6_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dvr7_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr0_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr1_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr2_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr3_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr4_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr5_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr6_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dcr7_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dwcr0_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dwcr1_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_du/dbg_bp_r +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/except_stop +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/tbia_dat_o +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/tbim_dat_o +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/tbar_dat_o +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_du/tbts_dat_o +add wave -noupdate -divider {CPU SPRs} +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/clk +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/rst +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/flagforw +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/flag_we +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/flag +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/cyforw +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/cy_we +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/carry +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/addrbase +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/addrofs +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/dat_i +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/alu_op +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/branch_op +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/epcr +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/eear +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/esr +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/except_started +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/to_wbmux +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/epcr_we +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/eear_we +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/esr_we +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/pc_we +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/sr_we +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/to_sr +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/sr +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_cfgr +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_rf +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_npc +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_ppc +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_mac +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_pic +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_tt +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_pm +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_dmmu +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_immu +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_du +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_addr +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_dat_o +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_cs +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/spr_we +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/du_addr +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/du_dat_du +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/du_read +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/du_write +add wave -noupdate -format Literal -radix hexadecimal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/du_dat_cpu +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/write_spr +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/read_spr +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/cfgr_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/rf_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/npc_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/ppc_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/sr_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/epcr_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/eear_sel +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/esr_sel +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/sys_data +add wave -noupdate -format Logic /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/du_access +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/sprs_op +add wave -noupdate -format Literal /xsv_fpga_top/or1200_top/or1200_cpu/or1200_sprs/unqualified_cs +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {6180 ps} 0} +configure wave -namecolwidth 391 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {0 ps} {6180 ps} Index: adv_dbg_if/bench/full_system/xsv_fpga_top.v =================================================================== --- adv_dbg_if/bench/full_system/xsv_fpga_top.v (nonexistent) +++ adv_dbg_if/bench/full_system/xsv_fpga_top.v (revision 3) @@ -0,0 +1,911 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1K test application for XESS XSV board, Top Level //// +//// //// +//// This file is part of the OR1K test application //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Top level instantiating all the blocks. //// +//// //// +//// To Do: //// +//// - nothing really //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: xsv_fpga_top.v,v $ +// Revision 1.3 2008/07/11 08:22:17 Nathan +// Added code to make the native TAP simulate a Xilinx BSCAN device, and code to simulate the behavior of the xilinx_internal_jtag module. The adv_dbg_module should get inputs that emulate the xilinx_internal_jtag device outputs. +// +// Revision 1.10 2004/04/05 08:44:35 lampret +// Merged branch_qmem into main tree. +// +// Revision 1.8 2003/04/07 21:05:58 lampret +// WB = 1/2 RISC clock test code enabled. +// +// Revision 1.7 2003/04/07 01:28:17 lampret +// Adding OR1200_CLMODE_1TO2 test code. +// +// Revision 1.6 2002/08/12 05:35:12 lampret +// rty_i are unused - tied to zero. +// +// Revision 1.5 2002/03/29 20:58:51 lampret +// Changed hardcoded address for fake MC to use a define. +// +// Revision 1.4 2002/03/29 16:30:47 lampret +// Fixed port names that changed. +// +// Revision 1.3 2002/03/29 15:50:03 lampret +// Added response from memory controller (addr 0x60000000) +// +// Revision 1.2 2002/03/21 17:39:16 lampret +// Fixed some typos +// +// + +`include "xsv_fpga_defines.v" +//`include "bench_defines.v" + +module xsv_fpga_top ( + + // + // Global signals + // + //clk, + //rstn, + + // UART signals + uart_stx, uart_srx + + // SDRAM signals + /* + sdram_clk_i, sdram_addr_o, sdram_ba_o, sdram_dqm_o, + sdram_we_o, sdram_cas_o, sdram_ras_o, + sdram_cke_o, sdram_cs_o, sdram_data_io + */ +); + +// +// I/O Ports +// + +// +// Global +// +//input clk; +//input rstn; + +// UART +input uart_srx; +output uart_stx; + +// SDRAM +/* +input sdram_clk_i; +output [11:0] sdram_addr_o; +output [1:0] sdram_ba_o; +output [3:0] sdram_dqm_o; +output sdram_we_o; +output sdram_cas_o; +output sdram_ras_o; +output sdram_cke_o; +output sdram_cs_o; +inout [31:0] sdram_data_io; +*/ + +// +// Internal wires +// + +wire clk; +wire rstn; + +// +// Debug core master i/f wires +// +wire [31:0] wb_dm_adr_o; +wire [31:0] wb_dm_dat_i; +wire [31:0] wb_dm_dat_o; +wire [3:0] wb_dm_sel_o; +wire wb_dm_we_o; +wire wb_dm_stb_o; +wire wb_dm_cyc_o; +wire wb_dm_cab_o; +wire wb_dm_ack_i; +wire wb_dm_err_i; + +// +// Debug <-> RISC wires +// +wire [3:0] dbg_lss; +wire [1:0] dbg_is; +wire [10:0] dbg_wp; +wire dbg_bp; +wire [31:0] dbg_dat_dbg; +wire [31:0] dbg_dat_risc; +wire [31:0] dbg_adr; +wire dbg_ewt; +wire dbg_stall; +wire dbg_we; +wire dbg_stb; +wire dbg_ack; +wire dbg_cpu0_rst; + +// +// TAP<->dbg_interface +// +wire debug_rst; +wire debug_select; +wire debug_tdi; +wire debug_tdo; +wire shift_dr; +wire pause_dr; +wire update_dr; +wire capture_dr; +wire drck; // To emulate the BSCAN_VIRTEX/SPARTAN devices + +// +// RISC instruction master i/f wires +// +wire [31:0] wb_rim_adr_o; +wire wb_rim_cyc_o; +wire [31:0] wb_rim_dat_i; +wire [31:0] wb_rim_dat_o; +wire [3:0] wb_rim_sel_o; +wire wb_rim_ack_i; +wire wb_rim_err_i; +wire wb_rim_rty_i = 1'b0; +wire wb_rim_we_o; +wire wb_rim_stb_o; +wire wb_rim_cab_o; +//wire [31:0] wb_rif_adr; +//reg prefix_flash; + +// +// RISC data master i/f wires +// +wire [31:0] wb_rdm_adr_o; +wire wb_rdm_cyc_o; +wire [31:0] wb_rdm_dat_i; +wire [31:0] wb_rdm_dat_o; +wire [3:0] wb_rdm_sel_o; +wire wb_rdm_ack_i; +wire wb_rdm_err_i; +wire wb_rdm_rty_i = 1'b0; +wire wb_rdm_we_o; +wire wb_rdm_stb_o; +wire wb_rdm_cab_o; + +// +// RISC misc +// +//wire [19:0] pic_ints; + +// +// SRAM controller slave i/f wires +// +wire [31:0] wb_ss_dat_i; +wire [31:0] wb_ss_dat_o; +wire [31:0] wb_ss_adr_i; +wire [3:0] wb_ss_sel_i; +wire wb_ss_we_i; +wire wb_ss_cyc_i; +wire wb_ss_stb_i; +wire wb_ss_ack_o; +wire wb_ss_err_o; + + +// +// UART16550 core slave i/f wires +// +wire [31:0] wb_us_dat_i; +wire [31:0] wb_us_dat_o; +wire [31:0] wb_us_adr_i; +wire [3:0] wb_us_sel_i; +wire wb_us_we_i; +wire wb_us_cyc_i; +wire wb_us_stb_i; +wire wb_us_ack_o; +wire wb_us_err_o; + +// +// UART external i/f wires +// +wire uart_stx; +wire uart_srx; + + +// +// Memory controller core slave i/f wires +// +/* +wire [31:0] wb_mem_dat_i; +wire [31:0] wb_mem_dat_o; +wire [31:0] wb_mem_adr_i; +wire [3:0] wb_mem_sel_i; +wire wb_mem_we_i; +wire wb_mem_cyc_i; +wire wb_mem_stb_i; +wire wb_mem_ack_o; +wire wb_mem_err_o; + +// Internal mem control wires +wire [7:0] mc_cs; +wire [12:0] mc_addr_o; + + +// Memory control external wires +wire sdram_clk_i; +wire [11:0] sdram_addr_o; +wire [1:0] sdram_ba_o; +wire [3:0] sdram_dqm_o; +wire sdram_we_o; +wire sdram_cas_o; +wire sdram_ras_o; +wire sdram_cke_o; +wire sdram_cs_o; +wire [31:0] sdram_data_io; +*/ + +// +// JTAG wires +// +wire jtag_tdi; +wire jtag_tms; +wire jtag_tck; +wire jtag_trst; +wire jtag_tdo; + + +// +// Reset debounce +// +reg rstn_debounce; +wire rst_r; +reg wb_rst; +reg cpu_rst; + +// +// Global clock +// +`ifdef OR1200_CLMODE_1TO2 +reg wb_clk; +`else +wire wb_clk; +`endif + +// +// Reset debounce +// +always @(posedge wb_clk or negedge rstn) + if (~rstn) + rstn_debounce <= 1'b0; + else + rstn_debounce <= #1 1'b1; + +assign rst_r = ~rstn_debounce; +//assign dbg_trst = rstn_debounce & jtag_trst; + +// +// Reset debounce +// +always @(posedge wb_clk) + wb_rst <= #1 rst_r; + +always @ (posedge wb_clk) + cpu_rst <= dbg_cpu0_rst | rst_r; + +// +// This is purely for testing 1/2 WB clock +// This should never be used when implementing in +// an FPGA. It is used only for simulation regressions. +// +`ifdef OR1200_CLMODE_1TO2 +initial wb_clk = 0; +always @(posedge clk) + wb_clk = ~wb_clk; +`else +// +// Some Xilinx P&R tools need this +// +`ifdef TARGET_VIRTEX +IBUFG IBUFG1 ( + .O ( wb_clk ), + .I ( clk ) +); +`else +assign wb_clk = clk; +`endif +`endif // OR1200_CLMODE_1TO2 + +// +// Unused WISHBONE signals +// +assign wb_us_err_o = 1'b0; + + +assign jtag_tvref = 1'b1; +assign jtag_tgnd = 1'b0; + +// JTAG / adv. debug control testbench +adv_debug_tb tb ( + +.jtag_tck_o(jtag_tck), +.jtag_tms_o(jtag_tms), +.jtag_tdo_o(jtag_tdi), +.jtag_tdi_i(jtag_tdo), + +.wb_clk_o(clk), +.sys_rstn_o(rstn) +); + +// +// JTAG TAP controller instantiation +// +tap_top tap ( + // JTAG pads + .tms_pad_i(jtag_tms), + .tck_pad_i(jtag_tck), + .trstn_pad_i(1'b1), + .tdi_pad_i(jtag_tdi), + .tdo_pad_o(jtag_tdo), + .tdo_padoe_o(), + + // TAP states + .test_logic_reset_o(debug_rst), + .run_test_idle_o(), + .shift_dr_o(shift_dr), + .pause_dr_o(), + .update_dr_o(update_dr), + .capture_dr_o(capture_dr), + + // Select signals for boundary scan or mbist + .extest_select_o(), + .sample_preload_select_o(), + .mbist_select_o(), + .debug_select_o(debug_select), + + // TDO signal that is connected to TDI of sub-modules. + .tdo_o(debug_tdi), + + // TDI signals from sub-modules + .debug_tdi_i(debug_tdo), // from debug module + .bs_chain_tdi_i(1'b0), // from Boundary Scan Chain + .mbist_tdi_i(1'b0) // from Mbist Chain + ); + +// This is taken from the xilinx bscan_virtex4.v module +// It simulates the DRCK output of a BSCAN_* block +assign drck = ((debug_select & !shift_dr & !capture_dr) || + (debug_select & shift_dr & jtag_tck) || + (debug_select & capture_dr & jtag_tck)); + +reg xshift; +reg xcapture; +reg xupdate; +reg xselect; + +// TAP state outputs are also delayed half a cycle. +always @(negedge jtag_tck) +begin + xshift = shift_dr; + xcapture = capture_dr; + xupdate = update_dr; + xselect = debug_select; +end + +////////////////////////////////////////// + + +wire tck2; +assign tck2 = (drck & !xupdate); + +reg update2; + +always @ (posedge xupdate or posedge xcapture or negedge xselect) +begin + if(xupdate) update2 <= 1'b1; + else if(xcapture) update2 <= 1'b0; + else if(!xselect) update2 <= 1'b0; +end + +// +// Instantiation of the development i/f +// +dbg_top dbg_top ( + + // JTAG pins + .tck_i ( tck2 ), + .tdi_i ( debug_tdi ), + .tdo_o ( debug_tdo ), + .rst_i ( debug_rst ), + + // TAP states + .shift_dr_i( xshift ), + .pause_dr_i( pause_dr ), + .update_dr_i( update2 ), + .capture_dr_i (xcapture), + + // Instructions + .debug_select_i( xselect ), + + // RISC signals + .cpu0_clk_i ( wb_clk ), + .cpu0_addr_o ( dbg_adr ), + .cpu0_data_i ( dbg_dat_risc ), + .cpu0_data_o ( dbg_dat_dbg ), + .cpu0_bp_i ( dbg_bp ), + .cpu0_stall_o ( dbg_stall ), + .cpu0_stb_o ( dbg_stb ), + .cpu0_we_o ( dbg_we ), + .cpu0_ack_i ( dbg_ack ), + .cpu0_rst_o ( dbg_cpu0_rst), + + // WISHBONE common + .wb_clk_i ( wb_clk ), + + // WISHBONE master interface + .wb_adr_o ( wb_dm_adr_o ), + .wb_dat_o ( wb_dm_dat_o ), + .wb_dat_i ( wb_dm_dat_i ), + .wb_cyc_o ( wb_dm_cyc_o ), + .wb_stb_o ( wb_dm_stb_o ), + .wb_sel_o ( wb_dm_sel_o ), + .wb_we_o ( wb_dm_we_o ), + .wb_ack_i ( wb_dm_ack_i ), + .wb_cab_o ( wb_dm_cab_o ), + .wb_err_i ( wb_dm_err_i ), + .wb_cti_o (), + .wb_bte_o () +); + + +// +// Instantiation of the OR1200 RISC +// +or1200_top or1200_top ( + + // Common + .rst_i ( cpu_rst ), + .clk_i ( clk ), +`ifdef OR1200_CLMODE_1TO2 + .clmode_i ( 2'b01 ), +`else +`ifdef OR1200_CLMODE_1TO4 + .clmode_i ( 2'b11 ), +`else + .clmode_i ( 2'b00 ), +`endif +`endif + + // WISHBONE Instruction Master + .iwb_clk_i ( wb_clk ), + .iwb_rst_i ( wb_rst ), + .iwb_cyc_o ( wb_rim_cyc_o ), + .iwb_adr_o ( wb_rim_adr_o ), + .iwb_dat_i ( wb_rim_dat_i ), + .iwb_dat_o ( wb_rim_dat_o ), + .iwb_sel_o ( wb_rim_sel_o ), + .iwb_ack_i ( wb_rim_ack_i ), + .iwb_err_i ( wb_rim_err_i ), + .iwb_rty_i ( wb_rim_rty_i ), + .iwb_we_o ( wb_rim_we_o ), + .iwb_stb_o ( wb_rim_stb_o ), + .iwb_cab_o ( wb_rim_cab_o ), + + // WISHBONE Data Master + .dwb_clk_i ( wb_clk ), + .dwb_rst_i ( wb_rst ), + .dwb_cyc_o ( wb_rdm_cyc_o ), + .dwb_adr_o ( wb_rdm_adr_o ), + .dwb_dat_i ( wb_rdm_dat_i ), + .dwb_dat_o ( wb_rdm_dat_o ), + .dwb_sel_o ( wb_rdm_sel_o ), + .dwb_ack_i ( wb_rdm_ack_i ), + .dwb_err_i ( wb_rdm_err_i ), + .dwb_rty_i ( wb_rdm_rty_i ), + .dwb_we_o ( wb_rdm_we_o ), + .dwb_stb_o ( wb_rdm_stb_o ), + .dwb_cab_o ( wb_rdm_cab_o ), + + // Debug + .dbg_stall_i ( dbg_stall ), // Set to 1'b0 if debug is absent / broken + .dbg_dat_i ( dbg_dat_dbg ), + .dbg_adr_i ( dbg_adr ), + .dbg_ewt_i ( 1'b0 ), + .dbg_lss_o ( ), + .dbg_is_o ( ), + .dbg_wp_o ( ), + .dbg_bp_o ( dbg_bp ), + .dbg_dat_o ( dbg_dat_risc ), + .dbg_ack_o ( dbg_ack ), + .dbg_stb_i ( dbg_stb ), + .dbg_we_i ( dbg_we ), + + // Power Management + .pm_clksd_o ( ), + .pm_cpustall_i ( 1'b0 ), + .pm_dc_gate_o ( ), + .pm_ic_gate_o ( ), + .pm_dmmu_gate_o ( ), + .pm_immu_gate_o ( ), + .pm_tt_gate_o ( ), + .pm_cpu_gate_o ( ), + .pm_wakeup_o ( ), + .pm_lvolt_o ( ), + + // Interrupts + .pic_ints_i (20'b0) +); + + +// +// Instantiation of the On-chip RAM controller +// +onchip_ram_top #( + .dwidth (32), + .size_bytes(16384) + ) onchip_ram_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_dat_i ( wb_ss_dat_i ), + .wb_dat_o ( wb_ss_dat_o ), + .wb_adr_i ( wb_ss_adr_i ), + .wb_sel_i ( wb_ss_sel_i ), + .wb_we_i ( wb_ss_we_i ), + .wb_cyc_i ( wb_ss_cyc_i ), + .wb_stb_i ( wb_ss_stb_i ), + .wb_ack_o ( wb_ss_ack_o ), + .wb_err_o ( wb_ss_err_o ) +); + +// +// Instantiation of the UART16550 +// +uart_top uart_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_adr_i ( wb_us_adr_i[4:0] ), + .wb_dat_i ( wb_us_dat_i ), + .wb_dat_o ( wb_us_dat_o ), + .wb_we_i ( wb_us_we_i ), + .wb_stb_i ( wb_us_stb_i ), + .wb_cyc_i ( wb_us_cyc_i ), + .wb_ack_o ( wb_us_ack_o ), + .wb_sel_i ( wb_us_sel_i ), + + // Interrupt request + .int_o ( ), + + // UART signals + // serial input/output + .stx_pad_o ( uart_stx ), + .srx_pad_i ( uart_srx ), + + // modem signals + .rts_pad_o ( ), + .cts_pad_i ( 1'b0 ), + .dtr_pad_o ( ), + .dsr_pad_i ( 1'b0 ), + .ri_pad_i ( 1'b0 ), + .dcd_pad_i ( 1'b0 ) +); + +/* +mc_wrapper mc_wrapper ( + .clk_i ( wb_clk ), + .rst_i ( wb_rst ), + .clk_mem_i ( sdram_clk_i ), + + .wb_data_i ( wb_mem_dat_i ), + .wb_data_o ( wb_mem_dat_o ), + .wb_addr_i ( wb_mem_adr_i ), + .wb_sel_i ( wb_mem_sel_i ), + .wb_we_i ( wb_mem_we_i ), + .wb_cyc_i ( wb_mem_cyc_i ), + .wb_stb_i ( wb_mem_stb_i ), + .wb_ack_o ( wb_mem_ack_o ), + .wb_err_o ( wb_mem_err_o ), + + .susp_req_i ( 1'b0 ), + .resume_req_i ( 1'b0 ), + .suspended_o (), + .poc_o ( ), // This is an output so the rest of the system can configure itself + + .sdram_addr_o ( mc_addr_o ), + .sdram_ba_o ( sdram_ba_o ), + .sdram_cas_n_o ( sdram_cas_o ), + .sdram_ras_n_o ( sdram_ras_o ), + .sdram_cke_n_o ( sdram_cke_o ), + + .mc_dqm_o ( sdram_dqm_o ), + .mc_we_n_o ( sdram_we_o ), + .mc_oe_n_o ( ), + .mc_data_io ( sdram_data_io ), + .mc_parity_io ( ), + .mc_cs_n_o ( mc_cs ) + ); + +assign sdram_cs_o = mc_cs[0]; +assign sdram_addr_o = mc_addr_o[11:0]; +*/ + +// +// Instantiation of the Traffic COP +// +wb_conbus_top #(.s0_addr_w (`APP_ADDR_DEC_W), + .s0_addr (`APP_ADDR_SDRAM), + .s1_addr_w (`APP_ADDR_DEC2_W), + .s1_addr (`APP_ADDR_OCRAM), + .s27_addr_w (`APP_ADDR_DECP_W), + .s2_addr (`APP_ADDR_VGA), + .s3_addr (`APP_ADDR_ETH), + .s4_addr (`APP_ADDR_AUDIO), + .s5_addr (`APP_ADDR_UART), + .s6_addr (`APP_ADDR_PS2), + .s7_addr (`APP_ADDR_RES1) + ) tc_top ( + + // WISHBONE common + .clk_i ( wb_clk ), + .rst_i ( wb_rst ), + + // WISHBONE Initiator 0 + .m0_cyc_i ( 1'b0 ), + .m0_stb_i ( 1'b0 ), + .m0_cab_i ( 1'b0 ), + .m0_adr_i ( 32'h0000_0000 ), + .m0_sel_i ( 4'b0000 ), + .m0_we_i ( 1'b0 ), + .m0_dat_i ( 32'h0000_0000 ), + .m0_dat_o ( ), + .m0_ack_o ( ), + .m0_err_o ( ), + + // WISHBONE Initiator 1 + .m1_cyc_i ( 1'b0 ), + .m1_stb_i ( 1'b0 ), + .m1_cab_i ( 1'b0 ), + .m1_adr_i ( 32'h0000_0000 ), + .m1_sel_i ( 4'b0000 ), + .m1_we_i ( 1'b0 ), + .m1_dat_i ( 32'h0000_0000 ), + .m1_dat_o ( ), + .m1_ack_o ( ), + .m1_err_o ( ), + + // WISHBONE Initiator 2 + .m2_cyc_i ( 1'b0 ), + .m2_stb_i ( 1'b0 ), + .m2_cab_i ( 1'b0 ), + .m2_adr_i ( 32'h0000_0000 ), + .m2_sel_i ( 4'b0000 ), + .m2_we_i ( 1'b0 ), + .m2_dat_i ( 32'h0000_0000 ), + .m2_dat_o ( ), + .m2_ack_o ( ), + .m2_err_o ( ), + + // WISHBONE Initiator 3 + .m3_cyc_i ( wb_dm_cyc_o ), + .m3_stb_i ( wb_dm_stb_o ), + .m3_cab_i ( wb_dm_cab_o ), + .m3_adr_i ( wb_dm_adr_o ), + .m3_sel_i ( wb_dm_sel_o ), + .m3_we_i ( wb_dm_we_o ), + .m3_dat_i ( wb_dm_dat_o ), + .m3_dat_o ( wb_dm_dat_i ), + .m3_ack_o ( wb_dm_ack_i ), + .m3_err_o ( wb_dm_err_i ), + + // WISHBONE Initiator 4 + .m4_cyc_i ( wb_rdm_cyc_o ), + .m4_stb_i ( wb_rdm_stb_o ), + .m4_cab_i ( wb_rdm_cab_o ), + .m4_adr_i ( wb_rdm_adr_o ), + .m4_sel_i ( wb_rdm_sel_o ), + .m4_we_i ( wb_rdm_we_o ), + .m4_dat_i ( wb_rdm_dat_o ), + .m4_dat_o ( wb_rdm_dat_i ), + .m4_ack_o ( wb_rdm_ack_i ), + .m4_err_o ( wb_rdm_err_i ), + + // WISHBONE Initiator 5 + .m5_cyc_i ( wb_rim_cyc_o ), + .m5_stb_i ( wb_rim_stb_o ), + .m5_cab_i ( wb_rim_cab_o ), + .m5_adr_i ( wb_rim_adr_o ), + .m5_sel_i ( wb_rim_sel_o ), + .m5_we_i ( wb_rim_we_o ), + .m5_dat_i ( wb_rim_dat_o ), + .m5_dat_o ( wb_rim_dat_i ), + .m5_ack_o ( wb_rim_ack_i ), + .m5_err_o ( wb_rim_err_i ), + + // WISHBONE Initiator 6 + .m6_cyc_i ( 1'b0 ), + .m6_stb_i ( 1'b0 ), + .m6_cab_i ( 1'b0 ), + .m6_adr_i ( 32'h0000_0000 ), + .m6_sel_i ( 4'b0000 ), + .m6_we_i ( 1'b0 ), + .m6_dat_i ( 32'h0000_0000 ), + .m6_dat_o ( ), + .m6_ack_o ( ), + .m6_err_o ( ), + + // WISHBONE Initiator 7 + .m7_cyc_i ( 1'b0 ), + .m7_stb_i ( 1'b0 ), + .m7_cab_i ( 1'b0 ), + .m7_adr_i ( 32'h0000_0000 ), + .m7_sel_i ( 4'b0000 ), + .m7_we_i ( 1'b0 ), + .m7_dat_i ( 32'h0000_0000 ), + .m7_dat_o ( ), + .m7_ack_o ( ), + .m7_err_o ( ), + + // WISHBONE Target 0 + .s0_cyc_o ( ), + .s0_stb_o ( ), + .s0_cab_o ( ), + .s0_adr_o ( ), + .s0_sel_o ( ), + .s0_we_o ( ), + .s0_dat_o ( ), + .s0_dat_i ( 32'h0000_0000 ), + .s0_ack_i ( 1'b0 ), + .s0_err_i ( 1'b0 ), + .s0_rty_i ( 1'b0 ), + /* + .s0_cyc_o ( wb_mem_cyc_i ), + .s0_stb_o ( wb_mem_stb_i ), + .s0_cab_o ( wb_mem_cab_i ), + .s0_adr_o ( wb_mem_adr_i ), + .s0_sel_o ( wb_mem_sel_i ), + .s0_we_o ( wb_mem_we_i ), + .s0_dat_o ( wb_mem_dat_i ), + .s0_dat_i ( wb_mem_dat_o ), + .s0_ack_i ( wb_mem_ack_o ), + .s0_err_i ( wb_mem_err_o ), + .s0_rty_i ( 1'b0), + */ + + // WISHBONE Target 1 + .s1_cyc_o ( wb_ss_cyc_i ), + .s1_stb_o ( wb_ss_stb_i ), + .s1_cab_o ( wb_ss_cab_i ), + .s1_adr_o ( wb_ss_adr_i ), + .s1_sel_o ( wb_ss_sel_i ), + .s1_we_o ( wb_ss_we_i ), + .s1_dat_o ( wb_ss_dat_i ), + .s1_dat_i ( wb_ss_dat_o ), + .s1_ack_i ( wb_ss_ack_o ), + .s1_err_i ( wb_ss_err_o ), + .s1_rty_i ( 1'b0 ), + + // WISHBONE Target 2 + .s2_cyc_o ( ), + .s2_stb_o ( ), + .s2_cab_o ( ), + .s2_adr_o ( ), + .s2_sel_o ( ), + .s2_we_o ( ), + .s2_dat_o ( ), + .s2_dat_i ( 32'h0000_0000 ), + .s2_ack_i ( 1'b0 ), + .s2_err_i ( 1'b0 ), + .s2_rty_i ( 1'b0 ), + + // WISHBONE Target 3 + .s3_cyc_o ( ), + .s3_stb_o ( ), + .s3_cab_o ( ), + .s3_adr_o ( ), + .s3_sel_o ( ), + .s3_we_o ( ), + .s3_dat_o ( ), + .s3_dat_i ( 32'h0000_0000 ), + .s3_ack_i ( 1'b0 ), + .s3_err_i ( 1'b0 ), + .s3_rty_i ( 1'b0), + + // WISHBONE Target 4 + .s4_cyc_o ( ), + .s4_stb_o ( ), + .s4_cab_o ( ), + .s4_adr_o ( ), + .s4_sel_o ( ), + .s4_we_o ( ), + .s4_dat_o ( ), + .s4_dat_i ( 32'h0000_0000 ), + .s4_ack_i ( 1'b0 ), + .s4_err_i ( 1'b0 ), + .s4_rty_i ( 1'b0), + + // WISHBONE Target 5 + .s5_cyc_o ( wb_us_cyc_i ), + .s5_stb_o ( wb_us_stb_i ), + .s5_cab_o ( wb_us_cab_i ), + .s5_adr_o ( wb_us_adr_i ), + .s5_sel_o ( wb_us_sel_i ), + .s5_we_o ( wb_us_we_i ), + .s5_dat_o ( wb_us_dat_i ), + .s5_dat_i ( wb_us_dat_o ), + .s5_ack_i ( wb_us_ack_o ), + .s5_err_i ( wb_us_err_o ), + .s5_rty_i ( 1'b0 ), + + // WISHBONE Target 6 + .s6_cyc_o ( ), + .s6_stb_o ( ), + .s6_cab_o ( ), + .s6_adr_o ( ), + .s6_sel_o ( ), + .s6_we_o ( ), + .s6_dat_o ( ), + .s6_dat_i ( 32'h0000_0000 ), + .s6_ack_i ( 1'b0 ), + .s6_err_i ( 1'b0 ), + .s6_rty_i ( 1'b0), + + // WISHBONE Target 7 + .s7_cyc_o ( ), + .s7_stb_o ( ), + .s7_cab_o ( ), + .s7_adr_o ( ), + .s7_sel_o ( ), + .s7_we_o ( ), + .s7_dat_o ( ), + .s7_dat_i ( 32'h0000_0000 ), + .s7_ack_i ( 1'b0 ), + .s7_err_i ( 1'b0 ), + .s7_rty_i ( 1'b0) + +); + +//initial begin +// $dumpvars(0); +// $dumpfile("dump.vcd"); +//end + +endmodule Index: adv_dbg_if/bench/full_system/xsv_fpga_defines.v =================================================================== --- adv_dbg_if/bench/full_system/xsv_fpga_defines.v (nonexistent) +++ adv_dbg_if/bench/full_system/xsv_fpga_defines.v (revision 3) @@ -0,0 +1,100 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1K test app definitions //// +//// //// +//// This file is part of the OR1K test application //// +//// http://www.opencores.org/cores/or1k/xess/ //// +//// //// +//// Description //// +//// DEfine target technology etc. Right now FIFOs are available //// +//// only for Xilinx Virtex FPGAs. (TARGET_VIRTEX) //// +//// //// +//// To Do: //// +//// - nothing really //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, damjan.lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: xsv_fpga_defines.v,v $ +// Revision 1.2 2008/07/11 08:16:01 Nathan +// Ran through dos2unix +// +// Revision 1.1 2008/07/08 19:11:54 Nathan +// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system. +// +// Revision 1.4 2004/04/05 08:44:35 lampret +// Merged branch_qmem into main tree. +// +// Revision 1.2 2002/03/29 20:58:51 lampret +// Changed hardcoded address for fake MC to use a define. +// +// Revision 1.1.1.1 2002/03/21 16:55:44 lampret +// First import of the "new" XESS XSV environment. +// +// +// + +// +// Define to target to Xilinx Virtex +// +//`define TARGET_VIRTEX + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_RES3 19:6 + +// +// Address map +// +`define APP_ADDR_DEC_W 3 +`define APP_ADDR_SDRAM `APP_ADDR_DEC_W'b001 +`define APP_ADDR_DEC2_W 8 +`define APP_ADDR_OCRAM `APP_ADDR_DEC2_W'h00 +`define APP_ADDR_DECP_W 8 +//`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h99 +`define APP_ADDR_VGA `APP_ADDR_DECP_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DECP_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DECP_W'h9d +`define APP_ADDR_UART `APP_ADDR_DECP_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DECP_W'h94 +`define APP_ADDR_RES1 `APP_ADDR_DECP_W'h9e +//`define APP_ADDR_RES2 `APP_ADDR_DECP_W'h9f +//`define APP_ADDR_FAKEMC 4'h6 + +// For simulation... +// `define DBG_IF_MODEL 1 Index: adv_dbg_if/bench/README_testbench.txt =================================================================== --- adv_dbg_if/bench/README_testbench.txt (nonexistent) +++ adv_dbg_if/bench/README_testbench.txt (revision 3) @@ -0,0 +1,25 @@ +1README_testbench.txt +Advanced Debug Module (adv_dbg_if) +Nathan Yawn, nathan.yawn@opencores.org + +Two testbenches are supplied with the advanced debug interface. The first +uses behavioral simulation of a wishbone bus with a memory attached, and +another behavioral simulatioin of an OR1200 CPU. This testbench performs +and tests bus / memory operations, and performs a few CPU operations, The +top-level module is in adv_dbg_tb.v. Other than the beavioral models, it +instantiates an adv_dbg_if (found in ../rtl/verilog/), and a JTAG TAP +("jtag" module, not included with this module). Note that the TAP +distributed by OpenCores will not work correctly; use the version modified +by Nathan Yawn. + +The second testbench includes an actuall wishbone/OR1200 system. Its +top-level entity is xsv_fpga_top. It instantiates a wb_conbus, an OR1200, +an onchipram, a jtag TAP, and a UART16550, along with an adv_dbg_if. The +testbench is also instantiated here, and is used to drive the inputs to +the JTAG TAP. This testbench is less polished, but includes a functional +test of the single-step capability of the CPU. + +Both testbenches were written for use in ModelSim (version 6.3). A +wave.do file is also included for each testbench, which will display a +useful collectino of signals in the ModelSim wave view. + Index: adv_dbg_if/bench/simulated_system/adv_dbg_tb.v =================================================================== --- adv_dbg_if/bench/simulated_system/adv_dbg_tb.v (nonexistent) +++ adv_dbg_if/bench/simulated_system/adv_dbg_tb.v (revision 3) @@ -0,0 +1,1065 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// adv_dbg_tb.v //// +//// //// +//// //// +//// Testbench for the SoC Advanced Debug Interface. //// +//// //// +//// Author(s): //// +//// Nathan Yawn (nathan.yawn@opencored.org) //// +//// //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: adv_dbg_tb.v,v $ +// Revision 1.2 2009/05/17 20:54:55 Nathan +// Changed email address to opencores.org +// +// Revision 1.1 2008/07/08 19:11:55 Nathan +// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system. +// +// Revision 1.11 2008/07/08 18:53:47 Nathan +// Fixed wrong include name. +// +// Revision 1.10 2008/06/30 20:09:19 Nathan +// Removed code to select top-level module as active (it served no purpose). Re-numbered modules, requiring changes to testbench and software driver. +// + + +`include "tap_defines.v" +`include "dbg_defines.v" +`include "dbg_wb_defines.v" +`include "wb_model_defines.v" + +// Polynomial for the CRC calculation +// Yes, it's backwards. Yes, this is on purpose. +// To decrease logic + routing, we want to shift the CRC calculation +// in the same direction we use to shift the data out, LSB first. +`define DBG_CRC_POLY 32'hedb88320 + +// These are indicies into an array which hold values for the JTAG outputs +`define JTAG_TMS 0 +`define JTAG_TCK 1 +`define JTAG_TDO 2 + +`define JTAG_TMS_bit 3'h1 +`define JTAG_TCK_bit 3'h2 +`define JTAG_TDO_bit 3'h4 + +`define wait_jtag_period #50 + + +module adv_debug_tb; + +// Connections to the JTAG TAP +reg jtag_tck_o; +reg jtag_tms_o; +reg jtag_tdo_o; +wire jtag_tdi_i; + +// Connections between TAP and debug module +wire capture_dr; +wire shift_dr; +wire pause_dr; +wire update_dr; +wire dbg_rst; +wire dbg_tdi; +wire dbg_tdo; +wire dbg_sel; + +// Connections between the debug module and the wishbone +`ifdef DBG_WISHBONE_SUPPORTED +wire [31:0] wb_adr; +wire [31:0] wb_dat_m; +wire [31:0] wb_dat_s; +wire wb_cyc; +wire wb_stb; +wire [3:0] wb_sel; +wire wb_we; +wire wb_ack; +wire wb_err; +reg wb_clk_i; // the wishbone clock +reg wb_rst_i; +`endif + +`ifdef DBG_CPU0_SUPPORTED +wire cpu0_clk; +wire [31:0]cpu0_addr; +wire [31:0] cpu0_data_c; +wire [31:0] cpu0_data_d; +wire cpu0_bp; +wire cpu0_stall; +wire cpu0_stb; +wire cpu0_we; +wire cpu0_ack; +wire cpu0_rst; +`endif + +`ifdef DBG_CPU1_SUPPORTED +reg cpu1_clk; +wire [31:0]cpu1_addr; +wire [31:0] cpu1_data_c; +wire [31:0] cpu1_data_d; +wire cpu1_bp; +wire cpu1_stall; +wire cpu1_stb; +wire cpu1_we; +wire cpu1_ack; +wire cpu1_rst; +`endif // `ifdef DBG_CPU1_SUPPORTED + +reg test_enabled; + +// Data which will be written to the WB interface +reg [31:0] static_data32 [0:15]; +reg [15:0] static_data16 [0:15]; +reg [7:0] static_data8 [0:15]; + +// Arrays to hold data read back from the WB interface, for comparison +reg [31:0] input_data32 [0:15]; +reg [15:0] input_data16 [0:15]; +reg [7:0] input_data8 [0:15]; + +reg [32:0] err_data; // holds the contents of the error register from the various modules + +reg failed; +integer i; + +initial +begin + jtag_tck_o = 1'b0; + jtag_tms_o = 1'b0; + jtag_tdo_o = 1'b0; +end + +// Provide the wishbone clock +`ifdef DBG_WISHBONE_SUPPORTED +initial +begin + wb_clk_i = 1'b0; + forever #7 wb_clk_i = ~wb_clk_i; // Odd frequency ratio to test the synchronization +end +`endif + +// Provide the CPU0 clock +//`ifdef DBG_CPU0_SUPPORTED +//initial +//begin + //cpu0_clk = 1'b0; + //forever #6 cpu0_clk = ~cpu0_clk; // Odd frequency ratio to test the synchronization +//end +//`endif + +// Start the test (and reset the wishbone) +initial +begin + test_enabled = 1'b0; + wb_rst_i = 1'b0; + #100; + wb_rst_i = 1'b1; + #100; + wb_rst_i = 1'b0; + + // Init the memory + initialize_memory(32'h0,32'h16); + + // Init the WB model + i_wb.cycle_response(`ACK_RESPONSE, 2, 0); // response type, wait cycles, retry_cycles + + #1 test_enabled<=#1 1'b1; +end + +// This is the main test procedure +always @ (posedge test_enabled) +begin + + $display("Starting advanced debug test"); + + reset_jtag; + #1000; + check_idcode; + #1000; + + // Select the debug module in the IR + set_ir(`DEBUG); + #1000; + + + /////////////////////////////////////////////////////////////////// + // Test CPU0 unit + //////////////////////////////////////////////////////////////////// +`ifdef DBG_CPU0_SUPPORTED + // Select the CPU0 unit in the debug module + #1000; + $display("Selecting CPU0 module at time %t", $time); + select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE); + + // Test reset, stall bits + #1000; + $display("Testing CPU0 intreg select at time %t", $time); + select_module_internal_register(32'h1, 1); // Really just a read, with discarded data + #1000; + select_module_internal_register(32'h0, 1); // Really just a read, with discarded data + #1000; + + // Read the stall and reset bits + $display("Testing reset and stall bits at time %t", $time); + read_module_internal_register(8'd2, err_data); // We assume the register is already selected + $display("Reset and stall bits are %x", err_data); + #1000; + + // Set rst/stall bits + $display("Setting reset and stall bits at time %t", $time); + write_module_internal_register(32'h0, 8'h1, 32'h3, 8'h2); // idx, idxlen, data, datalen + #1000; + + // Read the bits again + $display("Testing reset and stall bits again at time %t", $time); + read_module_internal_register(8'd2, err_data); // We assume the register is already selected + $display("Reset and stall bits are %x", err_data); + #1000; + + // Clear the bits + $display("Clearing reset and stall bits at time %t", $time); + write_module_internal_register(32'h0, 8'h1, 32'h0, 8'h2); // idx, idxlen, data, datalen + #1000; + + // Read the bits again + $display("Testing reset and stall bits again at time %t", $time); + read_module_internal_register(8'd2, err_data); // We assume the register is already selected + $display("Reset and stall bits are %x", err_data); + #1000; + + // Behavioral CPU model must be stalled in order to do SPR access + //$display("Setting reset and stall bits at time %t", $time); + write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h2); // idx, idxlen, data, datalen + #1000; + + // Test SPR bus access + $display("Testing CPU0 32-bit burst write at time %t", $time); + do_module_burst_write(3'h4, 16'd16, 32'h10); // 3-bit word size (bytes), 16-bit word count, 32-bit start address + #1000; + $display("Testing CPU0 32-bit burst read at time %t", $time); + do_module_burst_read(3'h4, 16'd16, 32'h0); + #1000; + +`endif + + + /////////////////////////////////////////////////////////////////// + // Test the Wishbone unit + //////////////////////////////////////////////////////////////////// + +`ifdef DBG_WISHBONE_SUPPORTED + // Select the WB unit in the debug module + #1000; + $display("Selecting Wishbone module at time %t", $time); + select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE); + + /* + // Test error conditions + #1000; + $display("Testing error (size 0 WB burst write) at time %t", $time); + do_module_burst_write(3'h1, 16'h0, 32'h0); // 0-word write = error, ignored + #1000; + $display("Testing error (size 0 WB burst read) at time %t", $time); + do_module_burst_read(3'h1, 16'h0, 32'h0); // 0-word read = error, ignored + + // Test NOP (a zero in the MSB, then a NOP opcode) + #1000; + $display("Testing NOP at time %t", $time); + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + jtag_write_stream(5'h0, 8'h5, 1); // write data, exit_1 + write_bit(`JTAG_TMS_bit); // update_dr + write_bit(3'h0); // idle + #1000; + */ + + #1000; + $display("Testing WB intreg select at time %t", $time); + select_module_internal_register(32'h1, 1); // Really just a read, with discarded data + #1000; + select_module_internal_register(32'h0, 1); // Really just a read, with discarded data + #1000; + + // Reset the error bit + write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h1); // idx, idxlen, data, datalen + #1000; + + // Read the error bit + read_module_internal_register(8'd33, err_data); // We assume the register is already selected + #1000; + + + ///////////////////////////////// + // Test 8-bit WB access + failed = 0; + $display("Testing WB 8-bit burst write at time %t: resetting ", $time); + do_module_burst_write(3'h1, 16'd16, 32'h0); // 3-bit word size (bytes), 16-bit word count, 32-bit start address + #1000; + $display("Testing WB 8-bit burst read at time %t", $time); + do_module_burst_read(3'h1, 16'd16, 32'h0); + #1000; + for(i = 0; i < 16; i = i+1) begin + if(static_data8[i] != input_data8[i]) begin + failed = 1; + $display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data8[i], input_data8[i]); + end + end + if(!failed) $display("8-bit read/write OK!"); + + /* try it unaligned + do_module_burst_write(3'h1, 16'd5, 32'h3); // 3-bit word size (bytes), 16-bit word count, 32-bit start address + #1000; + do_module_burst_read(3'h1, 16'd4, 32'h4); + #1000; + */ + + ///////////////////////////////// + // Test 16-bit WB access + failed = 0; + $display("Testing WB 16-bit burst write at time %t", $time); + do_module_burst_write(3'h2, 16'd16, 32'h0); // 3-bit word size (bytes), 16-bit word count, 32-bit start address + #1000; + $display("Testing WB 16-bit burst read at time %t", $time); + do_module_burst_read(3'h2, 16'd16, 32'h0); + #1000; + for(i = 0; i < 16; i = i+1) begin + if(static_data16[i] != input_data16[i]) begin + failed = 1; + $display("16-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data16[i], input_data16[i]); + end + end + if(!failed) $display("16-bit read/write OK!"); + + /* try it unaligned + do_module_burst_write(3'h2, 16'd5, 32'h2); // 3-bit word size (bytes), 16-bit word count, 32-bit start address + #1000; + do_module_burst_read(3'h2, 16'd4, 32'h4); + #1000; + */ + + //////////////////////////////////// + // Test 32-bit WB access + failed = 0; + $display("Testing WB 32-bit burst write at time %t", $time); + do_module_burst_write(3'h4, 16'd16, 32'h0); // 3-bit word size (bytes), 16-bit word count, 32-bit start address + #1000; + $display("Testing WB 32-bit burst read at time %t", $time); + do_module_burst_read(3'h4, 16'd16, 32'h0); + #1000; + for(i = 0; i < 16; i = i+1) begin + if(static_data32[i] != input_data32[i]) begin + failed = 1; + $display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data32[i], input_data32[i]); + end + end + if(!failed) $display("32-bit read/write OK!"); + + /* Try another address + do_module_burst_write(3'h4, 16'd16, 32'h200); // 3-bit word size (bytes), 16-bit word count, 32-bit start address + #1000; + do_module_burst_read(3'h4, 16'd15, 32'h204); + #1000; + */ + + //////////////////////////////// + // Test error register + err_data = 33'h0; + // Select and reset the error register + write_module_internal_register(`DBG_WB_INTREG_ERROR, `DBG_WB_REGSELECT_SIZE, 64'h1, 8'h1); // regidx,idxlen,writedata, datalen; + i_wb.cycle_response(`ERR_RESPONSE, 2, 0); // response type, wait cycles, retry_cycles + do_module_burst_write(3'h4, 16'd4, 32'hdeaddead); // 3-bit word size (bytes), 16-bit word count, 32-bit start address + read_module_internal_register(8'd33, err_data); // get the error register + $display("Error bit is %d, error address is %x", err_data[0], err_data>>1); + +`endif // WB module supported + +end + +task initialize_memory; + input [31:0] start_addr; + input [31:0] length; + integer i; + reg [31:0] addr; + begin + + for (i=0; i> 1; + crc_out = crc_out ^ ((d ^ c) & `DBG_CRC_POLY); + //$display("CRC Itr %d, inbit = %d, crc = 0x%x", i, data_in[i], crc_out); + end + end +endtask + +task check_idcode; +reg [63:0] readdata; +reg[31:0] idcode; +begin + set_ir(`IDCODE); + + // Read the IDCODE in the DR + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + jtag_read_write_stream(64'h0, 8'd32, 1, readdata); // write data, exit_1 + write_bit(`JTAG_TMS_bit); // update_ir + write_bit(3'h0); // idle + idcode = readdata[31:0]; + $display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE); +end +endtask; + +task select_debug_module; +input [1:0] moduleid; +reg validid; +begin + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + jtag_write_stream({1'b1,moduleid}, 8'h3, 1); // write data, exit_1 + write_bit(`JTAG_TMS_bit); // update_dr + write_bit(3'h0); // idle + + $display("Selecting module (%0x)", moduleid); + + // Read back the status to make sure a valid chain is selected + /* Pointless, the newly selected module would respond instead... + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + read_write_bit(`JTAG_TMS_bit, validid); // get data, exit_1 + write_bit(`JTAG_TMS_bit); // update_dr + write_bit(3'h0); // idle + + if(validid) $display("Selected valid module (%0x)", moduleid); + else $display("Failed to select module (%0x)", moduleid); + */ +end +endtask + + +task send_module_burst_command; +input [3:0] opcode; +input [31:0] address; +input [15:0] burstlength; +reg [63:0] streamdata; +begin + streamdata = {11'h0,1'b0,opcode,address,burstlength}; + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + jtag_write_stream(streamdata, 8'd53, 1); // write data, exit_1 + write_bit(`JTAG_TMS_bit); // update_dr + write_bit(3'h0); // idle +end +endtask + +task select_module_internal_register; // Really just a read, with discarded data + input [31:0] regidx; + input [7:0] len; // the length of the register index data, we assume not more than 32 + reg[63:0] streamdata; +begin + streamdata = 64'h0; + streamdata = streamdata | regidx; + streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len); + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + jtag_write_stream(streamdata, (len+5), 1); // write data, exit_1 + write_bit(`JTAG_TMS_bit); // update_dr + write_bit(3'h0); // idle +end +endtask + + +task read_module_internal_register; // We assume the register is already selected + //input [31:0] regidx; + input [7:0] len; // the length of the data desired, we assume a max of 64 bits + output [63:0] instream; + reg [63:0] bitmask; +begin + instream = 64'h0; + // We shift out all 0's, which is a NOP to the debug unit + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + // Shift at least 5 bits, as this is the min, for a valid NOP + jtag_read_write_stream(64'h0, len+4,1,instream); // exit_1 + write_bit(`JTAG_TMS_bit); // update_dr + write_bit(3'h0); // idle + bitmask = 64'hffffffffffffffff; + bitmask = bitmask << len; + bitmask = ~bitmask; + instream = instream & bitmask; // Cut off any unwanted excess bits +end +endtask + +task write_module_internal_register; + input [31:0] regidx; // the length of the register index data + input [7:0] idxlen; + input [63:0] writedata; + input [7:0] datalen; // the length of the data to write. We assume the two length combined are 59 or less. + reg[63:0] streamdata; +begin + streamdata = 64'h0; // This will 0 the toplevel/module select bit + streamdata = streamdata | writedata; + streamdata = streamdata | (regidx << datalen); + streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen)); + + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + jtag_write_stream(streamdata, (idxlen+datalen+5), 1); // write data, exit_1 + write_bit(`JTAG_TMS_bit); // update_dr + write_bit(3'h0); // idle +end +endtask + +// This includes the sending of the burst command +task do_module_burst_read; +input [5:0] word_size_bytes; +input [15:0] word_count; +input [31:0] start_address; +reg [3:0] opcode; +reg status; +reg [63:0] instream; +integer i; +integer j; +reg [31:0] crc_calc_i; +reg [31:0] crc_calc_o; // temp signal... +reg [31:0] crc_read; +reg [5:0] word_size_bits; +begin + $display("Doing burst read, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address); + instream = 64'h0; + word_size_bits = word_size_bytes << 3; + crc_calc_i = 32'hffffffff; + + // Send the command + case (word_size_bytes) + 3'h1: opcode = `DBG_WB_CMD_BREAD8; + 3'h2: opcode = `DBG_WB_CMD_BREAD16; + 3'h4: opcode = `DBG_WB_CMD_BREAD32; + default: + begin + $display("Tried burst read with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes); + opcode = `DBG_WB_CMD_BREAD32; + end + endcase + + send_module_burst_command(opcode,start_address, word_count); // returns to state idle + + // Get us back to shift_dr mode to read a burst + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + + // Now, repeat... + for(i = 0; i < word_count; i=i+1) begin + // Get 1 status bit, then word_size_bytes*8 bits + status = 1'b0; + j = 0; + while(!status) begin + read_write_bit(3'h0, status); + j = j + 1; + end + + if(j > 1) begin + $display("Took %0d tries before good status bit during burst read", j); + end + + jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream); + //$display("Read 0x%0x", instream[31:0]); + compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o); + crc_calc_i = crc_calc_o; + if(word_size_bytes == 1) input_data8[i] = instream[7:0]; + else if(word_size_bytes == 2) input_data16[i] = instream[15:0]; + else input_data32[i] = instream[31:0]; + end + + // Read the data CRC from the debug module. + jtag_read_write_stream(64'h0, 6'd32, 1, crc_read); + if(crc_calc_o != crc_read) $display("CRC ERROR! Computed 0x%x, read CRC 0x%x", crc_calc_o, crc_read); + else $display("CRC OK!"); + + // Finally, shift out 5 0's, to make the next command a NOP + // Not necessary, debug unit won't latch a new opcode at the end of a burst + //jtag_write_stream(64'h0, 8'h5, 1); + write_bit(`JTAG_TMS_bit); // update_ir + write_bit(3'h0); // idle +end +endtask + + +task do_module_burst_write; +input [5:0] word_size_bytes; +input [15:0] word_count; +input [31:0] start_address; +reg [3:0] opcode; +reg status; +reg [63:0] dataword; +integer i; +integer j; +reg [31:0] crc_calc_i; +reg [31:0] crc_calc_o; +reg crc_match; +reg [5:0] word_size_bits; +begin + $display("Doing burst write, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address); + word_size_bits = word_size_bytes << 3; + crc_calc_i = 32'hffffffff; + + // Send the command + case (word_size_bytes) + 3'h1: opcode = `DBG_WB_CMD_BWRITE8; + 3'h2: opcode = `DBG_WB_CMD_BWRITE16; + 3'h4: opcode = `DBG_WB_CMD_BWRITE32; + default: + begin + $display("Tried burst write with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes); + opcode = `DBG_WB_CMD_BWRITE32; + end + endcase + + send_module_burst_command(opcode, start_address, word_count); // returns to state idle + + // Get us back to shift_dr mode to write a burst + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + + + // Write a start bit (a 1) so it knows when to start counting + write_bit(`JTAG_TDO_bit); + + // Now, repeat... + for(i = 0; i < word_count; i=i+1) begin + // Write word_size_bytes*8 bits, then get 1 status bit + if(word_size_bytes == 4) dataword = {32'h0, static_data32[i]}; + else if(word_size_bytes == 2) dataword = {48'h0, static_data16[i]}; + else dataword = {56'h0, static_data8[i]}; + + + jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0); + compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o); + crc_calc_i = crc_calc_o; + + // Check if WB bus is ready + // *** THIS WILL NOT WORK IF THERE IS MORE THAN 1 DEVICE IN THE JTAG CHAIN!!! + status = 1'b0; + read_write_bit(3'h0, status); + + if(!status) begin + $display("Bad status bit during burst write, index %d", i); + end + + + //$display("Wrote 0x%0x", dataword); + end + + // Send the CRC we computed + jtag_write_stream(crc_calc_o, 6'd32,0); + + // Read the 'CRC match' bit, and go to exit1_dr + read_write_bit(`JTAG_TMS_bit, crc_match); + if(!crc_match) $display("CRC ERROR! match bit after write is %d (computed CRC 0x%x)", crc_match, crc_calc_o); + else $display("CRC OK!"); + + // Finally, shift out 5 0's, to make the next command a NOP + // Not necessary, module will not latch new opcode during burst + //jtag_write_stream(64'h0, 8'h5, 1); + write_bit(`JTAG_TMS_bit); // update_ir + write_bit(3'h0); // idle +end + +endtask + + +// Puts a value in the TAP IR, assuming we start in IDLE state. +// Returns to IDLE state when finished +task set_ir; +input [3:0] irval; +begin + write_bit(`JTAG_TMS_bit); // select_dr_scan + write_bit(`JTAG_TMS_bit); // select_ir_scan + write_bit(3'h0); // capture_ir + write_bit(3'h0); // shift_ir + jtag_write_stream({60'h0,irval}, 8'h4, 1); // write data, exit_1 + write_bit(`JTAG_TMS_bit); // update_ir + write_bit(3'h0); // idle +end +endtask + +// Resets the TAP and puts it into idle mode +task reset_jtag; +integer i; +begin + for(i = 0; i < 8; i=i+1) begin + write_bit(`JTAG_TMS_bit); // 5 TMS should put us in test_logic_reset mode + end + write_bit(3'h0); // idle +end +endtask + + +//////////////////////////////////////////////////////////////////////////// +// Tasks to write or read-write a string of data + +task jtag_write_stream; +input [63:0] stream; +input [7:0] len; +input set_last_bit; +integer i; +integer databit; +reg [2:0] bits; +begin + for(i = 0; i < (len-1); i=i+1) begin + databit = (stream >> i) & 1'h1; + bits = databit << `JTAG_TDO; + write_bit(bits); + end + + databit = (stream >> i) & 1'h1; + bits = databit << `JTAG_TDO; + if(set_last_bit) bits = (bits | `JTAG_TMS_bit); + write_bit(bits); + +end +endtask + + +task jtag_read_write_stream; +input [63:0] stream; +input [7:0] len; +input set_last_bit; +output [63:0] instream; +integer i; +integer databit; +reg [2:0] bits; +reg inbit; +begin + instream = 64'h0; + for(i = 0; i < (len-1); i=i+1) begin + databit = (stream >> i) & 1'h1; + bits = databit << `JTAG_TDO; + read_write_bit(bits, inbit); + instream = (instream | (inbit << i)); + end + + databit = (stream >> i) & 1'h1; + bits = databit << `JTAG_TDO; + if(set_last_bit) bits = (bits | `JTAG_TMS_bit); + read_write_bit(bits, inbit); + instream = (instream | (inbit << (len-1))); +end +endtask + +///////////////////////////////////////////////////////////////////////// +// Tasks which write or readwrite a single bit (including clocking) + +task write_bit; + input [2:0] bitvals; + begin + + // Set data + jtag_out(bitvals & ~(`JTAG_TCK_bit)); + `wait_jtag_period; + + // Raise clock + jtag_out(bitvals | `JTAG_TCK_bit); + `wait_jtag_period; + + // drop clock (making output available in the SHIFT_xR states) + jtag_out(bitvals & ~(`JTAG_TCK_bit)); + `wait_jtag_period; + end +endtask + +task read_write_bit; + input [2:0] bitvals; + output l_tdi_val; + begin + + // read bit state + l_tdi_val <= jtag_tdi_i; + + // Set data + jtag_out(bitvals & ~(`JTAG_TCK_bit)); + `wait_jtag_period; + + // Raise clock + jtag_out(bitvals | `JTAG_TCK_bit); + `wait_jtag_period; + + // drop clock (making output available in the SHIFT_xR states) + jtag_out(bitvals & ~(`JTAG_TCK_bit)); + `wait_jtag_period; + end +endtask + +///////////////////////////////////////////////////////////////// +// Basic functions to set the state of the JTAG TAP I/F bits + +task jtag_out; + input [2:0] bitvals; + begin + + jtag_tck_o <= bitvals[`JTAG_TCK]; + jtag_tms_o <= bitvals[`JTAG_TMS]; + jtag_tdo_o <= bitvals[`JTAG_TDO]; + end +endtask + + +task jtag_inout; + input [2:0] bitvals; + output l_tdi_val; + begin + + jtag_tck_o <= bitvals[`JTAG_TCK]; + jtag_tms_o <= bitvals[`JTAG_TMS]; + jtag_tdo_o <= bitvals[`JTAG_TDO]; + + l_tdi_val <= jtag_tdi_i; + end +endtask + +endmodule \ No newline at end of file Index: adv_dbg_if/bench/simulated_system/wb_slave_behavioral.v =================================================================== --- adv_dbg_if/bench/simulated_system/wb_slave_behavioral.v (nonexistent) +++ adv_dbg_if/bench/simulated_system/wb_slave_behavioral.v (revision 3) @@ -0,0 +1,425 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// wb_slave_behavioral.v //// +//// //// +//// //// +//// This file is part of the SoC Debug Interface. //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Tadej Markovic, tadej@opencores.org //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: wb_slave_behavioral.v,v $ +// Revision 1.1 2008/07/08 19:11:57 Nathan +// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system. +// +// Revision 1.2 2008/06/26 20:54:44 Nathan +// Testbench modified to use WB behavioral model instead of an onchip_ram. Added test of WB error register. +// +// Revision 1.1 2008/06/18 18:34:49 Nathan +// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface. +// +// Revision 1.1.1.1 2008/05/14 12:07:36 Nathan +// Original from OpenCores +// +// Revision 1.3 2004/03/28 20:27:40 igorm +// New release of the debug interface (3rd. release). +// +// Revision 1.2 2004/01/15 10:47:13 mohor +// Working. +// +// Revision 1.1 2003/12/23 14:26:01 mohor +// New version of the debug interface. Not finished, yet. +// +// +// +// + +//`include "timescale.v" +`include "wb_model_defines.v" +module wb_slave_behavioral +( + CLK_I, + RST_I, + ACK_O, + ADR_I, + CYC_I, + DAT_O, + DAT_I, + ERR_O, + RTY_O, + SEL_I, + STB_I, + WE_I, + CAB_I +); + +/*------------------------------------------------------------------------------------------------------ +WISHBONE signals +------------------------------------------------------------------------------------------------------*/ +input CLK_I; +input RST_I; +output ACK_O; +input `WB_ADDR_TYPE ADR_I; +input CYC_I; +output `WB_DATA_TYPE DAT_O; +input `WB_DATA_TYPE DAT_I; +output ERR_O; +output RTY_O; +input `WB_SEL_TYPE SEL_I; +input STB_I; +input WE_I; +input CAB_I; + +reg `WB_DATA_TYPE DAT_O; + +/*------------------------------------------------------------------------------------------------------ +Asynchronous dual-port RAM signals for storing and fetching the data +------------------------------------------------------------------------------------------------------*/ +//reg `WB_DATA_TYPE wb_memory [0:16777215]; // WB memory - 24 addresses connected - 2 LSB not used +reg `WB_DATA_TYPE wb_memory [0:1048575]; // WB memory - 20 addresses connected - 2 LSB not used +reg `WB_DATA_TYPE mem_wr_data_out; +reg `WB_DATA_TYPE mem_rd_data_in; + +/*------------------------------------------------------------------------------------------------------ +Maximum values for WAIT and RETRY counters and which response !!! +------------------------------------------------------------------------------------------------------*/ +reg [2:0] a_e_r_resp; // tells with which cycle_termination_signal must wb_slave respond ! +reg [8:0] wait_cyc; +reg [7:0] max_retry; + +// assign registers to default state while in reset +// always@(RST_I) +// begin +// if (RST_I) +// begin +// a_e_r_resp <= 3'b000; // do not respond +// wait_cyc <= 8'b0; // no wait cycles +// max_retry <= 8'h0; // no retries +// end +// end //reset + +task cycle_response; + input [2:0] ack_err_rty_resp; // acknowledge, error or retry response input flags + input [8:0] wait_cycles; // if wait cycles before each data termination cycle (ack, err or rty) + input [7:0] retry_cycles; // noumber of retry cycles before acknowledge cycle +begin + // assign values + a_e_r_resp <= #1 ack_err_rty_resp; + wait_cyc <= #1 wait_cycles; + max_retry <= #1 retry_cycles; +end +endtask // cycle_response + +/*------------------------------------------------------------------------------------------------------ +Tasks for writing and reading to and from memory !!! +------------------------------------------------------------------------------------------------------*/ +reg `WB_ADDR_TYPE task_wr_adr_i; +reg `WB_ADDR_TYPE task_rd_adr_i; +reg `WB_DATA_TYPE task_dat_i; +reg `WB_DATA_TYPE task_dat_o; +reg `WB_SEL_TYPE task_sel_i; +reg task_wr_data; +reg task_data_written; +reg `WB_DATA_TYPE task_mem_wr_data; + +// write to memory +task wr_mem; + input `WB_ADDR_TYPE adr_i; + input `WB_DATA_TYPE dat_i; + input `WB_SEL_TYPE sel_i; +begin + task_data_written = 0; + task_wr_adr_i = adr_i; + task_dat_i = dat_i; + task_sel_i = sel_i; + task_wr_data = 1; + wait(task_data_written); + task_wr_data = 0; +end +endtask + +// read from memory +task rd_mem; + input `WB_ADDR_TYPE adr_i; + output `WB_DATA_TYPE dat_o; + input `WB_SEL_TYPE sel_i; +begin + task_rd_adr_i = adr_i; + task_sel_i = sel_i; + #1; + dat_o = task_dat_o; +end +endtask + +/*------------------------------------------------------------------------------------------------------ +Internal signals and logic +------------------------------------------------------------------------------------------------------*/ +reg calc_ack; +reg calc_err; +reg calc_rty; + +reg [7:0] retry_cnt; +reg [7:0] retry_num; +reg retry_expired; + +// Retry counter +always@(posedge RST_I or posedge CLK_I) +begin + if (RST_I) + retry_cnt <= #1 8'h00; + else + begin + if (calc_ack || calc_err) + retry_cnt <= #1 8'h00; + else if (calc_rty) + retry_cnt <= #1 retry_num; + end +end + +always@(retry_cnt or max_retry) +begin + if (retry_cnt < max_retry) + begin + retry_num = retry_cnt + 1'b1; + retry_expired = 1'b0; + end + else + begin + retry_num = retry_cnt; + retry_expired = 1'b1; + end +end + +reg [8:0] wait_cnt; +reg [8:0] wait_num; +reg wait_expired; + +// Wait counter +always@(posedge RST_I or posedge CLK_I) +begin + if (RST_I) + wait_cnt <= #1 9'h0; + else + begin + if (wait_expired || ~STB_I) + wait_cnt <= #1 9'h0; + else + wait_cnt <= #1 wait_num; + end +end + +always@(wait_cnt or wait_cyc or STB_I or a_e_r_resp or retry_expired) +begin + if ((wait_cyc > 0) && (STB_I)) + begin + if (wait_cnt < wait_cyc) + begin + wait_num = wait_cnt + 1'b1; + wait_expired = 1'b0; + calc_ack = 1'b0; + calc_err = 1'b0; + calc_rty = 1'b0; + end + else + begin + wait_num = wait_cnt; + wait_expired = 1'b1; + if (a_e_r_resp == 3'b100) + begin + calc_ack = 1'b1; + calc_err = 1'b0; + calc_rty = 1'b0; + end + else + if (a_e_r_resp == 3'b010) + begin + calc_ack = 1'b0; + calc_err = 1'b1; + calc_rty = 1'b0; + end + else + if (a_e_r_resp == 3'b001) + begin + calc_err = 1'b0; + if (retry_expired) + begin + calc_ack = 1'b1; + calc_rty = 1'b0; + end + else + begin + calc_ack = 1'b0; + calc_rty = 1'b1; + end + end + else + begin + calc_ack = 1'b0; + calc_err = 1'b0; + calc_rty = 1'b0; + end + end + end + else + if ((wait_cyc == 0) && (STB_I)) + begin + wait_num = 9'h0; + wait_expired = 1'b1; + if (a_e_r_resp == 3'b100) + begin + calc_ack = 1'b1; + calc_err = 1'b0; + calc_rty = 1'b0; + end + else if (a_e_r_resp == 3'b010) + begin + calc_ack = 1'b0; + calc_err = 1'b1; + calc_rty = 1'b0; + end + else if (a_e_r_resp == 3'b001) + begin + calc_err = 1'b0; + if (retry_expired) + begin + calc_ack = 1'b1; + calc_rty = 1'b0; + end + else + begin + calc_ack = 1'b0; + calc_rty = 1'b1; + end + end + else + begin + calc_ack = 1'b0; + calc_err = 1'b0; + calc_rty = 1'b0; + end + end + else + begin + wait_num = 9'h0; + wait_expired = 1'b0; + calc_ack = 1'b0; + calc_err = 1'b0; + calc_rty = 1'b0; + end +end + +wire rd_sel = (CYC_I && STB_I && ~WE_I); +wire wr_sel = (CYC_I && STB_I && WE_I); + +// Generate cycle termination signals +assign ACK_O = calc_ack && STB_I; +assign ERR_O = calc_err && STB_I; +assign RTY_O = calc_rty && STB_I; + +// Assign address to asynchronous memory +always@(RST_I or ADR_I) +begin + if (RST_I) // this is added because at start of test bench we need address change in order to get data! + begin + #1 mem_rd_data_in = `WB_DATA_WIDTH'hxxxx_xxxx; + end + else + begin +// #1 mem_rd_data_in = wb_memory[ADR_I[25:2]]; + #1 mem_rd_data_in = wb_memory[ADR_I[21:2]]; + end +end + +// Data input/output interface +always@(rd_sel or mem_rd_data_in or RST_I) +begin + if (RST_I) + DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx; // assign outputs to unknown state while in reset + else if (rd_sel) + DAT_O <=#1 mem_rd_data_in; + else + DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx; +end + + +always@(RST_I or task_rd_adr_i) +begin + if (RST_I) + task_dat_o = `WB_DATA_WIDTH'hxxxx_xxxx; + else + task_dat_o = wb_memory[task_rd_adr_i[21:2]]; +end +always@(CLK_I or wr_sel or task_wr_data or ADR_I or task_wr_adr_i or + mem_wr_data_out or DAT_I or task_mem_wr_data or task_dat_i or + SEL_I or task_sel_i) +begin + if (task_wr_data) + begin + task_mem_wr_data = wb_memory[task_wr_adr_i[21:2]]; + + if (task_sel_i[3]) + task_mem_wr_data[31:24] = task_dat_i[31:24]; + if (task_sel_i[2]) + task_mem_wr_data[23:16] = task_dat_i[23:16]; + if (task_sel_i[1]) + task_mem_wr_data[15: 8] = task_dat_i[15: 8]; + if (task_sel_i[0]) + task_mem_wr_data[ 7: 0] = task_dat_i[ 7: 0]; + + wb_memory[task_wr_adr_i[21:2]] = task_mem_wr_data; // write data + task_data_written = 1; + end + else if (wr_sel && CLK_I) + begin +// mem_wr_data_out = wb_memory[ADR_I[25:2]]; // if no SEL_I is active, old value will be written + mem_wr_data_out = wb_memory[ADR_I[21:2]]; // if no SEL_I is active, old value will be written + + if (SEL_I[3]) + mem_wr_data_out[31:24] = DAT_I[31:24]; + if (SEL_I[2]) + mem_wr_data_out[23:16] = DAT_I[23:16]; + if (SEL_I[1]) + mem_wr_data_out[15: 8] = DAT_I[15: 8]; + if (SEL_I[0]) + mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0]; + +// wb_memory[ADR_I[25:2]] <= mem_wr_data_out; // write data + wb_memory[ADR_I[21:2]] = mem_wr_data_out; // write data + end +end + +endmodule Index: adv_dbg_if/bench/simulated_system/wave.do =================================================================== --- adv_dbg_if/bench/simulated_system/wave.do (nonexistent) +++ adv_dbg_if/bench/simulated_system/wave.do (revision 3) @@ -0,0 +1,350 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider {JTAG top} +add wave -noupdate -format Logic /adv_debug_tb/jtag_tck_o +add wave -noupdate -format Logic /adv_debug_tb/jtag_tms_o +add wave -noupdate -format Logic /adv_debug_tb/jtag_tdo_o +add wave -noupdate -format Logic /adv_debug_tb/jtag_tdi_i +add wave -noupdate -divider {TAP signals} +add wave -noupdate -format Logic /adv_debug_tb/dbg_rst +add wave -noupdate -format Logic /adv_debug_tb/capture_dr +add wave -noupdate -format Logic /adv_debug_tb/shift_dr +add wave -noupdate -format Logic /adv_debug_tb/pause_dr +add wave -noupdate -format Logic /adv_debug_tb/update_dr +add wave -noupdate -format Logic /adv_debug_tb/dbg_sel +add wave -noupdate -format Logic /adv_debug_tb/dbg_tdi +add wave -noupdate -format Logic /adv_debug_tb/dbg_tdo +add wave -noupdate -divider {Wishbone signals} +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/wb_adr +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/wb_dat_m +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/wb_dat_s +add wave -noupdate -format Logic /adv_debug_tb/wb_cyc +add wave -noupdate -format Logic /adv_debug_tb/wb_stb +add wave -noupdate -format Literal /adv_debug_tb/wb_sel +add wave -noupdate -format Logic /adv_debug_tb/wb_we +add wave -noupdate -format Logic /adv_debug_tb/wb_ack +add wave -noupdate -format Logic /adv_debug_tb/wb_err +add wave -noupdate -format Logic /adv_debug_tb/wb_clk_i +add wave -noupdate -format Logic /adv_debug_tb/wb_rst_i +add wave -noupdate -divider {CPU0 signals} +add wave -noupdate -format Logic /adv_debug_tb/cpu0_clk +add wave -noupdate -format Logic /adv_debug_tb/cpu0_rst +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/cpu0_addr +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/cpu0_data_c +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/cpu0_data_d +add wave -noupdate -format Logic /adv_debug_tb/cpu0_we +add wave -noupdate -format Logic /adv_debug_tb/cpu0_stb +add wave -noupdate -format Logic /adv_debug_tb/cpu0_ack +add wave -noupdate -format Logic /adv_debug_tb/cpu0_bp +add wave -noupdate -format Logic /adv_debug_tb/cpu0_stall +add wave -noupdate -divider {Debug top internals} +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tck_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdi_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/rst_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/shift_dr_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/pause_dr_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/update_dr_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/capture_dr_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/debug_select_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_clk_i +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_adr_o +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_dat_o +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/wb_dat_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_cyc_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_stb_o +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_sel_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_we_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_ack_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_cab_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/wb_err_i +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_cti_o +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/wb_bte_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_clk_i +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/cpu0_addr_o +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/cpu0_data_i +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/cpu0_data_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_bp_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_stall_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_stb_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_we_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_ack_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/cpu0_rst_o +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/input_shift_reg +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/module_id_reg +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/select_cmd +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/module_id_in +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/module_selects +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_wb +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_cpu0 +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/tdo_cpu1 +add wave -noupdate -divider {DBG Wishbone module internals} +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/tck_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/module_tdo_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/tdi_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/capture_dr_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/shift_dr_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/update_dr_i +add wave -noupdate -format Literal -radix binary /adv_debug_tb/i_dbg_module/i_dbg_wb/data_register_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/module_select_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/rst_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_clk_i +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_adr_o +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_dat_o +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_dat_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_cyc_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_stb_o +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_sel_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_we_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_ack_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_cab_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_err_i +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_cti_o +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/wb_bte_o +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/address_counter +add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_count +add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_wb/word_count +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/operation +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_out_shift_reg +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/internal_register_select +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/internal_reg_error +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/addr_sel +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/addr_ct_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/op_reg_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_ct_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_ct_rst +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/word_ct_sel +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/word_ct_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/out_reg_ld_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/out_reg_shift_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/out_reg_data_sel +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/tdo_output_sel +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_strobe +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_clr +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_in_sel +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_shift_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/regsel_ld_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/intreg_ld_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/error_reg_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_clr_err +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/word_count_zero +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_count_max +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/module_cmd +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_ready +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_err +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/burst_instruction +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/intreg_instruction +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/intreg_write +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/rd_op +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_match +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/bit_count_32 +add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_wb/word_size_bits +add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_wb/word_size_bytes +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/incremented_address +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_to_addr_counter +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_to_word_counter +add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_wb/decremented_word_count +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/address_data_in +add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_wb/count_data_in +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/operation_in +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_to_biu +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_from_biu +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_data_out +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_data_in +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/crc_serial_out +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/reg_select_data +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/out_reg_data +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/data_from_internal_reg +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu_rst +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/module_state +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/module_next_state +add wave -noupdate -divider {DBG WB module BIU internals} +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/tck_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/rst_i +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/data_i +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/data_o +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/addr_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/strobe_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/rd_wrn_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/rdy_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/err_o +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/word_size_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/wb_clk_i +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/wb_adr_o +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/wb_dat_o +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/wb_dat_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/wb_cyc_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/wb_stb_o +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/wb_sel_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/wb_we_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/wb_ack_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/wb_cab_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/wb_err_i +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/wb_cti_o +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/wb_bte_o +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/sel_reg +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/addr_reg +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/data_in_reg +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/data_out_reg +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/wr_reg +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/str_sync +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/rdy_sync +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/err_reg +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/rdy_sync_tff1 +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/rdy_sync_tff2 +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/rdy_sync_tff2q +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/str_sync_wbff1 +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/str_sync_wbff2 +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/str_sync_wbff2q +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/data_o_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/rdy_sync_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/err_en +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/be_dec +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/start_toggle +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/swapped_data_i +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/swapped_data_out +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/wb_fsm_state +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_wb/biu/next_fsm_state +add wave -noupdate -divider {DBG CPU0 module signals} +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/tck_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/module_tdo_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/tdi_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/capture_dr_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/shift_dr_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/update_dr_i +add wave -noupdate -format Literal -radix binary /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_register_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/module_select_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/rst_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_clk_i +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_addr_o +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_data_i +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_data_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_stb_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_we_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_ack_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_rst_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_bp_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/cpu_stall_o +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/address_counter +add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/bit_count +add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/word_count +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/operation +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_out_shift_reg +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/internal_register_select +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/internal_reg_status +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/addr_sel +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/addr_ct_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/op_reg_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/bit_ct_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/bit_ct_rst +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/word_ct_sel +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/word_ct_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/out_reg_ld_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/out_reg_shift_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/out_reg_data_sel +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/tdo_output_sel +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/biu_strobe +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_clr +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_in_sel +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_shift_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/regsel_ld_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/intreg_ld_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/word_count_zero +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/bit_count_max +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/module_cmd +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/biu_ready +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/burst_instruction +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/intreg_instruction +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/intreg_write +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/rd_op +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_match +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/bit_count_32 +add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/word_size_bits +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/incremented_address +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_to_addr_counter +add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_to_word_counter +add wave -noupdate -format Literal -radix decimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/decremented_word_count +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/address_data_in +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/count_data_in +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/operation_in +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_to_biu +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_from_biu +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_data_out +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_data_in +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/crc_serial_out +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/reg_select_data +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/out_reg_data +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/data_from_internal_reg +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/status_reg_wr +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/module_state +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/module_next_state +add wave -noupdate -divider {CPU0 BIU internals} +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/tck_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rst_i +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/data_i +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/data_o +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/addr_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/strobe_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rd_wrn_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rdy_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_clk_i +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_addr_o +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_data_i +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_data_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_stb_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_we_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_ack_i +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/addr_reg +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/data_in_reg +add wave -noupdate -format Literal -radix hexadecimal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/data_out_reg +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/wr_reg +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/str_sync +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_tff1 +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_tff2 +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_tff2q +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/str_sync_wbff1 +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/str_sync_wbff2 +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/str_sync_wbff2q +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/data_o_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/rdy_sync_en +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/start_toggle +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/cpu_fsm_state +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/or1k_biu_i/next_fsm_state +add wave -noupdate -divider {CPU0 Status register internals} +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/statusreg_i/data_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/statusreg_i/we_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/statusreg_i/tck_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/statusreg_i/bp_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/statusreg_i/rst_i +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/statusreg_i/cpu_clk_i +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/statusreg_i/ctrl_reg_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/statusreg_i/cpu_stall_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/statusreg_i/cpu_rst_o +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/statusreg_i/cpu_reset +add wave -noupdate -format Literal /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/statusreg_i/cpu_op_out +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/statusreg_i/stall_bp +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/statusreg_i/stall_bp_csff +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/statusreg_i/stall_bp_tck +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/statusreg_i/stall_reg +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/statusreg_i/stall_reg_csff +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/statusreg_i/stall_reg_cpu +add wave -noupdate -format Logic /adv_debug_tb/i_dbg_module/i_dbg_cpu_or1k/statusreg_i/cpu_reset_csff +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {50652 ns} 0} +configure wave -namecolwidth 409 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {38962 ns} {65318 ns} Index: adv_dbg_if/bench/simulated_system/cpu_behavioral.v =================================================================== --- adv_dbg_if/bench/simulated_system/cpu_behavioral.v (nonexistent) +++ adv_dbg_if/bench/simulated_system/cpu_behavioral.v (revision 3) @@ -0,0 +1,154 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// cpu_behavioral.v //// +//// //// +//// //// +//// This file is part of the SoC Debug Interface. //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: cpu_behavioral.v,v $ +// Revision 1.1 2008/07/08 19:11:55 Nathan +// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system. +// +// Revision 1.1 2008/06/18 18:34:48 Nathan +// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface. +// +// Revision 1.1.1.1 2008/05/14 12:07:35 Nathan +// Original from OpenCores +// +// Revision 1.4 2004/03/28 20:27:40 igorm +// New release of the debug interface (3rd. release). +// +// Revision 1.3 2004/01/22 11:07:28 mohor +// test stall_test added. +// +// Revision 1.2 2004/01/17 18:01:31 mohor +// New version. +// +// Revision 1.1 2004/01/17 17:01:25 mohor +// Almost finished. +// +// +// +// +// +`include "timescale.v" +`include "dbg_cpu_defines.v" + + + +module cpu_behavioral + ( + // CPU signals + cpu_rst_i, + cpu_clk_o, + cpu_addr_i, + cpu_data_o, + cpu_data_i, + cpu_bp_o, + cpu_stall_i, + cpu_stb_i, + cpu_we_i, + cpu_ack_o, + cpu_rst_o + ); + + +// CPU signals +input cpu_rst_i; +output cpu_clk_o; +input [31:0] cpu_addr_i; +output [31:0] cpu_data_o; +input [31:0] cpu_data_i; +output cpu_bp_o; +input cpu_stall_i; +input cpu_stb_i; +input cpu_we_i; +output cpu_ack_o; +output cpu_rst_o; + +reg cpu_clk_o; +reg [31:0] cpu_data_o; +reg cpu_bp_o; +reg cpu_ack_o; +reg cpu_ack_q; +wire cpu_ack; +initial +begin + cpu_clk_o = 1'b0; + forever #5 cpu_clk_o = ~cpu_clk_o; +end + + +initial +begin + cpu_bp_o = 1'b0; +end + +assign #200 cpu_ack = cpu_stall_i & cpu_stb_i; + + + +always @ (posedge cpu_clk_o or posedge cpu_rst_i) +begin + if (cpu_rst_i) + begin + cpu_ack_o <= #1 1'b0; + cpu_ack_q <= #1 1'b0; + end + else + begin + cpu_ack_o <= #1 cpu_ack; + cpu_ack_q <= #1 cpu_ack_o; + end +end + +always @ (posedge cpu_clk_o or posedge cpu_rst_i) +begin + if (cpu_rst_i) + cpu_data_o <= #1 32'h12345678; + else if (cpu_ack_o && (!cpu_ack_q)) + cpu_data_o <= #1 cpu_data_o + 32'h11111111; +end + + + + +endmodule + Index: adv_dbg_if/bench/simulated_system/wb_model_defines.v =================================================================== --- adv_dbg_if/bench/simulated_system/wb_model_defines.v (nonexistent) +++ adv_dbg_if/bench/simulated_system/wb_model_defines.v (revision 3) @@ -0,0 +1,163 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// wb_model_defines.v //// +//// //// +//// //// +//// This file is part of the SoC Debug Interface. //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: wb_model_defines.v,v $ +// Revision 1.1 2008/07/08 19:11:57 Nathan +// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system. +// +// Revision 1.1 2008/06/18 18:34:48 Nathan +// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface. +// +// Revision 1.1.1.1 2008/05/14 12:07:36 Nathan +// Original from OpenCores +// +// Revision 1.2 2004/03/28 20:27:40 igorm +// New release of the debug interface (3rd. release). +// +// Revision 1.1 2003/12/23 14:26:01 mohor +// New version of the debug interface. Not finished, yet. +// +// +// + +// WISHBONE frequency in GHz +`define WB_FREQ 0.100 + +// memory frequency in GHz +`define MEM_FREQ 0.100 + +// setup and hold time definitions for WISHBONE - used in BFMs for signal generation +`define Tsetup 4 +`define Thold 1 + +// how many clock cycles should model wait for design's response - integer 32 bit value +`define WAIT_FOR_RESPONSE 1023 + +// maximum number of transactions allowed in single call to block or cab transfer routines +`define MAX_BLK_SIZE 1024 + +// maximum retry terminations allowed for WISHBONE master to repeat an access +`define WB_TB_MAX_RTY 0 + + +// some common types and defines +`define WB_ADDR_WIDTH 32 +`define WB_DATA_WIDTH 32 +`define WB_SEL_WIDTH `WB_DATA_WIDTH/8 +`define WB_TAG_WIDTH 5 +`define WB_ADDR_TYPE [(`WB_ADDR_WIDTH - 1):0] +`define WB_DATA_TYPE [(`WB_DATA_WIDTH - 1):0] +`define WB_SEL_TYPE [(`WB_SEL_WIDTH - 1):0] +`define WB_TAG_TYPE [(`WB_TAG_WIDTH - 1):0] + +// read cycle stimulus - consists of: +// - address field - which address read will be performed from +// - sel field - what byte select value should be +// - tag field - what tag values should be put on the bus +`define READ_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0] +`define READ_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH) +`define READ_ADDRESS [(`WB_ADDR_WIDTH - 1):0] +`define READ_SEL [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH - 1):`WB_ADDR_WIDTH] +`define READ_TAG_STIM [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_SEL_WIDTH)] + +// read cycle return type consists of: +// - read data field +// - tag field received from WISHBONE +// - wishbone slave response fields - ACK, ERR and RTY +// - test bench error indicator (when testcase has not used wb master model properly) +// - how much data was actually transfered +`define READ_RETURN_TYPE [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):0] +`define READ_DATA [(32 + `WB_DATA_WIDTH + 4 - 1):32 + 4] +`define READ_TAG_RET [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):(`WB_DATA_WIDTH + 32 + 4)] +`define READ_RETURN_LENGTH (32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1) + +// write cycle stimulus type consists of +// - address field +// - data field +// - sel field +// - tag field +`define WRITE_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0] +`define WRITE_ADDRESS [(`WB_ADDR_WIDTH - 1):0] +`define WRITE_DATA [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH - 1):`WB_ADDR_WIDTH] +`define WRITE_SEL [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH)] +`define WRITE_TAG_STIM [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH)] + +// length of WRITE_STIMULUS +`define WRITE_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH) + +// write cycle return type consists of: +// - test bench error indicator (when testcase has not used wb master model properly) +// - wishbone slave response fields - ACK, ERR and RTY +// - tag field received from WISHBONE +// - how much data was actually transfered +`define WRITE_RETURN_TYPE [(32 + 4 + `WB_TAG_WIDTH - 1):0] +`define WRITE_TAG_RET [(32 + 4 + `WB_TAG_WIDTH - 1):32 + 4] + +// this four fields are common to both read and write routines return values +`define TB_ERROR_BIT [0] +`define CYC_ACK [1] +`define CYC_RTY [2] +`define CYC_ERR [3] +`define CYC_RESPONSE [3:1] +`define CYC_ACTUAL_TRANSFER [35:4] + +// block transfer flags +`define WB_TRANSFER_FLAGS [41:0] +// consists of: +// - number of transfer cycles to perform +// - flag that enables retry termination handling - if disabled, block transfer routines will return on any termination other than acknowledge +// - flag indicating CAB transfer is to be performed - ignored by all single transfer routines +// - number of initial wait states to insert +// - number of subsequent wait states to insert +`define WB_TRANSFER_SIZE [41:10] +`define WB_TRANSFER_AUTO_RTY [8] +`define WB_TRANSFER_CAB [9] +`define INIT_WAITS [3:0] +`define SUBSEQ_WAITS [7:4] + +// wb slave response +`define ACK_RESPONSE 3'b100 +`define ERR_RESPONSE 3'b010 +`define RTY_RESPONSE 3'b001 +`define NO_RESPONSE 3'b000 Index: adv_dbg_if/bench/simulated_system/timescale.v =================================================================== --- adv_dbg_if/bench/simulated_system/timescale.v (nonexistent) +++ adv_dbg_if/bench/simulated_system/timescale.v (revision 3) @@ -0,0 +1,68 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// timescale.v //// +//// //// +//// //// +//// This file is part of the SoC Debug Interface. //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: timescale.v,v $ +// Revision 1.1 2008/07/08 19:11:56 Nathan +// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system. +// +// Revision 1.1 2008/06/18 18:34:48 Nathan +// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface. +// +// Revision 1.1.1.1 2008/05/14 12:07:36 Nathan +// Original from OpenCores +// +// Revision 1.4 2004/03/28 20:27:40 igorm +// New release of the debug interface (3rd. release). +// +// Revision 1.3 2004/01/17 17:01:25 mohor +// Almost finished. +// +// Revision 1.2 2003/12/23 14:26:01 mohor +// New version of the debug interface. Not finished, yet. +// +// +// +// +`timescale 1ns/10ps + Index: adv_dbg_if/rtl/verilog/adbg_or1k_module.v =================================================================== --- adv_dbg_if/rtl/verilog/adbg_or1k_module.v (nonexistent) +++ adv_dbg_if/rtl/verilog/adbg_or1k_module.v (revision 3) @@ -0,0 +1,672 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// adbg_or1k_module.v //// +//// //// +//// //// +//// This file is part of the SoC Advanced Debug Interface. //// +//// //// +//// Author(s): //// +//// Nathan Yawn (nathan.yawn@opencores.org) //// +//// //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: adbg_or1k_module.v,v $ +// Revision 1.2 2009/05/17 20:54:56 Nathan +// Changed email address to opencores.org +// +// Revision 1.1 2008/07/22 20:28:31 Nathan +// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes. +// +// Revision 1.7 2008/07/11 08:13:29 Nathan +// Latch opcode on posedge, like other signals. This fixes a problem +// when the module is used with a Xilinx BSCAN TAP. Added signals to +// allow modules to inhibit latching of a new active module by the top +// module. This allows the sub-modules to force the top level module +// to ignore the command present in the input shift register after e.g. +// a burst read. +// + + +`include "adbg_or1k_defines.v" + +// Module interface +module adbg_or1k_module ( + // JTAG signals + tck_i, + module_tdo_o, + tdi_i, + + // TAP states + capture_dr_i, + shift_dr_i, + update_dr_i, + + data_register_i, // the data register is at top level, shared between all modules + module_select_i, + top_inhibit_o, + rst_i, + + // Interfate to the OR1K debug unit + cpu_clk_i, + cpu_addr_o, + cpu_data_i, + cpu_data_o, + cpu_bp_i, + cpu_stall_o, + cpu_stb_o, + cpu_we_o, + cpu_ack_i, + cpu_rst_o + ); + + // JTAG signals + input tck_i; + output module_tdo_o; + input tdi_i; // This is only used by the CRC module - data_register_i[MSB] is delayed a cycle + + // TAP states + input capture_dr_i; + input shift_dr_i; + input update_dr_i; + + input [52:0] data_register_i; + input module_select_i; + output top_inhibit_o; + input rst_i; + + // WISHBONE master interface + input cpu_clk_i; // 'bus' style interface to SPRs + output [31:0] cpu_addr_o; + input [31:0] cpu_data_i; + output [31:0] cpu_data_o; + output cpu_stb_o; + output cpu_we_o; + input cpu_ack_i; + output cpu_rst_o; // control lines + input cpu_bp_i; + output cpu_stall_o; + + // Declare inputs / outputs as wires / registers + reg module_tdo_o; + reg top_inhibit_o; + + + // Registers to hold state etc. + reg [31:0] address_counter; // Holds address for next Wishbone access + reg [5:0] bit_count; // How many bits have been shifted in/out + reg [15:0] word_count; // bytes remaining in current burst command + reg [3:0] operation; // holds the current command (rd/wr, word size) + reg [31:0] data_out_shift_reg; // parallel-load output shift register + reg [`DBG_OR1K_REGSELECT_SIZE-1:0] internal_register_select; // Holds index of currently selected register + wire [1:0] internal_reg_status; // Holds CPU stall and reset status - signal is output of separate module + + + // Control signals for the various counters / registers / state machines + reg addr_sel; // Selects data for address_counter. 0 = data_register_i, 1 = incremented address count + reg addr_ct_en; // Enable signal for address counter register + reg op_reg_en; // Enable signal for 'operation' register + reg bit_ct_en; // enable bit counter + reg bit_ct_rst; // reset (zero) bit count register + reg word_ct_sel; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count + reg word_ct_en; // Enable byte counter register + reg out_reg_ld_en; // Enable parallel load of data_out_shift_reg + reg out_reg_shift_en; // Enable shift of data_out_shift_reg + reg out_reg_data_sel; // 0 = BIU data, 1 = internal register data + reg [1:0] tdo_output_sel; // Selects signal to send to TDO. 0 = ready bit, 1 = output register, 2 = CRC match, 3 = CRC shift reg. + reg biu_strobe; // Indicates that the bus unit should latch data and start a transaction + reg crc_clr; // resets CRC module + reg crc_en; // does 1-bit iteration in CRC module + reg crc_in_sel; // selects incoming write data (=0) or outgoing read data (=1)as input to CRC module + reg crc_shift_en; // CRC reg is also it's own output shift register; this enables a shift + reg regsel_ld_en; // Reg. select register load enable + reg intreg_ld_en; // load enable for internal registers + + + // Status signals + wire word_count_zero; // true when byte counter is zero + wire bit_count_max; // true when bit counter is equal to current word size + wire module_cmd; // inverse of MSB of data_register_i. 1 means current cmd not for top level (but is for us) + wire biu_ready; // indicates that the BIU has finished the last command + wire burst_instruction; // True when the input_data_i reg has a valid burst instruction for this module + wire intreg_instruction; // True when the input_data_i reg has a valid internal register instruction + wire intreg_write; // True when the input_data_i reg has an internal register write op + wire rd_op; // True when operation in the opcode reg is a read, false when a write + wire crc_match; // indicates whether data_register_i matches computed CRC + wire bit_count_32; // true when bit count register == 32, for CRC after burst writes + + // Intermediate signals + wire [5:0] word_size_bits; // 8,16, or 32. Decoded from 'operation' + wire [2:0] address_increment; // How much to add to the address counter each iteration + wire [32:0] incremented_address; // value of address counter plus 'word_size' + wire [31:0] data_to_addr_counter; // output of the mux in front of the address counter inputs + wire [15:0] data_to_word_counter; // output of the mux in front of the byte counter input + wire [15:0] decremented_word_count; + wire [31:0] address_data_in; // from data_register_i + wire [15:0] count_data_in; // from data_register_i + wire [3:0] operation_in; // from data_register_i + wire [31:0] data_to_biu; // from data_register_i + wire [31:0] data_from_biu; // to data_out_shift_register + wire [31:0] crc_data_out; // output of CRC module, to output shift register + wire crc_data_in; // input to CRC module, either data_register_i[52] or data_out_shift_reg[0] + wire crc_serial_out; + wire [`DBG_OR1K_REGSELECT_SIZE-1:0] reg_select_data; // from data_register_i, input to internal register select register + wire [31:0] out_reg_data; // parallel input to the output shift register + reg [31:0] data_from_internal_reg; // data from internal reg. MUX to output shift register + wire status_reg_wr; + + + ///////////////////////////////////////////////// + // Combinatorial assignments + + assign module_cmd = ~(data_register_i[52]); + assign operation_in = data_register_i[51:48]; + assign address_data_in = data_register_i[47:16]; + assign count_data_in = data_register_i[15:0]; + assign data_to_biu = data_register_i[52:21]; + assign reg_select_data = data_register_i[47:(47-(`DBG_OR1K_REGSELECT_SIZE-1))]; + + //////////////////////////////////////////////// + // Operation decoder + + // These are only used before the operation is latched, so decode them from operation_in + assign burst_instruction = (operation_in == `DBG_OR1K_CMD_BWRITE32) | (operation_in == `DBG_OR1K_CMD_BREAD32); + assign intreg_instruction = ((operation_in == `DBG_OR1K_CMD_IREG_WR) | (operation_in == `DBG_OR1K_CMD_IREG_SEL)); + assign intreg_write = (operation_in == `DBG_OR1K_CMD_IREG_WR); + + // These are constant, the CPU module only does 32-bit accesses + assign word_size_bits = 5'd31; // Bits is actually bits-1, to make the FSM easier + assign address_increment = 3'd1; // This is only used to increment the address. SPRs are word-addressed. + + // This is the only thing that actually needs to be saved and 'decoded' from the latched opcode + // It goes to the BIU each time a transaction is started. + assign rd_op = operation[2]; + + + //////////////////////////////////////////////// + // Module-internal register select register (no, that's not redundant.) + // Also internal register output MUX + + always @ (posedge tck_i or posedge rst_i) + begin + if(rst_i) internal_register_select = 1'h0; + else if(regsel_ld_en) internal_register_select = reg_select_data; + end + + // This is completely unnecessary here, since the module has only 1 internal + // register. However, to make the module expandable, it is included anyway. + always @ (internal_register_select or internal_reg_status) + begin + case(internal_register_select) + `DBG_OR1K_INTREG_STATUS: data_from_internal_reg = {30'h0, internal_reg_status}; + default: data_from_internal_reg = {30'h0, internal_reg_status}; + endcase + end + + + + //////////////////////////////////////////////////////////////////// + // Module-internal registers + // These have generic read/write/select code, but + // individual registers may have special behavior, defined here. + + // This is the status register, which holds the reset and stall states. + + assign status_reg_wr = (intreg_ld_en & (reg_select_data == `DBG_OR1K_INTREG_STATUS)); + + adbg_or1k_status_reg or1k_statusreg_i ( + .data_i(data_register_i[(47-`DBG_OR1K_REGSELECT_SIZE):(47-(`DBG_OR1K_REGSELECT_SIZE+1))]), + .we_i(status_reg_wr), + .tck_i(tck_i), + .bp_i(cpu_bp_i), + .rst_i(rst_i), + .cpu_clk_i(cpu_clk_i), + .ctrl_reg_o(internal_reg_status), + .cpu_stall_o(cpu_stall_o), + .cpu_rst_o(cpu_rst_o) + ); + + + /////////////////////////////////////////////// + // Address counter + + assign data_to_addr_counter = (addr_sel) ? incremented_address[31:0] : address_data_in; + assign incremented_address = address_counter + address_increment; + + // Technically, since this data (sometimes) comes from the input shift reg, we should latch on + // negedge, per the JTAG spec. But that makes things difficult when incrementing. + always @ (posedge tck_i or posedge rst_i) // JTAG spec specifies latch on negative edge in UPDATE_DR state + begin + if(rst_i) + address_counter <= 32'h0; + else if(addr_ct_en) + address_counter <= data_to_addr_counter; + end + + //////////////////////////////////////// + // Opcode latch + + always @ (posedge tck_i or posedge rst_i) // JTAG spec specifies latch on negative edge in UPDATE_DR state + begin + if(rst_i) + operation <= 4'h0; + else if(op_reg_en) + operation <= operation_in; + end + + ////////////////////////////////////// + // Bit counter + + always @ (posedge tck_i or posedge rst_i) + begin + + if(rst_i) bit_count <= 6'h0; + else if(bit_ct_rst) bit_count <= 6'h0; + else if(bit_ct_en) bit_count <= bit_count + 6'h1; + + end + + assign bit_count_max = (bit_count == word_size_bits) ? 1'b1 : 1'b0 ; + assign bit_count_32 = (bit_count == 6'h20) ? 1'b1 : 1'b0; + + //////////////////////////////////////// + // Word counter + + assign data_to_word_counter = (word_ct_sel) ? decremented_word_count : count_data_in; + assign decremented_word_count = word_count - 16'h1; + + // Technically, since this data (sometimes) comes from the input shift reg, we should latch on + // negedge, per the JTAG spec. But that makes things difficult when incrementing. + always @ (posedge tck_i or posedge rst_i) // JTAG spec specifies latch on negative edge in UPDATE_DR state + begin + if(rst_i) + word_count <= 16'h0; + else if(word_ct_en) + word_count <= data_to_word_counter; + end + + assign word_count_zero = (word_count == 16'h0); + + ///////////////////////////////////////////////////// + // Output register and TDO output MUX + + assign out_reg_data = (out_reg_data_sel) ? data_from_internal_reg : data_from_biu; + + always @ (posedge tck_i or posedge rst_i) + begin + if(rst_i) data_out_shift_reg <= 32'h0; + else if(out_reg_ld_en) data_out_shift_reg <= out_reg_data; + else if(out_reg_shift_en) data_out_shift_reg <= {1'b0, data_out_shift_reg[31:1]}; + end + + + always @ (tdo_output_sel or data_out_shift_reg[0] or biu_ready or crc_match or crc_serial_out) + begin + if(tdo_output_sel == 2'h0) module_tdo_o <= biu_ready; + else if(tdo_output_sel == 2'h1) module_tdo_o <= data_out_shift_reg[0]; + else if(tdo_output_sel == 2'h2) module_tdo_o <= crc_match; + else module_tdo_o <= crc_serial_out; + end + + //////////////////////////////////////// + // Bus Interface Unit (to OR1K SPR bus) + // It is assumed that the BIU has internal registers, and will + // latch address, operation, and write data on rising clock edge + // when strobe is asserted + + adbg_or1k_biu or1k_biu_i ( + // Debug interface signals + .tck_i (tck_i), + .rst_i (rst_i), + .data_i (data_to_biu), + .data_o (data_from_biu), + .addr_i (address_counter), + .strobe_i (biu_strobe), + .rd_wrn_i (rd_op), // If 0, then write op + .rdy_o (biu_ready), + // This bus has no error signal + + // OR1K SPR bus signals + .cpu_clk_i(cpu_clk_i), + .cpu_addr_o(cpu_addr_o), + .cpu_data_i(cpu_data_i), + .cpu_data_o(cpu_data_o), + .cpu_stb_o(cpu_stb_o), + .cpu_we_o(cpu_we_o), + .cpu_ack_i(cpu_ack_i) + ); + + + + ///////////////////////////////////// + // CRC module + + assign crc_data_in = (crc_in_sel) ? tdi_i : data_out_shift_reg[0]; // MUX, write or read data + + adbg_crc32 or1k_crc_i + ( + .clk(tck_i), + .data(crc_data_in), + .enable(crc_en), + .shift(crc_shift_en), + .clr(crc_clr), + .rst(rst_i), + .crc_out(crc_data_out), + .serial_out(crc_serial_out) + ); + + assign crc_match = (data_register_i[52:21] == crc_data_out) ? 1'b1 : 1'b0; + + //////////////////////////////////////// + // Control FSM + + // Definition of machine state values. + // Don't worry too much about the state encoding, the synthesis tool + // will probably re-encode it anyway. + +`define STATE_idle 4'h0 +`define STATE_Rbegin 4'h1 +`define STATE_Rready 4'h2 +`define STATE_Rstatus 4'h3 +`define STATE_Rburst 4'h4 +`define STATE_Wready 4'h5 +`define STATE_Wwait 4'h6 +`define STATE_Wburst 4'h7 +`define STATE_Wstatus 4'h8 +`define STATE_Rcrc 4'h9 +`define STATE_Wcrc 4'ha +`define STATE_Wmatch 4'hb + + reg [3:0] module_state; // FSM state + reg [3:0] module_next_state; // combinatorial signal, not actually a register + + + + // sequential part of the FSM + always @ (posedge tck_i or posedge rst_i) + begin + if(rst_i) + module_state <= `STATE_idle; + else + module_state <= module_next_state; + end + + + // Determination of next state; purely combinatorial + always @ (module_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i or operation_in[2] + or word_count_zero or bit_count_max or data_register_i[52] or bit_count_32 or biu_ready + or module_cmd or intreg_write or decremented_word_count or burst_instruction) + begin + case(module_state) + `STATE_idle: + begin + if(module_cmd && module_select_i && update_dr_i && burst_instruction && operation_in[2]) module_next_state <= `STATE_Rbegin; + else if(module_cmd && module_select_i && update_dr_i && burst_instruction) module_next_state <= `STATE_Wready; + else module_next_state <= `STATE_idle; + end + + `STATE_Rbegin: + begin + if(word_count_zero) module_next_state <= `STATE_idle; // set up a burst of size 0, illegal. + else module_next_state <= `STATE_Rready; + end + `STATE_Rready: + begin + if(module_select_i && capture_dr_i) module_next_state <= `STATE_Rstatus; + else module_next_state <= `STATE_Rready; + end + `STATE_Rstatus: + begin + if(update_dr_i) module_next_state <= `STATE_idle; + else if (biu_ready) module_next_state <= `STATE_Rburst; + else module_next_state <= `STATE_Rstatus; + end + `STATE_Rburst: + begin + if(update_dr_i) module_next_state <= `STATE_idle; + else if(bit_count_max && word_count_zero) module_next_state <= `STATE_Rcrc; + else if(bit_count_max) module_next_state <= `STATE_Rstatus; + else module_next_state <= `STATE_Rburst; + end + `STATE_Rcrc: + begin + if(update_dr_i) module_next_state <= `STATE_idle; + // This doubles as the 'recovery' state, so stay here until update_dr_i. + else module_next_state <= `STATE_Rcrc; + end + + `STATE_Wready: + begin + if(word_count_zero) module_next_state <= `STATE_idle; + else if(module_select_i && capture_dr_i) module_next_state <= `STATE_Wwait; + else module_next_state <= `STATE_Wready; + end + `STATE_Wwait: + begin + if(update_dr_i) module_next_state <= `STATE_idle; // client terminated early + else if(module_select_i && data_register_i[52]) module_next_state <= `STATE_Wburst; // Got a start bit + else module_next_state <= `STATE_Wwait; + end + `STATE_Wburst: + begin + if(update_dr_i) module_next_state <= `STATE_idle; // client terminated early + else if(bit_count_max) module_next_state <= `STATE_Wstatus; + else module_next_state <= `STATE_Wburst; + end + `STATE_Wstatus: + begin + if(update_dr_i) module_next_state <= `STATE_idle; // client terminated early + else if(word_count_zero) module_next_state <= `STATE_Wcrc; + // can't wait until bus ready if multiple devices in chain... + // Would have to read postfix_bits, then send another start bit and push it through + // prefix_bits...potentially very inefficient. + else module_next_state <= `STATE_Wburst; + end + + `STATE_Wcrc: + begin + if(update_dr_i) module_next_state <= `STATE_idle; // client terminated early + else if(bit_count_32) module_next_state <= `STATE_Wmatch; + else module_next_state <= `STATE_Wcrc; + end + + `STATE_Wmatch: + begin + if(update_dr_i) module_next_state <= `STATE_idle; + // This doubles as our recovery state, stay here until update_dr_i + else module_next_state <= `STATE_Wmatch; + end + + default: module_next_state <= `STATE_idle; // shouldn't actually happen... + endcase + end + + + // Outputs of state machine, pure combinatorial + always @ (module_state or module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i or operation_in[2] + or word_count_zero or bit_count_max or data_register_i[52] or biu_ready or intreg_instruction + or module_cmd or intreg_write or decremented_word_count) + begin + // Default everything to 0, keeps the case statement simple + addr_sel <= 1'b1; // Selects data for address_counter. 0 = data_register_i, 1 = incremented address count + addr_ct_en <= 1'b0; // Enable signal for address counter register + op_reg_en <= 1'b0; // Enable signal for 'operation' register + bit_ct_en <= 1'b0; // enable bit counter + bit_ct_rst <= 1'b0; // reset (zero) bit count register + word_ct_sel <= 1'b1; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count + word_ct_en <= 1'b0; // Enable byte counter register + out_reg_ld_en <= 1'b0; // Enable parallel load of data_out_shift_reg + out_reg_shift_en <= 1'b0; // Enable shift of data_out_shift_reg + tdo_output_sel <= 2'b1; // 1 = data reg, 0 = biu_ready, 2 = crc_match, 3 = CRC data + biu_strobe <= 1'b0; + crc_clr <= 1'b0; + crc_en <= 1'b0; // add the input bit to the CRC calculation + crc_in_sel <= 1'b0; // 0 = tdo, 1 = tdi + crc_shift_en <= 1'b0; + out_reg_data_sel <= 1'b1; // 0 = BIU data, 1 = internal register data + regsel_ld_en <= 1'b0; + intreg_ld_en <= 1'b0; + top_inhibit_o <= 1'b0; // Don't disable the top-level module in the default case + + case(module_state) + `STATE_idle: + begin + addr_sel <= 1'b0; + word_ct_sel <= 1'b0; + + // Operations for internal registers - stay in idle state + if(module_select_i & shift_dr_i) out_reg_shift_en <= 1'b1; // For module regs + if(module_select_i & capture_dr_i) + begin + out_reg_data_sel <= 1'b1; // select internal register data + out_reg_ld_en <= 1'b1; // For module regs + end + if(module_select_i & module_cmd & update_dr_i) begin + if(intreg_instruction) regsel_ld_en <= 1'b1; // For module regs + if(intreg_write) intreg_ld_en <= 1'b1; // For module regs + end + + // Burst operations + if(module_next_state != `STATE_idle) begin // Do the same to receive read or write opcode + addr_ct_en <= 1'b1; + op_reg_en <= 1'b1; + bit_ct_rst <= 1'b1; + word_ct_en <= 1'b1; + crc_clr <= 1'b1; + end + end + + `STATE_Rbegin: + begin + if(!word_count_zero) begin // Start a biu read transaction + biu_strobe <= 1'b1; + addr_sel <= 1'b1; + addr_ct_en <= 1'b1; + end + end + + `STATE_Rready: + ; // Just a wait state + + `STATE_Rstatus: + begin + tdo_output_sel <= 2'h0; + top_inhibit_o <= 1'b1; // in case of early termination + + if (module_next_state == `STATE_Rburst) begin + out_reg_data_sel <= 1'b0; // select BIU data + out_reg_ld_en <= 1'b1; + bit_ct_rst <= 1'b1; + word_ct_sel <= 1'b1; + word_ct_en <= 1'b1; + if(!(decremented_word_count == 0) && !word_count_zero) begin // Start a biu read transaction + biu_strobe <= 1'b1; + addr_sel <= 1'b1; + addr_ct_en <= 1'b1; + end + end + end + + `STATE_Rburst: + begin + tdo_output_sel <= 2'h1; + out_reg_shift_en <= 1'b1; + bit_ct_en <= 1'b1; + crc_en <= 1'b1; + crc_in_sel <= 1'b0; // read data in output shift register LSB (tdo) + top_inhibit_o <= 1'b1; // in case of early termination + end + + `STATE_Rcrc: + begin + // Just shift out the data, don't bother counting, we don't move on until update_dr_i + tdo_output_sel <= 2'h3; + crc_shift_en <= 1'b1; + top_inhibit_o <= 1'b1; + end + + `STATE_Wready: + ; // Just a wait state + + `STATE_Wwait: + begin + tdo_output_sel <= 2'h1; + top_inhibit_o <= 1'b1; // in case of early termination + if(module_next_state == `STATE_Wburst) begin + bit_ct_en <= 1'b1; + word_ct_sel <= 1'b1; // Pre-decrement the byte count + word_ct_en <= 1'b1; + crc_en <= 1'b1; // CRC gets tdi_i, which is 1 cycle ahead of data_register_i, so we need the bit there now in the CRC + crc_in_sel <= 1'b1; // read data from tdi_i + end + end + + `STATE_Wburst: + begin + bit_ct_en <= 1'b1; + tdo_output_sel <= 2'h1; + crc_en <= 1'b1; + crc_in_sel <= 1'b1; // read data from tdi_i + top_inhibit_o <= 1'b1; // in case of early termination + end + + `STATE_Wstatus: + begin + tdo_output_sel <= 2'h0; // Send the status bit to TDO + // start transaction + biu_strobe <= 1'b1; // Start a BIU transaction + word_ct_sel <= 1'b1; // Decrement the byte count + word_ct_en <= 1'b1; + bit_ct_rst <= 1'b1; // Zero the bit count + addr_ct_en <= 1'b1; // Increment thte address counter + top_inhibit_o <= 1'b1; // in case of early termination + end + + `STATE_Wcrc: + begin + bit_ct_en <= 1'b1; + top_inhibit_o <= 1'b1; // in case of early termination + if(module_next_state == `STATE_Wmatch) tdo_output_sel <= 2'h2; // This is when the 'match' bit is actually read + end + + `STATE_Wmatch: + begin + tdo_output_sel <= 2'h2; + top_inhibit_o <= 1'b1; // in case of early termination + end + + default: ; + endcase + end + + +endmodule + Index: adv_dbg_if/rtl/verilog/adbg_top.v =================================================================== --- adv_dbg_if/rtl/verilog/adbg_top.v (nonexistent) +++ adv_dbg_if/rtl/verilog/adbg_top.v (revision 3) @@ -0,0 +1,386 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// adbg_top.v //// +//// //// +//// //// +//// This file is part of the SoC Advanced Debug Interface. //// +//// //// +//// Author(s): //// +//// Nathan Yawn (nathan.yawn@opencores.org) //// +//// //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: adbg_top.v,v $ +// Revision 1.2 2009/05/17 20:54:56 Nathan +// Changed email address to opencores.org +// +// Revision 1.1 2008/07/22 20:28:32 Nathan +// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes. +// +// Revision 1.10 2008/07/11 08:13:29 Nathan +// Latch opcode on posedge, like other signals. This fixes a problem +// when the module is used with a Xilinx BSCAN TAP. Added signals to +// allow modules to inhibit latching of a new active module by the top +// module. This allows the sub-modules to force the top level module +// to ignore the command present in the input shift register after e.g. +// a burst read. +// +// Revision 1.7 2008/06/30 20:09:20 Nathan +// Removed code to select top-level module as active (it served no +// purpose). Re-numbered modules, requiring changes to testbench and +// software driver. +// + + +`include "adbg_defines.v" + + +// Top module +module adbg_top( + // JTAG signals + tck_i, + tdi_i, + tdo_o, + rst_i, + + + // TAP states + shift_dr_i, + pause_dr_i, + update_dr_i, + capture_dr_i, + + // Instructions + debug_select_i + + + `ifdef DBG_WISHBONE_SUPPORTED + // WISHBONE common signals + , + wb_clk_i, + + // WISHBONE master interface + wb_adr_o, + wb_dat_o, + wb_dat_i, + wb_cyc_o, + wb_stb_o, + wb_sel_o, + wb_we_o, + wb_ack_i, + wb_cab_o, + wb_err_i, + wb_cti_o, + wb_bte_o + `endif + + `ifdef DBG_CPU0_SUPPORTED + // CPU signals + , + cpu0_clk_i, + cpu0_addr_o, + cpu0_data_i, + cpu0_data_o, + cpu0_bp_i, + cpu0_stall_o, + cpu0_stb_o, + cpu0_we_o, + cpu0_ack_i, + cpu0_rst_o + `endif + + `ifdef DBG_CPU1_SUPPORTED + // CPU signals + , + cpu1_clk_i, + cpu1_addr_o, + cpu1_data_i, + cpu1_data_o, + cpu1_bp_i, + cpu1_stall_o, + cpu1_stb_o, + cpu1_we_o, + cpu1_ack_i, + cpu1_rst_o + `endif + + ); + + + // JTAG signals + input tck_i; + input tdi_i; + output tdo_o; + input rst_i; + + // TAP states + input shift_dr_i; + input pause_dr_i; + input update_dr_i; + input capture_dr_i; + + // Module select from TAP + input debug_select_i; + + `ifdef DBG_WISHBONE_SUPPORTED + input wb_clk_i; + output [31:0] wb_adr_o; + output [31:0] wb_dat_o; + input [31:0] wb_dat_i; + output wb_cyc_o; + output wb_stb_o; + output [3:0] wb_sel_o; + output wb_we_o; + input wb_ack_i; + output wb_cab_o; + input wb_err_i; + output [2:0] wb_cti_o; + output [1:0] wb_bte_o; + `endif + + `ifdef DBG_CPU0_SUPPORTED + // CPU signals + input cpu0_clk_i; + output [31:0] cpu0_addr_o; + input [31:0] cpu0_data_i; + output [31:0] cpu0_data_o; + input cpu0_bp_i; + output cpu0_stall_o; + output cpu0_stb_o; + output cpu0_we_o; + input cpu0_ack_i; + output cpu0_rst_o; + `endif + + `ifdef DBG_CPU1_SUPPORTED + input cpu1_clk_i; + output [31:0] cpu1_addr_o; + input [31:0] cpu1_data_i; + output [31:0] cpu1_data_o; + input cpu1_bp_i; + output cpu1_stall_o; + output cpu1_stb_o; + output cpu1_we_o; + input cpu1_ack_i; + output cpu1_rst_o; + `endif + + + reg tdo_o; + wire tdo_wb; + wire tdo_cpu0; + wire tdo_cpu1; + + + // Registers + reg [`DBG_TOP_MODULE_DATA_LEN-1:0] input_shift_reg; // 1 bit sel/cmd, 4 bit opcode, 32 bit address, 16 bit length = 53 bits + //reg output_shift_reg; // Just 1 bit for status (valid module selected) + reg [`DBG_TOP_MODULE_ID_LENGTH -1:0] module_id_reg; // Module selection register + + + // Control signals + wire select_cmd; // True when the command (registered at Update_DR) is for top level/module selection + wire [(`DBG_TOP_MODULE_ID_LENGTH - 1) : 0] module_id_in; // The part of the input_shift_register to be used as the module select data + reg [(`DBG_TOP_MAX_MODULES - 1) : 0] module_selects; // Select signals for the individual modules + wire select_inhibit; // OR of inhibit signals from sub-modules, prevents latching of a new module ID + wire [2:0] module_inhibit; // signals to allow submodules to prevent top level from latching new module ID + + /////////////////////////////////////// + // Combinatorial assignments + +assign select_cmd = input_shift_reg[52]; +assign module_id_in = input_shift_reg[51:50]; + +////////////////////////////////////////////////////////// +// Module select register and select signals + +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + module_id_reg <= 2'b0; + else if(debug_select_i && select_cmd && update_dr_i && !select_inhibit) // Chain select + module_id_reg <= module_id_in; +end + + +always @ (module_id_reg) +begin + module_selects <= `DBG_TOP_MODULE_ID_LENGTH'h0; + module_selects[module_id_reg] <= 1'b1; +end + +/////////////////////////////////////////////// +// Data input shift register + +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + input_shift_reg <= 53'h0; + else if(debug_select_i && shift_dr_i) + input_shift_reg <= {tdi_i, input_shift_reg[52:1]}; +end + + +////////////////////////////////////////////// +// Debug module instantiations + +`ifdef DBG_WISHBONE_SUPPORTED +// Connecting wishbone module +adbg_wb_module i_dbg_wb ( + // JTAG signals + .tck_i (tck_i), + .module_tdo_o (tdo_wb), + .tdi_i (tdi_i), + + // TAP states + .capture_dr_i (capture_dr_i), + .shift_dr_i (shift_dr_i), + .update_dr_i (update_dr_i), + + .data_register_i (input_shift_reg), + .module_select_i (module_selects[`DBG_TOP_WISHBONE_DEBUG_MODULE]), + .top_inhibit_o (module_inhibit[`DBG_TOP_WISHBONE_DEBUG_MODULE]), + .rst_i (rst_i), + + // WISHBONE common signals + .wb_clk_i (wb_clk_i), + + // WISHBONE master interface + .wb_adr_o (wb_adr_o), + .wb_dat_o (wb_dat_o), + .wb_dat_i (wb_dat_i), + .wb_cyc_o (wb_cyc_o), + .wb_stb_o (wb_stb_o), + .wb_sel_o (wb_sel_o), + .wb_we_o (wb_we_o), + .wb_ack_i (wb_ack_i), + .wb_cab_o (wb_cab_o), + .wb_err_i (wb_err_i), + .wb_cti_o (wb_cti_o), + .wb_bte_o (wb_bte_o) + ); +`else +assign tdo_wb = 1'b0; +assign module_inhibit[`DBG_TOP_WISHBONE_DEBUG_MODULE] = 1'b0; +`endif + + + +`ifdef DBG_CPU0_SUPPORTED +adbg_or1k_module i_dbg_cpu_or1k ( + // JTAG signals + .tck_i (tck_i), + .module_tdo_o (tdo_cpu0), + .tdi_i (tdi_i), + + // TAP states + .capture_dr_i (capture_dr_i), + .shift_dr_i (shift_dr_i), + .update_dr_i (update_dr_i), + + .data_register_i (input_shift_reg), + .module_select_i (module_selects[`DBG_TOP_CPU0_DEBUG_MODULE]), + .top_inhibit_o (module_inhibit[`DBG_TOP_CPU0_DEBUG_MODULE]), + .rst_i (rst_i), + + // CPU signals + .cpu_clk_i (cpu0_clk_i), + .cpu_addr_o (cpu0_addr_o), + .cpu_data_i (cpu0_data_i), + .cpu_data_o (cpu0_data_o), + .cpu_bp_i (cpu0_bp_i), + .cpu_stall_o (cpu0_stall_o), + .cpu_stb_o (cpu0_stb_o), + .cpu_we_o (cpu0_we_o), + .cpu_ack_i (cpu0_ack_i), + .cpu_rst_o (cpu0_rst_o) + ); +`else +assign tdo_cpu0 = 1'b0; +assign module_inhibit[`DBG_TOP_CPU0_DEBUG_MODULE] = 1'b0; +`endif // DBG_CPU0_SUPPORTED + + + +`ifdef DBG_CPU1_SUPPORTED +// Connecting cpu module +adbg_or1k_module i_dbg_cpu_8051 ( + // JTAG signals + .tck_i (tck_i), + .module_tdo_o (tdo_cpu1), + .tdi_i (tdi_i), + + // TAP states + .capture_dr_i (capture_dr_i), + .shift_dr_i (shift_dr_i), + .update_dr_i (update_dr_i), + + .data_register_i (input_shift_reg), + .module_select_i (module_selects[`DBG_TOP_CPU1_DEBUG_MODULE]), + .top_inhibit_o (module_inhibit[`DBG_TOP_CPU1_DEBUG_MODULE]), + .rst_i (rst_i), + + // CPU signals + .cpu_clk_i (cpu1_clk_i), + .cpu_addr_o (cpu1_addr_o), + .cpu_data_i (cpu1_data_i), + .cpu_data_o (cpu1_data_o), + .cpu_bp_i (cpu1_bp_i), + .cpu_stall_o (cpu1_stall_o), + .cpu_stb_o (cpu1_stb_o), + .cpu_we_o (cpu1_we_o), + .cpu_ack_i (cpu1_ack_i), + .cpu_rst_o (cpu1_rst_o) + ); +`else +assign tdo_cpu1 = 1'b0; +assign module_inhibit[`DBG_TOP_CPU1_DEBUG_MODULE] = 1'b0; +`endif + +assign select_inhibit = |module_inhibit; + +///////////////////////////////////////////////// +// TDO output MUX + +always @ (module_id_reg or tdo_wb or tdo_cpu0 or tdo_cpu1) +begin + case (module_id_reg) + `DBG_TOP_WISHBONE_DEBUG_MODULE: tdo_o <= tdo_wb; + `DBG_TOP_CPU0_DEBUG_MODULE: tdo_o <= tdo_cpu0; + `DBG_TOP_CPU1_DEBUG_MODULE: tdo_o <= tdo_cpu1; + default: tdo_o <= 1'b0; + endcase + +end + + +endmodule Index: adv_dbg_if/rtl/verilog/adbg_wb_defines.v =================================================================== --- adv_dbg_if/rtl/verilog/adbg_wb_defines.v (nonexistent) +++ adv_dbg_if/rtl/verilog/adbg_wb_defines.v (revision 3) @@ -0,0 +1,89 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// adbg_wb_defines.v //// +//// //// +//// //// +//// This file is part of the SoC Advanced Debug Interface. //// +//// //// +//// Author(s): //// +//// Nathan Yawn (nathan.yawn@opencores.org) //// +//// //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: adbg_wb_defines.v,v $ +// Revision 1.3 2009/05/17 20:54:57 Nathan +// Changed email address to opencores.org +// +// Revision 1.2 2009/05/04 00:50:11 Nathan +// Changed the WB BIU to use big-endian byte ordering, to match the OR1000. Kept little-endian ordering as a compile-time option in case this is ever used with a little-endian CPU. +// +// Revision 1.1 2008/07/22 20:28:32 Nathan +// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes. +// + +// Endian-ness of the Wishbone interface. +// Default is BIG endian, to match the OR1200. +// If using a LITTLE endian CPU, e.g. an x86, un-comment this line. +//`define DBG_WB_LITTLE_ENDIAN + +// These relate to the number of internal registers, and how +// many bits are required in the Reg. Select register +`define DBG_WB_REGSELECT_SIZE 1 +`define DBG_WB_NUM_INTREG 1 + +// Register index definitions for module-internal registers +// The WB module has just 1, the error register +`define DBG_WB_INTREG_ERROR 1'b0 + +// Valid commands/opcodes for the wishbone debug module +// 0000 NOP +// 0001 Write burst, 8-bit access +// 0010 Write burst, 16-bit access +// 0011 Write burst, 32-bit access +// 0100 Reserved +// 0101 Read burst, 8-bit access +// 0110 Read burst, 16-bit access +// 0111 Read burst, 32-bit access +// 1000 Reserved +// 1001 Internal register select/write +// 1010 - 1100 Reserved +// 1101 Internal register select +// 1110 - 1111 Reserved + +`define DBG_WB_CMD_BWRITE8 4'h1 +`define DBG_WB_CMD_BWRITE16 4'h2 +`define DBG_WB_CMD_BWRITE32 4'h3 +`define DBG_WB_CMD_BREAD8 4'h5 +`define DBG_WB_CMD_BREAD16 4'h6 +`define DBG_WB_CMD_BREAD32 4'h7 +`define DBG_WB_CMD_IREG_WR 4'h9 +`define DBG_WB_CMD_IREG_SEL 4'hd Index: adv_dbg_if/rtl/verilog/adbg_wb_biu.v =================================================================== --- adv_dbg_if/rtl/verilog/adbg_wb_biu.v (nonexistent) +++ adv_dbg_if/rtl/verilog/adbg_wb_biu.v (revision 3) @@ -0,0 +1,434 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// adbg_wb_biu.v //// +//// //// +//// //// +//// This file is part of the SoC Debug Interface. //// +//// //// +//// Author(s): //// +//// Nathan Yawn (nathan.yawn@opencores.org) //// +//// //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: adbg_wb_biu.v,v $ +// Revision 1.3 2009/05/17 20:54:57 Nathan +// Changed email address to opencores.org +// +// Revision 1.2 2009/05/04 00:50:10 Nathan +// Changed the WB BIU to use big-endian byte ordering, to match the OR1000. Kept little-endian ordering as a compile-time option in case this is ever used with a little-endian CPU. +// +// Revision 1.1 2008/07/22 20:28:32 Nathan +// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes. +// +// Revision 1.4 2008/07/08 19:04:04 Nathan +// Many small changes to eliminate compiler warnings, no functional changes. +// System will now pass SRAM and CPU self-tests on Altera FPGA using +// altera_virtual_jtag TAP. +// + +`include "adbg_wb_defines.v" + +// Top module +module adbg_wb_biu + ( + // Debug interface signals + tck_i, + rst_i, + data_i, + data_o, + addr_i, + strobe_i, + rd_wrn_i, // If 0, then write op + rdy_o, + err_o, + word_size_i, // 1,2, or 4 + + // Wishbone signals + wb_clk_i, + wb_adr_o, + wb_dat_o, + wb_dat_i, + wb_cyc_o, + wb_stb_o, + wb_sel_o, + wb_we_o, + wb_ack_i, + wb_cab_o, + wb_err_i, + wb_cti_o, + wb_bte_o + ); + + // Debug interface signals + input tck_i; + input rst_i; + input [31:0] data_i; // Assume short words are in UPPER order bits! + output [31:0] data_o; + input [31:0] addr_i; + input strobe_i; + input rd_wrn_i; + output rdy_o; + output err_o; + input [2:0] word_size_i; + + // Wishbone signals + input wb_clk_i; + output [31:0] wb_adr_o; + output [31:0] wb_dat_o; + input [31:0] wb_dat_i; + output wb_cyc_o; + output wb_stb_o; + output [3:0] wb_sel_o; + output wb_we_o; + input wb_ack_i; + output wb_cab_o; + input wb_err_i; + output [2:0] wb_cti_o; + output [1:0] wb_bte_o; + + wire [31:0] data_o; + reg rdy_o; + wire err_o; + + wire [31:0] wb_adr_o; + reg wb_cyc_o; + reg wb_stb_o; + wire [31:0] wb_dat_o; + wire [3:0] wb_sel_o; + wire wb_we_o; + wire wb_cab_o; + wire [2:0] wb_cti_o; + wire [1:0] wb_bte_o; + + + // Registers + reg [3:0] sel_reg; + reg [29:0] addr_reg; // Don't need the two LSB, this info is in the SEL bits + reg [31:0] data_in_reg; // dbg->WB + reg [31:0] data_out_reg; // WB->dbg + reg wr_reg; + reg str_sync; // This is 'active-toggle' rather than -high or -low. + reg rdy_sync; // ditto, active-toggle + reg err_reg; + + // Sync registers. TFF indicates TCK domain, WBFF indicates wb_clk domain + reg rdy_sync_tff1; + reg rdy_sync_tff2; + reg rdy_sync_tff2q; // used to detect toggles + reg str_sync_wbff1; + reg str_sync_wbff2; + reg str_sync_wbff2q; // used to detect toggles + + + // Control Signals + reg data_o_en; // latch wb_data_i + reg rdy_sync_en; // toggle the rdy_sync signal, indicate ready to TCK domain + reg err_en; // latch the wb_err_i signal + + // Internal signals + reg [3:0] be_dec; // word_size and low-order address bits decoded to SEL bits + wire start_toggle; // WB domain, indicates a toggle on the start strobe + reg [31:0] swapped_data_i; + reg [31:0] swapped_data_out; + + ////////////////////////////////////////////////////// + // TCK clock domain + // There is no FSM here, just signal latching and clock + // domain synchronization + + // Create byte enable signals from word_size and address (combinatorial) + `ifdef DBG_WB_LITTLE_ENDIAN + // This uses LITTLE ENDIAN byte ordering...lowest-addressed bytes is the + // least-significant byte of the 32-bit WB bus. + always @ (word_size_i or addr_i) + begin + case (word_size_i) + 3'h1: + begin + if(addr_i[1:0] == 2'b00) be_dec <= 4'b0001; + else if(addr_i[1:0] == 2'b01) be_dec <= 4'b0010; + else if(addr_i[1:0] == 2'b10) be_dec <= 4'b0100; + else be_dec <= 4'b1000; + end + 3'h2: + begin + if(addr_i[1]) be_dec <= 4'b1100; + else be_dec <= 4'b0011; + end + 3'h4: be_dec <= 4'b1111; + default: be_dec <= 4'b1111; // default to 32-bit access + endcase + end + `else + // This is for a BIG ENDIAN CPU...lowest-addressed byte is + // the 8 most significant bits of the 32-bit WB bus. + always @ (word_size_i or addr_i) + begin + case (word_size_i) + 3'h1: + begin + if(addr_i[1:0] == 2'b00) be_dec <= 4'b1000; + else if(addr_i[1:0] == 2'b01) be_dec <= 4'b0100; + else if(addr_i[1:0] == 2'b10) be_dec <= 4'b0010; + else be_dec <= 4'b0001; + end + 3'h2: + begin + if(addr_i[1] == 1'b1) be_dec <= 4'b0011; + else be_dec <= 4'b1100; + end + 3'h4: be_dec <= 4'b1111; + default: be_dec <= 4'b1111; // default to 32-bit access + endcase + end + `endif + + + // Byte- or word-swap data as necessary. Use the non-latched be_dec signal, + // since it and the swapped data will be latched at the same time. + // Remember that since the data is shifted in LSB-first, shorter words + // will be in the high-order bits. (combinatorial) + always @ (be_dec or data_i) + begin + case (be_dec) + 4'b1111: swapped_data_i <= data_i; + 4'b0011: swapped_data_i <= {16'h0,data_i[31:16]}; + 4'b1100: swapped_data_i <= data_i; + 4'b0001: swapped_data_i <= {24'h0, data_i[31:24]}; + 4'b0010: swapped_data_i <= {16'h0, data_i[31:24], 8'h0}; + 4'b0100: swapped_data_i <= {8'h0, data_i[31:24], 16'h0}; + 4'b1000: swapped_data_i <= {data_i[31:24], 24'h0}; + default: swapped_data_i <= data_i; // Shouldn't be possible + endcase + end + + // Latch input data on 'start' strobe, if ready. + always @ (posedge tck_i or posedge rst_i) + begin + if(rst_i) begin + sel_reg <= 4'h0; + addr_reg <= 30'h0; + data_in_reg <= 32'h0; + wr_reg <= 1'b0; + end + else + if(strobe_i && rdy_o) begin + sel_reg <= be_dec; + addr_reg <= addr_i[31:2]; + if(!rd_wrn_i) data_in_reg <= swapped_data_i; + wr_reg <= ~rd_wrn_i; + end + end + + // Create toggle-active strobe signal for clock sync. This will start a transaction + // on the WB once the toggle propagates to the FSM in the WB domain. + always @ (posedge tck_i or posedge rst_i) + begin + if(rst_i) str_sync <= 1'b0; + else if(strobe_i && rdy_o) str_sync <= ~str_sync; + end + + // Create rdy_o output. Set on reset, clear on strobe (if set), set on input toggle + always @ (posedge tck_i or posedge rst_i) + begin + if(rst_i) begin + rdy_sync_tff1 <= 1'b0; + rdy_sync_tff2 <= 1'b0; + rdy_sync_tff2q <= 1'b0; + rdy_o <= 1'b1; + end + else begin + rdy_sync_tff1 <= rdy_sync; // Synchronize the ready signal across clock domains + rdy_sync_tff2 <= rdy_sync_tff1; + rdy_sync_tff2q <= rdy_sync_tff2; // used to detect toggles + + if(strobe_i && rdy_o) rdy_o <= 1'b0; + else if(rdy_sync_tff2 != rdy_sync_tff2q) rdy_o <= 1'b1; + end + + end + + ////////////////////////////////////////////////////////// + // Direct assignments, unsynchronized + + assign wb_dat_o = data_in_reg; + assign wb_we_o = wr_reg; + assign wb_adr_o = {addr_reg, 2'h0}; + assign wb_sel_o = sel_reg; + + assign data_o = data_out_reg; + assign err_o = err_reg; + + assign wb_cti_o = 3'h0; + assign wb_bte_o = 2'h0; + assign wb_cab_o = 1'b0; + + /////////////////////////////////////////////////////// + // Wishbone clock domain + + // synchronize the start strobe + always @ (posedge wb_clk_i or posedge rst_i) + begin + if(rst_i) begin + str_sync_wbff1 <= 1'b0; + str_sync_wbff2 <= 1'b0; + str_sync_wbff2q <= 1'b0; + end + else begin + str_sync_wbff1 <= str_sync; + str_sync_wbff2 <= str_sync_wbff1; + str_sync_wbff2q <= str_sync_wbff2; // used to detect toggles + end + end + + assign start_toggle = (str_sync_wbff2 != str_sync_wbff2q); + + // Error indicator register + always @ (posedge wb_clk_i or posedge rst_i) + begin + if(rst_i) err_reg <= 1'b0; + else if(err_en) err_reg <= wb_err_i; + end + + // Byte- or word-swap the WB->dbg data, as necessary (combinatorial) + // We assume bits not required by SEL are don't care. We reuse assignments + // where possible to keep the MUX smaller. (combinatorial) + always @ (sel_reg or wb_dat_i) + begin + case (sel_reg) + 4'b1111: swapped_data_out <= wb_dat_i; + 4'b0011: swapped_data_out <= wb_dat_i; + 4'b1100: swapped_data_out <= {16'h0, wb_dat_i[31:16]}; + 4'b0001: swapped_data_out <= wb_dat_i; + 4'b0010: swapped_data_out <= {24'h0, wb_dat_i[15:8]}; + 4'b0100: swapped_data_out <= {16'h0, wb_dat_i[31:16]}; + 4'b1000: swapped_data_out <= {24'h0, wb_dat_i[31:24]}; + default: swapped_data_out <= wb_dat_i; // Shouldn't be possible + endcase + end + + // WB->dbg data register + always @ (posedge wb_clk_i or posedge rst_i) + begin + if(rst_i) data_out_reg <= 32'h0; + else if(data_o_en) data_out_reg <= swapped_data_out; + end + + // Create a toggle-active ready signal to send to the TCK domain + always @ (posedge wb_clk_i or posedge rst_i) + begin + if(rst_i) rdy_sync <= 1'b0; + else if(rdy_sync_en) rdy_sync <= ~rdy_sync; + end + + ///////////////////////////////////////////////////// + // Small state machine to create WB accesses + // Not much more that an 'in_progress' bit, but easier + // to read. Deals with single-cycle and multi-cycle + // accesses. + + reg wb_fsm_state; + reg next_fsm_state; + +`define STATE_IDLE 1'h0 +`define STATE_TRANSFER 1'h1 + + // Sequential bit + always @ (posedge wb_clk_i or posedge rst_i) + begin + if(rst_i) wb_fsm_state <= `STATE_IDLE; + else wb_fsm_state <= next_fsm_state; + end + + // Determination of next state (combinatorial) + always @ (wb_fsm_state or start_toggle or wb_ack_i or wb_err_i) + begin + case (wb_fsm_state) + `STATE_IDLE: + begin + if(start_toggle && !(wb_ack_i || wb_err_i)) next_fsm_state <= `STATE_TRANSFER; // Don't go to next state for 1-cycle transfer + else next_fsm_state <= `STATE_IDLE; + end + `STATE_TRANSFER: + begin + if(wb_ack_i || wb_err_i) next_fsm_state <= `STATE_IDLE; + else next_fsm_state <= `STATE_TRANSFER; + end + endcase + end + + // Outputs of state machine (combinatorial) + always @ (wb_fsm_state or start_toggle or wb_ack_i or wb_err_i or wr_reg) + begin + rdy_sync_en <= 1'b0; + err_en <= 1'b0; + data_o_en <= 1'b0; + wb_cyc_o <= 1'b0; + wb_stb_o <= 1'b0; + + case (wb_fsm_state) + `STATE_IDLE: + begin + if(start_toggle) begin + wb_cyc_o <= 1'b1; + wb_stb_o <= 1'b1; + if(wb_ack_i || wb_err_i) begin + err_en <= 1'b1; + rdy_sync_en <= 1'b1; + end + + if (wb_ack_i && !wr_reg) begin + data_o_en <= 1'b1; + end + end + end + + `STATE_TRANSFER: + begin + wb_cyc_o <= 1'b1; + wb_stb_o <= 1'b1; + if(wb_ack_i) begin + err_en <= 1'b1; + data_o_en <= 1'b1; + rdy_sync_en <= 1'b1; + end + else if (wb_err_i) begin + err_en <= 1'b1; + rdy_sync_en <= 1'b1; + end + end + endcase + + end + +endmodule + Index: adv_dbg_if/rtl/verilog/adbg_or1k_defines.v =================================================================== --- adv_dbg_if/rtl/verilog/adbg_or1k_defines.v (nonexistent) +++ adv_dbg_if/rtl/verilog/adbg_or1k_defines.v (revision 3) @@ -0,0 +1,86 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// adbg_or1k_defines.v //// +//// //// +//// //// +//// This file is part of the SoC Advanced Debug Interface. //// +//// //// +//// Author(s): //// +//// Nathan Yawn (nathan.yawn@opencores.org) //// +//// //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: adbg_or1k_defines.v,v $ +// Revision 1.2 2009/05/17 20:54:56 Nathan +// Changed email address to opencores.org +// +// Revision 1.1 2008/07/22 20:28:31 Nathan +// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes. +// +// Revision 1.3 2008/07/06 20:02:54 Nathan +// Fixes for synthesis with Xilinx ISE (also synthesizable with +// Quartus II 7.0). Ran through dos2unix. +// +// Revision 1.2 2008/06/26 20:52:31 Nathan +// OR1K module tested and working. Added copyright / license info +// to _define files. Other cleanup. +// + + +// These relate to the number of internal registers, and how +// many bits are required in the Reg. Select register +`define DBG_OR1K_REGSELECT_SIZE 1 +`define DBG_OR1K_NUM_INTREG 1 + +// Register index definitions for module-internal registers +// Index 0 is the Status register, used for stall and reset +`define DBG_OR1K_INTREG_STATUS 1'b0 + +`define DBG_OR1K_STATUS_LEN 2 + +// Valid commands/opcodes for the or1k debug module +// 0000 NOP +// 0001 - 0010 Reserved +// 0011 Write burst, 32-bit access +// 0100 - 0110 Reserved +// 0111 Read burst, 32-bit access +// 1000 Reserved +// 1001 Internal register select/write +// 1010 - 1100 Reserved +// 1101 Internal register select +// 1110 - 1111 Reserved + + +`define DBG_OR1K_CMD_BWRITE32 4'h3 +`define DBG_OR1K_CMD_BREAD32 4'h7 +`define DBG_OR1K_CMD_IREG_WR 4'h9 +`define DBG_OR1K_CMD_IREG_SEL 4'hd Index: adv_dbg_if/rtl/verilog/adbg_or1k_biu.v =================================================================== --- adv_dbg_if/rtl/verilog/adbg_or1k_biu.v (nonexistent) +++ adv_dbg_if/rtl/verilog/adbg_or1k_biu.v (revision 3) @@ -0,0 +1,296 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// adbg_or1k_biu.v //// +//// //// +//// //// +//// This file is part of the SoC Advanced Debug Interface. //// +//// //// +//// Author(s): //// +//// Nathan Yawn (nathan.yawn@opencores.org) //// +//// //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: adbg_or1k_biu.v,v $ +// Revision 1.2 2009/05/17 20:54:56 Nathan +// Changed email address to opencores.org +// +// Revision 1.1 2008/07/22 20:28:30 Nathan +// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes. +// +// Revision 1.5 2008/07/08 19:04:03 Nathan +// Many small changes to eliminate compiler warnings, no functional +// changes. System will now pass SRAM and CPU self-tests on Altera +// FPGA using altera_virtual_jtag TAP. +// + + + +module adbg_or1k_biu + ( + // Debug interface signals + tck_i, + rst_i, + data_i, + data_o, + addr_i, + strobe_i, + rd_wrn_i, // If 0, then write op + rdy_o, + + // OR1K SPR bus signals + cpu_clk_i, + cpu_addr_o, + cpu_data_i, + cpu_data_o, + cpu_stb_o, + cpu_we_o, + cpu_ack_i + ); + + // Debug interface signals + input tck_i; + input rst_i; + input [31:0] data_i; // Assume short words are in UPPER order bits! + output [31:0] data_o; + input [31:0] addr_i; + input strobe_i; + input rd_wrn_i; + output rdy_o; + + + // OR1K SPR bus signals + input cpu_clk_i; + output [31:0] cpu_addr_o; + input [31:0] cpu_data_i; + output [31:0] cpu_data_o; + output cpu_stb_o; + output cpu_we_o; + input cpu_ack_i; + + reg rdy_o; + reg cpu_stb_o; + + + // Registers + reg [31:0] addr_reg; + reg [31:0] data_in_reg; // dbg->WB + reg [31:0] data_out_reg; // WB->dbg + reg wr_reg; + reg str_sync; // This is 'active-toggle' rather than -high or -low. + reg rdy_sync; // ditto, active-toggle + + + // Sync registers. TFF indicates TCK domain, WBFF indicates cpu_clk domain + reg rdy_sync_tff1; + reg rdy_sync_tff2; + reg rdy_sync_tff2q; // used to detect toggles + reg str_sync_wbff1; + reg str_sync_wbff2; + reg str_sync_wbff2q; // used to detect toggles + + + // Control Signals + reg data_o_en; // latch wb_data_i + reg rdy_sync_en; // toggle the rdy_sync signal, indicate ready to TCK domain + + + // Internal signals + wire start_toggle; // CPU domain, indicates a toggle on the start strobe + + + ////////////////////////////////////////////////////// + // TCK clock domain + // There is no FSM here, just signal latching and clock + // domain synchronization + + + // Latch input data on 'start' strobe, if ready. + always @ (posedge tck_i or posedge rst_i) + begin + if(rst_i) begin + addr_reg <= 32'h0; + data_in_reg <= 32'h0; + wr_reg <= 1'b0; + end + else + if(strobe_i && rdy_o) begin + addr_reg <= addr_i; + if(!rd_wrn_i) data_in_reg <= data_i; + wr_reg <= ~rd_wrn_i; + end + end + + // Create toggle-active strobe signal for clock sync. This will start a transaction + // to the CPU once the toggle propagates to the FSM in the cpu_clk domain. + always @ (posedge tck_i or posedge rst_i) + begin + if(rst_i) str_sync <= 1'b0; + else if(strobe_i && rdy_o) str_sync <= ~str_sync; + end + + // Create rdy_o output. Set on reset, clear on strobe (if set), set on input toggle + always @ (posedge tck_i or posedge rst_i) + begin + if(rst_i) begin + rdy_sync_tff1 <= 1'b0; + rdy_sync_tff2 <= 1'b0; + rdy_sync_tff2q <= 1'b0; + rdy_o <= 1'b1; + end + else begin + rdy_sync_tff1 <= rdy_sync; // Synchronize the ready signal across clock domains + rdy_sync_tff2 <= rdy_sync_tff1; + rdy_sync_tff2q <= rdy_sync_tff2; // used to detect toggles + + if(strobe_i && rdy_o) rdy_o <= 1'b0; + else if(rdy_sync_tff2 != rdy_sync_tff2q) rdy_o <= 1'b1; + end + + end + + ////////////////////////////////////////////////////////// + // Direct assignments, unsynchronized + + assign cpu_data_o = data_in_reg; + assign cpu_we_o = wr_reg; + assign cpu_addr_o = addr_reg; + + assign data_o = data_out_reg; + + + /////////////////////////////////////////////////////// + // Wishbone clock domain + + // synchronize the start strobe + always @ (posedge cpu_clk_i or posedge rst_i) + begin + if(rst_i) begin + str_sync_wbff1 <= 1'b0; + str_sync_wbff2 <= 1'b0; + str_sync_wbff2q <= 1'b0; + end + else begin + str_sync_wbff1 <= str_sync; + str_sync_wbff2 <= str_sync_wbff1; + str_sync_wbff2q <= str_sync_wbff2; // used to detect toggles + end + end + + assign start_toggle = (str_sync_wbff2 != str_sync_wbff2q); + + + // CPU->dbg data register + always @ (posedge cpu_clk_i or posedge rst_i) + begin + if(rst_i) data_out_reg <= 32'h0; + else if(data_o_en) data_out_reg <= cpu_data_i; + end + + // Create a toggle-active ready signal to send to the TCK domain + always @ (posedge cpu_clk_i or posedge rst_i) + begin + if(rst_i) rdy_sync <= 1'b0; + else if(rdy_sync_en) rdy_sync <= ~rdy_sync; + end + + ///////////////////////////////////////////////////// + // Small state machine to create OR1K SPR bus accesses + // Not much more that an 'in_progress' bit, but easier + // to read. Deals with single-cycle and multi-cycle + // accesses. + + reg cpu_fsm_state; + reg next_fsm_state; + +`define STATE_IDLE 1'h0 +`define STATE_TRANSFER 1'h1 + + // Sequential bit + always @ (posedge cpu_clk_i or posedge rst_i) + begin + if(rst_i) cpu_fsm_state <= `STATE_IDLE; + else cpu_fsm_state <= next_fsm_state; + end + + // Determination of next state (combinatorial) + always @ (cpu_fsm_state or start_toggle or cpu_ack_i) + begin + case (cpu_fsm_state) + `STATE_IDLE: + begin + if(start_toggle && !cpu_ack_i) next_fsm_state <= `STATE_TRANSFER; // Don't go to next state for 1-cycle transfer + else next_fsm_state <= `STATE_IDLE; + end + `STATE_TRANSFER: + begin + if(cpu_ack_i) next_fsm_state <= `STATE_IDLE; + else next_fsm_state <= `STATE_TRANSFER; + end + endcase + end + + // Outputs of state machine (combinatorial) + always @ (cpu_fsm_state or start_toggle or cpu_ack_i or wr_reg) + begin + rdy_sync_en <= 1'b0; + data_o_en <= 1'b0; + cpu_stb_o <= 1'b0; + + case (cpu_fsm_state) + `STATE_IDLE: + begin + if(start_toggle) begin + cpu_stb_o <= 1'b1; + if(cpu_ack_i) begin + rdy_sync_en <= 1'b1; + end + + if (cpu_ack_i && !wr_reg) begin // latch read data + data_o_en <= 1'b1; + end + end + end + + `STATE_TRANSFER: + begin + cpu_stb_o <= 1'b1; // OR1K behavioral model needs this. OR1200 should be indifferent. + if(cpu_ack_i) begin + data_o_en <= 1'b1; + rdy_sync_en <= 1'b1; + end + end + endcase + + end + +endmodule + Index: adv_dbg_if/rtl/verilog/adbg_crc32.v =================================================================== --- adv_dbg_if/rtl/verilog/adbg_crc32.v (nonexistent) +++ adv_dbg_if/rtl/verilog/adbg_crc32.v (revision 3) @@ -0,0 +1,114 @@ +////////////////////////////////////////////////////////////////////// +// File: CRC32.v +// Date: Thu Nov 27 13:56:49 2003 +// +// Copyright (C) 1999-2003 Easics NV. +// This source file may be used and distributed without restriction +// provided that this copyright statement is not removed from the file +// and that any derivative work contains the original copyright notice +// and the associated disclaimer. +// +// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS +// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. +// +// Purpose: Verilog module containing a synthesizable CRC function +// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) +// * data width: 1 +// +// Info: janz@easics.be (Jan Zegers) +// http://www.easics.com +// +// Modified by Nathan Yawn for the Advanced Debug Module +// Changes (C) 2008 Nathan Yawn +/////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: adbg_crc32.v,v $ +// Revision 1.1 2008/07/22 20:28:29 Nathan +// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes. +// +// Revision 1.3 2008/07/06 20:02:53 Nathan +// Fixes for synthesis with Xilinx ISE (also synthesizable with +// Quartus II 7.0). Ran through dos2unix. +// +// Revision 1.2 2008/06/20 19:22:10 Nathan +// Reversed the direction of the CRC computation shift, for a more +// hardware-efficient implementation. +// +// +// +// + + +module adbg_crc32 (clk, data, enable, shift, clr, rst, crc_out, serial_out); + +input clk; +input data; +input enable; +input shift; +input clr; +input rst; +output [31:0] crc_out; +output serial_out; + + +reg [31:0] crc; +wire [31:0] new_crc; + + +// You may notice that the 'poly' in this implementation is backwards. +// This is because the shift is also 'backwards', so that the data can +// be shifted out in the same direction, which saves on logic + routing. +assign new_crc[0] = crc[1]; +assign new_crc[1] = crc[2]; +assign new_crc[2] = crc[3]; +assign new_crc[3] = crc[4]; +assign new_crc[4] = crc[5]; +assign new_crc[5] = crc[6] ^ data ^ crc[0]; +assign new_crc[6] = crc[7]; +assign new_crc[7] = crc[8]; +assign new_crc[8] = crc[9] ^ data ^ crc[0]; +assign new_crc[9] = crc[10] ^ data ^ crc[0]; +assign new_crc[10] = crc[11]; +assign new_crc[11] = crc[12]; +assign new_crc[12] = crc[13]; +assign new_crc[13] = crc[14]; +assign new_crc[14] = crc[15]; +assign new_crc[15] = crc[16] ^ data ^ crc[0]; +assign new_crc[16] = crc[17]; +assign new_crc[17] = crc[18]; +assign new_crc[18] = crc[19]; +assign new_crc[19] = crc[20] ^ data ^ crc[0]; +assign new_crc[20] = crc[21] ^ data ^ crc[0]; +assign new_crc[21] = crc[22] ^ data ^ crc[0]; +assign new_crc[22] = crc[23]; +assign new_crc[23] = crc[24] ^ data ^ crc[0]; +assign new_crc[24] = crc[25] ^ data ^ crc[0]; +assign new_crc[25] = crc[26]; +assign new_crc[26] = crc[27] ^ data ^ crc[0]; +assign new_crc[27] = crc[28] ^ data ^ crc[0]; +assign new_crc[28] = crc[29]; +assign new_crc[29] = crc[30] ^ data ^ crc[0]; +assign new_crc[30] = crc[31] ^ data ^ crc[0]; +assign new_crc[31] = data ^ crc[0]; + +always @ (posedge clk or posedge rst) +begin + if(rst) + crc[31:0] <= #1 32'hffffffff; + else if(clr) + crc[31:0] <= #1 32'hffffffff; + else if(enable) + crc[31:0] <= #1 new_crc; + else if (shift) + crc[31:0] <= #1 {1'b0, crc[31:1]}; +end + + +//assign crc_match = (crc == 32'h0); +assign crc_out = crc; //[31]; +assign serial_out = crc[0]; + +endmodule Index: adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v =================================================================== --- adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v (nonexistent) +++ adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v (revision 3) @@ -0,0 +1,192 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// adbg_or1k_status_reg.v //// +//// //// +//// //// +//// This file is part of the SoC Debug Interface. //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2008 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: adbg_or1k_status_reg.v,v $ +// Revision 1.1 2008/07/22 20:28:31 Nathan +// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes. +// +// Revision 1.3 2008/07/06 20:02:54 Nathan +// Fixes for synthesis with Xilinx ISE (also synthesizable with +// Quartus II 7.0). Ran through dos2unix. +// +// Revision 1.2 2008/06/26 20:52:32 Nathan +// OR1K module tested and working. Added copyright / license info +// to _define files. Other cleanup. +// +// +// +// + +`include "adbg_or1k_defines.v" + +module adbg_or1k_status_reg ( + data_i, + we_i, + tck_i, + bp_i, + rst_i, + cpu_clk_i, + ctrl_reg_o, + cpu_stall_o, + cpu_rst_o + ); + + + input [`DBG_OR1K_STATUS_LEN - 1:0] data_i; + input we_i; + input tck_i; + input bp_i; + input rst_i; + input cpu_clk_i; + + output [`DBG_OR1K_STATUS_LEN - 1:0] ctrl_reg_o; + output cpu_stall_o; + output cpu_rst_o; + + reg cpu_reset; + wire [2:1] cpu_op_out; + + reg stall_bp, stall_bp_csff, stall_bp_tck; + reg stall_reg, stall_reg_csff, stall_reg_cpu; + reg cpu_reset_csff; + reg cpu_rst_o; + + + + // Breakpoint is latched and synchronized. Stall is set and latched. + // This is done in the CPU clock domain, because the JTAG clock (TCK) is + // irregular. By only allowing bp_i to set (but not reset) the stall_bp + // signal, we insure that the CPU will remain in the stalled state until + // the debug host can read the state. + always @ (posedge cpu_clk_i or posedge rst_i) + begin + if(rst_i) + stall_bp <= #1 1'b0; + else if(bp_i) + stall_bp <= #1 1'b1; + else if(stall_reg_cpu) + stall_bp <= #1 1'b0; + end + + + // Synchronizing + always @ (posedge tck_i or posedge rst_i) + begin + if (rst_i) + begin + stall_bp_csff <= #1 1'b0; + stall_bp_tck <= #1 1'b0; + end + else + begin + stall_bp_csff <= #1 stall_bp; + stall_bp_tck <= #1 stall_bp_csff; + end + end + + + always @ (posedge cpu_clk_i or posedge rst_i) + begin + if (rst_i) + begin + stall_reg_csff <= #1 1'b0; + stall_reg_cpu <= #1 1'b0; + end + else + begin + stall_reg_csff <= #1 stall_reg; + stall_reg_cpu <= #1 stall_reg_csff; + end + end + + // bp_i forces a stall immediately on a breakpoint + // stall_bp holds the stall until the debug host acts + // stall_reg_cpu allows the debug host to control a stall. + assign cpu_stall_o = bp_i | stall_bp | stall_reg_cpu; + + + // Writing data to the control registers (stall) + // This can be set either by the debug host, or by + // a CPU breakpoint. It can only be cleared by the host. + always @ (posedge tck_i or posedge rst_i) + begin + if (rst_i) + stall_reg <= #1 1'b0; + else if (stall_bp_tck) + stall_reg <= #1 1'b1; + else if (we_i) + stall_reg <= #1 data_i[0]; + end + + + // Writing data to the control registers (reset) + always @ (posedge tck_i or posedge rst_i) + begin + if (rst_i) + cpu_reset <= #1 1'b0; + else if(we_i) + cpu_reset <= #1 data_i[1]; + end + + + // Synchronizing signals from registers + always @ (posedge cpu_clk_i or posedge rst_i) + begin + if (rst_i) + begin + cpu_reset_csff <= #1 1'b0; + cpu_rst_o <= #1 1'b0; + end + else + begin + cpu_reset_csff <= #1 cpu_reset; + cpu_rst_o <= #1 cpu_reset_csff; + end + end + + + + // Value for read back + assign ctrl_reg_o = {cpu_reset, stall_reg}; + + +endmodule + Index: adv_dbg_if/rtl/verilog/adbg_defines.v =================================================================== --- adv_dbg_if/rtl/verilog/adbg_defines.v (nonexistent) +++ adv_dbg_if/rtl/verilog/adbg_defines.v (revision 3) @@ -0,0 +1,82 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// adbg_defines.v //// +//// //// +//// //// +//// This file is part of the Advanced Debug Interface. //// +//// //// +//// Author(s): //// +//// Nathan Yawn (nathan.yawn@opencores.org) //// +//// //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: adbg_defines.v,v $ +// Revision 1.2 2009/05/17 20:54:56 Nathan +// Changed email address to opencores.org +// +// Revision 1.1 2008/07/22 20:28:30 Nathan +// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes. +// +// Revision 1.5 2008/07/06 20:02:53 Nathan +// Fixes for synthesis with Xilinx ISE (also synthesizable with +// Quartus II 7.0). Ran through dos2unix. +// +// Revision 1.4 2008/06/30 20:09:20 Nathan +// Removed code to select top-level module as active (it served no +// purpose). Re-numbered modules, requiring changes to testbench and software driver. +// + +// Length of the MODULE ID register +`define DBG_TOP_MODULE_ID_LENGTH 2 + +// How many modules can be supported by the module id length +`define DBG_TOP_MAX_MODULES 4 + +// Chains +`define DBG_TOP_WISHBONE_DEBUG_MODULE 2'h0 +`define DBG_TOP_CPU0_DEBUG_MODULE 2'h1 +`define DBG_TOP_CPU1_DEBUG_MODULE 2'h2 + +// Length of data +`define DBG_TOP_MODULE_DATA_LEN 53 + + +// If WISHBONE sub-module is supported uncomment the folowing line +`define DBG_WISHBONE_SUPPORTED + +// If CPU_0 sub-module is supported uncomment the folowing line +`define DBG_CPU0_SUPPORTED + +// If CPU_1 sub-module is supported uncomment the folowing line +//`define DBG_CPU1_SUPPORTED + + Index: adv_dbg_if/rtl/verilog/adbg_wb_module.v =================================================================== --- adv_dbg_if/rtl/verilog/adbg_wb_module.v (nonexistent) +++ adv_dbg_if/rtl/verilog/adbg_wb_module.v (revision 3) @@ -0,0 +1,736 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// adbg_wb_module.v //// +//// //// +//// //// +//// This file is part of the SoC Advanced Debug Interface. //// +//// //// +//// Author(s): //// +//// Nathan Yawn (nathan.yawn@opencores.org) //// +//// //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: adbg_wb_module.v,v $ +// Revision 1.2 2009/05/17 20:54:57 Nathan +// Changed email address to opencores.org +// +// Revision 1.1 2008/07/22 20:28:33 Nathan +// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes. +// +// Revision 1.12 2008/07/11 08:13:30 Nathan +// Latch opcode on posedge, like other signals. This fixes a problem when +// the module is used with a Xilinx BSCAN TAP. Added signals to allow modules +// to inhibit latching of a new active module by the top module. This allows +// the sub-modules to force the top level module to ignore the command present +// in the input shift register after e.g. a burst read. +// + + +`include "adbg_wb_defines.v" + +// Top module +module adbg_wb_module ( + // JTAG signals + tck_i, + module_tdo_o, + tdi_i, + + // TAP states + capture_dr_i, + shift_dr_i, + update_dr_i, + + data_register_i, // the data register is at top level, shared between all modules + module_select_i, + top_inhibit_o, + rst_i, + + // WISHBONE common signals + wb_clk_i, + + // WISHBONE master interface + wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o, + wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o + + ); + + // JTAG signals + input tck_i; + output module_tdo_o; + input tdi_i; // This is only used by the CRC module - data_register_i[MSB] is delayed a cycle + + // TAP states + input capture_dr_i; + input shift_dr_i; + input update_dr_i; + + input [52:0] data_register_i; + input module_select_i; + output top_inhibit_o; + input rst_i; + + // WISHBONE master interface + input wb_clk_i; + output [31:0] wb_adr_o; + output [31:0] wb_dat_o; + input [31:0] wb_dat_i; + output wb_cyc_o; + output wb_stb_o; + output [3:0] wb_sel_o; + output wb_we_o; + input wb_ack_i; + output wb_cab_o; + input wb_err_i; + output [2:0] wb_cti_o; + output [1:0] wb_bte_o; + //reg wb_cyc_o; + + // Declare inputs / outputs as wires / registers + reg module_tdo_o; + reg top_inhibit_o; + + + // Registers to hold state etc. + reg [31:0] address_counter; // Holds address for next Wishbone access + reg [5:0] bit_count; // How many bits have been shifted in/out + reg [15:0] word_count; // bytes remaining in current burst command + reg [3:0] operation; // holds the current command (rd/wr, word size) + reg [32:0] data_out_shift_reg; // 32 bits to accomodate the internal_reg_error + reg [`DBG_WB_REGSELECT_SIZE-1:0] internal_register_select; // Holds index of currently selected register + reg [32:0] internal_reg_error; // WB error module internal register. 32 bit address + error bit (LSB) + + + // Control signals for the various counters / registers / state machines + reg addr_sel; // Selects data for address_counter. 0 = data_register_i, 1 = incremented address count + reg addr_ct_en; // Enable signal for address counter register + reg op_reg_en; // Enable signal for 'operation' register + reg bit_ct_en; // enable bit counter + reg bit_ct_rst; // reset (zero) bit count register + reg word_ct_sel; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count + reg word_ct_en; // Enable byte counter register + reg out_reg_ld_en; // Enable parallel load of data_out_shift_reg + reg out_reg_shift_en; // Enable shift of data_out_shift_reg + reg out_reg_data_sel; // 0 = BIU data, 1 = internal register data + reg [1:0] tdo_output_sel; // Selects signal to send to TDO. 0 = ready bit, 1 = output register, 2 = CRC match, 3 = CRC shift reg. + reg biu_strobe; // Indicates that the bus unit should latch data and start a transaction + reg crc_clr; // resets CRC module + reg crc_en; // does 1-bit iteration in CRC module + reg crc_in_sel; // selects incoming write data (=0) or outgoing read data (=1)as input to CRC module + reg crc_shift_en; // CRC reg is also it's own output shift register; this enables a shift + reg regsel_ld_en; // Reg. select register load enable + reg intreg_ld_en; // load enable for internal registers + reg error_reg_en; // Tells the error register to check for and latch a bus error + reg biu_clr_err; // Allows FSM to reset BIU, to clear the biu_err bit which may have been set on the last transaction of the last burst. + + // Status signals + wire word_count_zero; // true when byte counter is zero + wire bit_count_max; // true when bit counter is equal to current word size + wire module_cmd; // inverse of MSB of data_register_i. 1 means current cmd not for top level (but is for us) + wire biu_ready; // indicates that the BIU has finished the last command + wire biu_err; // indicates wishbone error during BIU transaction + wire burst_instruction; // True when the input_data_i reg has a valid burst instruction for this module + wire intreg_instruction; // True when the input_data_i reg has a valid internal register instruction + wire intreg_write; // True when the input_data_i reg has an internal register write op + reg rd_op; // True when operation in the opcode reg is a read, false when a write + wire crc_match; // indicates whether data_register_i matches computed CRC + wire bit_count_32; // true when bit count register == 32, for CRC after burst writes + + // Intermediate signals + reg [5:0] word_size_bits; // 8,16, or 32. Decoded from 'operation' + reg [2:0] word_size_bytes; // 1,2, or 4 + wire [32:0] incremented_address; // value of address counter plus 'word_size' + wire [31:0] data_to_addr_counter; // output of the mux in front of the address counter inputs + wire [15:0] data_to_word_counter; // output of the mux in front of the byte counter input + wire [15:0] decremented_word_count; + wire [31:0] address_data_in; // from data_register_i + wire [15:0] count_data_in; // from data_register_i + wire [3:0] operation_in; // from data_register_i + wire [31:0] data_to_biu; // from data_register_i + wire [31:0] data_from_biu; // to data_out_shift_register + wire [31:0] crc_data_out; // output of CRC module, to output shift register + wire crc_data_in; // input to CRC module, either data_register_i[52] or data_out_shift_reg[0] + wire crc_serial_out; + wire [`DBG_WB_REGSELECT_SIZE-1:0] reg_select_data; // from data_register_i, input to internal register select register + wire [32:0] out_reg_data; // parallel input to the output shift register + reg [32:0] data_from_internal_reg; // data from internal reg. MUX to output shift register + wire biu_rst; // logical OR of rst_i and biu_clr_err + + ///////////////////////////////////////////////// + // Combinatorial assignments + + assign module_cmd = ~(data_register_i[52]); + assign operation_in = data_register_i[51:48]; + assign address_data_in = data_register_i[47:16]; + assign count_data_in = data_register_i[15:0]; + assign data_to_biu = data_register_i[52:21]; + assign reg_select_data = data_register_i[47:(47-(`DBG_WB_REGSELECT_SIZE-1))]; + + //////////////////////////////////////////////// + // Operation decoder + + // These are only used before the operation is latched, so decode them from operation_in + assign burst_instruction = (~operation_in[3]) & (operation_in[0] | operation_in[1]); + assign intreg_instruction = ((operation_in == `DBG_WB_CMD_IREG_WR) | (operation_in == `DBG_WB_CMD_IREG_SEL)); + assign intreg_write = (operation_in == `DBG_WB_CMD_IREG_WR); + + + // This is decoded from the registered operation + always @ (operation) + begin + case(operation) + `DBG_WB_CMD_BWRITE8: + begin + word_size_bits <= 5'd7; // Bits is actually bits-1, to make the FSM easier + word_size_bytes <= 3'd1; + rd_op <= 1'b0; + end + `DBG_WB_CMD_BWRITE16: + begin + word_size_bits <= 5'd15; // Bits is actually bits-1, to make the FSM easier + word_size_bytes <= 3'd2; + rd_op <= 1'b0; + end + `DBG_WB_CMD_BWRITE32: + begin + word_size_bits <= 5'd31; // Bits is actually bits-1, to make the FSM easier + word_size_bytes <= 3'd4; + rd_op <= 1'b0; + end + `DBG_WB_CMD_BREAD8: + begin + word_size_bits <= 5'd7; // Bits is actually bits-1, to make the FSM easier + word_size_bytes <= 3'd1; + rd_op <= 1'b1; + end + `DBG_WB_CMD_BREAD16: + begin + word_size_bits <= 5'd15; // Bits is actually bits-1, to make the FSM easier + word_size_bytes <= 3'd2; + rd_op <= 1'b1; + end + `DBG_WB_CMD_BREAD32: + begin + word_size_bits <= 5'd31; // Bits is actually bits-1, to make the FSM easier + word_size_bytes <= 3'd4; + rd_op <= 1'b1; + end + default: + begin + word_size_bits <= 5'hXX; + word_size_bytes <= 3'hX; + rd_op <= 1'bX; + end + endcase + end + + + //////////////////////////////////////////////// + // Module-internal register select register (no, that's not redundant.) + // Also internal register output MUX + + always @ (posedge tck_i or posedge rst_i) + begin + if(rst_i) internal_register_select = 1'h0; + else if(regsel_ld_en) internal_register_select = reg_select_data; + end + + // This is completely unnecessary here, since the WB module has only 1 internal + // register. However, to make the module expandable, it is included anyway. + always @ (internal_register_select or internal_reg_error) + begin + case(internal_register_select) + `DBG_WB_INTREG_ERROR: data_from_internal_reg = internal_reg_error; + default: data_from_internal_reg = internal_reg_error; + endcase + end + + + + //////////////////////////////////////////////////////////////////// + // Module-internal registers + // These have generic read/write/select code, but + // individual registers may have special behavior, defined here. + + // This is the bus error register, which traps WB errors + // We latch every new BIU address in the upper 32 bits, so we always have the address for the transaction which + // generated the error (the address counter might increment, esp. for writes) + // We stop latching addresses when the error bit (bit 0) is set. Keep the error bit set until it is + // manually cleared by a module internal register write. + // Note we use reg_select_data straight from data_register_i, rather than the latched version - + // otherwise, we would write the previously selected register. + + + always @ (posedge tck_i or posedge rst_i) + begin + if(rst_i) internal_reg_error = 33'h0; + else if(intreg_ld_en && (reg_select_data == `DBG_WB_INTREG_ERROR)) // do load from data input register + begin + if(data_register_i[46]) internal_reg_error[0] = 1'b0; // if write data is 1, reset the error bit + end + else if(error_reg_en && !internal_reg_error[0]) + begin + if(biu_err) internal_reg_error[0] = 1'b1; + else if(biu_strobe) internal_reg_error[32:1] = address_counter; + end + else if(biu_strobe && !internal_reg_error[0]) internal_reg_error[32:1] = address_counter; // When no error, latch this whether error_reg_en or not + end + + /////////////////////////////////////////////// + // Address counter + + assign data_to_addr_counter = (addr_sel) ? incremented_address[31:0] : address_data_in; + assign incremented_address = address_counter + word_size_bytes; + + // Technically, since this data (sometimes) comes from the input shift reg, we should latch on + // negedge, per the JTAG spec. But that makes things difficult when incrementing. + always @ (posedge tck_i or posedge rst_i) // JTAG spec specifies latch on negative edge in UPDATE_DR state + begin + if(rst_i) + address_counter <= 32'h0; + else if(addr_ct_en) + address_counter <= data_to_addr_counter; + end + + //////////////////////////////////////// + // Opcode latch + + always @ (posedge tck_i or posedge rst_i) // JTAG spec specifies latch on negative edge in UPDATE_DR state + begin + if(rst_i) + operation <= 4'h0; + else if(op_reg_en) + operation <= operation_in; + end + + ////////////////////////////////////// + // Bit counter + + always @ (posedge tck_i or posedge rst_i) + begin + + if(rst_i) bit_count <= 6'h0; + else if(bit_ct_rst) bit_count <= 6'h0; + else if(bit_ct_en) bit_count <= bit_count + 6'h1; + + end + + assign bit_count_max = (bit_count == word_size_bits) ? 1'b1 : 1'b0 ; + assign bit_count_32 = (bit_count == 6'h20) ? 1'b1 : 1'b0; + + //////////////////////////////////////// + // Word counter + + assign data_to_word_counter = (word_ct_sel) ? decremented_word_count : count_data_in; + assign decremented_word_count = word_count - 16'h1; + + // Technically, since this data (sometimes) comes from the input shift reg, we should latch on + // negedge, per the JTAG spec. But that makes things difficult when incrementing. + always @ (posedge tck_i or posedge rst_i) // JTAG spec specifies latch on negative edge in UPDATE_DR state + begin + if(rst_i) + word_count <= 16'h0; + else if(word_ct_en) + word_count <= data_to_word_counter; + end + + assign word_count_zero = (word_count == 16'h0); + + ///////////////////////////////////////////////////// + // Output register and TDO output MUX + + assign out_reg_data = (out_reg_data_sel) ? data_from_internal_reg : {1'b0,data_from_biu}; + + always @ (posedge tck_i or posedge rst_i) + begin + if(rst_i) data_out_shift_reg <= 33'h0; + else if(out_reg_ld_en) data_out_shift_reg <= out_reg_data; + else if(out_reg_shift_en) data_out_shift_reg <= {1'b0, data_out_shift_reg[32:1]}; + end + + + always @ (tdo_output_sel or data_out_shift_reg[0] or biu_ready or crc_match or crc_serial_out) + begin + if(tdo_output_sel == 2'h0) module_tdo_o <= biu_ready; + else if(tdo_output_sel == 2'h1) module_tdo_o <= data_out_shift_reg[0]; + else if(tdo_output_sel == 2'h2) module_tdo_o <= crc_match; + else module_tdo_o <= crc_serial_out; + end + + //////////////////////////////////////// + // Bus Interface Unit + // It is assumed that the BIU has internal registers, and will + // latch address, operation, and write data on rising clock edge + // when strobe is asserted + + assign biu_rst = rst_i | biu_clr_err; + + adbg_wb_biu wb_biu_i + ( + // Debug interface signals + .tck_i (tck_i), + .rst_i (biu_rst), + .data_i (data_to_biu), + .data_o (data_from_biu), + .addr_i (address_counter), + .strobe_i (biu_strobe), + .rd_wrn_i (rd_op), // If 0, then write op + .rdy_o (biu_ready), + .err_o (biu_err), + .word_size_i (word_size_bytes), + + // Wishbone signals + .wb_clk_i (wb_clk_i), + .wb_adr_o (wb_adr_o), + .wb_dat_o (wb_dat_o), + .wb_dat_i (wb_dat_i), + .wb_cyc_o (wb_cyc_o), + .wb_stb_o (wb_stb_o), + .wb_sel_o (wb_sel_o), + .wb_we_o (wb_we_o), + .wb_ack_i (wb_ack_i), + .wb_cab_o (wb_cab_o), + .wb_err_i (wb_err_i), + .wb_cti_o (wb_cti_o), + .wb_bte_o (wb_bte_o) + ); + + ///////////////////////////////////// + // CRC module + + assign crc_data_in = (crc_in_sel) ? tdi_i : data_out_shift_reg[0]; // MUX, write or read data + + adbg_crc32 wb_crc_i + ( + .clk(tck_i), + .data(crc_data_in), + .enable(crc_en), + .shift(crc_shift_en), + .clr(crc_clr), + .rst(rst_i), + .crc_out(crc_data_out), + .serial_out(crc_serial_out) + ); + + assign crc_match = (data_register_i[52:21] == crc_data_out) ? 1'b1 : 1'b0; + + //////////////////////////////////////// + // Control FSM + + // Definition of machine state values. + // Don't worry too much about the state encoding, the synthesis tool + // will probably re-encode it anyway. + +`define STATE_idle 4'h0 +`define STATE_Rbegin 4'h1 +`define STATE_Rready 4'h2 +`define STATE_Rstatus 4'h3 +`define STATE_Rburst 4'h4 +`define STATE_Wready 4'h5 +`define STATE_Wwait 4'h6 +`define STATE_Wburst 4'h7 +`define STATE_Wstatus 4'h8 +`define STATE_Rcrc 4'h9 +`define STATE_Wcrc 4'ha +`define STATE_Wmatch 4'hb + + reg [3:0] module_state; // FSM state + reg [3:0] module_next_state; // combinatorial signal, not actually a register + + + + // sequential part of the FSM + always @ (posedge tck_i or posedge rst_i) + begin + if(rst_i) + module_state <= `STATE_idle; + else + module_state <= module_next_state; + end + + + // Determination of next state; purely combinatorial + always @ (module_state or module_select_i or module_cmd or update_dr_i or capture_dr_i or operation_in[2] + or word_count_zero or bit_count_max or data_register_i[52] or bit_count_32 or biu_ready or burst_instruction) + begin + case(module_state) + `STATE_idle: + begin + if(module_cmd && module_select_i && update_dr_i && burst_instruction && operation_in[2]) module_next_state <= `STATE_Rbegin; + else if(module_cmd && module_select_i && update_dr_i && burst_instruction) module_next_state <= `STATE_Wready; + else module_next_state <= `STATE_idle; + end + + `STATE_Rbegin: + begin + if(word_count_zero) module_next_state <= `STATE_idle; // set up a burst of size 0, illegal. + else module_next_state <= `STATE_Rready; + end + `STATE_Rready: + begin + if(module_select_i && capture_dr_i) module_next_state <= `STATE_Rstatus; + else module_next_state <= `STATE_Rready; + end + `STATE_Rstatus: + begin + if(update_dr_i) module_next_state <= `STATE_idle; + else if (biu_ready) module_next_state <= `STATE_Rburst; + else module_next_state <= `STATE_Rstatus; + end + `STATE_Rburst: + begin + if(update_dr_i) module_next_state <= `STATE_idle; + else if(bit_count_max && word_count_zero) module_next_state <= `STATE_Rcrc; + else if(bit_count_max) module_next_state <= `STATE_Rstatus; + else module_next_state <= `STATE_Rburst; + end + `STATE_Rcrc: + begin + if(update_dr_i) module_next_state <= `STATE_idle; + // This doubles as the 'recovery' state, so stay here until update_dr_i. + else module_next_state <= `STATE_Rcrc; + end + + `STATE_Wready: + begin + if(word_count_zero) module_next_state <= `STATE_idle; + else if(module_select_i && capture_dr_i) module_next_state <= `STATE_Wwait; + else module_next_state <= `STATE_Wready; + end + `STATE_Wwait: + begin + if(update_dr_i) module_next_state <= `STATE_idle; // client terminated early + else if(module_select_i && data_register_i[52]) module_next_state <= `STATE_Wburst; // Got a start bit + else module_next_state <= `STATE_Wwait; + end + `STATE_Wburst: + begin + if(update_dr_i) module_next_state <= `STATE_idle; // client terminated early + else if(bit_count_max) module_next_state <= `STATE_Wstatus; + else module_next_state <= `STATE_Wburst; + end + `STATE_Wstatus: + begin + if(update_dr_i) module_next_state <= `STATE_idle; // client terminated early + else if(word_count_zero) module_next_state <= `STATE_Wcrc; + // can't wait until bus ready if multiple devices in chain... + // Would have to read postfix_bits, then send another start bit and push it through + // prefix_bits...potentially very inefficient. + else module_next_state <= `STATE_Wburst; + end + + `STATE_Wcrc: + begin + if(update_dr_i) module_next_state <= `STATE_idle; // client terminated early + else if(bit_count_32) module_next_state <= `STATE_Wmatch; + else module_next_state <= `STATE_Wcrc; + end + + `STATE_Wmatch: + begin + if(update_dr_i) module_next_state <= `STATE_idle; + // This doubles as our recovery state, stay here until update_dr_i + else module_next_state <= `STATE_Wmatch; + end + + default: module_next_state <= `STATE_idle; // shouldn't actually happen... + endcase + end + + + // Outputs of state machine, pure combinatorial + always @ (module_state or module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i or operation_in[2] + or word_count_zero or bit_count_max or data_register_i[52] or biu_ready or intreg_instruction or module_cmd + or intreg_write or decremented_word_count) + begin + // Default everything to 0, keeps the case statement simple + addr_sel <= 1'b1; // Selects data for address_counter. 0 = data_register_i, 1 = incremented address count + addr_ct_en <= 1'b0; // Enable signal for address counter register + op_reg_en <= 1'b0; // Enable signal for 'operation' register + bit_ct_en <= 1'b0; // enable bit counter + bit_ct_rst <= 1'b0; // reset (zero) bit count register + word_ct_sel <= 1'b1; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count + word_ct_en <= 1'b0; // Enable byte counter register + out_reg_ld_en <= 1'b0; // Enable parallel load of data_out_shift_reg + out_reg_shift_en <= 1'b0; // Enable shift of data_out_shift_reg + tdo_output_sel <= 2'b1; // 1 = data reg, 0 = biu_ready, 2 = crc_match, 3 = CRC data + biu_strobe <= 1'b0; + crc_clr <= 1'b0; + crc_en <= 1'b0; // add the input bit to the CRC calculation + crc_in_sel <= 1'b0; // 0 = tdo, 1 = tdi + crc_shift_en <= 1'b0; + out_reg_data_sel <= 1'b1; // 0 = BIU data, 1 = internal register data + regsel_ld_en <= 1'b0; + intreg_ld_en <= 1'b0; + error_reg_en <= 1'b0; + biu_clr_err <= 1'b0; // Set this to reset the BIU, clearing the biu_err bit + top_inhibit_o <= 1'b0; // Don't disable the top-level module in the default case + + case(module_state) + `STATE_idle: + begin + addr_sel <= 1'b0; + word_ct_sel <= 1'b0; + + // Operations for internal registers - stay in idle state + if(module_select_i & shift_dr_i) out_reg_shift_en <= 1'b1; // For module regs + if(module_select_i & capture_dr_i) + begin + out_reg_data_sel <= 1'b1; // select internal register data + out_reg_ld_en <= 1'b1; // For module regs + end + if(module_select_i & module_cmd & update_dr_i) begin + if(intreg_instruction) regsel_ld_en <= 1'b1; // For module regs + if(intreg_write) intreg_ld_en <= 1'b1; // For module regs + end + + // Burst operations + if(module_next_state != `STATE_idle) begin // Do the same to receive read or write opcode + addr_ct_en <= 1'b1; + op_reg_en <= 1'b1; + bit_ct_rst <= 1'b1; + word_ct_en <= 1'b1; + crc_clr <= 1'b1; + end + end + + `STATE_Rbegin: + begin + if(!word_count_zero) begin // Start a biu read transaction + biu_strobe <= 1'b1; + addr_sel <= 1'b1; + addr_ct_en <= 1'b1; + end + end + + `STATE_Rready: + ; // Just a wait state + + `STATE_Rstatus: + begin + tdo_output_sel <= 2'h0; + top_inhibit_o <= 1'b1; // in case of early termination + + if (module_next_state == `STATE_Rburst) begin + error_reg_en <= 1'b1; // Check the wb_error bit + out_reg_data_sel <= 1'b0; // select BIU data + out_reg_ld_en <= 1'b1; + bit_ct_rst <= 1'b1; + word_ct_sel <= 1'b1; + word_ct_en <= 1'b1; + if(!(decremented_word_count == 0) && !word_count_zero) begin // Start a biu read transaction + biu_strobe <= 1'b1; + addr_sel <= 1'b1; + addr_ct_en <= 1'b1; + end + end + end + + `STATE_Rburst: + begin + tdo_output_sel <= 2'h1; + out_reg_shift_en <= 1'b1; + bit_ct_en <= 1'b1; + crc_en <= 1'b1; + crc_in_sel <= 1'b0; // read data in output shift register LSB (tdo) + top_inhibit_o <= 1'b1; // in case of early termination + end + + `STATE_Rcrc: + begin + // Just shift out the data, don't bother counting, we don't move on until update_dr_i + tdo_output_sel <= 2'h3; + crc_shift_en <= 1'b1; + top_inhibit_o <= 1'b1; + end + + `STATE_Wready: + ; // Just a wait state + + `STATE_Wwait: + begin + tdo_output_sel <= 2'h1; + top_inhibit_o <= 1'b1; // in case of early termination + if(module_next_state == `STATE_Wburst) begin + biu_clr_err <= 1'b1; // If error occurred on last transaction of last burst, biu_err is still set. Clear it. + bit_ct_en <= 1'b1; + word_ct_sel <= 1'b1; // Pre-decrement the byte count + word_ct_en <= 1'b1; + crc_en <= 1'b1; // CRC gets tdi_i, which is 1 cycle ahead of data_register_i, so we need the bit there now in the CRC + crc_in_sel <= 1'b1; // read data from tdi_i + end + end + + `STATE_Wburst: + begin + bit_ct_en <= 1'b1; + tdo_output_sel <= 2'h1; + crc_en <= 1'b1; + crc_in_sel <= 1'b1; // read data from tdi_i + top_inhibit_o <= 1'b1; // in case of early termination + end + + `STATE_Wstatus: + begin + tdo_output_sel <= 2'h0; // Send the status bit to TDO + error_reg_en <= 1'b1; // Check the wb_error bit + // start transaction + biu_strobe <= 1'b1; // Start a BIU transaction + word_ct_sel <= 1'b1; // Decrement the byte count + word_ct_en <= 1'b1; + bit_ct_rst <= 1'b1; // Zero the bit count + addr_ct_en <= 1'b1; // Increment thte address counter + top_inhibit_o <= 1'b1; // in case of early termination + end + + `STATE_Wcrc: + begin + bit_ct_en <= 1'b1; + top_inhibit_o <= 1'b1; // in case of early termination + if(module_next_state == `STATE_Wmatch) tdo_output_sel <= 2'h2; // This is when the 'match' bit is actually read + end + + `STATE_Wmatch: + begin + tdo_output_sel <= 2'h2; + top_inhibit_o <= 1'b1; + // Bit of a hack here...an error on the final write won't be detected in STATE_Wstatus like the rest, + // so we assume the bus transaction is done and check it / latch it into the error register here. + if(module_next_state == `STATE_idle) error_reg_en <= 1'b1; + end + + default: ; + endcase + end + + +endmodule + Index: adv_dbg_if/doc/License_FDL-1.2.txt =================================================================== --- adv_dbg_if/doc/License_FDL-1.2.txt (nonexistent) +++ adv_dbg_if/doc/License_FDL-1.2.txt (revision 3) @@ -0,0 +1,397 @@ + GNU Free Documentation License + Version 1.2, November 2002 + + + Copyright (C) 2000,2001,2002 Free Software Foundation, Inc. + 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + +0. 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Index: adv_dbg_if/doc/AdvancedDebugInterface.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: adv_dbg_if/doc/AdvancedDebugInterface.pdf =================================================================== --- adv_dbg_if/doc/AdvancedDebugInterface.pdf (nonexistent) +++ adv_dbg_if/doc/AdvancedDebugInterface.pdf (revision 3)
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adv_dbg_if/doc/src/system_block_diagram.odg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: adv_dbg_if/doc/gpl-2.0.txt =================================================================== --- adv_dbg_if/doc/gpl-2.0.txt (nonexistent) +++ adv_dbg_if/doc/gpl-2.0.txt (revision 3) @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. 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Index: jtag/cells/rtl/verilog/InputCell.v =================================================================== --- jtag/cells/rtl/verilog/InputCell.v (nonexistent) +++ jtag/cells/rtl/verilog/InputCell.v (revision 3) @@ -0,0 +1,62 @@ +/********************************************************************************** +* * +* This verilog file is a part of the Boundary Scan Implementation and comes in * +* a pack with several other files. It is fully IEEE 1149.1 compliant. * +* For details check www.opencores.org (pdf files, bsdl file, etc.) * +* * +* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG * +* * +* This program is free software; you can redistribute it and/or modify * +* it under the terms of the GNU General Public License as published by * +* the Free Software Foundation; either version 2 of the License, or * +* (at your option) any later version. * +* * +* See the file COPYING for the full details of the license. * +* * +* OPENCORES.ORG is looking for new open source IP cores and developers that * +* would like to help in our mission. * +* * +**********************************************************************************/ + + + +/********************************************************************************** +* * +* Input Cell: * +* * +* InputPin: Value that comes from on-chip logic and goes to pin * +* FromPreviousBSCell: Value from previous boundary scan cell * +* ToNextBSCell: Value for next boundary scan cell * +* CaptureDR, ShiftDR: TAP states * +* TCK: Test Clock * +* * +**********************************************************************************/ + +// This is not a top module +module InputCell( InputPin, FromPreviousBSCell, CaptureDR, ShiftDR, TCK, ToNextBSCell); +input InputPin; +input FromPreviousBSCell; +input CaptureDR; +input ShiftDR; +input TCK; + +reg Latch; + +output ToNextBSCell; +reg ToNextBSCell; + +wire SelectedInput = CaptureDR? InputPin : FromPreviousBSCell; + +always @ (posedge TCK) +begin + if(CaptureDR | ShiftDR) + Latch<=SelectedInput; +end + +always @ (negedge TCK) +begin + ToNextBSCell<=Latch; +end + + +endmodule // InputCell \ No newline at end of file Index: jtag/cells/rtl/verilog/ControlCell.v =================================================================== --- jtag/cells/rtl/verilog/ControlCell.v (nonexistent) +++ jtag/cells/rtl/verilog/ControlCell.v (revision 3) @@ -0,0 +1,77 @@ +/********************************************************************************** +* * +* This verilog file is a part of the Boundary Scan Implementation and comes in * +* a pack with several other files. It is fully IEEE 1149.1 compliant. * +* For details check www.opencores.org (pdf files, bsdl file, etc.) * +* * +* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG * +* * +* This program is free software; you can redistribute it and/or modify * +* it under the terms of the GNU General Public License as published by * +* the Free Software Foundation; either version 2 of the License, or * +* (at your option) any later version. * +* * +* See the file COPYING for the full details of the license. * +* * +* OPENCORES.ORG is looking for new open source IP cores and developers that * +* would like to help in our mission. * +* * +**********************************************************************************/ + + +/********************************************************************************** +* * +* I/O Control Cell: * +* * +* OutputControl: Output Control from on-chip logic * +* FromPreviousBSCell: Value from previous boundary scan cell * +* ToNextBSCell: Value for next boundary scan cell * +* CaptureDR, ShiftDR, UpdateDR: TAP states * +* extest: Instruction Register Command * +* TCK: Test Clock * +* * +* Output Enable can be generated by running CaptureDR-UpdateDR sequence or * +* shifting data for the exact number of time * +* * +**********************************************************************************/ + +// This is not a top module +module ControlCell( OutputControl, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, ToOutputEnable); +input OutputControl; +input FromPreviousBSCell; +input CaptureDR; +input ShiftDR; +input UpdateDR; +input extest; +input TCK; + +reg Latch; + +output ToNextBSCell; +output ToOutputEnable; + +reg ToNextBSCell; +reg ShiftedControl; + +wire SelectedInput = CaptureDR? OutputControl : FromPreviousBSCell; + +always @ (posedge TCK) +begin + if(CaptureDR | ShiftDR) + Latch<=SelectedInput; +end + +always @ (negedge TCK) +begin + ToNextBSCell<=Latch; +end + +always @ (negedge TCK) +begin + if(UpdateDR) + ShiftedControl<=ToNextBSCell; +end + +assign ToOutputEnable = extest? ShiftedControl : OutputControl; + +endmodule // ControlCell \ No newline at end of file Index: jtag/cells/rtl/verilog/OutputCell.v =================================================================== --- jtag/cells/rtl/verilog/OutputCell.v (nonexistent) +++ jtag/cells/rtl/verilog/OutputCell.v (revision 3) @@ -0,0 +1,83 @@ +/********************************************************************************** +* * +* This verilog file is a part of the Boundary Scan Implementation and comes in * +* a pack with several other files. It is fully IEEE 1149.1 compliant. * +* For details check www.opencores.org (pdf files, bsdl file, etc.) * +* * +* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG * +* * +* This program is free software; you can redistribute it and/or modify * +* it under the terms of the GNU General Public License as published by * +* the Free Software Foundation; either version 2 of the License, or * +* (at your option) any later version. * +* * +* See the file COPYING for the full details of the license. * +* * +* OPENCORES.ORG is looking for new open source IP cores and developers that * +* would like to help in our mission. * +* * +**********************************************************************************/ + + + +/********************************************************************************** +* * +* Output Cell: * +* * +* FromCore: Value that comes from on-chip logic and goes to pin * +* FromPreviousBSCell: Value from previous boundary scan cell * +* ToNextBSCell: Value for next boundary scan cell * +* CaptureDR, ShiftDR, UpdateDR: TAP states * +* extest: Instruction Register Command * +* TCK: Test Clock * +* TristatedPin: Signal from core is connected to this output pin via BS * +* FromOutputEnable: This pin comes from core or ControlCell * +* * +* Signal that is connected to TristatedPin comes from core or BS chain. * +* Tristate control is generated in core or BS chain (ControlCell). * +* * +**********************************************************************************/ + +// This is not a top module +module OutputCell( FromCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, TristatedPin); +input FromCore; +input FromPreviousBSCell; +input CaptureDR; +input ShiftDR; +input UpdateDR; +input extest; +input TCK; +input FromOutputEnable; + +reg Latch; + +output ToNextBSCell; +reg ToNextBSCell; + +output TristatedPin; + +reg ShiftedControl; + +wire SelectedInput = CaptureDR? FromCore : FromPreviousBSCell; + +always @ (posedge TCK) +begin + if(CaptureDR | ShiftDR) + Latch<=SelectedInput; +end + +always @ (negedge TCK) +begin + ToNextBSCell<=Latch; +end + +always @ (negedge TCK) +begin + if(UpdateDR) + ShiftedControl<=ToNextBSCell; +end + +wire MuxedSignal = extest? ShiftedControl : FromCore; +assign TristatedPin = FromOutputEnable? MuxedSignal : 1'bz; + +endmodule // OutputCell \ No newline at end of file Index: jtag/cells/rtl/verilog/BiDirectionalCell.v =================================================================== --- jtag/cells/rtl/verilog/BiDirectionalCell.v (nonexistent) +++ jtag/cells/rtl/verilog/BiDirectionalCell.v (revision 3) @@ -0,0 +1,66 @@ +/********************************************************************************** +* * +* BiDirectional Cell: * +* * +* FromCore: Value that comes from on-chip logic and goes to pin * +* ToCore: Value that is read-in from the pin and goes to core * +* FromPreviousBSCell: Value from previous boundary scan cell * +* ToNextBSCell: Value for next boundary scan cell * +* CaptureDR, ShiftDR, UpdateDR: TAP states * +* extest: Instruction Register Command * +* TCK: Test Clock * +* BiDirPin: Bidirectional pin connected to this BS cell * +* FromOutputEnable: This pin comes from core or ControlCell * +* * +* Signal that is connected to BiDirPin comes from core or BS chain. Tristate * +* control is generated in core or BS chain (ControlCell). * +* * +**********************************************************************************/ + +module BiDirectionalCell( FromCore, ToCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, BiDirPin); +input FromCore; +input FromPreviousBSCell; +input CaptureDR; +input ShiftDR; +input UpdateDR; +input extest; +input TCK; +input FromOutputEnable; + +reg Latch; + +output ToNextBSCell; +reg ToNextBSCell; + +output BiDirPin; +output ToCore; + +reg ShiftedControl; + +wire SelectedInput = CaptureDR? BiDirPin : FromPreviousBSCell; + +always @ (posedge TCK) +begin + if(CaptureDR | ShiftDR) + Latch<=SelectedInput; +end + +always @ (negedge TCK) +begin + ToNextBSCell<=Latch; +end + +always @ (negedge TCK) +begin + if(UpdateDR) + ShiftedControl<=ToNextBSCell; +end + +wire MuxedSignal = extest? ShiftedControl : FromCore; +assign BiDirPin = FromOutputEnable? MuxedSignal : 1'bz; + +//BUF Buffer (.I(BiDirPin), .O(ToCore)); +assign ToCore = BiDirPin; + + +endmodule // TristateCell \ No newline at end of file Index: jtag/BSDL/opencores_tap.bsd =================================================================== --- jtag/BSDL/opencores_tap.bsd (nonexistent) +++ jtag/BSDL/opencores_tap.bsd (revision 3) @@ -0,0 +1,35 @@ +-- This is a minimal BSDL file describing the particulars +-- of the OpenCores standard / native TAP. It is designed +-- only to be used by the adv_jtag_bridge program. This +-- file almost certainly lacks key entries and attributes +-- required by other JTAG / BSDL systems. +-- +-- by Nathan Yawn (nathan.yawn@opencores.org) +-- Copyright: This file is released into the public domain. +-- + + +entity OC_TAP is + + +attribute INSTRUCTION_LENGTH of OC_TAP : entity is 4; + + +attribute INSTRUCTION_OPCODE of OC_TAP : entity is + "EXTEST (0000)," & + "SAMPLE_PRELOAD (0001)," & + "IDCODE (0010)," & + "MBIST (1001)," & + "DEBUG (1000)," & + "BYPASS (1111),"; + + +attribute IDCODE_REGISTER of OC_TAP : entity is + "0001" & -- version + "0100100101010001" & -- part number + "00011100001" & -- manufacturer (flextronics) + "1"; -- required by 1149.1 + + +end OC_TAP; + Index: jtag/tap/rtl/verilog/tap_defines.v =================================================================== --- jtag/tap/rtl/verilog/tap_defines.v (nonexistent) +++ jtag/tap/rtl/verilog/tap_defines.v (revision 3) @@ -0,0 +1,79 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// tap_defines.v //// +//// //// +//// //// +//// This file is part of the JTAG Test Access Port (TAP) //// +//// http://www.opencores.org/projects/jtag/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2003 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: tap_defines.v,v $ +// Revision 1.1.1.1 2008/05/14 12:07:33 Nathan +// Original from OpenCores +// +// Revision 1.3 2004/03/02 17:39:45 mohor +// IDCODE_VALUE changed to Flextronics ID. +// +// Revision 1.2 2004/01/27 10:00:33 mohor +// Unused registers removed. +// +// Revision 1.1 2003/12/23 14:52:14 mohor +// Directory structure changed. New version of TAP. +// +// +// + + +// Define IDCODE Value +`define IDCODE_VALUE 32'h149511c3 +// 0001 version +// 0100100101010001 part number (IQ) +// 00011100001 manufacturer id (flextronics) +// 1 required by standard + +// Length of the Instruction register +`define IR_LENGTH 4 + +// Supported Instructions +`define EXTEST 4'b0000 +`define SAMPLE_PRELOAD 4'b0001 +`define IDCODE 4'b0010 +`define DEBUG 4'b1000 +`define MBIST 4'b1001 +`define BYPASS 4'b1111 + Index: jtag/tap/rtl/verilog/tap_top.v =================================================================== --- jtag/tap/rtl/verilog/tap_top.v (nonexistent) +++ jtag/tap/rtl/verilog/tap_top.v (revision 3) @@ -0,0 +1,577 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// tap_top.v //// +//// //// +//// //// +//// This file is part of the JTAG Test Access Port (TAP) //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// Nathan Yawn (nathan.yawn@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the jtag.pdf //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2008 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: tap_top.v,v $ +// Revision 1.4 2009/05/17 20:54:38 Nathan +// Changed email address to opencores.org +// +// Revision 1.3 2008/06/18 18:45:07 Nathan +// Improved reset slightly. Cleanup. +// +// +// Revision 1.2 2008/05/14 13:13:24 Nathan +// Rewrote TAP FSM in canonical form, for readability. Switched +// from one-hot to binary encoding. Made reset signal active- +// low, per JTAG spec. Removed FF chain for 5 TMS reset - reset +// done in Test Logic Reset mode. Added test_logic_reset_o and +// run_test_idle_o signals. Removed double registers from IR data +// path. Unified the registers at the output of each data register +// to a single shared FF. +// +// Revision 1.6 2004/01/27 10:00:33 mohor +// Unused registers removed. +// +// Revision 1.5 2004/01/18 09:27:39 simons +// Blocking non blocking assignmenst fixed. +// +// Revision 1.4 2004/01/17 17:37:44 mohor +// capture_dr_o added to ports. +// +// Revision 1.3 2004/01/14 13:50:56 mohor +// 5 consecutive TMS=1 causes reset of TAP. +// +// Revision 1.2 2004/01/08 10:29:44 mohor +// Control signals for tdo_pad_o mux are changed to negedge. +// +// Revision 1.1 2003/12/23 14:52:14 mohor +// Directory structure changed. New version of TAP. +// +// Revision 1.10 2003/10/23 18:08:01 mohor +// MBIST chain connection fixed. +// +// Revision 1.9 2003/10/23 16:17:02 mohor +// CRC logic changed. +// +// Revision 1.8 2003/10/21 09:48:31 simons +// Mbist support added. +// +// Revision 1.7 2002/11/06 14:30:10 mohor +// Trst active high. Inverted on higher layer. +// +// Revision 1.6 2002/04/22 12:55:56 mohor +// tdo_padoen_o changed to tdo_padoe_o. Signal is active high. +// +// Revision 1.5 2002/03/26 14:23:38 mohor +// Signal tdo_padoe_o changed back to tdo_padoen_o. +// +// Revision 1.4 2002/03/25 13:16:15 mohor +// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just +// not named correctly. +// +// Revision 1.3 2002/03/12 14:30:05 mohor +// Few outputs for boundary scan chain added. +// +// Revision 1.2 2002/03/12 10:31:53 mohor +// tap_top and dbg_top modules are put into two separate modules. tap_top +// contains only tap state machine and related logic. dbg_top contains all +// logic necessery for debugging. +// +// Revision 1.1 2002/03/08 15:28:16 mohor +// Structure changed. Hooks for jtag chain added. +// +// +// +// + +`include "tap_defines.v" + +// Top module +module tap_top( + // JTAG pads + tms_pad_i, + tck_pad_i, + trstn_pad_i, + tdi_pad_i, + tdo_pad_o, + tdo_padoe_o, + + // TAP states + test_logic_reset_o, + run_test_idle_o, + shift_dr_o, + pause_dr_o, + update_dr_o, + capture_dr_o, + + // Select signals for boundary scan or mbist + extest_select_o, + sample_preload_select_o, + mbist_select_o, + debug_select_o, + + // TDO signal that is connected to TDI of sub-modules. + tdo_o, + + // TDI signals from sub-modules + debug_tdi_i, // from debug module + bs_chain_tdi_i, // from Boundary Scan Chain + mbist_tdi_i // from Mbist Chain + ); + + +// JTAG pins +input tms_pad_i; // JTAG test mode select pad +input tck_pad_i; // JTAG test clock pad +input trstn_pad_i; // JTAG test reset pad +input tdi_pad_i; // JTAG test data input pad +output tdo_pad_o; // JTAG test data output pad +output tdo_padoe_o; // Output enable for JTAG test data output pad + +// TAP states +output test_logic_reset_o; +output run_test_idle_o; +output shift_dr_o; +output pause_dr_o; +output update_dr_o; +output capture_dr_o; + +// Select signals for boundary scan or mbist +output extest_select_o; +output sample_preload_select_o; +output mbist_select_o; +output debug_select_o; + +// TDO signal that is connected to TDI of sub-modules. +output tdo_o; + +// TDI signals from sub-modules +input debug_tdi_i; // from debug module +input bs_chain_tdi_i; // from Boundary Scan Chain +input mbist_tdi_i; // from Mbist Chain + +// Wires which depend on the state of the TAP FSM +reg test_logic_reset; +reg run_test_idle; +reg select_dr_scan; +reg capture_dr; +reg shift_dr; +reg exit1_dr; +reg pause_dr; +reg exit2_dr; +reg update_dr; +reg select_ir_scan; +reg capture_ir; +reg shift_ir; +reg exit1_ir; +reg pause_ir; +reg exit2_ir; +reg update_ir; + +// Wires which depend on the current value in the IR +reg extest_select; +reg sample_preload_select; +reg idcode_select; +reg mbist_select; +reg debug_select; +reg bypass_select; + +// TDO and enable +reg tdo_pad_o; +reg tdo_padoe_o; + +assign tdo_o = tdi_pad_i; + +assign test_logic_reset_o = test_logic_reset; +assign run_test_idle_o = run_test_idle; +assign shift_dr_o = shift_dr; +assign pause_dr_o = pause_dr; +assign update_dr_o = update_dr; +assign capture_dr_o = capture_dr; + +assign extest_select_o = extest_select; +assign sample_preload_select_o = sample_preload_select; +assign mbist_select_o = mbist_select; +assign debug_select_o = debug_select; + + +/********************************************************************************** +* * +* TAP State Machine: Fully JTAG compliant * +* * +**********************************************************************************/ +// Definition of machine state values. We could one-hot encode this, and use 16 +// registers, but this uses binary encoding for the minimum of 4 DFF's instead. +`define STATE_test_logic_reset 4'hF +`define STATE_run_test_idle 4'hC +`define STATE_select_dr_scan 4'h7 +`define STATE_capture_dr 4'h6 +`define STATE_shift_dr 4'h2 +`define STATE_exit1_dr 4'h1 +`define STATE_pause_dr 4'h3 +`define STATE_exit2_dr 4'h0 +`define STATE_update_dr 4'h5 +`define STATE_select_ir_scan 4'h4 +`define STATE_capture_ir 4'hE +`define STATE_shift_ir 4'hA +`define STATE_exit1_ir 4'h9 +`define STATE_pause_ir 4'hB +`define STATE_exit2_ir 4'h8 +`define STATE_update_ir 4'hD + +reg [3:0] TAP_state = `STATE_test_logic_reset; // current state of the TAP controller +reg [3:0] next_TAP_state; // state TAP will take at next rising TCK, combinational signal + +// sequential part of the FSM +always @ (posedge tck_pad_i or negedge trstn_pad_i) +begin + if(trstn_pad_i == 0) + TAP_state = `STATE_test_logic_reset; + else + TAP_state = next_TAP_state; +end + + +// Determination of next state; purely combinatorial +always @ (TAP_state or tms_pad_i) +begin + case(TAP_state) + `STATE_test_logic_reset: + begin + if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset; + else next_TAP_state = `STATE_run_test_idle; + end + `STATE_run_test_idle: + begin + if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan; + else next_TAP_state = `STATE_run_test_idle; + end + `STATE_select_dr_scan: + begin + if(tms_pad_i) next_TAP_state = `STATE_select_ir_scan; + else next_TAP_state = `STATE_capture_dr; + end + `STATE_capture_dr: + begin + if(tms_pad_i) next_TAP_state = `STATE_exit1_dr; + else next_TAP_state = `STATE_shift_dr; + end + `STATE_shift_dr: + begin + if(tms_pad_i) next_TAP_state = `STATE_exit1_dr; + else next_TAP_state = `STATE_shift_dr; + end + `STATE_exit1_dr: + begin + if(tms_pad_i) next_TAP_state = `STATE_update_dr; + else next_TAP_state = `STATE_pause_dr; + end + `STATE_pause_dr: + begin + if(tms_pad_i) next_TAP_state = `STATE_exit2_dr; + else next_TAP_state = `STATE_pause_dr; + end + `STATE_exit2_dr: + begin + if(tms_pad_i) next_TAP_state = `STATE_update_dr; + else next_TAP_state = `STATE_shift_dr; + end + `STATE_update_dr: + begin + if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan; + else next_TAP_state = `STATE_run_test_idle; + end + `STATE_select_ir_scan: + begin + if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset; + else next_TAP_state = `STATE_capture_ir; + end + `STATE_capture_ir: + begin + if(tms_pad_i) next_TAP_state = `STATE_exit1_ir; + else next_TAP_state = `STATE_shift_ir; + end + `STATE_shift_ir: + begin + if(tms_pad_i) next_TAP_state = `STATE_exit1_ir; + else next_TAP_state = `STATE_shift_ir; + end + `STATE_exit1_ir: + begin + if(tms_pad_i) next_TAP_state = `STATE_update_ir; + else next_TAP_state = `STATE_pause_ir; + end + `STATE_pause_ir: + begin + if(tms_pad_i) next_TAP_state = `STATE_exit2_ir; + else next_TAP_state = `STATE_pause_ir; + end + `STATE_exit2_ir: + begin + if(tms_pad_i) next_TAP_state = `STATE_update_ir; + else next_TAP_state = `STATE_shift_ir; + end + `STATE_update_ir: + begin + if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan; + else next_TAP_state = `STATE_run_test_idle; + end + default: next_TAP_state = `STATE_test_logic_reset; // can't actually happen + endcase +end + + +// Outputs of state machine, pure combinatorial +always @ (TAP_state) +begin + // Default everything to 0, keeps the case statement simple + test_logic_reset = 1'b0; + run_test_idle = 1'b0; + select_dr_scan = 1'b0; + capture_dr = 1'b0; + shift_dr = 1'b0; + exit1_dr = 1'b0; + pause_dr = 1'b0; + exit2_dr = 1'b0; + update_dr = 1'b0; + select_ir_scan = 1'b0; + capture_ir = 1'b0; + shift_ir = 1'b0; + exit1_ir = 1'b0; + pause_ir = 1'b0; + exit2_ir = 1'b0; + update_ir = 1'b0; + + case(TAP_state) + `STATE_test_logic_reset: test_logic_reset = 1'b1; + `STATE_run_test_idle: run_test_idle = 1'b1; + `STATE_select_dr_scan: select_dr_scan = 1'b1; + `STATE_capture_dr: capture_dr = 1'b1; + `STATE_shift_dr: shift_dr = 1'b1; + `STATE_exit1_dr: exit1_dr = 1'b1; + `STATE_pause_dr: pause_dr = 1'b1; + `STATE_exit2_dr: exit2_dr = 1'b1; + `STATE_update_dr: update_dr = 1'b1; + `STATE_select_ir_scan: select_ir_scan = 1'b1; + `STATE_capture_ir: capture_ir = 1'b1; + `STATE_shift_ir: shift_ir = 1'b1; + `STATE_exit1_ir: exit1_ir = 1'b1; + `STATE_pause_ir: pause_ir = 1'b1; + `STATE_exit2_ir: exit2_ir = 1'b1; + `STATE_update_ir: update_ir = 1'b1; + default: ; + endcase +end + +/********************************************************************************** +* * +* End: TAP State Machine * +* * +**********************************************************************************/ + + + +/********************************************************************************** +* * +* jtag_ir: JTAG Instruction Register * +* * +**********************************************************************************/ +reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register +reg [`IR_LENGTH-1:0] latched_jtag_ir; //, latched_jtag_ir_neg; +wire instruction_tdo; + +always @ (posedge tck_pad_i or negedge trstn_pad_i) +begin + if(trstn_pad_i == 0) + jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0; + else if (test_logic_reset == 1) + jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0; + else if(capture_ir) + jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection + else if(shift_ir) + jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]}; +end + +assign instruction_tdo = jtag_ir[0]; // This is latched on a negative TCK edge after the output MUX + +// Updating jtag_ir (Instruction Register) +// jtag_ir should be latched on FALLING EDGE of TCK when capture_ir == 1 +always @ (negedge tck_pad_i or negedge trstn_pad_i) +begin + if(trstn_pad_i == 0) + latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset + else if (test_logic_reset) + latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset + else if(update_ir) + latched_jtag_ir <=#1 jtag_ir; +end + +/********************************************************************************** +* * +* End: jtag_ir * +* * +**********************************************************************************/ + + + +/********************************************************************************** +* * +* idcode logic * +* * +**********************************************************************************/ +reg [31:0] idcode_reg; +wire idcode_tdo; + +always @ (posedge tck_pad_i or negedge trstn_pad_i) +begin + if(trstn_pad_i == 0) + idcode_reg <=#1 `IDCODE_VALUE; // IDCODE selected after reset + else if (test_logic_reset) + idcode_reg <=#1 `IDCODE_VALUE; // IDCODE selected after reset + else if(idcode_select & capture_dr) + idcode_reg <= #1 `IDCODE_VALUE; + else if(idcode_select & shift_dr) + idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]}; + +end + +assign idcode_tdo = idcode_reg[0]; // This is latched on a negative TCK edge after the output MUX + +/********************************************************************************** +* * +* End: idcode logic * +* * +**********************************************************************************/ + + +/********************************************************************************** +* * +* Bypass logic * +* * +**********************************************************************************/ +wire bypassed_tdo; +reg bypass_reg; // This is a 1-bit register + +always @ (posedge tck_pad_i or negedge trstn_pad_i) +begin + if (trstn_pad_i == 0) + bypass_reg <= #1 1'b0; + else if (test_logic_reset == 1) + bypass_reg <= #1 1'b0; + else if (bypass_select & capture_dr) + bypass_reg<=#1 1'b0; + else if(bypass_select & shift_dr) + bypass_reg<=#1 tdi_pad_i; +end + +assign bypassed_tdo = bypass_reg; // This is latched on a negative TCK edge after the output MUX + +/********************************************************************************** +* * +* End: Bypass logic * +* * +**********************************************************************************/ + + +/********************************************************************************** +* * +* Selecting active data register * +* * +**********************************************************************************/ +always @ (latched_jtag_ir) +begin + extest_select = 1'b0; + sample_preload_select = 1'b0; + idcode_select = 1'b0; + mbist_select = 1'b0; + debug_select = 1'b0; + bypass_select = 1'b0; + + case(latched_jtag_ir) /* synthesis parallel_case */ + `EXTEST: extest_select = 1'b1; // External test + `SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload + `IDCODE: idcode_select = 1'b1; // ID Code + `MBIST: mbist_select = 1'b1; // Mbist test + `DEBUG: debug_select = 1'b1; // Debug + `BYPASS: bypass_select = 1'b1; // BYPASS + default: bypass_select = 1'b1; // BYPASS + endcase +end + + +/********************************************************************************** +* * +* Multiplexing TDO data * +* * +**********************************************************************************/ +reg tdo_mux_out; // really just a wire + +always @ (shift_ir or instruction_tdo or latched_jtag_ir or idcode_tdo or + debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or bypassed_tdo or + bs_chain_tdi_i) +begin + if(shift_ir) + tdo_mux_out = instruction_tdo; + else + begin + case(latched_jtag_ir) // synthesis parallel_case + `IDCODE: tdo_mux_out = idcode_tdo; // Reading ID code + `DEBUG: tdo_mux_out = debug_tdi_i; // Debug + `SAMPLE_PRELOAD: tdo_mux_out = bs_chain_tdi_i; // Sampling/Preloading + `EXTEST: tdo_mux_out = bs_chain_tdi_i; // External test + `MBIST: tdo_mux_out = mbist_tdi_i; // Mbist test + default: tdo_mux_out = bypassed_tdo; // BYPASS instruction + endcase + end +end + + +// TDO changes state at negative edge of TCK +always @ (negedge tck_pad_i) +begin + tdo_pad_o = tdo_mux_out; +end + + +// Tristate control for tdo_pad_o pin +always @ (posedge tck_pad_i) +begin + tdo_padoe_o <= #1 shift_ir | shift_dr; +end +/********************************************************************************** +* * +* End: Multiplexing TDO data * +* * +**********************************************************************************/ + +endmodule Index: jtag/tap/doc/src/oc_jtag_sys_diag.odg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: jtag/tap/doc/src/oc_jtag_sys_diag.odg =================================================================== --- jtag/tap/doc/src/oc_jtag_sys_diag.odg (nonexistent) +++ jtag/tap/doc/src/oc_jtag_sys_diag.odg (revision 3)
jtag/tap/doc/src/oc_jtag_sys_diag.odg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: jtag/tap/doc/src/jtag.odt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: jtag/tap/doc/src/jtag.odt =================================================================== --- jtag/tap/doc/src/jtag.odt (nonexistent) +++ jtag/tap/doc/src/jtag.odt (revision 3)
jtag/tap/doc/src/jtag.odt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: jtag/tap/doc/src/system_block_diagram.odg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: jtag/tap/doc/src/system_block_diagram.odg =================================================================== --- jtag/tap/doc/src/system_block_diagram.odg (nonexistent) +++ jtag/tap/doc/src/system_block_diagram.odg (revision 3)
jtag/tap/doc/src/system_block_diagram.odg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: jtag/tap/doc/gpl-2.0.txt =================================================================== --- jtag/tap/doc/gpl-2.0.txt (nonexistent) +++ jtag/tap/doc/gpl-2.0.txt (revision 3) @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. 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Index: jtag/tap/doc/jtag.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: jtag/tap/doc/jtag.pdf =================================================================== --- jtag/tap/doc/jtag.pdf (nonexistent) +++ jtag/tap/doc/jtag.pdf (revision 3)
jtag/tap/doc/jtag.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: xilinx_internal_jtag/rtl/verilog/xilinx_internal_jtag.v =================================================================== --- xilinx_internal_jtag/rtl/verilog/xilinx_internal_jtag.v (nonexistent) +++ xilinx_internal_jtag/rtl/verilog/xilinx_internal_jtag.v (revision 3) @@ -0,0 +1,433 @@ +/////////////////////////////////////////////////////////////////////// +//// //// +//// xilinx_internal_jtag.v //// +//// //// +//// //// +//// //// +//// Author(s): //// +//// Nathan Yawn (nathan.yawn@opencores.org) //// +//// //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// // +// This file is a wrapper for the various Xilinx internal BSCAN // +// TAP devices. It is designed to take the place of a separate TAP // +// controller in Xilinx systems, to allow a user to access a CPU // +// debug module (such as that of the OR1200) through the FPGA's // +// dedicated JTAG / configuration port. // +// // +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: xilinx_internal_jtag.v,v $ +// Revision 1.2 2009/05/17 20:54:16 Nathan +// Changed email address to opencores.org +// +// Revision 1.1 2008/07/18 20:07:32 Nathan +// Changed the directory structure to match existing projects. +// +// Revision 1.4 2008/07/11 08:26:10 Nathan +// Ran through dos2unix +// +// Revision 1.3 2008/07/11 08:25:52 Nathan +// Added logic to provide CAPTURE_DR signal when necessary, and to provide a TCK while UPDATE_DR is asserted. Note that there is no TCK event between SHIFT_DR and UPDATE_DR, and no TCK event between UPDATE_DR and the next CAPTURE_DR; the Xilinx BSCAN devices do not provide it. Tested successfully with the adv_dbg_if on Virtex-4. +// +// Revision 1.2 2008/06/09 19:34:14 Nathan +// Syntax and functional fixes made after compiling each type of BSCAN module using Xilinx tools. +// +// Revision 1.1 2008/05/22 19:54:07 Nathan +// Initial version +// + + +`include "xilinx_internal_jtag_options.v" + +// Note that the SPARTAN BSCAN controllers have more than one channel. +// This implementation always uses channel 1, this is not configurable. +// If you want to use another channel, then it is probably because you +// want to attach multiple devices to the BSCAN device, which means +// you'll be making changes to this file anyway. +// Virtex BSCAN devices are instantiated separately for each channel. +// To select something other than the default (1), change the parameter +// "virtex_jtag_chain". + + +module xilinx_internal_jtag ( + tck_o, + debug_tdi_i, + tdo_o, + test_logic_reset_o, + run_test_idle_o, + shift_dr_o, + capture_dr_o, + pause_dr_o, + update_dr_o, + debug_select_o +); + +// May be 1, 2, 3, or 4 +// Only used for Virtex 4/5 devices +parameter virtex_jtag_chain = 1; + +input debug_tdi_i; +output tck_o; +output tdo_o; +output test_logic_reset_o; +output run_test_idle_o; +output shift_dr_o; +output capture_dr_o; +output pause_dr_o; +output update_dr_o; +output debug_select_o; + +wire debug_tdi_i; +wire tck_o; +wire drck; +wire tdo_o; +wire test_logic_reset_o; +wire run_test_idle_o; +wire shift_dr_o; +wire pause_dr_o; +wire update_dr_o; +wire debug_select_o; + + + +`ifdef SPARTAN2 + +// Note that this version is missing three outputs. +// It also does not have a real TCK...DRCK1 is only active when USER1 is selected +// AND the TAP is in SHIFT_DR or CAPTURE_DR states...except there's no +// capture_dr output. + +reg capture_dr_o; +wire update_bscan; +reg update_out; + +BSCAN_SPARTAN2 BSCAN_SPARTAN2_inst ( +.DRCK1(drck), // Data register output for USER1 functions +.DRCK2(), // Data register output for USER2 functions +.RESET(test_logic_reset_o), // Reset output from TAP controller +.SEL1(debug_select_o), // USER1 active output +.SEL2(), // USER2 active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TDI(tdo_o), // TDI output from TAP controller +.UPDATE(update_bscan), // UPDATE output from TAP controller +.TDO1(debug_tdi_i), // Data input for USER1 function +.TDO2( 1'b0 ) // Data input for USER2 function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; +assign capture_dr_o = 1'b0; + +// We get one TCK during capture_dr state (low,high,SHIFT goes high on next DRCK high) +// On that negative edge, set capture_dr, and it will get registered on the rising +// edge. +always @ (negedge tck_o) +begin + if(debug_select_o && !shift_dr_o) + capture_dr_o <= 1'b1; + else + capture_dr_o <= 1'b0; +end + +// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered +// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block). +// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module. +assign tck_o = (drck & debug_select_o & !update_bscan); + +// This will hold the update_dr output so it can be registered on the rising edge +// of the clock created above. +always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o) +begin + if(update_bscan) update_out <= 1'b1; + else if(capture_dr_o) update_out <= 1'b0; + else if(!debug_select_o) update_out <= 1'b0; +end + +assign update_dr_o = update_out; + +`else +`ifdef SPARTAN3 +// Note that this version is missing two outputs. +// It also does not have a real TCK...DRCK1 is only active when USER1 is selected. + +wire capture_dr_o; +wire update_bscan; +reg update_out; + +BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst ( +.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller +.DRCK1(drck), // Data register output for USER1 functions +.DRCK2(), // Data register output for USER2 functions +.RESET(test_logic_reset_o), // Reset output from TAP controller +.SEL1(debug_select_o), // USER1 active output +.SEL2(), // USER2 active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TDI(tdo_o), // TDI output from TAP controller +.UPDATE(update_bscan), // UPDATE output from TAP controller +.TDO1(debug_tdi_i), // Data input for USER1 function +.TDO2(1'b0) // Data input for USER2 function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; + +// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered +// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block). +// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module. +assign tck_o = (drck & debug_select_o & !update_bscan); + +// This will hold the update_dr output so it can be registered on the rising edge +// of the clock created above. +always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o) +begin + if(update_bscan) update_out <= 1'b1; + else if(capture_dr_o) update_out <= 1'b0; + else if(!debug_select_o) update_out <= 1'b0; +end + +assign update_dr_o = update_out; + +`else +`ifdef SPARTAN3A +// Note that this version is missing two outputs. +// At least it has a real TCK. + +wire capture_dr_o; + +BSCAN_SPARTAN3A BSCAN_SPARTAN3A_inst ( +.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller +.DRCK1(), // Data register output for USER1 functions +.DRCK2(), // Data register output for USER2 functions +.RESET(test_logic_reset_o), // Reset output from TAP controller +.SEL1(debug_select_o), // USER1 active output +.SEL2(), // USER2 active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TCK(tck_o), // TCK output from TAP controller +.TDI(tdo_o), // TDI output from TAP controller +.TMS(), // TMS output from TAP controller +.UPDATE(update_dr_o), // UPDATE output from TAP controller +.TDO1(debug_tdi_i), // Data input for USER1 function +.TDO2( 1'b0) // Data input for USER2 function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; + +`else +`ifdef VIRTEX + +// Note that this version is missing three outputs. +// It also does not have a real TCK...DRCK1 is only active when USER1 is selected. + +reg capture_dr_o; +wire update_bscan; +reg update_out; + +BSCAN_VIRTEX BSCAN_VIRTEX_inst ( +.DRCK1(drck), // Data register output for USER1 functions +.DRCK2(), // Data register output for USER2 functions +.RESET(test_logic_reset_o), // Reset output from TAP controller +.SEL1(debug_select_o), // USER1 active output +.SEL2(), // USER2 active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TDI(tdo_o), // TDI output from TAP controller +.UPDATE(update_bscan), // UPDATE output from TAP controller +.TDO1(debug_tdi_i), // Data input for USER1 function +.TDO2( 1'b0) // Data input for USER2 function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; + +// We get one TCK during capture_dr state (low,high,SHIFT goes high on next DRCK low) +// On that negative edge, set capture_dr, and it will get registered on the rising +// edge, then de-asserted on the same edge that SHIFT goes high. +always @ (negedge tck_o) +begin + if(debug_select_o && !shift_dr_o) + capture_dr_o <= 1'b1; + else + capture_dr_o <= 1'b0; +end + +// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered +// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block). +// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module. +assign tck_o = (drck & debug_select_o & !update_bscan); + +// This will hold the update_dr output so it can be registered on the rising edge +// of the clock created above. +always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o) +begin + if(update_bscan) update_out <= 1'b1; + else if(capture_dr_o) update_out <= 1'b0; + else if(!debug_select_o) update_out <= 1'b0; +end + +assign update_dr_o = update_out; + +`else +`ifdef VIRTEX2 + +// Note that this version is missing two outputs. +// It also does not have a real TCK...DRCK1 is only active when USER1 is selected. + +wire capture_dr_o; +wire update_bscan; +reg update_out; + +BSCAN_VIRTEX2 BSCAN_VIRTEX2_inst ( +.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller +.DRCK1(drck), // Data register output for USER1 functions +.DRCK2(), // Data register output for USER2 functions +.RESET(test_logic_reset_o), // Reset output from TAP controller +.SEL1(debug_select_o), // USER1 active output +.SEL2(), // USER2 active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TDI(tdo_o), // TDI output from TAP controller +.UPDATE(update_bscan), // UPDATE output from TAP controller +.TDO1(debug_tdi_i), // Data input for USER1 function +.TDO2( 1'b0 ) // Data input for USER2 function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; + +// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered +// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block). +// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module. +assign tck_o = (drck & debug_select_o & !update_bscan); + +// This will hold the update_dr output so it can be registered on the rising edge +// of the clock created above. +always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o) +begin + if(update_bscan) update_out <= 1'b1; + else if(capture_dr_o) update_out <= 1'b0; + else if(!debug_select_o) update_out <= 1'b0; +end + +assign update_dr_o = update_out; + +`else +`ifdef VIRTEX4 +// Note that this version is missing two outputs. +// It also does not have a real TCK...DRCK is only active when USERn is selected. + +wire capture_dr_o; +wire update_bscan; +reg update_out; + +BSCAN_VIRTEX4 #( +.JTAG_CHAIN(virtex_jtag_chain) +) BSCAN_VIRTEX4_inst ( +.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller +.DRCK(drck), // Data register output for USER function +.RESET(test_logic_reset_o), // Reset output from TAP controller +.SEL(debug_select_o), // USER active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TDI(tdo_o), // TDI output from TAP controller +.UPDATE(update_bscan), // UPDATE output from TAP controller +.TDO( debug_tdi_i ) // Data input for USER function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; + +// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered +// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block). +// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module. +assign tck_o = (drck & debug_select_o & !update_bscan); + +// This will hold the update_dr output so it can be registered on the rising edge +// of the clock created above. +always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o) +begin + if(update_bscan) update_out <= 1'b1; + else if(capture_dr_o) update_out <= 1'b0; + else if(!debug_select_o) update_out <= 1'b0; +end + +assign update_dr_o = update_out; + +`else +`ifdef VIRTEX5 +// Note that this version is missing two outputs. +// It also does not have a real TCK...DRCK is only active when USERn is selected. + +wire capture_dr_o; +wire update_bscan; +reg update_out; + +BSCAN_VIRTEX5 #( +.JTAG_CHAIN(virtex_jtag_chain) +) BSCAN_VIRTEX5_inst ( +.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller +.DRCK(drck), // Data register output for USER function +.RESET(test_logic_reset), // Reset output from TAP controller +.SEL(debug_select_o), // USER active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TDI(tdo_o), // TDI output from TAP controller +.UPDATE(update_bscan), // UPDATE output from TAP controller +.TDO(debug_tdi_i) // Data input for USER function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; + +// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered +// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block). +// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module. +assign tck_o = (drck & debug_select_o & !update_bscan); + +// This will hold the update_dr output so it can be registered on the rising edge +// of the clock created above. +always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o) +begin + if(update_bscan) update_out <= 1'b1; + else if(capture_dr_o) update_out <= 1'b0; + else if(!debug_select_o) update_out <= 1'b0; +end + +assign update_dr_o = update_out; + + +`endif +`endif +`endif +`endif +`endif +`endif +`endif + +endmodule \ No newline at end of file Index: xilinx_internal_jtag/rtl/verilog/xilinx_internal_jtag_options.v =================================================================== --- xilinx_internal_jtag/rtl/verilog/xilinx_internal_jtag_options.v (nonexistent) +++ xilinx_internal_jtag/rtl/verilog/xilinx_internal_jtag_options.v (revision 3) @@ -0,0 +1,12 @@ + + +// Xilinx has a different HDL entity for the internal JTAG in each of these. +// How thoughtful. + +//`define SPARTAN2 +//`define SPARTAN3 // This is also used for SPARTAN 3E devices +//`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 // Also used for the VIRTEX 2P +`define VIRTEX4 +//`define VIRTEX5 \ No newline at end of file Index: xilinx_internal_jtag/doc/License_FDL-1.2.txt =================================================================== --- xilinx_internal_jtag/doc/License_FDL-1.2.txt (nonexistent) +++ xilinx_internal_jtag/doc/License_FDL-1.2.txt (revision 3) @@ -0,0 +1,397 @@ + GNU Free Documentation License + Version 1.2, November 2002 + + + Copyright (C) 2000,2001,2002 Free Software Foundation, Inc. + 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + +0. 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TRANSLATION + +Translation is considered a kind of modification, so you may +distribute translations of the Document under the terms of section 4. +Replacing Invariant Sections with translations requires special +permission from their copyright holders, but you may include +translations of some or all Invariant Sections in addition to the +original versions of these Invariant Sections. You may include a +translation of this License, and all the license notices in the +Document, and any Warranty Disclaimers, provided that you also include +the original English version of this License and the original versions +of those notices and disclaimers. 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Index: xilinx_internal_jtag/doc/xilinx_internal_jtag.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: xilinx_internal_jtag/doc/xilinx_internal_jtag.pdf =================================================================== --- xilinx_internal_jtag/doc/xilinx_internal_jtag.pdf (nonexistent) +++ xilinx_internal_jtag/doc/xilinx_internal_jtag.pdf (revision 3)
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xilinx_internal_jtag/doc/src/xilinx_internal_jtag.odt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: xilinx_internal_jtag/doc/gpl-2.0.txt =================================================================== --- xilinx_internal_jtag/doc/gpl-2.0.txt (nonexistent) +++ xilinx_internal_jtag/doc/gpl-2.0.txt (revision 3) @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Lesser General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +this service if you wish), that you receive source code or can get it +if you want it, that you can change the software or use pieces of it +in new free programs; and that you know you can do these things. + + To protect your rights, we need to make restrictions that forbid +anyone to deny you these rights or to ask you to surrender the rights. +These restrictions translate to certain responsibilities for you if you +distribute copies of the software, or if you modify it. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must give the recipients all the rights that +you have. You must make sure that they, too, receive or can get the +source code. And you must show them these terms so they know their +rights. + + We protect your rights with two steps: (1) copyright the software, and +(2) offer you this license which gives you legal permission to copy, +distribute and/or modify the software. + + Also, for each author's protection and ours, we want to make certain +that everyone understands that there is no warranty for this free +software. If the software is modified by someone else and passed on, we +want its recipients to know that what they have is not the original, so +that any problems introduced by others will not reflect on the original +authors' reputations. + + Finally, any free program is threatened constantly by software +patents. We wish to avoid the danger that redistributors of a free +program will individually obtain patent licenses, in effect making the +program proprietary. To prevent this, we have made it clear that any +patent must be licensed for everyone's free use or not licensed at all. + + The precise terms and conditions for copying, distribution and +modification follow. + + GNU GENERAL PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + 0. This License applies to any program or other work which contains +a notice placed by the copyright holder saying it may be distributed +under the terms of this General Public License. The "Program", below, +refers to any such program or work, and a "work based on the Program" +means either the Program or any derivative work under copyright law: +that is to say, a work containing the Program or a portion of it, +either verbatim or with modifications and/or translated into another +language. (Hereinafter, translation is included without limitation in +the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running the Program is not restricted, and the output from the Program +is covered only if its contents constitute a work based on the +Program (independent of having been made by running the Program). +Whether that is true depends on what the Program does. + + 1. You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. + +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. + + 2. You may modify your copy or copies of the Program or any portion +of it, thus forming a work based on the Program, and copy and +distribute such modifications or work under the terms of Section 1 +above, provided that you also meet all of these conditions: + + a) You must cause the modified files to carry prominent notices + stating that you changed the files and the date of any change. + + b) You must cause any work that you distribute or publish, that in + whole or in part contains or is derived from the Program or any + part thereof, to be licensed as a whole at no charge to all third + parties under the terms of this License. + + c) If the modified program normally reads commands interactively + when run, you must cause it, when started running for such + interactive use in the most ordinary way, to print or display an + announcement including an appropriate copyright notice and a + notice that there is no warranty (or else, saying that you provide + a warranty) and that users may redistribute the program under + these conditions, and telling the user how to view a copy of this + License. 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But when you +distribute the same sections as part of a whole which is a work based +on the Program, the distribution of the whole must be on the terms of +this License, whose permissions for other licensees extend to the +entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest +your rights to work written entirely by you; rather, the intent is to +exercise the right to control the distribution of derivative or +collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program +with the Program (or with a work based on the Program) on a volume of +a storage or distribution medium does not bring the other work under +the scope of this License. + + 3. You may copy and distribute the Program (or a work based on it, +under Section 2) in object code or executable form under the terms of +Sections 1 and 2 above provided that you also do one of the following: + + a) Accompany it with the complete corresponding machine-readable + source code, which must be distributed under the terms of Sections + 1 and 2 above on a medium customarily used for software interchange; or, + + b) Accompany it with a written offer, valid for at least three + years, to give any third party, for a charge no more than your + cost of physically performing source distribution, a complete + machine-readable copy of the corresponding source code, to be + distributed under the terms of Sections 1 and 2 above on a medium + customarily used for software interchange; or, + + c) Accompany it with the information you received as to the offer + to distribute corresponding source code. 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Any attempt +otherwise to copy, modify, sublicense or distribute the Program is +void, and will automatically terminate your rights under this License. +However, parties who have received copies, or rights, from you under +this License will not have their licenses terminated so long as such +parties remain in full compliance. + + 5. You are not required to accept this License, since you have not +signed it. However, nothing else grants you permission to modify or +distribute the Program or its derivative works. These actions are +prohibited by law if you do not accept this License. Therefore, by +modifying or distributing the Program (or any work based on the +Program), you indicate your acceptance of this License to do so, and +all its terms and conditions for copying, distributing or modifying +the Program or works based on it. + + 6. Each time you redistribute the Program (or any work based on the +Program), the recipient automatically receives a license from the +original licensor to copy, distribute or modify the Program subject to +these terms and conditions. You may not impose any further +restrictions on the recipients' exercise of the rights granted herein. +You are not responsible for enforcing compliance by third parties to +this License. + + 7. If, as a consequence of a court judgment or allegation of patent +infringement or for any other reason (not limited to patent issues), +conditions are imposed on you (whether by court order, agreement or +otherwise) that contradict the conditions of this License, they do not +excuse you from the conditions of this License. If you cannot +distribute so as to satisfy simultaneously your obligations under this +License and any other pertinent obligations, then as a consequence you +may not distribute the Program at all. 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The Free Software Foundation may publish revised and/or new versions +of the General Public License from time to time. Such new versions will +be similar in spirit to the present version, but may differ in detail to +address new problems or concerns. + +Each version is given a distinguishing version number. If the Program +specifies a version number of this License which applies to it and "any +later version", you have the option of following the terms and conditions +either of that version or of any later version published by the Free +Software Foundation. If the Program does not specify a version number of +this License, you may choose any version ever published by the Free Software +Foundation. + + 10. If you wish to incorporate parts of the Program into other free +programs whose distribution conditions are different, write to the author +to ask for permission. For software which is copyrighted by the Free +Software Foundation, write to the Free Software Foundation; we sometimes +make exceptions for this. Our decision will be guided by the two goals +of preserving the free status of all derivatives of our free software and +of promoting the sharing and reuse of software generally. + + NO WARRANTY + + 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + + 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License.

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