URL
https://opencores.org/ocsvn/aemb/aemb/trunk
Subversion Repositories aemb
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- This comparison shows the changes necessary to convert path
/aemb/trunk/rtl/verilog
- from Rev 206 to Rev 207
- ↔ Reverse comparison
Rev 206 → Rev 207
/aeMB2_edk63.v
250,6 → 250,9
.rpc_if (rpc_if[31:2]), |
.alu_ex (alu_ex[31:0]), |
.ich_dat (ich_dat[31:0]), |
.exc_dwb (exc_dwb[1:0]), |
.exc_ill (exc_ill), |
.exc_iwb (exc_iwb), |
.gclk (gclk), |
.grst (grst), |
.dena (dena), |
/aeMB2_ctrl.v
33,7 → 33,7
mux_of, mux_ex, hzd_bpc, hzd_fwd, |
// Inputs |
opa_if, opb_if, opd_if, brk_if, bra_ex, rpc_if, alu_ex, ich_dat, |
gclk, grst, dena, iena, gpha |
exc_dwb, exc_ill, exc_iwb, gclk, grst, dena, iena, gpha |
); |
parameter AEMB_HTX = 1; |
|
63,6 → 63,10
input [31:2] rpc_if; |
input [31:0] alu_ex; |
input [31:0] ich_dat; |
|
input [1:0] exc_dwb; |
input exc_ill; |
input exc_iwb; |
|
output hzd_bpc; |
output hzd_fwd; |
196,8 → 200,9
end |
|
assign fINT = brk_if[0] & gpha & !rFIM1; |
assign fXCE = brk_if[1]; |
// & ((gpha & !rFIM1) | (!gpha & rFIM0)); |
//assign fXCE = brk_if[1]; |
assign fXCE = |{exc_ill, exc_iwb, exc_dwb}; |
// & ((gpha & !rFIM1) | (!gpha & rFIM0)); |
|
// operand latch |
reg wrb_ex; |