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https://opencores.org/ocsvn/aemb/aemb/trunk
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- This comparison shows the changes necessary to convert path
/aemb/trunk/rtl
- from Rev 203 to Rev 204
- ↔ Reverse comparison
Rev 203 → Rev 204
/verilog/aeMB2_intu.v
52,7 → 52,7
input [15:0] imm_of; |
input [4:0] rd_of, |
ra_of; |
output [7:0] msr_ex; |
output [9:0] msr_ex; |
output [31:0] sfr_mx; |
|
// SYS signals |
80,6 → 80,8
MUX_NOP = 3'o0; |
|
reg rMSR_C, |
rMSR_EE, |
rMSR_EIP, |
rMSR_CC, |
rMSR_MTX, |
rMSR_DTE, |
181,6 → 183,8
*/ |
|
assign msr_ex = { |
rMSR_EIP, |
rMSR_EE, |
rMSR_DTE, |
1'b0, |
rMSR_ITE, |
192,19 → 196,26
}; |
|
// MSRSET/MSRCLR (small ALU) |
wire [7:0] wRES = (ra_of[0]) ? |
(msr_ex[7:0]) & ~imm_of[7:0] : // MSRCLR |
(msr_ex[7:0]) | imm_of[7:0]; // MSRSET |
wire [9:0] wRES = (ra_of[0]) ? |
(msr_ex[9:0]) & ~imm_of[9:0] : // MSRCLR |
(msr_ex[9:0]) | imm_of[9:0]; // MSRSET |
|
// 0 - Break |
// 1 - Interrupt |
// 2 - Exception |
// 3 - Reserved |
|
// break |
wire fRTBD = (opc_of == 6'o55) & rd_of[1]; |
wire fBRKB = ((opc_of == 6'o46) | (opc_of == 6'o56)) & (ra_of[4:0] == 5'hC); |
|
// interrupt |
wire fRTID = (opc_of == 6'o55) & rd_of[0]; |
wire fRTBD = (opc_of == 6'o55) & rd_of[1]; |
|
wire fBRKI = (opc_of == 6'o56) & (ra_of[4:0] == 5'hD); |
wire fBRKB = ((opc_of == 6'o46) | (opc_of == 6'o56)) & (ra_of[4:0] == 5'hC); |
|
// exception |
wire fRTED = (opc_of == 6'o55) & rd_of[2]; |
wire fBRKE = (opc_of == 6'o56) & (ra_of[4:0] == 5'hE); |
|
wire fMOV = (opc_of == 6'o45); |
wire fMTS = fMOV & &imm_of[15:14]; |
275,6 → 286,21
(fMTS) ? opa_of[3] : |
(fMOP) ? wRES[3] : |
rMSR_BIP; |
|
rMSR_EE <= #1 |
(fBRKE) ? 1'b0 : |
(fRTED) ? 1'b1 : |
(fMTS) ? opa_of[8] : |
(fMOP) ? wRES[8] : |
rMSR_EE; |
|
rMSR_EIP <= #1 |
(fBRKE) ? 1'b1 : |
(fRTED) ? 1'b0 : |
(fMTS) ? opa_of[9] : |
(fMOP) ? wRES[9] : |
rMSR_EIP; |
|
/* |
|
case ({fMTS, fMOP}) |
357,23 → 383,3
|
endmodule // aeMB2_intu |
|
/* |
$Log: not supported by cvs2svn $ |
Revision 1.6 2008/04/28 08:15:25 sybreon |
Optimisations. |
|
Revision 1.5 2008/04/26 17:57:43 sybreon |
Minor performance improvements. |
|
Revision 1.4 2008/04/26 01:09:06 sybreon |
Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor. |
|
Revision 1.3 2008/04/23 14:18:30 sybreon |
Fixed CMP bug. |
|
Revision 1.2 2008/04/21 12:11:38 sybreon |
Passes arithmetic tests with single thread. |
|
Revision 1.1 2008/04/18 00:21:52 sybreon |
Initial import. |
*/ |
/verilog/aeMB2_pipe.v
31,8 → 31,8
// Outputs |
brk_if, gpha, gclk, grst, dena, iena, |
// Inputs |
bra_ex, dwb_fb, xwb_fb, ich_fb, fet_fb, msr_ex, sys_clk_i, |
sys_int_i, sys_rst_i, sys_ena_i |
bra_ex, dwb_fb, xwb_fb, ich_fb, fet_fb, msr_ex, exc_dwb, exc_iwb, |
exc_ill, sys_clk_i, sys_int_i, sys_rst_i, sys_ena_i |
); |
parameter AEMB_HTX = 1; |
|
42,7 → 42,7
input xwb_fb; |
input ich_fb; |
input fet_fb; |
input [3:0] msr_ex; |
input [9:0] msr_ex; |
|
output gpha, |
gclk, |
49,6 → 49,10
grst, |
dena, |
iena; |
|
input [1:0] exc_dwb; |
input exc_iwb; |
input exc_ill; |
|
input sys_clk_i, |
sys_int_i, |
77,9 → 81,9
// run data side pipeline |
assign dena = iena; |
|
// interrupt process |
// interrupt process - latches onto any interrupt until it is handled |
reg int_lat; ///< interrupt latch |
|
|
always @(posedge sys_clk_i) |
if (sys_rst_i) begin |
/*AUTORESET*/ |
90,6 → 94,10
int_lat <= #1 msr_ex[1] & (int_lat | sys_int_i); |
end |
|
// exception process - exceptions handled immediately |
wire exc_lat; ///< exception latch |
assign exc_lat = exc_ill | exc_dwb[1]; |
|
always @(posedge gclk) |
if (grst) begin |
/*AUTORESET*/ |
97,7 → 105,9
brk_if <= 2'h0; |
// End of automatics |
end else if (dena) begin |
brk_if[0] <= #1 !msr_ex[3] & int_lat; // interrupt & not BIP |
// TODO: consider MSR[9:8] |
brk_if[1] <= #1 exc_lat; // HIGH PRIORITY - exception |
brk_if[0] <= #1 !exc_lat & !msr_ex[9] & !msr_ex[3] & int_lat; // LOW PRIORITY - interrupt (not BIP/EIP) |
end |
|
// RESET DELAY |
124,14 → 134,3
|
endmodule // aeMB2_pipe |
|
/* |
$Log: not supported by cvs2svn $ |
Revision 1.3 2008/04/26 01:09:06 sybreon |
Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor. |
|
Revision 1.2 2008/04/20 16:34:32 sybreon |
Basic version with some features left out. |
|
Revision 1.1 2008/04/18 00:21:52 sybreon |
Initial import. |
*/ |
/verilog/aeMB2_ctrl.v
88,8 → 88,8
reg [4:0] rd_of; |
// End of automatics |
|
wire fINT; |
//wire [31:0] wXCEOP = 32'hBA2D0020; // Vector 0x20 |
wire fINT, fXCE; |
wire [31:0] wXCEOP = 32'hBA2E0020; // Vector 0x20 |
wire [31:0] wINTOP = 32'hB9CD0010; // Vector 0x10 |
//wire [31:0] wNOPOP = 32'h88000000; // branch-no-delay/stall |
|
101,7 → 101,9
wire [15:0] wIMM; |
wire [31:0] imm_if; |
|
assign {wOPC, wRD, wRA, wIMM} = (fINT) ? wINTOP : ich_dat; |
assign {wOPC, wRD, wRA, wIMM} = (fXCE) ? wXCEOP : |
(fINT) ? wINTOP : |
ich_dat; |
assign wRB = wIMM[15:11]; |
|
// decode main opgroups |
194,6 → 196,7
end |
|
assign fINT = brk_if[0] & gpha & !rFIM1; |
assign fXCE = brk_if[1] & !rFIM1; |
|
// operand latch |
reg wrb_ex; |
279,24 → 282,3
assign hzd_bpc = (bra_ex[1] & !bra_ex[0]); |
|
endmodule // aeMB2_ctrl |
|
/* |
$Log: not supported by cvs2svn $ |
Revision 1.6 2008/05/01 08:32:58 sybreon |
Added interrupt capability. |
|
Revision 1.5 2008/04/28 08:15:25 sybreon |
Optimisations. |
|
Revision 1.4 2008/04/26 17:57:43 sybreon |
Minor performance improvements. |
|
Revision 1.3 2008/04/26 01:09:05 sybreon |
Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor. |
|
Revision 1.2 2008/04/20 16:34:32 sybreon |
Basic version with some features left out. |
|
Revision 1.1 2008/04/18 00:21:52 sybreon |
Initial import. |
*/ |