OpenCores
URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /aemb/trunk/sim/verilog
    from Rev 164 to Rev 191
    ↔ Reverse comparison
  •

Rev 164 → Rev 191

/edk62.v
0,0 → 1,278
/* $Id: edk62.v,v 1.4 2008-05-30 14:02:59 sybreon Exp $
**
** AEMB2 EDK 6.2 COMPATIBLE CORE
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
**
** This file is part of AEMB.
**
** AEMB is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
*/
 
/**
Simulation Test Bench
@file edk62.v
*/
 
`include "random.v"
module edk62();
localparam AEMB_DWB = 18;
localparam AEMB_XWB = 5;
localparam AEMB_IWB = 18;
localparam AEMB_ICH = 11;
localparam AEMB_IDX = 6;
localparam AEMB_HTX = 1;
localparam AEMB_BSF = 1;
localparam AEMB_MUL = 1;
localparam AEMB_XSL = 1;
localparam AEMB_DIV = 0;
localparam AEMB_FPU = 0;
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg dwb_ack_i; // To uut of aeMB2_edk62.v
reg iwb_ack_i; // To uut of aeMB2_edk62.v
reg sys_clk_i; // To uut of aeMB2_edk62.v
reg sys_ena_i; // To uut of aeMB2_edk62.v
reg sys_int_i; // To uut of aeMB2_edk62.v
reg sys_rst_i; // To uut of aeMB2_edk62.v
reg xwb_ack_i; // To uut of aeMB2_edk62.v
// End of automatics
 
always #5 sys_clk_i <= !sys_clk_i;
initial begin
`ifdef VCD_DUMP
$dumpfile ("dump.vcd");
$dumpvars (1,uut);
`endif
sys_clk_i = $random(`randseed);
sys_rst_i = 1;
sys_ena_i = 1;
sys_int_i = 1;
xwb_ack_i = 0;
#50 sys_rst_i = 0;
#4000000 $displayh("\n*** TIMEOUT ", $stime, " ***"); $finish;
end // initial begin
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [AEMB_DWB-1:2] dwb_adr_o; // From uut of aeMB2_edk62.v
wire dwb_cyc_o; // From uut of aeMB2_edk62.v
wire [31:0] dwb_dat_o; // From uut of aeMB2_edk62.v
wire [3:0] dwb_sel_o; // From uut of aeMB2_edk62.v
wire dwb_stb_o; // From uut of aeMB2_edk62.v
wire dwb_tag_o; // From uut of aeMB2_edk62.v
wire dwb_wre_o; // From uut of aeMB2_edk62.v
wire [AEMB_IWB-1:2] iwb_adr_o; // From uut of aeMB2_edk62.v
wire iwb_cyc_o; // From uut of aeMB2_edk62.v
wire [3:0] iwb_sel_o; // From uut of aeMB2_edk62.v
wire iwb_stb_o; // From uut of aeMB2_edk62.v
wire iwb_tag_o; // From uut of aeMB2_edk62.v
wire iwb_wre_o; // From uut of aeMB2_edk62.v
wire [AEMB_XWB-1:2] xwb_adr_o; // From uut of aeMB2_edk62.v
wire xwb_cyc_o; // From uut of aeMB2_edk62.v
wire [31:0] xwb_dat_o; // From uut of aeMB2_edk62.v
wire [3:0] xwb_sel_o; // From uut of aeMB2_edk62.v
wire xwb_stb_o; // From uut of aeMB2_edk62.v
wire xwb_tag_o; // From uut of aeMB2_edk62.v
wire xwb_wre_o; // From uut of aeMB2_edk62.v
// End of automatics
 
// FAKE MEMORY ////////////////////////////////////////////////////////
 
reg [31:0] rom[0:65535];
reg [31:0] ram[0:65535];
reg [31:0] dwblat;
reg [31:0] xwblat;
reg [31:2] dadr, iadr;
wire [31:0] dwb_dat_t = ram[dwb_adr_o];
wire [31:0] iwb_dat_i = rom[iadr];
wire [31:0] dwb_dat_i = ram[dadr];
wire [31:0] xwb_dat_i = xwblat;
always @(posedge sys_clk_i)
if (sys_rst_i) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
dwb_ack_i <= 1'h0;
iwb_ack_i <= 1'h0;
xwb_ack_i <= 1'h0;
// End of automatics
end else begin
iwb_ack_i <= #1 iwb_stb_o & !iwb_ack_i;
dwb_ack_i <= #1 dwb_stb_o & !dwb_ack_i;
xwb_ack_i <= #1 xwb_stb_o & !xwb_ack_i;
end // else: !if(sys_rst_i)
always @(posedge sys_clk_i) begin
iadr <= #1 iwb_adr_o;
dadr <= #1 dwb_adr_o;
 
if (xwb_wre_o & xwb_stb_o & xwb_ack_i) begin
xwblat <= #1 xwb_dat_o;
end
// SPECIAL PORTS
if (dwb_wre_o & dwb_stb_o & dwb_ack_i) begin
case ({dwb_adr_o,2'o0})
32'hFFFFFFD0: $displayh(dwb_dat_o);
32'hFFFFFFC0: $write("%c",dwb_dat_o[31:24]);
32'hFFFFFFE0: sys_int_i <= #1 !sys_int_i;
endcase // case ({dwb_adr_o,2'o0})
case (dwb_sel_o)
4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
default: begin
$displayh("\n*** INVALID WRITE ",{dwb_adr_o,2'o0}, " ***");
$finish;
end
endcase // case (dwb_sel_o)
end // if (dwb_wre_o & dwb_stb_o & dwb_ack_i)
 
if (dwb_stb_o & !dwb_wre_o & dwb_ack_i) begin
case (dwb_sel_o)
4'h1,4'h2,4'h4,4'h8,4'h3,4'hC,4'hF: begin
end
default: begin
$displayh("\n*** INVALID READ ",{dwb_adr_o,2'd0}, " ***");
$finish;
end
endcase // case (dwb_sel_o)
end
end // always @ (posedge sys_clk_i)
integer i;
initial begin
for (i=0;i<65535;i=i+1) begin
ram[i] <= $random;
end
#1 $readmemh("dump.vmem",rom);
#1 $readmemh("dump.vmem",ram);
end
 
// DUMP CYCLES
always @(posedge sys_clk_i)
if (uut.dena) begin
//begin
`ifdef AEMB2_SIM_KERNEL
$displayh("TME=",($stime/10),
",PHA=",uut.gpha,
",IWB=",{uut.rpc_if,2'o0},
",ASM=",uut.ich_dat,
",OPA=",uut.opa_of,
",OPB=",uut.opb_of,
",OPD=",uut.opd_of,
",MSR=",uut.msr_ex,
",MEM=",{uut.mem_ex,2'o0},
",BRA=",uut.bra_ex,
",BPC=",{uut.bpc_ex,2'o0},
",MUX=",uut.mux_ex,
",ALU=",uut.alu_mx,
//",WRE=",dwb_wre_o,
",SEL=",dwb_sel_o,
//",DWB=",dwb_dat_o,
",REG=",uut.regs0.gprf0.wRW0,
//",DAT=",uut.regs0.gprf0.regd,
",MUL=",uut.mul_mx,
",BSF=",uut.bsf_mx,
",DWB=",uut.dwb_mx,
",LNK=",{uut.rpc_mx,2'o0},
",SFR=",uut.sfr_mx,
",E"
);
`endif
if (uut.ich_dat == 32'hB8000000) begin
$displayh("\n*** EXIT ", $stime, " ***");
$finish;
end
end // if (uut.dena)
aeMB2_edk62
#(/*AUTOINSTPARAM*/
// Parameters
.AEMB_IWB (AEMB_IWB),
.AEMB_DWB (AEMB_DWB),
.AEMB_XWB (AEMB_XWB),
.AEMB_ICH (AEMB_ICH),
.AEMB_IDX (AEMB_IDX),
.AEMB_BSF (AEMB_BSF),
.AEMB_MUL (AEMB_MUL),
.AEMB_DIV (AEMB_DIV),
.AEMB_FPU (AEMB_FPU))
uut
(/*AUTOINST*/
// Outputs
.dwb_adr_o (dwb_adr_o[AEMB_DWB-1:2]),
.dwb_cyc_o (dwb_cyc_o),
.dwb_dat_o (dwb_dat_o[31:0]),
.dwb_sel_o (dwb_sel_o[3:0]),
.dwb_stb_o (dwb_stb_o),
.dwb_tag_o (dwb_tag_o),
.dwb_wre_o (dwb_wre_o),
.iwb_adr_o (iwb_adr_o[AEMB_IWB-1:2]),
.iwb_cyc_o (iwb_cyc_o),
.iwb_sel_o (iwb_sel_o[3:0]),
.iwb_stb_o (iwb_stb_o),
.iwb_tag_o (iwb_tag_o),
.iwb_wre_o (iwb_wre_o),
.xwb_adr_o (xwb_adr_o[AEMB_XWB-1:2]),
.xwb_cyc_o (xwb_cyc_o),
.xwb_dat_o (xwb_dat_o[31:0]),
.xwb_sel_o (xwb_sel_o[3:0]),
.xwb_stb_o (xwb_stb_o),
.xwb_tag_o (xwb_tag_o),
.xwb_wre_o (xwb_wre_o),
// Inputs
.dwb_ack_i (dwb_ack_i),
.dwb_dat_i (dwb_dat_i[31:0]),
.iwb_ack_i (iwb_ack_i),
.iwb_dat_i (iwb_dat_i[31:0]),
.sys_clk_i (sys_clk_i),
.sys_ena_i (sys_ena_i),
.sys_int_i (sys_int_i),
.sys_rst_i (sys_rst_i),
.xwb_ack_i (xwb_ack_i),
.xwb_dat_i (xwb_dat_i[31:0]));
 
endmodule // edk62
 
// $Log: not supported by cvs2svn $
// Revision 1.3 2008/05/01 08:33:20 sybreon
// Added interrupt capability.
//
// Revision 1.2 2008/04/27 16:28:19 sybreon
// Fixed minor typos.
//
// Revision 1.1 2008/04/26 18:09:16 sybreon
// initial import
//
 
// Local Variables:
// verilog-library-directories:("." "../../rtl/verilog/")
// verilog-library-files:("")
// End:
/edk32.v
0,0 → 1,279
/* $Id: edk32.v,v 1.13 2008-05-30 14:02:49 sybreon Exp $
**
** AEMB EDK 3.2 Compatible Core TEST
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
**
** This file is part of AEMB.
**
** AEMB is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
*/
 
`include "random.v"
module edk32 ();
 
// INITIAL SETUP //////////////////////////////////////////////////////
reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
reg svc;
integer inttime;
integer seed;
integer theend;
always #5 sys_clk_i = ~sys_clk_i;
 
initial begin
`ifdef VCD_DUMP
$dumpfile("dump.vcd");
$dumpvars(1,dut);
`endif
//seed = `randseed;
theend = 0;
svc = 0;
sys_clk_i = $random(`randseed);
sys_rst_i = 1;
sys_int_i = 0;
sys_exc_i = 0;
#50 sys_rst_i = 0;
#40000000 $displayh("\n*** TIMEOUT ",$stime," ***"); $finish;
end
// FAKE MEMORY ////////////////////////////////////////////////////////
 
wire fsl_stb_o;
wire fsl_wre_o;
wire [31:0] fsl_dat_o;
wire [31:0] fsl_dat_i;
wire [6:2] fsl_adr_o;
wire [15:2] iwb_adr_o;
wire iwb_stb_o;
wire dwb_stb_o;
reg [31:0] rom [0:65535];
wire [31:0] iwb_dat_i;
reg iwb_ack_i, dwb_ack_i, fsl_ack_i;
 
reg [31:0] ram[0:65535];
wire [31:0] dwb_dat_i;
reg [31:0] dwblat;
wire dwb_we_o;
reg [15:2] dadr,iadr;
wire [3:0] dwb_sel_o;
wire [31:0] dwb_dat_o;
wire [15:2] dwb_adr_o;
wire [31:0] dwb_dat_t;
 
initial begin
dwb_ack_i = 0;
iwb_ack_i = 0;
fsl_ack_i = 0;
end
assign dwb_dat_t = ram[dwb_adr_o];
assign iwb_dat_i = ram[iadr];
assign dwb_dat_i = ram[dadr];
assign fsl_dat_i = fsl_adr_o;
 
`ifdef POSEDGE
always @(posedge sys_clk_i)
if (sys_rst_i) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
dwb_ack_i <= 1'h0;
fsl_ack_i <= 1'h0;
iwb_ack_i <= 1'h0;
// End of automatics
end else begin
iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i;
dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i;
fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i;
end // else: !if(sys_rst_i)
always @(posedge sys_clk_i) begin
iadr <= #1 iwb_adr_o;
dadr <= #1 dwb_adr_o;
if (dwb_we_o & dwb_stb_o) begin
case (dwb_sel_o)
4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
endcase // case (dwb_sel_o)
end // if (dwb_we_o & dwb_stb_o)
end // always @ (posedge sys_clk_i)
 
`else // !`ifdef POSEDGE
always @(negedge sys_clk_i)
if (sys_rst_i) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
dwb_ack_i <= 1'h0;
fsl_ack_i <= 1'h0;
iwb_ack_i <= 1'h0;
// End of automatics
end else begin
iwb_ack_i <= #1 iwb_stb_o;
dwb_ack_i <= #1 dwb_stb_o;
fsl_ack_i <= #1 fsl_stb_o;
end // else: !if(sys_rst_i)
always @(negedge sys_clk_i) begin
iadr <= #1 iwb_adr_o;
dadr <= #1 dwb_adr_o;
if (dwb_we_o & dwb_stb_o) begin
case (dwb_sel_o)
4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
endcase // case (dwb_sel_o)
end // if (dwb_we_o & dwb_stb_o)
end // always @ (negedge sys_clk_i)
`endif // !`ifdef POSEDGE
 
integer i;
initial begin
for (i=0;i<65535;i=i+1) begin
ram[i] <= $random;
end
#1 $readmemh("dump.vmem",ram);
end
 
// DISPLAY OUTPUTS ///////////////////////////////////////////////////
 
integer rnd;
always @(posedge sys_clk_i) begin
 
// Interrupt Monitors
if (!dut.cpu.rMSR_IE) begin
rnd = $random % 30;
inttime = $stime + 1000 + (rnd*rnd * 10);
end
if ($stime > inttime) begin
sys_int_i = 1;
svc = 0;
end
if (($stime > inttime + 500) && !svc) begin
$display("\n\t*** INTERRUPT TIMEOUT ***", inttime);
$finish;
end
if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;
if (dut.cpu.regf.fRDWE && (dut.cpu.rRD == 5'h0e) && !svc && dut.cpu.gena) begin
svc = 1;
//$display("\nLATENCY: ", ($stime - inttime)/10);
end
// Pass/Fail Monitors
if (dwb_we_o & (dwb_dat_o == "FAIL")) begin
$display("\n\tFAIL");
$finish;
end
if (iwb_dat_i == 32'hb8000000) begin
theend = theend + 1;
end
 
if (theend == 5) begin
$display("\n\t*** PASSED ALL TESTS ***");
$finish;
end
end // always @ (posedge sys_clk_i)
// INTERNAL WIRING ////////////////////////////////////////////////////
aeMB_sim #(16,16)
dut (
.sys_int_i(sys_int_i),
.dwb_ack_i(dwb_ack_i),
.dwb_stb_o(dwb_stb_o),
.dwb_adr_o(dwb_adr_o),
.dwb_dat_o(dwb_dat_o),
.dwb_dat_i(dwb_dat_i),
.dwb_wre_o(dwb_we_o),
.dwb_sel_o(dwb_sel_o),
 
.fsl_ack_i(fsl_ack_i),
.fsl_stb_o(fsl_stb_o),
.fsl_adr_o(fsl_adr_o),
.fsl_dat_o(fsl_dat_o),
.fsl_dat_i(fsl_dat_i),
.fsl_wre_o(fsl_we_o),
 
.iwb_adr_o(iwb_adr_o),
.iwb_dat_i(iwb_dat_i),
.iwb_stb_o(iwb_stb_o),
.iwb_ack_i(iwb_ack_i),
.sys_clk_i(sys_clk_i),
.sys_rst_i(sys_rst_i)
);
 
endmodule // edk32
 
/*
$Log: not supported by cvs2svn $
Revision 1.12 2007/12/23 20:40:51 sybreon
Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.
 
Revision 1.11 2007/12/11 00:44:31 sybreon
Modified for AEMB2
 
Revision 1.10 2007/11/30 17:08:30 sybreon
Moved simulation kernel into code.
 
Revision 1.9 2007/11/20 18:36:00 sybreon
Removed unnecessary byte acrobatics with VMEM data.
 
Revision 1.8 2007/11/18 19:41:45 sybreon
Minor simulation fixes.
 
Revision 1.7 2007/11/14 22:11:41 sybreon
Added posedge/negedge bus interface.
Modified interrupt test system.
 
Revision 1.6 2007/11/13 23:37:28 sybreon
Updated simulation to also check BRI 0x00 instruction.
 
Revision 1.5 2007/11/09 20:51:53 sybreon
Added GET/PUT support through a FSL bus.
 
Revision 1.4 2007/11/08 14:18:00 sybreon
Parameterised optional components.
 
Revision 1.3 2007/11/05 10:59:31 sybreon
Added random seed for simulation.
 
Revision 1.2 2007/11/02 19:16:10 sybreon
Added interrupt simulation.
Changed "human readable" simulation output.
 
Revision 1.1 2007/11/02 03:25:45 sybreon
New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.
*/
/aemb2.v
0,0 → 1,242
/* $Id: aemb2.v,v 1.3 2007-12-28 21:44:50 sybreon Exp $
**
** AEMB2 TEST BENCH
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
**
** This file is part of AEMB.
**
** AEMB is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
*/
 
module aemb2 ();
parameter IWB=16;
parameter DWB=16;
 
parameter TXE = 0; ///< thread execution enable
parameter MUL = 1; ///< enable hardware multiplier
parameter BSF = 1; ///< enable barrel shifter
parameter FSL = 1; ///< enable FSL bus
parameter DIV = 0; ///< enable hardware divider
`include "random.v"
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [6:2] cwb_adr_o; // From dut of aeMB2_sim.v
wire [31:0] cwb_dat_o; // From dut of aeMB2_sim.v
wire [3:0] cwb_sel_o; // From dut of aeMB2_sim.v
wire cwb_stb_o; // From dut of aeMB2_sim.v
wire [1:0] cwb_tga_o; // From dut of aeMB2_sim.v
wire cwb_wre_o; // From dut of aeMB2_sim.v
wire [DWB-1:2] dwb_adr_o; // From dut of aeMB2_sim.v
wire dwb_cyc_o; // From dut of aeMB2_sim.v
wire [31:0] dwb_dat_o; // From dut of aeMB2_sim.v
wire [3:0] dwb_sel_o; // From dut of aeMB2_sim.v
wire dwb_stb_o; // From dut of aeMB2_sim.v
wire dwb_tga_o; // From dut of aeMB2_sim.v
wire dwb_wre_o; // From dut of aeMB2_sim.v
wire [IWB-1:2] iwb_adr_o; // From dut of aeMB2_sim.v
wire iwb_stb_o; // From dut of aeMB2_sim.v
wire iwb_tga_o; // From dut of aeMB2_sim.v
wire iwb_wre_o; // From dut of aeMB2_sim.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg cwb_ack_i; // To dut of aeMB2_sim.v
reg dwb_ack_i; // To dut of aeMB2_sim.v
reg iwb_ack_i; // To dut of aeMB2_sim.v
reg sys_clk_i; // To dut of aeMB2_sim.v
reg sys_int_i; // To dut of aeMB2_sim.v
reg sys_rst_i; // To dut of aeMB2_sim.v
// End of automatics
// INITIAL SETUP //////////////////////////////////////////////////////
//reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
reg svc;
integer inttime;
integer seed;
integer theend;
always #5 sys_clk_i = ~sys_clk_i;
 
initial begin
//$dumpfile("dump.vcd");
//$dumpvars(1,dut, dut.bpcu);
end
initial begin
seed = randseed;
theend = 0;
svc = 0;
sys_clk_i = $random(seed);
sys_rst_i = 1;
sys_int_i = 0;
#50 sys_rst_i = 0;
#3500000 $finish;
end
// FAKE MEMORY ////////////////////////////////////////////////////////
 
reg [31:0] rom [0:65535];
reg [31:0] ram[0:65535];
reg [31:0] dwblat;
reg [15:2] dadr, iadr;
 
wire [31:0] dwb_dat_t = ram[dwb_adr_o];
wire [31:0] iwb_dat_i = rom[iadr];
wire [31:0] dwb_dat_i = ram[dadr];
wire [31:0] cwb_dat_i = cwb_adr_o;
 
`ifdef POSEDGE
`else // !`ifdef POSEDGE
always @(negedge sys_clk_i)
if (sys_rst_i) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
cwb_ack_i <= 1'h0;
dwb_ack_i <= 1'h0;
iwb_ack_i <= 1'h0;
// End of automatics
end else begin
iwb_ack_i <= #1 iwb_stb_o;
dwb_ack_i <= #1 dwb_stb_o;
cwb_ack_i <= #1 cwb_stb_o;
end // else: !if(sys_rst_i)
always @(negedge sys_clk_i) begin
iadr <= #1 iwb_adr_o;
dadr <= #1 dwb_adr_o;
if (dwb_wre_o & dwb_stb_o) begin
case (dwb_sel_o)
4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
endcase // case (dwb_sel_o)
end // if (dwb_we_o & dwb_stb_o)
end // always @ (negedge sys_clk_i)
`endif // !`ifdef POSEDGE
 
integer i;
initial begin
for (i=0;i<65535;i=i+1) begin
ram[i] <= $random;
end
#1 $readmemh("dump.vmem",rom);
#1 $readmemh("dump.vmem",ram);
end
 
// DISPLAY OUTPUTS ///////////////////////////////////////////////////
 
integer rnd;
always @(posedge sys_clk_i) begin
// Interrupt Monitors
if (!dut.sim.rMSR_IE) begin
rnd = $random % 30;
inttime = $stime + 1000 + (rnd*rnd * 10);
end
if ($stime > inttime) begin
sys_int_i = 1;
svc = 0;
end
if (($stime > inttime + 500) && !svc) begin
$display("\n\t*** INTERRUPT TIMEOUT ***", inttime);
$finish;
end
if (dwb_wre_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;
/*
if (dut.regf.fRDWE && (dut.rRD == 5'h0e) && !svc && dut.gena) begin
svc = 1;
//$display("\nLATENCY: ", ($stime - inttime)/10);
end
*/
// Pass/Fail Monitors
if (dwb_wre_o & (dwb_dat_o == "FAIL")) begin
$display("\n\tFAIL");
$finish;
end
if (iwb_dat_i == 32'hb8000000) begin
theend = theend + 1;
end
 
if (theend == 5) begin
$display("\n\t*** PASSED ALL TESTS ***");
$finish;
end
end // always @ (posedge sys_clk_i)
// INTERNAL WIRING ////////////////////////////////////////////////////
aeMB2_sim
#(/*AUTOINSTPARAM*/
// Parameters
.IWB (IWB),
.DWB (DWB),
.TXE (TXE),
.MUL (MUL),
.BSF (BSF),
.FSL (FSL),
.DIV (DIV))
dut (/*AUTOINST*/
// Outputs
.cwb_adr_o (cwb_adr_o[6:2]),
.cwb_dat_o (cwb_dat_o[31:0]),
.cwb_sel_o (cwb_sel_o[3:0]),
.cwb_stb_o (cwb_stb_o),
.cwb_tga_o (cwb_tga_o[1:0]),
.cwb_wre_o (cwb_wre_o),
.dwb_adr_o (dwb_adr_o[DWB-1:2]),
.dwb_cyc_o (dwb_cyc_o),
.dwb_dat_o (dwb_dat_o[31:0]),
.dwb_sel_o (dwb_sel_o[3:0]),
.dwb_stb_o (dwb_stb_o),
.dwb_tga_o (dwb_tga_o),
.dwb_wre_o (dwb_wre_o),
.iwb_adr_o (iwb_adr_o[IWB-1:2]),
.iwb_stb_o (iwb_stb_o),
.iwb_tga_o (iwb_tga_o),
.iwb_wre_o (iwb_wre_o),
// Inputs
.cwb_ack_i (cwb_ack_i),
.cwb_dat_i (cwb_dat_i[31:0]),
.dwb_ack_i (dwb_ack_i),
.dwb_dat_i (dwb_dat_i[31:0]),
.iwb_ack_i (iwb_ack_i),
.iwb_dat_i (iwb_dat_i[31:0]),
.sys_clk_i (sys_clk_i),
.sys_int_i (sys_int_i),
.sys_rst_i (sys_rst_i));
 
endmodule // edk32
 
/* $Log $ */
 
// Local Variables:
// verilog-library-directories:("." "../../rtl/verilog/")
// verilog-library-files:("")
// End:

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.