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Rev 194 → Rev 195
/trunk/lib/fasm/fasm_stack.v
0,0 → 1,113
/* $Id: fasm_fifo.v,v 1.2 2008/06/05 21:07:13 sybreon Exp $ |
** |
** FASM MEMORY LIBRARY |
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net> |
** All rights reserved. |
** |
** FASM is free software: you can redistribute it and/or modify it |
** under the terms of the GNU Lesser General Public License as |
** published by the Free Software Foundation, either version 3 of the |
** License, or (at your option) any later version. |
** |
** FASM is distributed in the hope that it will be useful, but WITHOUT |
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General |
** Public License for more details. |
** |
** You should have received a copy of the GNU Lesser General Public |
** License along with FASM. If not, see <http:**www.gnu.org/licenses/>. |
*/ |
|
module fasm_stack (/*AUTOARG*/ |
// Outputs |
dat_o, rok_o, wok_o, |
// Inputs |
dat_i, rde_i, wre_i, rst_i, ena_i, clk_i |
); |
|
parameter AW = 4; |
parameter DW = 32; |
|
output [DW-1:0] dat_o; |
output rok_o, |
wok_o; |
|
input [DW-1:0] dat_i; |
input rde_i, |
wre_i; |
|
input rst_i, |
ena_i, |
clk_i; |
|
/*AUTOREG*/ |
// Beginning of automatic regs (for this module's undeclared outputs) |
reg rok_o; |
reg wok_o; |
// End of automatics |
|
reg [AW:1] rRADR; |
wire [AW:1] rWADR = (rde_i) ? rRADR - 1 : rRADR + 1; |
|
always @(posedge clk_i) |
if (rst_i) begin |
/*AUTORESET*/ |
// Beginning of autoreset for uninitialized flops |
rRADR <= {(1+(AW)-(1)){1'b0}}; |
// End of automatics |
end else if (ena_i) begin |
rRADR <= #1 rWADR; |
end |
|
/* |
fasm_tparam AUTO_TEMPLATE ( |
.AW(AW), |
.DW(DW), |
|
.clk_i(clk_i), |
.rst_i(), |
.stb_i(), |
.wre_i(), |
.dat_i(), |
.adr_i(rRADR), |
.dat_o(dat_o), |
|
.xclk_i(clk_i), |
.xrst_i(), |
.xstb_i(), |
.xwre_i(wWRE), |
.xadr_i(rWADR), |
.xdat_i(dat_i), |
.xdat_o(), |
) |
*/ |
|
fasm_tparam |
#(/*AUTOINSTPARAM*/ |
// Parameters |
.AW (AW), // Templated |
.DW (DW)) // Templated |
stack0 |
(/*AUTOINST*/ |
// Outputs |
.dat_o (dat_o), // Templated |
.xdat_o (), // Templated |
// Inputs |
.dat_i (), // Templated |
.adr_i (rRADR), // Templated |
.wre_i (), // Templated |
.stb_i (), // Templated |
.rst_i (), // Templated |
.clk_i (clk_i), // Templated |
.xdat_i (dat_i), // Templated |
.xadr_i (rWADR), // Templated |
.xwre_i (wWRE), // Templated |
.xstb_i (), // Templated |
.xrst_i (), // Templated |
.xclk_i (clk_i)); // Templated |
|
endmodule // fasm_stack |
|
/* |
$Log$ |
*/ |
/trunk/lib/fasm/fasm_spsram_rbw.v
0,0 → 1,73
/* $Id: fasm_spsram.v,v 1.1 2008/06/05 20:51:56 sybreon Exp $ |
** |
** FASM MEMORY LIBRARY |
** Copyright (C) 2004-2009 Shawn Tan <shawn.tan@aeste.net> |
** All rights reserved. |
** |
** FASM is free software: you can redistribute it and/or modify it |
** under the terms of the GNU Lesser General Public License as |
** published by the Free Software Foundation, either version 3 of the |
** License, or (at your option) any later version. |
** |
** FASM is distributed in the hope that it will be useful, but WITHOUT |
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General |
** Public License for more details. |
** |
** You should have received a copy of the GNU Lesser General Public |
** License along with FASM. If not, see <http:**www.gnu.org/licenses/>. |
*/ |
/* |
* SINGLE PORT SYNCHRONOUS RAM - READ-BEFORE-WRITE |
* Synthesis proven on: |
* - Xilinx ISE |
* - Altera Quartus (>=8.0) |
*/ |
|
module fasm_spsram_rbw (/*AUTOARG*/ |
// Outputs |
dat_o, |
// Inputs |
dat_i, adr_i, wre_i, stb_i, rst_i, clk_i |
); |
|
parameter AW = 8; ///< address space (2^AW) words |
parameter DW = 32; ///< data word width bits |
|
// wishbone port a |
output [DW-1:0] dat_o; // DO |
input [DW-1:0] dat_i; // DI |
input [AW-1:0] adr_i; // A |
input wre_i; // WE |
input stb_i; // CS |
|
input rst_i, |
clk_i; |
|
// output latch |
reg [DW-1:0] rA; |
|
// memory block |
reg [DW-1:0] bram [(1<<AW)-1:0]; |
|
always @(posedge clk_i) |
if (stb_i) |
begin |
rA <= #1 bram[adr_i]; |
if (wre_i) // strobe and write-enable |
bram[adr_i] <= #1 dat_i; |
end |
|
assign dat_o = rA; // write-thru |
|
// ### SIMULATION ONLY ### |
// synopsys translate_off |
integer i; |
initial begin |
for (i=0; i<(1<<AW); i=i+1) begin |
bram[i] <= $random; |
end |
end |
// synopsys translate_on |
|
endmodule // fasm_spsram |
/trunk/lib/fasm/fasm_spsram_wbr.v
0,0 → 1,73
/* $Id: fasm_spsram.v,v 1.1 2008/06/05 20:51:56 sybreon Exp $ |
** |
** FASM MEMORY LIBRARY |
** Copyright (C) 2004-2009 Shawn Tan <shawn.tan@aeste.net> |
** All rights reserved. |
** |
** FASM is free software: you can redistribute it and/or modify it |
** under the terms of the GNU Lesser General Public License as |
** published by the Free Software Foundation, either version 3 of the |
** License, or (at your option) any later version. |
** |
** FASM is distributed in the hope that it will be useful, but WITHOUT |
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General |
** Public License for more details. |
** |
** You should have received a copy of the GNU Lesser General Public |
** License along with FASM. If not, see <http:**www.gnu.org/licenses/>. |
*/ |
/* |
* SINGLE PORT SYNCHRONOUS RAM - WRITE-BEFORE-READ |
* Synthesis proven on: |
* - Xilinx ISE |
* - Altera Quartus (>=8.0) |
*/ |
|
module fasm_spsram_wbr (/*AUTOARG*/ |
// Outputs |
dat_o, |
// Inputs |
dat_i, adr_i, wre_i, stb_i, rst_i, clk_i |
); |
|
parameter AW = 8; ///< address space (2^AW) words |
parameter DW = 32; ///< data word width bits |
|
// wishbone port a |
output [DW-1:0] dat_o; // DO |
input [DW-1:0] dat_i; // DI |
input [AW-1:0] adr_i; // A |
input wre_i; // WE |
input stb_i; // CS |
|
input rst_i, |
clk_i; |
|
// address latch |
reg [AW-1:0] rA; |
|
// memory block |
reg [DW-1:0] bram [(1<<AW)-1:0]; |
|
always @(posedge clk_i) |
if (stb_i) |
begin |
rA <= #1 adr_i; |
if (wre_i) // strobe and write-enable |
bram[adr_i] <= #1 dat_i; |
end |
|
assign dat_o = bram[rA]; // write-thru |
|
// ### SIMULATION ONLY ### |
// synopsys translate_off |
integer i; |
initial begin |
for (i=0; i<(1<<AW); i=i+1) begin |
bram[i] <= $random; |
end |
end |
// synopsys translate_on |
|
endmodule // fasm_spsram_wbr |
/trunk/lib/fasm/fasm_dpsram_rbw.v
0,0 → 1,92
/* $Id: fasm_dpsram.v,v 1.3 2008/06/05 20:51:56 sybreon Exp $ |
** |
** FASM MEMORY LIBRARY |
** Copyright (C) 2004-2009 Shawn Tan <shawn.tan@aeste.net> |
** All rights reserved. |
** |
** FASM is free software: you can redistribute it and/or modify it |
** under the terms of the GNU Lesser General Public License as |
** published by the Free Software Foundation, either version 3 of the |
** License, or (at your option) any later version. |
** |
** FASM is distributed in the hope that it will be useful, but WITHOUT |
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General |
** Public License for more details. |
** |
** You should have received a copy of the GNU Lesser General Public |
** License along with FASM. If not, see <http:**www.gnu.org/licenses/>. |
*/ |
/* |
* DUAL PORT SYNCHRONOUS RAM - READ-BEFORE-WRITE |
* Synthesis proven on: |
* - Xilinx ISE |
* - Altera Quartus (>=8.0) |
*/ |
|
module fasm_dpsram_rbw (/*AUTOARG*/ |
// Outputs |
dat_o, xdat_o, |
// Inputs |
dat_i, adr_i, wre_i, stb_i, rst_i, clk_i, xdat_i, xadr_i, xwre_i, |
xstb_i, xrst_i, xclk_i |
); |
|
parameter AW = 8; ///< address space (2^AW) words |
parameter DW = 32; ///< data word width bits |
|
// wishbone port a |
output [DW-1:0] dat_o; // DO |
input [DW-1:0] dat_i; // DI |
input [AW-1:0] adr_i; // A |
input wre_i; // WE |
input stb_i; // CS |
|
input rst_i, |
clk_i; |
|
// wishbone port x |
output [DW-1:0] xdat_o; // DO |
input [DW-1:0] xdat_i; // DI |
input [AW-1:0] xadr_i; // A |
input xwre_i; // WE |
input xstb_i; // CS |
|
input xrst_i, |
xclk_i; |
|
// address latch |
reg [AW-1:0] rA, rX; |
|
// memory block |
reg [DW-1:0] bram [(1<<AW)-1:0]; |
|
always @(posedge xclk_i) |
if (xstb_i) |
begin |
rX <= #1 bram[xadr_i]; |
if (xwre_i) // strobe and write-enable |
bram[xadr_i] <= #1 xdat_i; |
end |
always @(posedge clk_i) |
if (stb_i) |
begin |
rA <= #1 bram[adr_i]; |
if (wre_i) // strobe and write-enable |
bram[adr_i] <= #1 dat_i; |
end |
|
assign xdat_o = rX; // write-thru |
assign dat_o = rA; // write-thru |
|
// ### SIMULATION ONLY ### |
// synopsys translate_off |
integer i; |
initial begin |
for (i=0; i<(1<<AW); i=i+1) begin |
bram[i] <= $random; |
end |
end |
// synopsys translate_on |
|
endmodule // fasm_dpsram_rbw |
/trunk/lib/fasm/fasm_dpsram_wbr.v
0,0 → 1,92
/* $Id: fasm_dpsram.v,v 1.3 2008/06/05 20:51:56 sybreon Exp $ |
** |
** FASM MEMORY LIBRARY |
** Copyright (C) 2004-2009 Shawn Tan <shawn.tan@aeste.net> |
** All rights reserved. |
** |
** FASM is free software: you can redistribute it and/or modify it |
** under the terms of the GNU Lesser General Public License as |
** published by the Free Software Foundation, either version 3 of the |
** License, or (at your option) any later version. |
** |
** FASM is distributed in the hope that it will be useful, but WITHOUT |
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General |
** Public License for more details. |
** |
** You should have received a copy of the GNU Lesser General Public |
** License along with FASM. If not, see <http:**www.gnu.org/licenses/>. |
*/ |
/* |
* DUAL PORT SYNCHRONOUS RAM - WRITE-BEFORE-READ |
* Synthesis proven on: |
* - Xilinx ISE |
* - Altera Quartus (>=8.0) |
*/ |
|
module fasm_dpsram_wbr (/*AUTOARG*/ |
// Outputs |
dat_o, xdat_o, |
// Inputs |
dat_i, adr_i, wre_i, stb_i, rst_i, clk_i, xdat_i, xadr_i, xwre_i, |
xstb_i, xrst_i, xclk_i |
); |
|
parameter AW = 8; ///< address space (2^AW) words |
parameter DW = 32; ///< data word width bits |
|
// wishbone port a |
output [DW-1:0] dat_o; // DO |
input [DW-1:0] dat_i; // DI |
input [AW-1:0] adr_i; // A |
input wre_i; // WE |
input stb_i; // CS |
|
input rst_i, |
clk_i; |
|
// wishbone port x |
output [DW-1:0] xdat_o; // DO |
input [DW-1:0] xdat_i; // DI |
input [AW-1:0] xadr_i; // A |
input xwre_i; // WE |
input xstb_i; // CS |
|
input xrst_i, |
xclk_i; |
|
// address latch |
reg [AW-1:0] rA, rX; |
|
// memory block |
reg [DW-1:0] bram [(1<<AW)-1:0]; |
|
always @(posedge xclk_i) |
if (xstb_i) |
begin |
rX <= #1 xadr_i; |
if (xwre_i) // strobe and write-enable |
bram[xadr_i] <= #1 xdat_i; |
end |
always @(posedge clk_i) |
if (stb_i) |
begin |
rA <= #1 adr_i; |
if (wre_i) // strobe and write-enable |
bram[adr_i] <= #1 dat_i; |
end |
|
assign xdat_o = bram[rX]; // write-thru |
assign dat_o = bram[rA]; // write-thru |
|
// ### SIMULATION ONLY ### |
// synopsys translate_off |
integer i; |
initial begin |
for (i=0; i<(1<<AW); i=i+1) begin |
bram[i] <= $random; |
end |
end |
// synopsys translate_on |
|
endmodule // fasm_dpsram_wbr |
/trunk/lib/fasm/fasm_tpsram_rbw.v
0,0 → 1,91
/* $Id: fasm_tpsram.v,v 1.1 2008/06/05 20:51:56 sybreon Exp $ |
** |
** FASM MEMORY LIBRARY |
** Copyright (C) 2004-2009 Shawn Tan <shawn.tan@aeste.net> |
** All rights reserved. |
** |
** FASM is free software: you can redistribute it and/or modify it |
** under the terms of the GNU Lesser General Public License as |
** published by the Free Software Foundation, either version 3 of the |
** License, or (at your option) any later version. |
** |
** FASM is distributed in the hope that it will be useful, but WITHOUT |
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General |
** Public License for more details. |
** |
** You should have received a copy of the GNU Lesser General Public |
** License along with FASM. If not, see <http:**www.gnu.org/licenses/>. |
*/ |
/* |
* TWO PORT SYNCHRONOUS RAM - READ-BEFORE-WRITE |
* Synthesis proven on: |
* - Xilinx ISE |
* - Altera Quartus (>=8.0) |
*/ |
|
module fasm_tpsram_rbw (/*AUTOARG*/ |
// Outputs |
dat_o, xdat_o, |
// Inputs |
dat_i, adr_i, wre_i, stb_i, rst_i, clk_i, xdat_i, xadr_i, xwre_i, |
xstb_i, xrst_i, xclk_i |
); |
|
parameter AW = 8; ///< address space (2^AW) words |
parameter DW = 32; ///< data word width bits |
|
// wishbone port a |
output [DW-1:0] dat_o; // DO |
input [DW-1:0] dat_i; // DI - unused |
input [AW-1:0] adr_i; // A |
input wre_i; // WE - unused |
input stb_i; // CS |
|
input rst_i, |
clk_i; |
|
// wishbone port x |
output [DW-1:0] xdat_o; // DO - unused |
input [DW-1:0] xdat_i; // DI |
input [AW-1:0] xadr_i; // A |
input xwre_i; // WE |
input xstb_i; // CS |
|
input xrst_i, |
xclk_i; |
|
// address latch |
reg [AW-1:0] rA, rX; |
|
// memory block |
reg [DW-1:0] bram [(1<<AW)-1:0]; |
|
always @(posedge xclk_i) |
if (xstb_i) |
begin |
rX <= #1 bram[xadr_i]; |
end |
|
always @(posedge clk_i) |
if (stb_i) |
begin |
rA <= #1 bram[adr_i]; |
if (wre_i) // strobe and write-enable |
bram[adr_i] <= #1 dat_i; |
end |
|
assign xdat_o = rX; // write-thru |
assign dat_o = rA; // write-thru |
|
// ### SIMULATION ONLY ### |
// synopsys translate_off |
integer i; |
initial begin |
for (i=0; i<(1<<AW); i=i+1) begin |
bram[i] <= $random; |
end |
end |
// synopsys translate_on |
|
endmodule // fasm_dpsram |
/trunk/lib/fasm/fasm_tpsram_wbr.v
0,0 → 1,92
/* $Id: fasm_tpsram.v,v 1.1 2008/06/05 20:51:56 sybreon Exp $ |
** |
** FASM MEMORY LIBRARY |
** Copyright (C) 2004-2009 Shawn Tan <shawn.tan@aeste.net> |
** All rights reserved. |
** |
** FASM is free software: you can redistribute it and/or modify it |
** under the terms of the GNU Lesser General Public License as |
** published by the Free Software Foundation, either version 3 of the |
** License, or (at your option) any later version. |
** |
** FASM is distributed in the hope that it will be useful, but WITHOUT |
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General |
** Public License for more details. |
** |
** You should have received a copy of the GNU Lesser General Public |
** License along with FASM. If not, see <http:**www.gnu.org/licenses/>. |
*/ |
/* |
* TWO PORT SYNCHRONOUS RAM - WRITE-BEFORE-READ |
* Synthesis proven on: |
* - Xilinx ISE |
* - Altera Quartus (>=8.0) |
*/ |
|
module fasm_tpsram_wbr (/*AUTOARG*/ |
// Outputs |
dat_o, xdat_o, |
// Inputs |
dat_i, adr_i, wre_i, stb_i, rst_i, clk_i, xdat_i, xadr_i, xwre_i, |
xstb_i, xrst_i, xclk_i |
); |
|
parameter AW = 8; ///< address space (2^AW) words |
parameter DW = 32; ///< data word width bits |
|
// wishbone port a |
output [DW-1:0] dat_o; // DO |
input [DW-1:0] dat_i; // DI - unused |
input [AW-1:0] adr_i; // A |
input wre_i; // WE - unused |
input stb_i; // CS |
|
input rst_i, |
clk_i; |
|
// wishbone port x |
output [DW-1:0] xdat_o; // DO - unused |
input [DW-1:0] xdat_i; // DI |
input [AW-1:0] xadr_i; // A |
input xwre_i; // WE |
input xstb_i; // CS |
|
input xrst_i, |
xclk_i; |
|
// address latch |
reg [AW-1:0] rA, rX; |
|
// memory block |
reg [DW-1:0] bram [(1<<AW)-1:0]; |
|
always @(posedge clk_i) |
if (stb_i) |
begin |
rA <= #1 adr_i; |
if (wre_i) // strobe and write-enable |
bram[adr_i] <= #1 dat_i; |
end |
|
always @(posedge xclk_i) |
if (xstb_i) |
begin |
rX <= #1 xadr_i; |
end |
|
//assign xdat_o = {(DW){1'bX}}; // write-thru |
assign xdat_o = bram[rX]; // write-thru |
assign dat_o = bram[rA]; // write-thru |
|
// ### SIMULATION ONLY ### |
// synopsys translate_off |
integer i; |
initial begin |
for (i=0; i<(1<<AW); i=i+1) begin |
bram[i] <= $random; |
end |
end |
// synopsys translate_on |
|
endmodule // fasm_dpsram |
/trunk/lib/fasm/fasm_memory.vi
0,0 → 1,37
/* $Id: fasm_tparam.v,v 1.2 2008/06/05 20:53:36 sybreon Exp $ |
** |
** FASM MEMORY LIBRARY |
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net> |
** All rights reserved. |
** |
** FASM is free software: you can redistribute it and/or modify it |
** under the terms of the GNU Lesser General Public License as |
** published by the Free Software Foundation, either version 3 of the |
** License, or (at your option) any later version. |
** |
** FASM is distributed in the hope that it will be useful, but WITHOUT |
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General |
** Public License for more details. |
** |
** You should have received a copy of the GNU Lesser General Public |
** License along with FASM. If not, see <http:**www.gnu.org/licenses/>. |
*/ |
/* |
* Synthesis proven on: |
* - Xilinx ISE |
* - Altera Quartus (>=8.0) |
*/ |
|
`include "fasm_tparam.v" |
`include "fasm_sparam.v" |
`include "fasm_dparam.v" |
|
`include "fasm_spsram.v" |
`include "fasm_dpsram.v" |
`include "fasm_tpsram.v" |
|
`include "fasm_fifo.v" |
|
`include "fasm_tparam_n.v" |
|
/trunk/lib/fasm/fasm_fifo.v
0,0 → 1,148
/* $Id: fasm_fifo.v,v 1.2 2008/06/05 21:07:13 sybreon Exp $ |
** |
** FASM MEMORY LIBRARY |
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net> |
** All rights reserved. |
** |
** FASM is free software: you can redistribute it and/or modify it |
** under the terms of the GNU Lesser General Public License as |
** published by the Free Software Foundation, either version 3 of the |
** License, or (at your option) any later version. |
** |
** FASM is distributed in the hope that it will be useful, but WITHOUT |
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General |
** Public License for more details. |
** |
** You should have received a copy of the GNU Lesser General Public |
** License along with FASM. If not, see <http:**www.gnu.org/licenses/>. |
*/ |
/* |
* SMALL INTERNAL BUFFER (FIFO) |
* Synthesis proven on: |
* - Xilinx ISE |
* - Altera Quartus (>=8.0) |
*/ |
|
module fasm_fifo (/*AUTOARG*/ |
// Outputs |
dat_o, rok_o, wok_o, |
// Inputs |
dat_i, rde_i, wre_i, clr_i, rst_i, ena_i, clk_i |
); |
parameter AW = 4; // fifo depth |
parameter DW = 32; // fifo width |
|
output [DW-1:0] dat_o; |
output rok_o, // empty signal |
wok_o; // full signal |
|
input [DW-1:0] dat_i; |
input rde_i, |
wre_i; |
|
input clr_i, |
rst_i, |
ena_i, |
clk_i; // global clock |
|
/*AUTOREG*/ |
// Beginning of automatic regs (for this module's undeclared outputs) |
reg rok_o; |
reg wok_o; |
// End of automatics |
|
reg [AW:1] rRADR, |
rWADR; |
|
wire wWRE = wre_i & wok_o; |
wire wRDE = rde_i & rok_o; |
|
//wire [AW:1] wRNXT = {~^rRADR[2:1],rRADR[AW:2]}; |
//wire [AW:1] wWNXT = {~^rWADR[2:1],rWADR[AW:2]}; |
wire [AW:1] wRNXT = rRADR + 1; |
wire [AW:1] wWNXT = rWADR + 1; |
|
always @(posedge clk_i) |
if (rst_i | clr_i) begin |
rok_o <= 1'b0; |
wok_o <= 1'b1; |
/*AUTORESET*/ |
// Beginning of autoreset for uninitialized flops |
rRADR <= {(1+(AW)-(1)){1'b0}}; |
rWADR <= {(1+(AW)-(1)){1'b0}}; |
// End of automatics |
end else if (ena_i) begin |
|
if (wWRE) rWADR <= #1 wWNXT; |
if (wRDE) rRADR <= #1 wRNXT; |
|
if (wWRE ^ wRDE) begin |
if (wWRE) begin |
wok_o <= #1 (wWNXT != rRADR); // FIXME: use XOR |
rok_o <= #1 1'b1; |
end else begin |
wok_o <= #1 1'b1; |
rok_o <= #1 (wRNXT != rWADR); |
end |
end |
|
end // if (ena_i) |
|
/* fasm_tparam AUTO_TEMPLATE |
( |
.AW(AW), |
.DW(DW), |
|
.clk_i(clk_i), |
.rst_i(), |
.stb_i(), |
.wre_i(), |
.dat_i(), |
.adr_i(rRADR), |
.dat_o(dat_o), |
|
.xclk_i(clk_i), |
.xrst_i(), |
.xstb_i(), |
.xwre_i(wWRE), |
.xadr_i(rWADR), |
.xdat_i(dat_i), |
.xdat_o(), |
); */ |
|
fasm_tparam |
#(/*AUTOINSTPARAM*/ |
// Parameters |
.AW (AW), // Templated |
.DW (DW)) // Templated |
fiforam0 |
(/*AUTOINST*/ |
// Outputs |
.dat_o (dat_o), // Templated |
.xdat_o (), // Templated |
// Inputs |
.dat_i (), // Templated |
.adr_i (rRADR), // Templated |
.wre_i (), // Templated |
.stb_i (), // Templated |
.rst_i (), // Templated |
.clk_i (clk_i), // Templated |
.xdat_i (dat_i), // Templated |
.xadr_i (rWADR), // Templated |
.xwre_i (wWRE), // Templated |
.xstb_i (), // Templated |
.xrst_i (), // Templated |
.xclk_i (clk_i)); // Templated |
|
// ### SIMULATION ONLY ### |
// synopsys translate_on |
initial begin |
// This depends on target technology. All regular FPGAs have a |
// 16x1 dual port asynchronous RAM block. |
if (AW > 4) $display("Warning: FIFO too large!"); |
if (AW < 2) $display("Warning: FIFO too small!"); |
end |
// synopsys translate_off |
|
endmodule // fasm_fifo |
/trunk/lib/fasm/fasm_sparam.v
0,0 → 1,65
/* $Id: fasm_sparam.v,v 1.2 2008/06/05 20:55:15 sybreon Exp $ |
** |
** FASM MEMORY LIBRARY |
** Copyright (C) 2004-2009 Shawn Tan <shawn.tan@aeste.net> |
** All rights reserved. |
** |
** FASM is free software: you can redistribute it and/or modify it |
** under the terms of the GNU Lesser General Public License as |
** published by the Free Software Foundation, either version 3 of the |
** License, or (at your option) any later version. |
** |
** FASM is distributed in the hope that it will be useful, but WITHOUT |
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General |
** Public License for more details. |
** |
** You should have received a copy of the GNU Lesser General Public |
** License along with FASM. If not, see <http:**www.gnu.org/licenses/>. |
*/ |
/* |
* SINGLE PORT ASYNCHRONOUS MEMORY BLOCK |
* Synthesis proven on: |
* - Xilinx ISE |
* - Altera Quartus (>=8.0) |
*/ |
|
module fasm_sparam (/*AUTOARG*/ |
// Outputs |
dat_o, |
// Inputs |
dat_i, adr_i, wre_i, stb_i, clk_i, rst_i |
) ; |
parameter AW = 5; // 32 |
parameter DW = 2; // x2 |
|
// PORT A - READ/WRITE |
output [DW-1:0] dat_o; |
input [DW-1:0] dat_i; |
input [AW-1:0] adr_i; |
input wre_i; |
input stb_i; // ignored |
|
input clk_i, |
rst_i; |
|
// memory block |
reg [DW-1:0] lram [(1<<AW)-1:0]; |
|
always @(posedge clk_i) |
if (wre_i) |
lram[adr_i] <= #1 dat_i; |
|
assign dat_o = lram[adr_i]; |
|
// ### SIMULATION ONLY ### |
// synopsys translate_off |
integer i; |
initial begin |
for (i=0; i<(1<<AW); i=i+1) begin |
lram[i] <= $random; |
end |
end |
// synopsys translate_on |
|
endmodule // fasm_sparam |
/trunk/lib/fasm/fasm_dparam.v
0,0 → 1,75
/* $Id: fasm_dparam.v,v 1.2 2008/06/05 20:53:16 sybreon Exp $ |
** |
** FASM MEMORY LIBRARY |
** Copyright (C) 2004-2009 Shawn Tan <shawn.tan@aeste.net> |
** All rights reserved. |
** |
** FASM is free software: you can redistribute it and/or modify it |
** under the terms of the GNU Lesser General Public License as |
** published by the Free Software Foundation, either version 3 of the |
** License, or (at your option) any later version. |
** |
** FASM is distributed in the hope that it will be useful, but WITHOUT |
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General |
** Public License for more details. |
** |
** You should have received a copy of the GNU Lesser General Public |
** License along with FASM. If not, see <http:**www.gnu.org/licenses/>. |
*/ |
/* |
* DUAL PORT ASYNCHRONOUS MEMORY BLOCK |
* Synthesis proven on: |
* - Xilinx ISE |
* - Altera Quartus (>=8.0) |
*/ |
|
module fasm_dparam (/*AUTOARG*/ |
// Outputs |
dat_o, xdat_o, |
// Inputs |
dat_i, adr_i, wre_i, stb_i, clk_i, rst_i, xdat_i, xadr_i, xwre_i, |
xstb_i, xclk_i, xrst_i |
) ; |
parameter AW = 5; // 32 |
parameter DW = 2; // x2 |
|
// PORT A - READ-ONLY |
output [DW-1:0] dat_o; |
input [DW-1:0] dat_i; // ignored |
input [AW-1:0] adr_i; |
input wre_i; // ignored |
input stb_i; // ignored |
|
input clk_i, |
rst_i; |
|
// PORT X - READ/WRITE |
output [DW-1:0] xdat_o; |
input [DW-1:0] xdat_i; |
input [AW-1:0] xadr_i; |
input xwre_i; |
input xstb_i; // ignored |
|
input xclk_i, |
xrst_i; |
|
reg [DW-1:0] lram [(1<<AW)-1:0]; |
|
always @(posedge xclk_i) |
if (xwre_i) lram[xadr_i] <= #1 xdat_i; |
|
assign dat_o = lram[adr_i]; |
assign xdat_o = lram[xadr_i]; |
|
// ### SIMULATION ONLY ### |
// synopsys translate_off |
integer i; |
initial begin |
for (i=0; i<(1<<AW); i=i+1) begin |
lram[i] <= $random; |
end |
end |
// synopsys translate_on |
|
endmodule // fasm_dparam |
/trunk/lib/fasm/fasm_tparam.v
0,0 → 1,75
/* $Id: fasm_tparam.v,v 1.2 2008/06/05 20:53:36 sybreon Exp $ |
** |
** FASM MEMORY LIBRARY |
** Copyright (C) 2004-2009 Shawn Tan <shawn.tan@aeste.net> |
** All rights reserved. |
** |
** FASM is free software: you can redistribute it and/or modify it |
** under the terms of the GNU Lesser General Public License as |
** published by the Free Software Foundation, either version 3 of the |
** License, or (at your option) any later version. |
** |
** FASM is distributed in the hope that it will be useful, but WITHOUT |
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General |
** Public License for more details. |
** |
** You should have received a copy of the GNU Lesser General Public |
** License along with FASM. If not, see <http:**www.gnu.org/licenses/>. |
*/ |
/* |
* TWO PORT ASYNCHRONOUS MEMORY BLOCK |
* Synthesis proven on: |
* - Xilinx ISE |
* - Altera Quartus (>=8.0) |
*/ |
|
module fasm_tparam (/*AUTOARG*/ |
// Outputs |
dat_o, xdat_o, |
// Inputs |
dat_i, adr_i, wre_i, stb_i, rst_i, clk_i, xdat_i, xadr_i, xwre_i, |
xstb_i, xrst_i, xclk_i |
) ; |
parameter AW = 4; |
parameter DW = 6; |
|
// wishbone port a |
output [DW-1:0] dat_o; // DO |
input [DW-1:0] dat_i; // DI - unused |
input [AW-1:0] adr_i; // A |
input wre_i; // WE - unused |
input stb_i; // CS - unused |
|
input rst_i, |
clk_i; |
|
// wishbone port x |
output [DW-1:0] xdat_o; // DO - unused |
input [DW-1:0] xdat_i; // DI |
input [AW-1:0] xadr_i; // A |
input xwre_i; // WE |
input xstb_i; // CS |
|
input xrst_i, |
xclk_i; |
|
reg [DW-1:0] lram [(1<<AW)-1:0]; |
|
always @(posedge xclk_i) |
if (xwre_i) lram[xadr_i] <= #1 xdat_i; |
|
assign xdat_o = {(DW){1'bX}}; |
assign dat_o = lram[adr_i]; |
|
// ### SIMULATION ONLY ### |
// synopsys translate_off |
integer i; |
initial begin |
for (i=0; i<(1<<AW); i=i+1) begin |
lram[i] <= $random; |
end |
end |
// synopsys translate_on |
|
endmodule // fasm_tparam |
/trunk/lib/vpio/vpio_gpio.v
0,0 → 1,100
/* $Id: fasm_sparam.v,v 1.2 2008/06/05 20:55:15 sybreon Exp $ |
** |
** VIRTUAL PERIPHERAL INPUT/OUTPUT LIBRARY |
** Copyright (C) 2004-2009 Shawn Tan <shawn.tan@aeste.net> |
** All rights reserved. |
** |
** LITE is free software: you can redistribute it and/or modify it |
** under the terms of the GNU Lesser General Public License as |
** published by the Free Software Foundation, either version 3 of the |
** License, or (at your option) any later version. |
** |
** LITE is distributed in the hope that it will be useful, but WITHOUT |
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General |
** Public License for more details. |
** |
** You should have received a copy of the GNU Lesser General Public |
** License along with FASM. If not, see <http:**www.gnu.org/licenses/>. |
*/ |
/* |
* GENERAL PURPOSE I/O |
*/ |
|
module vpio_gpio (/*AUTOARG*/ |
// Outputs |
wb_dat_o, wb_ack_o, |
// Inouts |
gpio_io, |
// Inputs |
wb_dat_i, wb_adr_i, wb_stb_i, wb_sel_i, wb_wre_i, wb_clk_i, |
wb_rst_i |
); |
parameter IO = 8; |
|
// WISHBONE SLAVE |
output [IO-1:0] wb_dat_o; |
output wb_ack_o; |
|
input [IO-1:0] wb_dat_i; |
input wb_adr_i; |
input wb_stb_i, |
wb_sel_i, |
wb_wre_i, |
wb_clk_i, |
wb_rst_i; |
|
// GPIO I/F |
inout [IO-1:0] gpio_io; |
|
/*AUTOREG*/ |
// Beginning of automatic regs (for this module's undeclared outputs) |
reg wb_ack_o; |
reg [IO-1:0] wb_dat_o; |
// End of automatics |
|
reg [IO-1:0] rTRIS, // Direction - 1:output, 0:input |
rPORT; |
|
wire wb_stb = wb_stb_i & wb_sel_i; |
wire wb_wre = wb_stb_i & wb_sel_i & wb_wre_i; |
|
// WISHBONE SIDE |
always @(posedge wb_clk_i) |
if (wb_rst_i) begin |
/*AUTORESET*/ |
// Beginning of autoreset for uninitialized flops |
rPORT <= {(1+(IO-1)){1'b0}}; |
rTRIS <= {(1+(IO-1)){1'b0}}; |
// End of automatics |
end else if (wb_wre) begin |
if (wb_adr_i) rPORT <= #1 wb_dat_i; |
if (!wb_adr_i) rTRIS <= #1 wb_dat_i; |
end |
|
always @(posedge wb_clk_i) |
if (wb_rst_i) begin |
/*AUTORESET*/ |
// Beginning of autoreset for uninitialized flops |
wb_ack_o <= 1'h0; |
wb_dat_o <= {(1+(IO-1)){1'b0}}; |
// End of automatics |
end else begin |
wb_ack_o <= #1 !wb_ack_o & wb_stb; |
|
case (wb_adr_i) // WAR |
1'b0: wb_dat_o <= #1 rTRIS; |
1'b1: wb_dat_o <= #1 rPORT; |
endcase // case (wb_adr_i) |
end // else: !if(wb_rst_i) |
|
// GPIO SIDE |
integer i; |
reg [IO-1:0] rGPIO; // async latch |
assign gpio_io = rGPIO; |
|
always @(/*AUTOSENSE*/rPORT or rTRIS) |
for (i=0;i<IO;i=i+1) |
rGPIO[i] <= (rTRIS[i]) ? rPORT[i] : 1'bZ; |
|
endmodule // vpio_gpio |
/trunk/lib/vpio/vpio_mspi.v
0,0 → 1,211
/* $Id: fasm_sparam.v,v 1.2 2008/06/05 20:55:15 sybreon Exp $ |
** |
** VIRTUAL PERIPHERAL INPUT/OUTPUT LIBRARY |
** Copyright (C) 2004-2009 Shawn Tan <shawn.tan@aeste.net> |
** All rights reserved. |
** |
** LITE is free software: you can redistribute it and/or modify it |
** under the terms of the GNU Lesser General Public License as |
** published by the Free Software Foundation, either version 3 of the |
** License, or (at your option) any later version. |
** |
** LITE is distributed in the hope that it will be useful, but WITHOUT |
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General |
** Public License for more details. |
** |
** You should have received a copy of the GNU Lesser General Public |
** License along with FASM. If not, see <http:**www.gnu.org/licenses/>. |
*/ |
/* |
* MASTER SERIAL PERIPHERAL INTERFACE |
*/ |
|
module vpio_mspi (/*AUTOARG*/ |
// Outputs |
wb_dat_o, wb_ack_o, int_o, mspi_dat_o, mspi_clk_o, |
// Inputs |
wb_dat_i, wb_adr_i, wb_sel_i, wb_wre_i, wb_stb_i, wb_clk_i, |
wb_rst_i, mspi_dat_i |
); |
|
// WISHBONE SLAVE INTERFACE |
output [7:0] wb_dat_o; |
output wb_ack_o; |
output int_o; |
input [7:0] wb_dat_i; |
input wb_adr_i; |
input wb_sel_i, |
wb_wre_i, |
wb_stb_i, |
//wb_cyc_i, |
wb_clk_i, |
wb_rst_i; |
|
// MASTER SPI INTERFACE |
output mspi_dat_o, // MOSI |
//mspi_sel_o, // SSEL |
mspi_clk_o; // SCLK |
input mspi_dat_i; // MISO |
|
/*AUTOREG*/ |
// Beginning of automatic regs (for this module's undeclared outputs) |
reg int_o; |
reg mspi_clk_o; |
reg wb_ack_o; |
reg [7:0] wb_dat_o; |
// End of automatics |
|
localparam [1:0] // synopsys enum state FSM |
FSM_IDLE = 2'o0, |
FSM_PHA0 = 2'o1, |
FSM_PHA1 = 2'o2, |
FSM_NULL = 2'o3; |
|
reg [1:0] // synopsys enum state FSM |
rFSM, rFSM_; |
|
reg [1:0] rSPIC_MODE, rSPIC_DIVI; |
reg rSPIC_SPIE, rSPIC_SPEN; |
reg rSPIC_SPIF, rSPIC_WCOL; |
|
reg rFULL; |
reg [7:0] rSPID, rTBUF; |
reg [2:0] rBCNT; |
|
wire [7:0] rSPIC = {rSPIC_SPIE, // RW-SPI interrupt enable |
rSPIC_SPEN, // RW_SPI enable |
rSPIC_SPIF, // RO-flag |
rSPIC_WCOL, // RO-write collision |
rSPIC_MODE, // RW-SPI mode |
rSPIC_DIVI}; // RW-SPI clock divider |
|
wire CPOL = rSPIC[3]; // CPOL |
wire CPHA = rSPIC[2]; // CPHA |
wire [1:0] CDIV = rSPIC[1:0]; // CDIV |
wire SPIE = rSPIC[7]; |
wire SPEN = rSPIC[6]; |
|
wire wb_stb = wb_sel_i & wb_stb_i; |
wire wb_wre = wb_sel_i & wb_stb_i & wb_wre_i; |
|
// WISHBONE INTERFACE - Synchronous Single Transfers |
always @(posedge wb_clk_i) |
if (wb_rst_i) begin |
/*AUTORESET*/ |
// Beginning of autoreset for uninitialized flops |
rSPIC_DIVI <= 2'h0; |
rSPIC_MODE <= 2'h0; |
rSPIC_SPEN <= 1'h0; |
rSPIC_SPIE <= 1'h0; |
rSPID <= 8'h0; |
// End of automatics |
end else if (wb_wre) begin |
if (!wb_adr_i) {rSPIC_SPIE, |
rSPIC_SPEN, |
rSPIC_MODE, |
rSPIC_DIVI} = #1 {wb_dat_i[7:6], |
wb_dat_i[3:0]}; |
if (wb_adr_i) rSPID <= #1 wb_dat_i; |
end |
|
always @(posedge wb_clk_i) |
if (wb_rst_i) begin |
/*AUTORESET*/ |
// Beginning of autoreset for uninitialized flops |
wb_ack_o <= 1'h0; |
wb_dat_o <= 8'h0; |
// End of automatics |
end else if (wb_stb) begin |
|
wb_ack_o <= !wb_ack_o & wb_stb_i; |
|
case (wb_adr_i) |
1'b0: wb_dat_o <= rSPIC; |
1'b1: wb_dat_o <= rSPID; |
endcase // case (wb_adr_i) |
end |
|
// CLOCK - Loadable Counter |
reg [3:0] rFCNT; |
wire wena = ~|rFCNT; |
always @(posedge wb_clk_i) |
if (wb_rst_i) begin // reset |
/*AUTORESET*/ |
// Beginning of autoreset for uninitialized flops |
rFCNT <= 4'h0; |
// End of automatics |
end else if (rFSM == FSM_IDLE) begin |
case (CDIV) |
2'o0: rFCNT <= #1 4'h0; // 2 -- original HC11 |
2'o1: rFCNT <= #1 4'h1; // 4 -- original HC11 |
2'o2: rFCNT <= #1 4'h7; // 16 -- original HC11 |
2'o3: rFCNT <= #1 4'hF; // 32 -- original HC11 |
endcase // case (CDIV) |
end else if (|rFCNT) begin |
rFCNT <= #1 rFCNT - 1; |
end |
|
// STATE MACHINE |
wire wbit = ~|rBCNT; |
assign mspi_dat_o = rTBUF[7]; |
|
always @(posedge wb_clk_i) |
if (wb_rst_i) begin |
rFSM <= FSM_IDLE; |
/*AUTORESET*/ |
// Beginning of autoreset for uninitialized flops |
mspi_clk_o <= 1'h0; |
rBCNT <= 3'h0; |
rFULL <= 1'h0; |
rTBUF <= 8'h0; |
// End of automatics |
end else begin |
|
// BIT COUNT |
case (rFSM) |
FSM_IDLE: rBCNT <= #1 3'o7; |
FSM_PHA1: rBCNT <= #1 rBCNT - 1; |
default: rBCNT <= #1 rBCNT; |
endcase // case (rFSM) |
|
// MOSI/MISO |
case (rFSM) |
FSM_IDLE: rTBUF <= #1 rSPID; |
FSM_PHA1: rTBUF <= #1 {rTBUF[6:0], mspi_dat_i}; |
default: rTBUF <= #1 rTBUF; |
endcase // case (rFSM) |
|
// SCLK |
case (rFSM) |
FSM_IDLE: mspi_clk_o <= #1 CPOL; |
FSM_PHA0: mspi_clk_o <= #1 (wena) ? ~mspi_clk_o : mspi_clk_o; |
FSM_PHA1: mspi_clk_o <= #1 (!wena) ? mspi_clk_o : (wbit) ? CPOL : ~mspi_clk_o; |
/* |
FSM_PHA1: case ({wena, wbit}) |
2'o3: mspi_clk_o <= #1 CPOL; |
2'o2: mspi_clk_o <= #1 ~mspi_clk_o; |
default: mspi_clk_o <= #1 mspi_clk_o; |
endcase // case ({wena, wbit}) |
*/ |
default: mspi_clk_o <= #1 mspi_clk_o; |
endcase // case (rFSM) |
|
// FULL/WCOL |
case (rFSM) |
FSM_IDLE: rFULL <= #1 (wb_wre & wb_adr_i) | rFULL; |
FSM_NULL: rFULL <= #1 1'b0; |
default: rFULL <= #1 rFULL; |
endcase // case (rFSM) |
|
// STATE |
case (rFSM) |
FSM_IDLE: rFSM <= #1 (rFULL) ? FSM_PHA0 : FSM_IDLE; |
FSM_PHA0: rFSM <= #1 (wena) ? FSM_PHA1 : FSM_PHA0; |
FSM_PHA1: rFSM <= #1 (!wena) ? FSM_PHA1 : (~|rBCNT) ? FSM_IDLE : FSM_PHA0; |
default: rFSM <= #1 FSM_IDLE; |
endcase // case (rFSM) |
|
end // else: !if(wb_rst_i) |
|
endmodule // vpio_mspi |