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https://opencores.org/ocsvn/aemb/aemb/trunk
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- This comparison shows the changes necessary to convert path
/aemb
- from Rev 202 to Rev 203
- ↔ Reverse comparison
Rev 202 → Rev 203
/trunk/rtl/verilog/aeMB2_exec.v
77,9 → 77,11
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//TODO: OPTIMISE! |
wire wILL = |
((opc_of[5:4] == 2'o1) & opc_of[2]) | // illegal extended arithmetic |
((opc_of[5:4] == 2'o3) & &opc_of[1:0]); // illegal LD/ST |
//(opc_of == 6'o23) | (opc_of == 6'o24) | (opc_of == 6'o25) | (opc_of == 6'o26) | opc_of == 6'o27) | |
//(opc_of == 6'o32) | (opc_of == 6'o34) | (opc_of == 6'o35) | (opc_of == 6'o36) | opc_of == 6'o37) | |
(opc_of == 6'o63) | (opc_of == 6'o67) | (opc_of == 6'o73) | (opc_of == 6'o77); // illegal load/store |
//(opc_of == 6'o63) | (opc_of == 6'o67) | (opc_of == 6'o73) | (opc_of == 6'o77); // illegal load/store |
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always @(posedge gclk) |
if (grst) begin |
/trunk/rtl/verilog/aeMB2_dwbif.v
32,7 → 32,7
dwb_adr_o, dwb_sel_o, dwb_stb_o, dwb_cyc_o, dwb_tag_o, dwb_wre_o, |
dwb_dat_o, dwb_fb, sel_mx, dwb_mx, exc_dwb, |
// Inputs |
dwb_dat_i, dwb_ack_i, dwb_err_i, imm_of, opd_of, opc_of, opa_of, |
dwb_dat_i, dwb_ack_i, imm_of, opd_of, opc_of, opa_of, |
opb_of, msr_ex, mem_ex, sfr_mx, gclk, grst, dena, gpha |
); |
parameter AEMB_DWB = 32; ///< data bus address width |
47,7 → 47,7
output [31:0] dwb_dat_o; |
input [31:0] dwb_dat_i; |
input dwb_ack_i; |
input dwb_err_i; // for bus error exception |
//input dwb_err_i; // for bus error exception |
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// INTERNAL |
output dwb_fb; |
84,7 → 84,9
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assign dwb_fb = (dwb_stb_o ~^ dwb_ack_i); // feedback |
assign dwb_adr_o = mem_ex; // data-bus passthru |
assign exc_dwb = {dwb_exc, dwb_err_i}; // exception signal |
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// TODO: enable dwb_err_i exception pass-thru |
assign exc_dwb = {dwb_exc, 1'b0}; |
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// STORE SIZER |
// TODO: Move the right words to the right place |
153,12 → 155,19
endcase // case (wSEL) |
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// exception checking |
dwb_exc <= #1 &opc_of[5:4] & // only for LD/ST commands |
((opc_of[0] & wOFF[0]) | // misaligned 16-bit |
(opc_of[1] & |wOFF[1:0]) // misaligned 32-bit |
); |
/* |
case (opc_of[1:0]) |
2'o2: dwb_exc <= #1 |wOFF[1:0]; |
2'o1: dwb_exc <= #1 wOFF[0]; |
2'o2: dwb_exc <= #1 |wOFF[1:0] & &opc_of[5:4]; |
2'o1: dwb_exc <= #1 wOFF[0] & &opc_of[5:4]; |
default: dwb_exc <= #1 1'b0; |
endcase // case (opc_of[1:0]) |
*/ |
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end // if (dena) |
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// Independent of pipeline |
/trunk/rtl/verilog/aeMB2_iwbif.v
33,7 → 33,7
iwb_adr_o, iwb_stb_o, iwb_sel_o, iwb_wre_o, iwb_cyc_o, iwb_tag_o, |
ich_adr, fet_fb, rpc_if, rpc_mx, exc_iwb, |
// Inputs |
iwb_ack_i, iwb_dat_i, iwb_err_i, ich_hit, msr_ex, hzd_bpc, hzd_fwd, |
iwb_ack_i, iwb_dat_i, ich_hit, msr_ex, hzd_bpc, hzd_fwd, |
bra_ex, bpc_ex, gclk, grst, dena, iena, gpha |
); |
parameter AEMB_IWB = 32; |
48,7 → 48,7
output iwb_tag_o; |
input iwb_ack_i; |
input [31:0] iwb_dat_i; |
input iwb_err_i; // bus error exception |
//input iwb_err_i; // bus error exception |
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// Cache |
output [AEMB_IWB-1:2] ich_adr; |
156,7 → 156,8
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assign fet_fb = iwb_stb_o ~^ iwb_ack_i; // no WB cycle |
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assign exc_iwb = iwb_err_i; // exception pass-thru |
// TODO: enable iwb_err_i exception pass-thru |
assign exc_iwb = 1'b0; |
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endmodule // aeMB2_iwbif |
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