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https://opencores.org/ocsvn/aemb/aemb/trunk
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- This comparison shows the changes necessary to convert path
/aemb
- from Rev 205 to Rev 206
- ↔ Reverse comparison
Rev 205 → Rev 206
/trunk/rtl/verilog/aeMB2_edk63.v
34,7 → 34,7
dwb_cyc_o, dwb_adr_o, |
// Inputs |
xwb_dat_i, xwb_ack_i, sys_rst_i, sys_int_i, sys_ena_i, sys_clk_i, |
iwb_dat_i, iwb_ack_i, exc_dwb, dwb_dat_i, dwb_ack_i |
iwb_dat_i, iwb_ack_i, dwb_dat_i, dwb_ack_i |
); |
// BUS WIDTHS |
parameter AEMB_IWB = 32; ///< INST bus width |
82,7 → 82,6
// Beginning of automatic inputs (from unused autoinst inputs) |
input dwb_ack_i; // To memif0 of aeMB2_memif.v |
input [31:0] dwb_dat_i; // To memif0 of aeMB2_memif.v |
input [1:0] exc_dwb; // To pip0 of aeMB2_pipe.v |
input iwb_ack_i; // To iche0 of aeMB2_iche.v, ... |
input [31:0] iwb_dat_i; // To iche0 of aeMB2_iche.v, ... |
input sys_clk_i; // To pip0 of aeMB2_pipe.v |
103,6 → 102,7
wire dena; // From pip0 of aeMB2_pipe.v |
wire dwb_fb; // From memif0 of aeMB2_memif.v |
wire [31:0] dwb_mx; // From memif0 of aeMB2_memif.v |
wire [1:0] exc_dwb; // From memif0 of aeMB2_memif.v |
wire exc_ill; // From exec0 of aeMB2_exec.v |
wire exc_iwb; // From iwbif0 of aeMB2_iwbif.v |
wire fet_fb; // From iwbif0 of aeMB2_iwbif.v |
326,6 → 326,7
.dwb_stb_o (dwb_stb_o), |
.dwb_tag_o (dwb_tag_o), |
.dwb_wre_o (dwb_wre_o), |
.exc_dwb (exc_dwb[1:0]), |
.sel_mx (sel_mx[3:0]), |
.xwb_adr_o (xwb_adr_o[AEMB_XWB-1:2]), |
.xwb_cyc_o (xwb_cyc_o), |
/trunk/rtl/verilog/aeMB2_exec.v
78,7 → 78,7
//TODO: OPTIMISE! |
wire wILL = |
((opc_of[5:4] == 2'o1) & opc_of[2]) | // illegal extended arithmetic |
((opc_of[5:4] == 2'o3) & &opc_of[1:0]); // illegal LD/ST |
(&opc_of[5:4] & &opc_of[1:0]); // illegal LD/ST |
//(opc_of == 6'o23) | (opc_of == 6'o24) | (opc_of == 6'o25) | (opc_of == 6'o26) | opc_of == 6'o27) | |
//(opc_of == 6'o32) | (opc_of == 6'o34) | (opc_of == 6'o35) | (opc_of == 6'o36) | opc_of == 6'o37) | |
//(opc_of == 6'o63) | (opc_of == 6'o67) | (opc_of == 6'o73) | (opc_of == 6'o77); // illegal load/store |
/trunk/rtl/verilog/aeMB2_dwbif.v
32,8 → 32,8
dwb_adr_o, dwb_sel_o, dwb_stb_o, dwb_cyc_o, dwb_tag_o, dwb_wre_o, |
dwb_dat_o, dwb_fb, sel_mx, dwb_mx, exc_dwb, |
// Inputs |
dwb_dat_i, dwb_ack_i, imm_of, opd_of, opc_of, opa_of, |
opb_of, msr_ex, mem_ex, sfr_mx, gclk, grst, dena, gpha |
dwb_dat_i, dwb_ack_i, imm_of, opd_of, opc_of, opa_of, opb_of, |
msr_ex, mem_ex, sfr_mx, gclk, grst, dena, gpha |
); |
parameter AEMB_DWB = 32; ///< data bus address width |
|
72,12 → 72,16
gpha; |
|
/*AUTOREG*/ |
reg [3:0] dwb_sel_o; |
reg dwb_stb_o, dwb_cyc_o, dwb_wre_o; |
reg [31:0] dwb_dat_o; |
reg [3:0] sel_mx; |
reg [31:0] dwb_mx; |
reg dwb_exc; |
// Beginning of automatic regs (for this module's undeclared outputs) |
reg dwb_cyc_o; |
reg [31:0] dwb_dat_o; |
reg [31:0] dwb_mx; |
reg [3:0] dwb_sel_o; |
reg dwb_stb_o; |
reg dwb_wre_o; |
reg [3:0] sel_mx; |
// End of automatics |
reg dwb_exc; |
|
wire [1:0] wOFF = (opa_of[1:0] + opb_of[1:0]); // small adder |
wire [3:0] wSEL = {opc_of[1:0], wOFF}; // byte selector info |
/trunk/rtl/verilog/aeMB2_memif.v
31,9 → 31,9
module aeMB2_memif (/*AUTOARG*/ |
// Outputs |
xwb_wre_o, xwb_tag_o, xwb_stb_o, xwb_sel_o, xwb_mx, xwb_fb, |
xwb_dat_o, xwb_cyc_o, xwb_adr_o, sel_mx, dwb_wre_o, dwb_tag_o, |
dwb_stb_o, dwb_sel_o, dwb_mx, dwb_fb, dwb_dat_o, dwb_cyc_o, |
dwb_adr_o, |
xwb_dat_o, xwb_cyc_o, xwb_adr_o, sel_mx, exc_dwb, dwb_wre_o, |
dwb_tag_o, dwb_stb_o, dwb_sel_o, dwb_mx, dwb_fb, dwb_dat_o, |
dwb_cyc_o, dwb_adr_o, |
// Inputs |
xwb_dat_i, xwb_ack_i, sfr_mx, opd_of, opc_of, opb_of, opa_of, |
msr_ex, mem_ex, imm_of, grst, gpha, gclk, dwb_dat_i, dwb_ack_i, |
54,6 → 54,7
output dwb_stb_o; // From dwbif0 of aeMB2_dwbif.v |
output dwb_tag_o; // From dwbif0 of aeMB2_dwbif.v |
output dwb_wre_o; // From dwbif0 of aeMB2_dwbif.v |
output [1:0] exc_dwb; // From dwbif0 of aeMB2_dwbif.v |
output [3:0] sel_mx; // From dwbif0 of aeMB2_dwbif.v |
output [AEMB_XWB-1:2] xwb_adr_o; // From xslif0 of aeMB2_xslif.v |
output xwb_cyc_o; // From xslif0 of aeMB2_xslif.v |
131,6 → 132,7
.dwb_fb (dwb_fb), |
.sel_mx (sel_mx[3:0]), |
.dwb_mx (dwb_mx[31:0]), |
.exc_dwb (exc_dwb[1:0]), |
// Inputs |
.dwb_dat_i (dwb_dat_i[31:0]), |
.dwb_ack_i (dwb_ack_i), |
/trunk/rtl/verilog/aeMB2_ctrl.v
196,7 → 196,8
end |
|
assign fINT = brk_if[0] & gpha & !rFIM1; |
assign fXCE = brk_if[1] & !rFIM1; |
assign fXCE = brk_if[1]; |
// & ((gpha & !rFIM1) | (!gpha & rFIM0)); |
|
// operand latch |
reg wrb_ex; |
/trunk/sim/verilog/edk63.v
0,0 → 1,266
/* |
** AEMB2 EDK 6.3 COMPATIBLE CORE |
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net> |
** |
** This file is part of AEMB. |
** |
** AEMB is free software: you can redistribute it and/or modify it |
** under the terms of the GNU Lesser General Public License as |
** published by the Free Software Foundation, either version 3 of the |
** License, or (at your option) any later version. |
** |
** AEMB is distributed in the hope that it will be useful, but WITHOUT |
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General |
** Public License for more details. |
** |
** You should have received a copy of the GNU Lesser General Public |
** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>. |
*/ |
|
/** |
Simulation Test Bench |
@file edk62.v |
|
*/ |
|
`include "random.v" |
|
module edk63(); |
localparam AEMB_DWB = 18; |
localparam AEMB_XWB = 5; |
localparam AEMB_IWB = 18; |
localparam AEMB_ICH = 11; |
localparam AEMB_IDX = 6; |
localparam AEMB_HTX = 1; |
localparam AEMB_BSF = 1; |
localparam AEMB_MUL = 1; |
localparam AEMB_XSL = 1; |
localparam AEMB_DIV = 0; |
localparam AEMB_FPU = 0; |
|
/*AUTOREGINPUT*/ |
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs) |
reg dwb_ack_i; // To uut of aeMB2_edk63.v |
reg iwb_ack_i; // To uut of aeMB2_edk63.v |
reg sys_clk_i; // To uut of aeMB2_edk63.v |
reg sys_ena_i; // To uut of aeMB2_edk63.v |
reg sys_int_i; // To uut of aeMB2_edk63.v |
reg sys_rst_i; // To uut of aeMB2_edk63.v |
reg xwb_ack_i; // To uut of aeMB2_edk63.v |
// End of automatics |
|
always #5 sys_clk_i <= !sys_clk_i; |
|
initial begin |
`ifdef VCD_DUMP |
$dumpfile ("dump.vcd"); |
$dumpvars (1,uut); |
`endif |
|
sys_clk_i = $random(`randseed); |
sys_rst_i = 1; |
sys_ena_i = 1; |
sys_int_i = 1; |
|
xwb_ack_i = 0; |
|
#50 sys_rst_i = 0; |
#4000000 $displayh("\n*** TIMEOUT ", $stime, " ***"); $finish; |
|
end // initial begin |
|
/*AUTOWIRE*/ |
// Beginning of automatic wires (for undeclared instantiated-module outputs) |
wire [AEMB_DWB-1:2] dwb_adr_o; // From uut of aeMB2_edk63.v |
wire dwb_cyc_o; // From uut of aeMB2_edk63.v |
wire [31:0] dwb_dat_o; // From uut of aeMB2_edk63.v |
wire [3:0] dwb_sel_o; // From uut of aeMB2_edk63.v |
wire dwb_stb_o; // From uut of aeMB2_edk63.v |
wire dwb_tag_o; // From uut of aeMB2_edk63.v |
wire dwb_wre_o; // From uut of aeMB2_edk63.v |
wire [AEMB_IWB-1:2] iwb_adr_o; // From uut of aeMB2_edk63.v |
wire iwb_cyc_o; // From uut of aeMB2_edk63.v |
wire [3:0] iwb_sel_o; // From uut of aeMB2_edk63.v |
wire iwb_stb_o; // From uut of aeMB2_edk63.v |
wire iwb_tag_o; // From uut of aeMB2_edk63.v |
wire iwb_wre_o; // From uut of aeMB2_edk63.v |
wire [AEMB_XWB-1:2] xwb_adr_o; // From uut of aeMB2_edk63.v |
wire xwb_cyc_o; // From uut of aeMB2_edk63.v |
wire [31:0] xwb_dat_o; // From uut of aeMB2_edk63.v |
wire [3:0] xwb_sel_o; // From uut of aeMB2_edk63.v |
wire xwb_stb_o; // From uut of aeMB2_edk63.v |
wire xwb_tag_o; // From uut of aeMB2_edk63.v |
wire xwb_wre_o; // From uut of aeMB2_edk63.v |
// End of automatics |
|
// FAKE MEMORY //////////////////////////////////////////////////////// |
|
reg [31:0] rom[0:65535]; |
reg [31:0] ram[0:65535]; |
reg [31:0] dwblat; |
reg [31:0] xwblat; |
reg [31:2] dadr, iadr; |
|
wire [31:0] dwb_dat_t = ram[dwb_adr_o]; |
wire [31:0] iwb_dat_i = rom[iadr]; |
wire [31:0] dwb_dat_i = ram[dadr]; |
wire [31:0] xwb_dat_i = xwblat; |
|
always @(posedge sys_clk_i) |
if (sys_rst_i) begin |
/*AUTORESET*/ |
// Beginning of autoreset for uninitialized flops |
dwb_ack_i <= 1'h0; |
iwb_ack_i <= 1'h0; |
xwb_ack_i <= 1'h0; |
// End of automatics |
end else begin |
iwb_ack_i <= #1 iwb_stb_o & !iwb_ack_i; |
dwb_ack_i <= #1 dwb_stb_o & !dwb_ack_i; |
xwb_ack_i <= #1 xwb_stb_o & !xwb_ack_i; |
end // else: !if(sys_rst_i) |
|
always @(posedge sys_clk_i) begin |
iadr <= #1 iwb_adr_o; |
dadr <= #1 dwb_adr_o; |
|
if (xwb_wre_o & xwb_stb_o & xwb_ack_i) begin |
xwblat <= #1 xwb_dat_o; |
end |
|
// SPECIAL PORTS |
if (dwb_wre_o & dwb_stb_o & dwb_ack_i) begin |
case ({dwb_adr_o,2'o0}) |
32'hFFFFFFD0: $displayh(dwb_dat_o); |
32'hFFFFFFC0: $write("%c",dwb_dat_o[31:24]); |
32'hFFFFFFE0: sys_int_i <= #1 !sys_int_i; |
endcase // case ({dwb_adr_o,2'o0}) |
|
case (dwb_sel_o) |
4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]}; |
4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]}; |
4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]}; |
4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]}; |
4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]}; |
4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]}; |
4'hF: ram[dwb_adr_o] <= {dwb_dat_o}; |
default: begin |
$displayh("\n*** INVALID WRITE ",{dwb_adr_o,2'o0}, " ***"); |
//$finish; |
end |
endcase // case (dwb_sel_o) |
end // if (dwb_wre_o & dwb_stb_o & dwb_ack_i) |
|
if (dwb_stb_o & !dwb_wre_o & dwb_ack_i) begin |
case (dwb_sel_o) |
4'h1,4'h2,4'h4,4'h8,4'h3,4'hC,4'hF: begin |
end |
default: begin |
$displayh("\n*** INVALID READ ",{dwb_adr_o,2'd0}, " ***"); |
//$finish; |
end |
endcase // case (dwb_sel_o) |
end |
|
end // always @ (posedge sys_clk_i) |
|
integer i; |
initial begin |
for (i=0;i<65535;i=i+1) begin |
ram[i] <= $random; |
end |
#1 $readmemh("dump.vmem",rom); |
#1 $readmemh("dump.vmem",ram); |
end |
|
// DUMP CYCLES |
always @(posedge sys_clk_i) |
if (uut.dena) begin |
//begin |
`ifdef AEMB2_SIM_KERNEL |
$displayh("TME=",($stime/10), |
",PHA=",uut.gpha, |
",IWB=",{uut.rpc_if,2'o0}, |
",ASM=",uut.ich_dat, |
",OPA=",uut.opa_of, |
",OPB=",uut.opb_of, |
",OPD=",uut.opd_of, |
",MSR=",uut.msr_ex, |
",MEM=",{uut.mem_ex,2'o0}, |
",BRA=",uut.bra_ex, |
",BPC=",{uut.bpc_ex,2'o0}, |
",MUX=",uut.mux_ex, |
",ALU=",uut.alu_mx, |
//",WRE=",dwb_wre_o, |
",SEL=",dwb_sel_o, |
//",DWB=",dwb_dat_o, |
",REG=",uut.regs0.gprf0.wRW0, |
//",DAT=",uut.regs0.gprf0.regd, |
",MUL=",uut.mul_mx, |
",BSF=",uut.bsf_mx, |
",DWB=",uut.dwb_mx, |
",LNK=",{uut.rpc_mx,2'o0}, |
",SFR=",uut.sfr_mx, |
",E" |
); |
`endif |
if (uut.ich_dat == 32'hB8000000) begin |
$displayh("\n*** EXIT ", $stime, " ***"); |
$finish; |
end |
end // if (uut.dena) |
|
aeMB2_edk63 |
#(/*AUTOINSTPARAM*/ |
// Parameters |
.AEMB_IWB (AEMB_IWB), |
.AEMB_DWB (AEMB_DWB), |
.AEMB_XWB (AEMB_XWB), |
.AEMB_ICH (AEMB_ICH), |
.AEMB_IDX (AEMB_IDX), |
.AEMB_BSF (AEMB_BSF), |
.AEMB_MUL (AEMB_MUL), |
.AEMB_DIV (AEMB_DIV), |
.AEMB_FPU (AEMB_FPU)) |
uut |
(/*AUTOINST*/ |
// Outputs |
.dwb_adr_o (dwb_adr_o[AEMB_DWB-1:2]), |
.dwb_cyc_o (dwb_cyc_o), |
.dwb_dat_o (dwb_dat_o[31:0]), |
.dwb_sel_o (dwb_sel_o[3:0]), |
.dwb_stb_o (dwb_stb_o), |
.dwb_tag_o (dwb_tag_o), |
.dwb_wre_o (dwb_wre_o), |
.iwb_adr_o (iwb_adr_o[AEMB_IWB-1:2]), |
.iwb_cyc_o (iwb_cyc_o), |
.iwb_sel_o (iwb_sel_o[3:0]), |
.iwb_stb_o (iwb_stb_o), |
.iwb_tag_o (iwb_tag_o), |
.iwb_wre_o (iwb_wre_o), |
.xwb_adr_o (xwb_adr_o[AEMB_XWB-1:2]), |
.xwb_cyc_o (xwb_cyc_o), |
.xwb_dat_o (xwb_dat_o[31:0]), |
.xwb_sel_o (xwb_sel_o[3:0]), |
.xwb_stb_o (xwb_stb_o), |
.xwb_tag_o (xwb_tag_o), |
.xwb_wre_o (xwb_wre_o), |
// Inputs |
.dwb_ack_i (dwb_ack_i), |
.dwb_dat_i (dwb_dat_i[31:0]), |
.iwb_ack_i (iwb_ack_i), |
.iwb_dat_i (iwb_dat_i[31:0]), |
.sys_clk_i (sys_clk_i), |
.sys_ena_i (sys_ena_i), |
.sys_int_i (sys_int_i), |
.sys_rst_i (sys_rst_i), |
.xwb_ack_i (xwb_ack_i), |
.xwb_dat_i (xwb_dat_i[31:0])); |
|
endmodule // edk62 |
|
// Local Variables: |
// verilog-library-directories:("." "../../rtl/verilog/") |
// verilog-library-files:("") |
// End: |
/trunk/sw/cc/exception.S
0,0 → 1,13
|
|
.section .vectors.hw_exception |
|
.global _hw_exception_handler |
.func _hw_exception_handler |
_hw_exception_handler: |
//rtsd r15, 8 |
rted r17, 0 |
nop |
|
.end |
|
/trunk/sw/cc/corefunc.hh
29,8 → 29,44
#ifndef COREFUNC_HH |
#define COREFUNC_HH |
|
#define MAGIC 0xAE62AE62 // magic number |
#ifdef __cplusplus |
extern "C" { |
#endif |
|
#define MAGIC 0xAE63AE63 // magic number |
|
volatile int exce = 0; |
|
void exceptionHandler() |
{ |
exce++; // flag the exception service routine |
} |
|
|
volatile void _hw_exception_handler() |
{ |
//exceptionHandler(); |
exce++; |
asm volatile (//"lwi r15,r1,0\n" |
"rted r17, 0\n" |
"nop\n"); |
//"addik r1,r1,28\n"); |
} |
|
/** |
EXCEPTION TEST ROUTINE |
*/ |
|
int exceptionTest(int timeout) |
{ |
volatile int *toggle = (int *)0xFFFFFFE2; |
// enable exceptions |
asm volatile (".long 0xDEADC0DE"); // define illegal instruction (1 error) |
*toggle = *toggle; // test unaligned memory access (2 errors) |
// disable exceptions |
return (exce != 3) ? EXIT_FAILURE : EXIT_SUCCESS; |
} |
|
volatile int intr = 0; |
|
void __attribute__ ((interrupt_handler)) interruptHandler() |
96,17 → 132,9
return (magic == MAGIC) ? EXIT_SUCCESS : EXIT_FAILURE; |
} |
|
#ifdef __cplusplus |
} |
#endif |
|
/* |
$Log: not supported by cvs2svn $ |
Revision 1.3 2008/05/01 08:37:37 sybreon |
Added interrupt capability. |
#endif |
|
Revision 1.2 2008/04/28 20:30:24 sybreon |
Changed to new headers. |
|
Revision 1.1 2008/04/27 16:04:42 sybreon |
Minor cosmetic changes. |
|
*/ |
/trunk/sw/cc/testbench.cc
75,7 → 75,11
printtest("Hardware Interrupts"); |
checkcode(interruptTest(MAX_TEST)); |
|
// *** 6. EXTENSION *** |
// *** 6. EXCEPTIONS *** |
printtest("Hardware Exceptions"); |
checkcode(exceptionTest(MAX_TEST)); |
|
// *** 7. EXTENSION *** |
printtest("Accellerator Link"); |
checkcode(xslTest(MAX_TEST)); |
} |
90,19 → 94,3
|
return EXIT_SUCCESS; |
} |
|
/* |
$Log: not supported by cvs2svn $ |
Revision 1.5 2008/04/26 19:32:00 sybreon |
Made headers C compatible. |
|
Revision 1.4 2008/04/26 18:08:12 sybreon |
Made single-thread compatible. |
|
Revision 1.3 2008/04/26 00:25:19 sybreon |
switched printf's to iprintf's because iprintf's don't work by |
-O3 for some reason. |
|
Revision 1.2 2008/04/21 12:13:12 sybreon |
Passes arithmetic tests with single thread. |
*/ |