URL
https://opencores.org/ocsvn/aes_highthroughput_lowarea/aes_highthroughput_lowarea/trunk
Subversion Repositories aes_highthroughput_lowarea
Compare Revisions
- This comparison shows the changes necessary to convert path
/aes_highthroughput_lowarea/trunk
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/doc/HT LA AES Core Specifications.odt
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
doc/HT LA AES Core Specifications.odt
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: doc/HT LA AES Core Specifications.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: doc/HT LA AES Core Specifications.pdf
===================================================================
--- doc/HT LA AES Core Specifications.pdf (nonexistent)
+++ doc/HT LA AES Core Specifications.pdf (revision 8)
doc/HT LA AES Core Specifications.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: verilog/bench/test_imc.v
===================================================================
--- verilog/bench/test_imc.v (revision 7)
+++ verilog/bench/test_imc.v (nonexistent)
@@ -1,29 +0,0 @@
-`include "timescale.v"
-module top();
-`include "mix_columns.v"
-`include "shift_rows.v"
-
-reg [7:0] a,b,c,d;
-wire [7:0] datao;
-wire [31:0] data2o;
-wire [127:0] data3o;
-assign datao[7:0] = inv_byte_mix_columns(a,b,c,d);
-assign data2o[31:0] = inv_word_mix_columns({a,b,c,d});
-//assign data3o[127:0] = inv_mix_columns(128'h2c21a820306f154ab712c75eee0da04f);
-assign data3o = inv_shift_rows(128'haa5ece06ee6e3c56dde68bac2621bebf);
-
-initial
-begin
- #10;
- a = 8'h2c;
- b = 8'h21;
- c = 8'ha8;
- d = 8'h20;
- #10;
- $display("datao is %h",datao);
- $display("data2o is %h",data2o);
- $display("data3o is %h",data3o);
- $finish;
-end
-
-endmodule
Index: verilog/bench/tb_kat.v
===================================================================
--- verilog/bench/tb_kat.v (revision 7)
+++ verilog/bench/tb_kat.v (revision 8)
@@ -1,4 +1,26 @@
+//---------------------------------------------------------------------------------------
+// Project: High Throughput & Low Area AES Core
+//
+// File name: tb_kat.v (Jan 1, 2011)
+//
+// Writer: Moti Litochevski
+//
+// Description:
+// This file contains the core test bench to check compatibility with the Known
+// Answer Test (KAT) vectors. The test bench runs all files listed in the
+// "KAT_files.txt" file.
+// Note that only ECB mode test vectors should be included since other modes require
+// additional logic to be implemented around the AES algorithm core.
+//
+// Revision History:
+//
+// Rev
+//
+//
+//---------------------------------------------------------------------------------------
+
`timescale 1ns / 10ps
+
module test ();
// define input list file name
@@ -18,6 +40,7 @@
`define CHAR_f 8'h66
`define CHAR_z 8'h7A
+//---------------------------------------------------------------------------------------
// test bench signals
reg clk;
reg reset;
@@ -119,6 +142,8 @@
end
endfunction
+//---------------------------------------------------------------------------------------
+// test bench implementation
// global clock generator
initial clk = 1'b1;
always #10 clk = ~clk;
@@ -451,3 +476,6 @@
$display("Data Out: %16h",data_out);
endmodule
+//---------------------------------------------------------------------------------------
+// Th.. Th.. Th.. Thats all folks !!!
+//---------------------------------------------------------------------------------------
/verilog/bench/tb.v
1,119 → 1,485
//--------------------------------------------------------------------------------------- |
// Project: High Throughput & Low Area AES Core |
// |
// File name: tb_kat.v (Jan 1, 2011) |
// |
// Writer: Moti Litochevski |
// |
// Description: |
// This file contains a basic test bench to demonstrate the core functionality & |
// interfaces including pipelined operation. For each key length the test bench |
// encrypts four plain text vectors using a single key and then decrypts the four |
// cipher text vectors using the same key. |
// The test bench demonstrates the key expansion, encryption and decryption for all |
// three key lengths with pipelined operation. |
// |
// Revision History: |
// |
// Rev <revnumber> <Date> <owner> |
// <comment> |
// |
//--------------------------------------------------------------------------------------- |
|
`timescale 1ns / 10ps |
module tb (); |
module test (); |
|
reg clk; |
//--------------------------------------------------------------------------------------- |
// global signals |
reg clock; |
reg reset; |
reg [7:0] din; |
wire [7:0] dout; |
|
// test bench variables |
integer dout_count; |
|
// UUT interface signals |
reg key_start; |
reg [255:0] key_in; |
reg data_in_valid; |
reg [127:0] data_in; |
wire key_ready; |
wire ready_out; |
reg enable; |
initial |
begin |
clk = 1'b1; |
key_in = 1'b0; |
key_start = 1'b0; |
data_in_valid = 1'b0; |
reg enable; |
reg enc_dec; |
reg [255:0] key_in; |
reg [1:0] key_mode; |
reg [127:0] data_in; |
reg data_in_valid; |
wire ready_out; |
wire [127:0] data_out; |
wire data_out_valid; |
wire key_ready; |
|
//--------------------------------------------------------------------------------------- |
// test bench implementation |
// global clock generator |
initial clock = 1'b1; |
always #10 clock = ~clock; |
|
// gloabl reset generator |
initial |
begin |
reset = 1'b1; |
enable = 1; |
#100; |
reset = 1'b0; |
#100; |
din = 8'hae; |
@ (posedge clk); |
end |
|
// cosmetics |
initial |
begin |
// announce start of simulation |
$display(""); |
$display("-------------------------------------"); |
$display(" AES_HT_LA Simulation"); |
$display("-------------------------------------"); |
$display(""); |
|
// VCD dump |
$dumpfile("test.vcd"); |
$dumpvars(0, test); |
$display(""); |
end |
|
// main test bench process control |
initial |
begin |
// default input values |
key_start = 1'b0; |
enable = 1'b1; |
enc_dec = 1'b0; |
key_in = 256'b0; |
key_mode = 2'b0; |
data_in = 128'b0; |
data_in_valid = 1'b0; |
dout_count = 0; |
|
// wait for reset release |
@(posedge clock); |
wait (~reset); |
@(posedge clock); |
|
// encryption for 128 bit key mode |
$display("Testing encryption for 128 bit key:"); |
$display("-------------------------------------"); |
// set core mode to encryption and key size to 128 |
enc_dec <= 1'b0; |
key_mode <= 2'b00; |
// set the key value and start key expansion |
key_in[255:128] <= 128'h2b7e151628aed2a6abf7158809cf4f3c; |
key_start <= 1'b1; |
//key_in[255:128] = 128'h2b7e151628aed2a6abf7158809cf4f3c; |
//key_in[255:64] = 192'h8e73b0f7da0e6452c810f32b809079e562f8ead2522c6b7b; |
//key_in[255:0] = 256'h603deb1015ca71be2b73aef0857d77811f352c073b6108d72d9810a30914dff4; |
key_in[255:64] = 192'h000102030405060708090a0b0c0d0e0f1011121314151617; |
//key_in[255:0] = 256'h000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f; |
@ (posedge clk); |
@(posedge clock); |
key_start <= 1'b0; |
wait (key_ready); |
data_in_valid <= 1'b1; |
//data_in[127:0] = 128'h3243f6a8885a308d313198a2e0370731; |
//data_in[127:0] = 128'h00112233445566778899aabbccddeeff; |
//data_in[127:0] = 128'h8ea2b7ca516745bfeafc49904b496089; |
data_in[127:0] = 128'hdda97ca4864cdfe06eaf70a0ec0d7191; |
//@ (posedge clk); |
//data_in[127:0] = 128'h3243f6a8885a308d313198a2e0370734; |
//@ (posedge clk); |
//data_in_valid <= 1'b0; |
//data_in[127:0] = 128'h3243f6a8885a308d313198a2e0370731; |
//@ (posedge clk); |
//data_in_valid <= 1'b1; |
//data_in[127:0] = 128'h3243f6a8885a308d313198a2e0370734; |
//data_in[127:0] = 128'h00112233445566778899aabbccddeeff; |
@ (posedge clk); |
data_in_valid <= 1'b0; |
repeat (3) @ (posedge clk); |
wait (ready_out); |
@ (posedge clk); |
//data_in_valid <= 1'b1; |
@ (posedge clk); |
@(posedge clock); |
// display key value |
$display("Key: 128'h%32h", key_in[255:128]); |
// wait for key expansion to finish |
while (!key_ready) @(posedge clock); |
// announce key expansion ended |
$display("Key expansion done"); |
$display(""); |
|
// first plain text input data |
data_in[127:0] <= 128'hdda97ca4864cdfe06eaf70a0ec0d7191; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Plaintext Data 1: 128'h%32h", data_in); |
// second plain text input data |
data_in[127:0] <= 128'h3243f6a8885a308d313198a2e0370731; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Plaintext Data 2: 128'h%32h", data_in); |
// third plain text input data |
data_in[127:0] <= 128'h00112233445566778899aabbccddeeff; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Plaintext Data 3: 128'h%32h", data_in); |
// forth plain text input data |
data_in[127:0] <= 128'h8ea2b7ca516745bfeafc49904b496089; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Plaintext Data 4: 128'h%32h", data_in); |
// no more data can be given to the core |
data_in_valid <= 1'b0; |
repeat (6) @(posedge clk); |
//enable <= 0; |
//repeat (15) @(posedge clk); |
//enable <= 1; |
#200; |
//$display("dout is %h",dout); |
din = 8'h1e; |
#2000; |
//$display("dout is %h",dout); |
#100; |
@(posedge clock); |
|
// announce state |
$display(""); |
$display("Waiting for cipher text data"); |
|
// wait for all output cipher text data |
dout_count = 0; |
while (dout_count < 4) |
begin |
// check for a new output data |
if (data_out_valid) |
dout_count <= dout_count + 1; |
// wait for next clock cycle |
@(posedge clock); |
end |
$display(""); |
|
// continue with decryption of the same cipher text without key expansion |
$display("Testing decryption for 128 bit key:"); |
$display("-------------------------------------"); |
// set core mode to decryption |
enc_dec <= 1'b1; |
@(posedge clock); |
// display key value |
$display("Key: 128'h%32h", key_in[255:128]); |
// announce key expansion is not done again |
$display("Using the same key, expansion is not required."); |
$display(""); |
|
// first cipher text input data |
data_in[127:0] <= 128'hef0bc156ed8ff21223f247b3e0318a99; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Ciphertext Data 1: 128'h%32h", data_in); |
// second cipher text input data |
data_in[127:0] <= 128'hf91914cd01924b124c2ec316b4b35a79; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Ciphertext Data 2: 128'h%32h", data_in); |
// third cipher text input data |
data_in[127:0] <= 128'h8df4e9aac5c7573a27d8d055d6e4d64b; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Ciphertext Data 3: 128'h%32h", data_in); |
// forth cipher text input data |
data_in[127:0] <= 128'hec8ce641087165a463d4118dc35f9001; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Ciphertext Data 4: 128'h%32h", data_in); |
// no more data can be given to the core |
data_in_valid <= 1'b0; |
|
// announce state |
$display(""); |
$display("Waiting for plain text data"); |
|
// wait for all output plain text data |
dout_count = 0; |
while (dout_count < 4) |
begin |
// check for a new output data |
if (data_out_valid) |
dout_count <= dout_count + 1; |
// wait for next clock cycle |
@(posedge clock); |
end |
$display(""); |
|
// encryption for 192 bit key mode |
$display("Testing encryption for 192 bit key:"); |
$display("-------------------------------------"); |
// set core mode to encryption and key size to 192 |
enc_dec <= 1'b0; |
key_mode <= 2'b01; |
// set the key value and start key expansion |
key_in[255:64] <= 192'h8e73b0f7da0e6452c810f32b809079e562f8ead2522c6b7b; |
key_start <= 1'b1; |
@(posedge clock); |
key_start <= 1'b0; |
@(posedge clock); |
// display key value |
$display("Key: 192'h%32h", key_in[255:64]); |
// wait for key expansion to finish |
while (!key_ready) @(posedge clock); |
// announce key expansion ended |
$display("Key expansion done"); |
$display(""); |
|
// first plain text input data |
data_in[127:0] <= 128'hdda97ca4864cdfe06eaf70a0ec0d7191; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Plaintext Data 1: 128'h%32h", data_in); |
// second plain text input data |
data_in[127:0] <= 128'h3243f6a8885a308d313198a2e0370731; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Plaintext Data 2: 128'h%32h", data_in); |
// third plain text input data |
data_in[127:0] <= 128'h00112233445566778899aabbccddeeff; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Plaintext Data 3: 128'h%32h", data_in); |
// forth plain text input data |
data_in[127:0] <= 128'h8ea2b7ca516745bfeafc49904b496089; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Plaintext Data 4: 128'h%32h", data_in); |
// no more data can be given to the core |
data_in_valid <= 1'b0; |
@(posedge clock); |
|
// announce state |
$display(""); |
$display("Waiting for cipher text data"); |
|
// wait for all output cipher text data |
dout_count = 0; |
while (dout_count < 4) |
begin |
// check for a new output data |
if (data_out_valid) |
dout_count <= dout_count + 1; |
// wait for next clock cycle |
@(posedge clock); |
end |
$display(""); |
|
// continue with decryption of the same cipher text without key expansion |
$display("Testing decryption for 192 bit key:"); |
$display("-------------------------------------"); |
// set core mode to decryption |
enc_dec <= 1'b1; |
@(posedge clock); |
// display key value |
$display("Key: 192'h%32h", key_in[255:64]); |
// announce key expansion is not done again |
$display("Using the same key, expansion is not required."); |
$display(""); |
|
// first cipher text input data |
data_in[127:0] <= 128'h17d3cbb6a98f64ccd134e0d0b7695aa9; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Ciphertext Data 1: 128'h%32h", data_in); |
// second cipher text input data |
data_in[127:0] <= 128'h4a7d86377de2a8faf00f8ef97c2eb982; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Ciphertext Data 2: 128'h%32h", data_in); |
// third cipher text input data |
data_in[127:0] <= 128'heb1b03f2acb64bcf28c9991cc8a4fa50; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Ciphertext Data 3: 128'h%32h", data_in); |
// forth cipher text input data |
data_in[127:0] <= 128'h2adc503e1c9b669de6b5bc904035547d; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Ciphertext Data 4: 128'h%32h", data_in); |
// no more data can be given to the core |
data_in_valid <= 1'b0; |
|
// announce state |
$display(""); |
$display("Waiting for plain text data"); |
|
// wait for all output plain text data |
dout_count = 0; |
while (dout_count < 4) |
begin |
// check for a new output data |
if (data_out_valid) |
dout_count <= dout_count + 1; |
// wait for next clock cycle |
@(posedge clock); |
end |
$display(""); |
|
// encryption for 256 bit key mode |
$display("Testing encryption for 256 bit key:"); |
$display("-------------------------------------"); |
// set core mode to encryption and key size to 256 |
enc_dec <= 1'b0; |
key_mode <= 2'b10; |
// set the key value and start key expansion |
key_in[255:0] <= 256'h603deb1015ca71be2b73aef0857d77811f352c073b6108d72d9810a30914dff4; |
key_start <= 1'b1; |
@(posedge clock); |
key_start <= 1'b0; |
@(posedge clock); |
// display key value |
$display("Key: 256'h%32h", key_in[255:64]); |
// wait for key expansion to finish |
while (!key_ready) @(posedge clock); |
// announce key expansion ended |
$display("Key expansion done"); |
$display(""); |
|
// first plain text input data |
data_in[127:0] <= 128'hdda97ca4864cdfe06eaf70a0ec0d7191; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Plaintext Data 1: 128'h%32h", data_in); |
// second plain text input data |
data_in[127:0] <= 128'h3243f6a8885a308d313198a2e0370731; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Plaintext Data 2: 128'h%32h", data_in); |
// third plain text input data |
data_in[127:0] <= 128'h00112233445566778899aabbccddeeff; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Plaintext Data 3: 128'h%32h", data_in); |
// forth plain text input data |
data_in[127:0] <= 128'h8ea2b7ca516745bfeafc49904b496089; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Plaintext Data 4: 128'h%32h", data_in); |
// no more data can be given to the core |
data_in_valid <= 1'b0; |
@(posedge clock); |
|
// announce state |
$display(""); |
$display("Waiting for cipher text data"); |
|
// wait for all output cipher text data |
dout_count = 0; |
while (dout_count < 4) |
begin |
// check for a new output data |
if (data_out_valid) |
dout_count <= dout_count + 1; |
// wait for next clock cycle |
@(posedge clock); |
end |
$display(""); |
|
// continue with decryption of the same cipher text without key expansion |
$display("Testing decryption for 256 bit key:"); |
$display("-------------------------------------"); |
// set core mode to decryption |
enc_dec <= 1'b1; |
@(posedge clock); |
// display key value |
$display("Key: 256'h%32h", key_in[255:0]); |
// announce key expansion is not done again |
$display("Using the same key, expansion is not required."); |
$display(""); |
|
// first cipher text input data |
data_in[127:0] <= 128'h32573d9003bfd345029779298be53b96; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Ciphertext Data 1: 128'h%32h", data_in); |
// second cipher text input data |
data_in[127:0] <= 128'ha5f464b57512d05db2bae8d2415b921d; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Ciphertext Data 2: 128'h%32h", data_in); |
// third cipher text input data |
data_in[127:0] <= 128'hd83414223d20a0c928b136c884d07ea2; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Ciphertext Data 3: 128'h%32h", data_in); |
// forth cipher text input data |
data_in[127:0] <= 128'hc1f968d2a6859137bd9ad9111ad7f6dc; |
data_in_valid <= 1'b1; |
@ (posedge clock); |
// display data value |
$display("Ciphertext Data 4: 128'h%32h", data_in); |
// no more data can be given to the core |
data_in_valid <= 1'b0; |
|
// announce state |
$display(""); |
$display("Waiting for plain text data"); |
|
// wait for all output plain text data |
dout_count = 0; |
while (dout_count < 4) |
begin |
// check for a new output data |
if (data_out_valid) |
dout_count <= dout_count + 1; |
// wait for next clock cycle |
@(posedge clock); |
end |
$display(""); |
|
// announce simulation end |
$display(" Simulation Done !!!"); |
|
repeat (10) @(posedge clock); |
$finish; |
end |
|
/*sbox u_sbox( |
.clk(clk), |
.reset_n(reset_n), |
.din(din), |
.ende(1'b1), |
.dout(dout));*/ |
//wire wr; |
//wire [4:0] wr_addr; |
//wire [63:0] wr_data; |
|
wire [127:0] data_out; |
aes dut( |
.clk(clk), |
.reset(reset), |
.i_start(key_start), |
.i_enable(enable), //TBD |
.i_ende(1'b1), |
.i_key(key_in), |
.i_key_mode(2'b01), |
.i_data(data_in), |
.i_data_valid(data_in_valid), |
.o_ready(ready_out), |
.o_data(data_out), |
.o_data_valid(data_out_valid), |
.o_key_ready(key_ready) |
// unit under test |
aes dut |
( |
.clk(clock), |
.reset(reset), |
.i_start(key_start), |
.i_enable(enable), |
.i_ende(enc_dec), |
.i_key(key_in), |
.i_key_mode(key_mode), |
.i_data(data_in), |
.i_data_valid(data_in_valid), |
.o_ready(ready_out), |
.o_data(data_out), |
.o_data_valid(data_out_valid), |
.o_key_ready(key_ready) |
); |
|
/*key_exp u_key_exp ( |
.clk(clk), |
.reset_n(reset_n), |
.key_in(key_in), |
.key_mode(2'b10), |
.key_start(key_start), |
.wr(wr), |
.wr_addr(wr_addr), |
.wr_data(wr_data) |
);*/ |
|
always @ (posedge clk) |
// display output data from the core |
always @ (posedge clock) |
if (data_out_valid) |
$display("DATA: %16h",data_out); |
$display("Output Data %1d: 128'h%16h", dout_count+1, data_out); |
|
|
always |
#10 clk = ~clk; |
|
endmodule |
//--------------------------------------------------------------------------------------- |
// Th.. Th.. Th.. Thats all folks !!! |
//--------------------------------------------------------------------------------------- |
/verilog/rtl/key_exp.v
200,16 → 200,16
// key expansion calculation |
// |
// |
assign w0_next[31:0] = sbox_out[31:0]^rcon[31:0]^w0[31:0]; |
assign w1_next[31:0] = w0_next[31:0]^w1[31:0]; |
assign w2_next[31:0] = w1_next[31:0]^w2[31:0]; |
assign w3_next[31:0] = w2_next[31:0]^w3[31:0]; |
assign w4_next1[31:0] = w3_next[31:0] ^ w4[31:0]; |
assign w5_next1[31:0] = w4_next1[31:0]^w5[31:0]; |
assign w0_next[31:0] = sbox_out[31:0] ^ rcon[31:0]^w0[31:0]; |
assign w1_next[31:0] = w0_next[31:0] ^ w1[31:0]; |
assign w2_next[31:0] = w1_next[31:0] ^ w2[31:0]; |
assign w3_next[31:0] = w2_next[31:0] ^ w3[31:0]; |
assign w4_next1[31:0] = w3_next[31:0] ^ w4[31:0]; |
assign w5_next1[31:0] = w4_next1[31:0] ^ w5[31:0]; |
assign w4_next2[31:0] = sbox_out[31:0] ^ w4[31:0]; |
assign w5_next2[31:0] = w4_next2[31:0]^w5[31:0]; |
assign w6_next[31:0] = w5_next2[31:0]^w6[31:0]; |
assign w7_next[31:0] = w6_next[31:0]^w7[31:0]; |
assign w5_next2[31:0] = w4_next2[31:0] ^ w5[31:0]; |
assign w6_next[31:0] = w5_next2[31:0] ^ w6[31:0]; |
assign w7_next[31:0] = w6_next[31:0] ^ w7[31:0]; |
|
always @ (posedge clk or posedge reset) |
begin |
/verilog/rtl/aes_top_example.v
0,0 → 1,147
//--------------------------------------------------------------------------------------- |
// Project: High Throughput / Low Area AES Core |
// |
// File name: aes_top_example.v (March 30, 2012) |
// |
// Writer: Moti Litochevski |
// |
// Description: |
// This file contains a very simple and not very area efficient implementation of |
// instance instantiate ting the AES core. This file is also used to estimate the |
// core synthesis results. |
// The AES core includes direct interfaces to the key and data vectors which are |
// fairly wide (256 & 128 bits). This file includes a simple wrapper to enable 32 |
// bit data bus and 4 bit address to select the input and output word portion. |
// |
// Revision History: |
// |
// Rev <revnumber> <Date> <owner> |
// <comment> |
// |
//--------------------------------------------------------------------------------------- |
|
module aes_top_example |
( |
clk, reset, |
i_enable, i_enc_dec, |
i_key_mode, i_data, |
i_data_sel, i_data_valid, |
o_data_sel, o_key_ready, |
o_ready, o_data, |
o_data_valid |
); |
//--------------------------------------------------------------------------------------- |
// module interfaces |
// global signals |
input clk; |
input reset; |
// AES core interface |
// inputs |
input i_enable; |
input i_enc_dec; |
input [1:0] i_key_mode; |
input [31:0] i_data; |
input [3:0] i_data_sel; |
input i_data_valid; |
input [1:0] o_data_sel; |
// outputs |
output o_key_ready; |
output o_ready; |
output [31:0] o_data; |
output o_data_valid; |
|
//--------------------------------------------------------------------------------------- |
// registered outputs |
reg [31:0] o_data; |
|
// internal signals and registers |
reg [255:0] int_key; |
reg [127:0] int_data; |
reg int_key_start, int_data_valid; |
wire [127:0] int_o_data; |
|
//--------------------------------------------------------------------------------------- |
// module implementation |
// internal key and data vectors write process |
always @ (posedge reset or posedge clk) |
begin |
if (reset) |
begin |
int_key <= 256'b0; |
int_data <= 128'b0; |
int_key_start <= 1'b0; |
int_data_valid <= 1'b0; |
end |
else |
begin |
// input key and data write control |
if (i_data_valid) |
begin |
case (i_data_sel) |
4'h0: int_key[31:0] <= i_data; |
4'h1: int_key[63:32] <= i_data; |
4'h2: int_key[95:64] <= i_data; |
4'h3: int_key[127:96] <= i_data; |
4'h4: int_key[159:128] <= i_data; |
4'h5: int_key[191:160] <= i_data; |
4'h6: int_key[223:192] <= i_data; |
4'h7: int_key[255:224] <= i_data; |
4'h8: int_data[31:0] <= i_data; |
4'h9: int_data[63:32] <= i_data; |
4'ha: int_data[95:64] <= i_data; |
4'hb: int_data[127:96] <= i_data; |
endcase |
end |
|
// key expansion start control |
if ((i_data_sel == 4'h7) && i_data_valid) |
int_key_start <= 1'b1; |
else |
int_key_start <= 1'b0; |
|
// encryption / decryption start control |
if ((i_data_sel == 4'hb) && i_data_valid) |
int_data_valid <= 1'b1; |
else |
int_data_valid <= 1'b0; |
end |
end |
|
// output data read control process |
always @ (posedge reset or posedge clk) |
begin |
if (reset) |
o_data <= 32'b0; |
else |
begin |
case (o_data_sel) |
2'h0: o_data <= int_o_data[31:0]; |
2'h1: o_data <= int_o_data[63:32]; |
2'h2: o_data <= int_o_data[95:64]; |
2'h3: o_data <= int_o_data[127:96]; |
endcase |
end |
end |
|
// AES core instance |
aes u_aes |
( |
.clk(clk), |
.reset(reset), |
.i_start(int_key_start), |
.i_enable(i_enable), |
.i_ende(i_enc_dec), |
.i_key(int_key), |
.i_key_mode(i_key_mode), |
.i_data(int_data), |
.i_data_valid(int_data_valid), |
.o_ready(o_ready), |
.o_data(int_o_data), |
.o_data_valid(o_data_valid), |
.o_key_ready(o_key_ready) |
); |
|
endmodule |
//--------------------------------------------------------------------------------------- |
// Th.. Th.. Th.. Thats all folks !!! |
//--------------------------------------------------------------------------------------- |
/verilog/rtl/ram_16x64.v
30,8 → 30,6
mem[wr_addr] <= wr_data; |
end |
|
//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI |
|
reg [3:0] srd_addr; |
|
always @ (posedge clk) |
42,14 → 40,4
|
assign rd_data = mem[srd_addr]; |
|
//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI |
|
// always @ (posedge clk) |
// begin |
// if (rd) |
// rd_data <= mem[rd_addr]; |
// end |
|
//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI |
|
endmodule |
/verilog/rtl/aes.v
1,52 → 1,52
////////////////////////////////////////////////////////////////////// |
//// //// |
//// AES top file //// |
//// //// |
//// Description: //// |
//// AES top //// |
//// //// |
//// To Do: //// |
//// - done //// |
//// //// |
//// Author(s): //// |
//// - Luo Dongjun, dongjun_luo@hotmail.com //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------------------------------------- |
// |
// AES core top module |
// |
// Description: |
// AES core top module with direct interface to key and data buses. |
// |
// To Do: |
// - done |
// |
// Author(s): |
// - Luo Dongjun, dongjun_luo@hotmail.com |
// |
//--------------------------------------------------------------------------------------- |
|
// uncomment the following define to enable use of distributed RAM implementation |
// for XILINX FPGAs instead of block memory. |
// NOTE: when commenting the following define, core size is slightly smaller but maximum |
// achievable clock frequency is also slightly lower. |
`define XILINX 1 |
|
module aes ( |
clk, |
reset, |
i_start, |
i_enable, |
i_ende, |
i_key, |
i_key_mode, |
i_data, |
i_data_valid, |
o_ready, |
o_data, |
o_data_valid, |
o_key_ready |
clk, reset, |
i_start, i_enable, |
i_ende, i_key, |
i_key_mode, i_data, |
i_data_valid, o_ready, |
o_data, o_data_valid, |
o_key_ready |
); |
|
input clk; |
input reset; |
input i_start; |
input i_enable; |
input [1:0] i_key_mode; // 0: 128; 1: 192; 2: 256 |
input [255:0] i_key; // if key size is 128/192, upper bits are the inputs |
input [127:0] i_data; |
input i_data_valid; |
input i_ende; // 0: encryption; 1: decryption |
output o_ready; // user shall not input data if IP is not ready |
output [127:0] o_data; // output data |
output o_data_valid; |
output o_key_ready; // key expansion procedure completes |
|
//--------------------------------------------------------------------------------------- |
// module interfaces |
input clk; // core global clock |
input reset; // core global async reset control |
input i_start; // key expansion start pulse |
input i_enable; // enable encryption / decryption core operation |
input [1:0] i_key_mode; // key length: 0 => 128; 1 => 192; 2 => 256 |
input [255:0] i_key; // if key size is 128/192, upper bits are the inputs |
input [127:0] i_data; // plain/cipher text data input |
input i_data_valid; // data input valid |
input i_ende; // core mode of operation: 0 => encryption; 1 => decryption |
output o_ready; // indicates core is ready for new input data at the next clock cycle |
output [127:0] o_data; // data output |
output o_data_valid; // data output valid |
output o_key_ready; // key expansion procedure done |
|
//--------------------------------------------------------------------------------------- |
// module registers and signals |
genvar i; |
wire final_round; |
reg [3:0] max_round; |
63,7 → 63,9
wire [4:0] wr_addr; |
wire [63:0] wr_data; |
wire [127:0] imc_round_key,en_ark_data,de_ark_data,ark_data_final,ark_data_init; |
|
|
//--------------------------------------------------------------------------------------- |
// module implementation |
assign final_round = sb_round_cnt3[3:0] == max_round[3:0]; |
//assign o_ready = ~sb_valid[1]; // if ready is asserted, user can input data for the same cycle |
assign o_ready = ~sb_valid[0]; // if ready is asserted, user can input data for the next cycle |
78,7 → 80,7
endcase |
end |
|
/*****************************************************************************/ |
//--------------------------------------------------------------------------------------- |
// Sub Bytes |
// |
// |
105,7 → 107,7
sb_data[127:0] <= i_ende ? de_sb_data[127:0] : en_sb_data[127:0]; |
end |
|
/*****************************************************************************/ |
//--------------------------------------------------------------------------------------- |
// Shift Rows |
// |
// |
116,7 → 118,7
|
assign sr_data[127:0] = i_ende ? ishrows : shrows; |
|
/*****************************************************************************/ |
//--------------------------------------------------------------------------------------- |
// Mix Columns |
// |
// |
136,13 → 138,13
end |
end |
|
/*****************************************************************************/ |
//--------------------------------------------------------------------------------------- |
// Inverse Mix Columns |
// |
// |
inv_mix_columns imxc_u (.in(sr_data), .out(imc_data)); |
|
/*****************************************************************************/ |
//--------------------------------------------------------------------------------------- |
// add round key for decryption |
// |
inv_mix_columns imxk_u (.in(round_key), .out(imc_round_key)); |
155,7 → 157,7
(final_round ? ark_data_final[127:0] : |
(i_ende ? de_ark_data[127:0] : en_ark_data[127:0])); |
|
/*****************************************************************************/ |
//--------------------------------------------------------------------------------------- |
// Data outputs after each round |
// |
always @ (posedge clk or posedge reset) |
166,7 → 168,7
o_data[127:0] <= ark_data[127:0]; |
end |
|
/*****************************************************************************/ |
//--------------------------------------------------------------------------------------- |
// in sbox, we have 3 stages (sb_valid), |
// before the end of each round, we have another stage (round_valid) |
// |
209,7 → 211,7
end |
end |
|
/*****************************************************************************/ |
//--------------------------------------------------------------------------------------- |
// round key generation: the expansion keys are stored in 4 16*32 rams or |
// 2 16*64 rams or 1 16*128 rams |
// |
288,7 → 290,7
.rd(sb_valid[1] | i_data_valid) |
); |
`endif |
/*****************************************************************************/ |
//--------------------------------------------------------------------------------------- |
// Key Expansion module |
// |
// |
305,4 → 307,4
); |
|
endmodule |
/*****************************************************************************/ |
//--------------------------------------------------------------------------------------- |
verilog/rtl
Property changes :
Added: svn:ignore
## -0,0 +1 ##
+*.bak
Index: verilog/sim/icarus/test.log
===================================================================
--- verilog/sim/icarus/test.log (nonexistent)
+++ verilog/sim/icarus/test.log (revision 8)
@@ -0,0 +1,104 @@
+
+-------------------------------------
+ AES_HT_LA Simulation
+-------------------------------------
+
+VCD info: dumpfile test.vcd opened for output.
+
+Testing encryption for 128 bit key:
+-------------------------------------
+Key: 128'h2b7e151628aed2a6abf7158809cf4f3c
+Key expansion done
+
+Plaintext Data 1: 128'hdda97ca4864cdfe06eaf70a0ec0d7191
+Plaintext Data 2: 128'h3243f6a8885a308d313198a2e0370731
+Plaintext Data 3: 128'h00112233445566778899aabbccddeeff
+Plaintext Data 4: 128'h8ea2b7ca516745bfeafc49904b496089
+
+Waiting for cipher text data
+Output Data 1: 128'hef0bc156ed8ff21223f247b3e0318a99
+Output Data 2: 128'hf91914cd01924b124c2ec316b4b35a79
+Output Data 3: 128'h8df4e9aac5c7573a27d8d055d6e4d64b
+Output Data 4: 128'hec8ce641087165a463d4118dc35f9001
+
+Testing decryption for 128 bit key:
+-------------------------------------
+Key: 128'h2b7e151628aed2a6abf7158809cf4f3c
+Using the same key, expansion is not required.
+
+Ciphertext Data 1: 128'hef0bc156ed8ff21223f247b3e0318a99
+Ciphertext Data 2: 128'hf91914cd01924b124c2ec316b4b35a79
+Ciphertext Data 3: 128'h8df4e9aac5c7573a27d8d055d6e4d64b
+Ciphertext Data 4: 128'hec8ce641087165a463d4118dc35f9001
+
+Waiting for plain text data
+Output Data 1: 128'hdda97ca4864cdfe06eaf70a0ec0d7191
+Output Data 2: 128'h3243f6a8885a308d313198a2e0370731
+Output Data 3: 128'h00112233445566778899aabbccddeeff
+Output Data 4: 128'h8ea2b7ca516745bfeafc49904b496089
+
+Testing encryption for 192 bit key:
+-------------------------------------
+Key: 192'h8e73b0f7da0e6452c810f32b809079e562f8ead2522c6b7b
+Key expansion done
+
+Plaintext Data 1: 128'hdda97ca4864cdfe06eaf70a0ec0d7191
+Plaintext Data 2: 128'h3243f6a8885a308d313198a2e0370731
+Plaintext Data 3: 128'h00112233445566778899aabbccddeeff
+Plaintext Data 4: 128'h8ea2b7ca516745bfeafc49904b496089
+
+Waiting for cipher text data
+Output Data 1: 128'h17d3cbb6a98f64ccd134e0d0b7695aa9
+Output Data 2: 128'h4a7d86377de2a8faf00f8ef97c2eb982
+Output Data 3: 128'heb1b03f2acb64bcf28c9991cc8a4fa50
+Output Data 4: 128'h2adc503e1c9b669de6b5bc904035547d
+
+Testing decryption for 192 bit key:
+-------------------------------------
+Key: 192'h8e73b0f7da0e6452c810f32b809079e562f8ead2522c6b7b
+Using the same key, expansion is not required.
+
+Ciphertext Data 1: 128'h17d3cbb6a98f64ccd134e0d0b7695aa9
+Ciphertext Data 2: 128'h4a7d86377de2a8faf00f8ef97c2eb982
+Ciphertext Data 3: 128'heb1b03f2acb64bcf28c9991cc8a4fa50
+Ciphertext Data 4: 128'h2adc503e1c9b669de6b5bc904035547d
+
+Waiting for plain text data
+Output Data 1: 128'hdda97ca4864cdfe06eaf70a0ec0d7191
+Output Data 2: 128'h3243f6a8885a308d313198a2e0370731
+Output Data 3: 128'h00112233445566778899aabbccddeeff
+Output Data 4: 128'h8ea2b7ca516745bfeafc49904b496089
+
+Testing encryption for 256 bit key:
+-------------------------------------
+Key: 256'h603deb1015ca71be2b73aef0857d77811f352c073b6108d7
+Key expansion done
+
+Plaintext Data 1: 128'hdda97ca4864cdfe06eaf70a0ec0d7191
+Plaintext Data 2: 128'h3243f6a8885a308d313198a2e0370731
+Plaintext Data 3: 128'h00112233445566778899aabbccddeeff
+Plaintext Data 4: 128'h8ea2b7ca516745bfeafc49904b496089
+
+Waiting for cipher text data
+Output Data 1: 128'h32573d9003bfd345029779298be53b96
+Output Data 2: 128'ha5f464b57512d05db2bae8d2415b921d
+Output Data 3: 128'hd83414223d20a0c928b136c884d07ea2
+Output Data 4: 128'hc1f968d2a6859137bd9ad9111ad7f6dc
+
+Testing decryption for 256 bit key:
+-------------------------------------
+Key: 256'h603deb1015ca71be2b73aef0857d77811f352c073b6108d72d9810a30914dff4
+Using the same key, expansion is not required.
+
+Ciphertext Data 1: 128'h32573d9003bfd345029779298be53b96
+Ciphertext Data 2: 128'ha5f464b57512d05db2bae8d2415b921d
+Ciphertext Data 3: 128'hd83414223d20a0c928b136c884d07ea2
+Ciphertext Data 4: 128'hc1f968d2a6859137bd9ad9111ad7f6dc
+
+Waiting for plain text data
+Output Data 1: 128'hdda97ca4864cdfe06eaf70a0ec0d7191
+Output Data 2: 128'h3243f6a8885a308d313198a2e0370731
+Output Data 3: 128'h00112233445566778899aabbccddeeff
+Output Data 4: 128'h8ea2b7ca516745bfeafc49904b496089
+
+ Simulation Done !!!
Index: verilog/syn/altera/aes_ht_la.qpf
===================================================================
--- verilog/syn/altera/aes_ht_la.qpf (nonexistent)
+++ verilog/syn/altera/aes_ht_la.qpf (revision 8)
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2011 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 11.1 Build 173 11/01/2011 SJ Web Edition
+# Date created = 12:00:49 March 30, 2012
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "11.1"
+DATE = "12:00:49 March 30, 2012"
+
+# Revisions
+
+PROJECT_REVISION = "aes_ht_la"
Index: verilog/syn/altera/aes_ht_la.sdc
===================================================================
--- verilog/syn/altera/aes_ht_la.sdc (nonexistent)
+++ verilog/syn/altera/aes_ht_la.sdc (revision 8)
@@ -0,0 +1,40 @@
+#************************************************************
+# THIS IS A WIZARD-GENERATED FILE.
+#
+# Version 11.1 Build 173 11/01/2011 SJ Web Edition
+#
+#************************************************************
+
+# Copyright (C) 1991-2011 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+
+# Clock constraints
+
+create_clock -name "clk" -period 10.000ns [get_ports {clk}]
+
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
Index: verilog/syn/xilinx/aes_top_example.ucf
===================================================================
--- verilog/syn/xilinx/aes_top_example.ucf (nonexistent)
+++ verilog/syn/xilinx/aes_top_example.ucf (revision 8)
@@ -0,0 +1,4 @@
+
+#Created by Constraints Editor (xc3s1500-fg676-4) - 2012/03/30
+NET "clk" TNM_NET = clk;
+TIMESPEC TS_clk = PERIOD "clk" 10 ns HIGH 50%;
Index: verilog/syn/xilinx/aes_ht_la.xise
===================================================================
--- verilog/syn/xilinx/aes_ht_la.xise (nonexistent)
+++ verilog/syn/xilinx/aes_ht_la.xise (revision 8)
@@ -0,0 +1,411 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+