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URL https://opencores.org/ocsvn/aes_pipe/aes_pipe/trunk

Subversion Repositories aes_pipe

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  • This comparison shows the changes necessary to convert path 
    /aes_pipe/trunk/bench/vhdl
    from Rev 9 to Rev 12
    ↔ Reverse comparison
  •

Rev 9 → Rev 12

/tb_aes.vhdl
73,7 → 73,8
signal key: datablock;
signal cipher: datablock;
signal rst: std_logic; -- reset input
signal op_start: std_logic; -- signal that simulation ended
signal op_start: std_logic; -- signal that output started
signal sim_end: std_logic := '0'; -- signal that simulation ended
constant clk_period: time := 10 ns;
 
component aes_top is
98,10 → 99,14
-- Generate clock
gen_clk: process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
if(sim_end = '0') then
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
else
wait;
end if;
end process;
-- Generate Reset
gen_rst: process
116,24 → 121,24
gen_in: process
file testfile: text open read_mode is "../src/vectors.dat";
variable line_in: line;
variable plaintext_byte, key_byte: std_logic_vector(7 downto 0);
variable plaintext_block, key_block: std_logic_vector(127 downto 0);
begin
if(endfile(testfile)) then
file_close(testfile);
wait;
end if;
readline(testfile, line_in);
hread(line_in, plaintext_block);
hread(line_in, key_block);
readline(testfile, line_in);
for i in 3 downto 0 loop
for j in 3 downto 0 loop
hread(line_in, plaintext_byte);
plaintext(3-j,3-i) <= plaintext_byte;
plaintext(3-j,3-i) <= plaintext_block((i*32 + j*8 + 7) downto (i*32 + j*8));
end loop;
end loop;
for i in 3 downto 0 loop
for j in 3 downto 0 loop
hread(line_in, key_byte);
key(3-j,3-i) <= key_byte;
key(3-j,3-i) <= key_block((i*32 + j*8 + 7) downto (i*32 + j*8));
end loop;
end loop;
151,25 → 156,39
-- Compare output with actual output file
op_chk: process
file chkfile: text open read_mode is "../src/cipher.dat";
file opfile: text open write_mode is "../log/output.log";
variable line_in, line_out_file, line_out: line;
variable exp_cipher_byte: std_logic_vector(7 downto 0);
file opfile: text open read_mode is "../src/cipher.dat";
file logfile: text open write_mode is "../log/output.log";
variable line_in, line_out, line_out_file: line;
variable exp_cipher_block: std_logic_vector(127 downto 0);
variable succeded: boolean;
variable all_ok: boolean := true;
begin
-- if required cycles have passed
if(op_start = '1') then
if(endfile(chkfile)) then -- end of simulation
file_close(chkfile);
if(endfile(opfile)) then -- end of simulation
file_close(opfile);
if(all_ok = true) then
write(line_out, string'("OK"));
writeline(OUTPUT, line_out);
write(line_out_file, string'("OK"));
writeline(logfile, line_out_file);
else
write(line_out, string'("FAIL"));
writeline(OUTPUT, line_out);
write(line_out_file, string'("FAIL"));
writeline(logfile, line_out_file);
end if;
sim_end <= '1';
wait;
end if;
succeded := true;
readline(chkfile, line_in); -- read in one expected result
readline(opfile, line_in); -- read in one expected result
hread(line_in, exp_cipher_block); -- read in one byte
for i in 3 downto 0 loop
for j in 3 downto 0 loop
hread(line_in, exp_cipher_byte); -- read in one byte
if(exp_cipher_byte /= cipher(3-j,3-i)) then
if(exp_cipher_block((i*32 + j*8 + 7) downto (i*32 + j*8)) /= cipher(3-j,3-i)) then
succeded := false; -- check failed
all_ok := false;
end if;
end loop;
end loop;
176,17 → 195,17
-- writing the output line
for i in 3 downto 0 loop
for j in 3 downto 0 loop
hwrite(line_out, cipher(3-j,3-i));
hwrite(line_out_file, cipher(3-j,3-i));
hwrite(line_out, cipher(3-j,3-i));
end loop;
end loop;
write(line_out, ' ');
write(line_out_file, ' ');
write(line_out, ' ');
-- writing the comparison result
write(line_out_file, succeded);
write(line_out, succeded);
writeline(opfile, line_out_file);
writeline(OUTPUT, line_out);
write(line_out_file, succeded);
writeline(logfile, line_out_file);
end if;
wait for clk_period;
end process;

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