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URL https://opencores.org/ocsvn/aes_pipe/aes_pipe/trunk

Subversion Repositories aes_pipe

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  • This comparison shows the changes necessary to convert path 
    /aes_pipe/trunk/rtl/vhdl
    from Rev 5 to Rev 9
    ↔ Reverse comparison
  •

Rev 5 → Rev 9

/subsh.vhdl
44,7 → 44,7
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Last Modified: 25/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
72,6 → 72,7
entity sboxshr is
port(
clk: in std_logic;
rst: in std_logic;
blockin: in datablock;
fc3: in blockcol;
c0: in blockcol;
87,6 → 88,7
component sbox is
port(
clk: in std_logic;
rst: in std_logic;
bytein: in std_logic_vector(7 downto 0);
byteout: out std_logic_vector(7 downto 0)
);
97,14 → 99,17
g1: for j in 3 downto 0 generate
sub: sbox port map(
clk => clk,
rst => rst,
bytein => blockin(i,j),
byteout => blockout(i,(j-i) mod 4)
);
end generate;
end generate;
process(clk)
process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
nextkey <= zero_data;
elsif(rising_edge(clk)) then
-- col0 of nextkey = fc3 xor col0
-- col1 of nextkey = fc3 xor col0 xor col1
-- col2 of nextkey = fc3 xor col0 xor col1 xor col2
/aes_pkg.vhdl
44,7 → 44,7
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Last Modified: 25/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
-- Common library file containing common data path definitions
56,8 → 56,10
package aes_pkg is
-- A column of 4 bytes
type blockcol is array(3 downto 0) of std_logic_vector(7 downto 0);
constant zero_col: blockcol := (X"00", X"00", X"00", X"00");
-- A datablock of 16 bytes
type datablock is array(3 downto 0, 3 downto 0) of std_logic_vector(7 downto 0);
constant zero_data: datablock := ((X"00", X"00", X"00", X"00"),(X"00", X"00", X"00", X"00"), (X"00", X"00", X"00", X"00"), (X"00", X"00", X"00", X"00"));
-- Vector of columns
type colnet is array(natural range<>) of blockcol;
-- Vector of blocks
/aes_top.vhdl
1,8 → 1,27
----------------------------------------------------------------------
---- ----
---- Pipelined Aes IP Core ----
---- ----
---- This file is part of the Pipelined AES project ----
---- http://www.opencores.org/cores/aes_pipe/ ----
---- ----
---- Description ----
---- Implementation of AES IP core according to ----
---- FIPS PUB 197 specification document. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Subhasis Das, subhasis256@gmail.com ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
14,7 → 33,7
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
25,7 → 44,7
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Last Modified: 25/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
48,6 → 67,7
entity aes_top is
port(
clk_i: in std_logic;
rst_i: in std_logic;
plaintext_i: in datablock;
keyblock_i: in datablock;
ciphertext_o: out datablock
63,6 → 83,7
component sboxshr is
port(
clk: in std_logic;
rst: in std_logic;
blockin: in datablock;
fc3: in blockcol;
c0: in blockcol;
76,6 → 97,7
component colmix is
port(
clk: in std_logic;
rst: in std_logic;
datain: in datablock;
inrkey: in datablock;
outrkey: out datablock;
85,6 → 107,7
component addkey is
port(
clk: in std_logic;
rst: in std_logic;
roundkey: in datablock;
datain: in datablock;
rcon: in std_logic_vector(7 downto 0);
109,6 → 132,7
proc: for i in 8 downto 0 generate
add: addkey port map(
clk => clk_i,
rst => rst_i,
roundkey => key_m(i),
datain => textnet_m_a(i),
rcon => rcon(i),
121,6 → 145,7
);
sbox: sboxshr port map(
clk => clk_i,
rst => rst_i,
blockin => textnet_a_s(i),
fc3 => fc3(i),
c0 => c0(i),
132,6 → 157,7
);
mix: colmix port map(
clk => clk_i,
rst => rst_i,
datain => textnet_s_m(i),
inrkey => key_s(i),
outrkey => key_m(i+1),
140,6 → 166,7
end generate;
add_f_1: addkey port map(
clk => clk_i,
rst => rst_i,
roundkey => key_m(9),
datain => textnet_m_a(9),
rcon => rcon(9),
152,6 → 179,7
);
sbox_f_1: sboxshr port map(
clk => clk_i,
rst => rst_i,
blockin => textnet_a_s(9),
fc3 => fc3(9),
c0 => c0(9),
163,6 → 191,7
);
add_f: addkey port map(
clk => clk_i,
rst => rst_i,
roundkey => key_s(9),
datain => textnet_s_a,
rcon => X"00",
/colmix.vhdl
44,7 → 44,7
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Last Modified: 25/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
69,6 → 69,7
entity colmix is
port(
clk: in std_logic;
rst: in std_logic;
datain: in datablock;
inrkey: in datablock;
outrkey: out datablock;
80,6 → 81,7
component mixcol is
port(
clk: in std_logic;
rst: in std_logic;
in0: in std_logic_vector(7 downto 0);
in1: in std_logic_vector(7 downto 0);
in2: in std_logic_vector(7 downto 0);
96,6 → 98,7
g0: for i in 3 downto 0 generate
mix: mixcol port map(
clk => clk,
rst => rst,
in0 => datain(0, i),
in1 => datain(1, i),
in2 => datain(2, i),
106,9 → 109,11
out3 => dataout(3, i)
);
end generate;
process(clk)
process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
outrkey <= zero_data;
elsif(rising_edge(clk)) then
outrkey <= inrkey;
end if;
end process;
/mixcol.vhdl
44,7 → 44,7
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Last Modified: 25/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
74,6 → 74,7
entity mixcol is
port(
clk: in std_logic;
rst: in std_logic;
in0: in std_logic_vector(7 downto 0);
in1: in std_logic_vector(7 downto 0);
in2: in std_logic_vector(7 downto 0);
125,9 → 126,14
t3 <= d3 xor in3;
xored <= in0 xor in1 xor in2 xor in3;
process(clk)
process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
out0 <= X"00";
out1 <= X"00";
out2 <= X"00";
out3 <= X"00";
elsif(rising_edge(clk)) then
out0 <= xored xor t0 xor d1;
out1 <= xored xor t1 xor d2;
out2 <= xored xor t2 xor d3;
/sbox.vhdl
44,7 → 44,7
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Last Modified: 25/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
70,6 → 70,7
entity sbox is
port(
clk: in std_logic;
rst: in std_logic;
bytein: in std_logic_vector(7 downto 0);
byteout: out std_logic_vector(7 downto 0)
);
97,9 → 98,11
X"76", X"ab", X"d7", X"fe", X"2b", X"67", X"01", X"30", X"c5", X"6f", X"6b", X"f2", X"7b", X"77", X"7c", X"63"
);
begin
process(clk)
process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
byteout <= X"00";
elsif(rising_edge(clk)) then
byteout <= sbox_ram(conv_integer(bytein));
end if;
end process;
/keysched1.vhdl
44,7 → 44,7
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Last Modified: 25/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
71,6 → 71,7
entity keysched1 is
port(
clk: in std_logic;
rst: in std_logic;
roundkey: in datablock;
rcon: in std_logic_vector(7 downto 0);
fc3: out blockcol;
87,6 → 88,7
component sbox is
port(
clk: in std_logic;
rst: in std_logic;
bytein: in std_logic_vector(7 downto 0);
byteout: out std_logic_vector(7 downto 0)
);
95,21 → 97,25
begin
sub0: sbox port map(
clk => clk,
rst => rst,
bytein => roundkey(0, 3),
byteout => subst(3)
);
sub1: sbox port map(
clk => clk,
rst => rst,
bytein => roundkey(1, 3),
byteout => subst(0)
);
sub2: sbox port map(
clk => clk,
rst => rst,
bytein => roundkey(2, 3),
byteout => subst(1)
);
sub3: sbox port map(
clk => clk,
rst => rst,
bytein => roundkey(3, 3),
byteout => subst(2)
);
117,9 → 123,15
fc3(1) <= subst(1);
fc3(2) <= subst(2);
fc3(3) <= subst(3);
process(clk)
process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
rcon_d <= X"00";
c0 <= zero_col;
c1 <= zero_col;
c2 <= zero_col;
c3 <= zero_col;
elsif(rising_edge(clk)) then
rcon_d <= rcon;
for j in 3 downto 0 loop
c0(j) <= roundkey(j, 0);
/addkey.vhdl
44,7 → 44,7
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Last Modified: 25/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
73,6 → 73,7
entity addkey is
port(
clk: in std_logic;
rst: in std_logic;
roundkey: in datablock;
datain: in datablock;
rcon: in std_logic_vector(7 downto 0);
89,6 → 90,7
component keysched1 is
port(
clk: in std_logic;
rst: in std_logic;
roundkey: in datablock;
rcon: in std_logic_vector(7 downto 0);
fc3: out blockcol;
102,6 → 104,7
begin
step1: keysched1 port map(
clk => clk,
rst => rst,
roundkey => roundkey,
rcon => rcon,
fc3 => fc3,
116,9 → 119,11
end generate;
end generate;
process(clk)
process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
dataout <= zero_data;
elsif(rising_edge(clk)) then
dataout <= added;
end if;
end process;

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