OpenCores
URL https://opencores.org/ocsvn/aes_pipe/aes_pipe/trunk

Subversion Repositories aes_pipe

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /aes_pipe
    from Rev 11 to Rev 12
    ↔ Reverse comparison
  •

Rev 11 → Rev 12

/trunk/bench/vhdl/tb_aes.vhdl
73,7 → 73,8
signal key: datablock;
signal cipher: datablock;
signal rst: std_logic; -- reset input
signal op_start: std_logic; -- signal that simulation ended
signal op_start: std_logic; -- signal that output started
signal sim_end: std_logic := '0'; -- signal that simulation ended
constant clk_period: time := 10 ns;
 
component aes_top is
98,10 → 99,14
-- Generate clock
gen_clk: process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
if(sim_end = '0') then
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
else
wait;
end if;
end process;
-- Generate Reset
gen_rst: process
116,24 → 121,24
gen_in: process
file testfile: text open read_mode is "../src/vectors.dat";
variable line_in: line;
variable plaintext_byte, key_byte: std_logic_vector(7 downto 0);
variable plaintext_block, key_block: std_logic_vector(127 downto 0);
begin
if(endfile(testfile)) then
file_close(testfile);
wait;
end if;
readline(testfile, line_in);
hread(line_in, plaintext_block);
hread(line_in, key_block);
readline(testfile, line_in);
for i in 3 downto 0 loop
for j in 3 downto 0 loop
hread(line_in, plaintext_byte);
plaintext(3-j,3-i) <= plaintext_byte;
plaintext(3-j,3-i) <= plaintext_block((i*32 + j*8 + 7) downto (i*32 + j*8));
end loop;
end loop;
for i in 3 downto 0 loop
for j in 3 downto 0 loop
hread(line_in, key_byte);
key(3-j,3-i) <= key_byte;
key(3-j,3-i) <= key_block((i*32 + j*8 + 7) downto (i*32 + j*8));
end loop;
end loop;
151,25 → 156,39
-- Compare output with actual output file
op_chk: process
file chkfile: text open read_mode is "../src/cipher.dat";
file opfile: text open write_mode is "../log/output.log";
variable line_in, line_out_file, line_out: line;
variable exp_cipher_byte: std_logic_vector(7 downto 0);
file opfile: text open read_mode is "../src/cipher.dat";
file logfile: text open write_mode is "../log/output.log";
variable line_in, line_out, line_out_file: line;
variable exp_cipher_block: std_logic_vector(127 downto 0);
variable succeded: boolean;
variable all_ok: boolean := true;
begin
-- if required cycles have passed
if(op_start = '1') then
if(endfile(chkfile)) then -- end of simulation
file_close(chkfile);
if(endfile(opfile)) then -- end of simulation
file_close(opfile);
if(all_ok = true) then
write(line_out, string'("OK"));
writeline(OUTPUT, line_out);
write(line_out_file, string'("OK"));
writeline(logfile, line_out_file);
else
write(line_out, string'("FAIL"));
writeline(OUTPUT, line_out);
write(line_out_file, string'("FAIL"));
writeline(logfile, line_out_file);
end if;
sim_end <= '1';
wait;
end if;
succeded := true;
readline(chkfile, line_in); -- read in one expected result
readline(opfile, line_in); -- read in one expected result
hread(line_in, exp_cipher_block); -- read in one byte
for i in 3 downto 0 loop
for j in 3 downto 0 loop
hread(line_in, exp_cipher_byte); -- read in one byte
if(exp_cipher_byte /= cipher(3-j,3-i)) then
if(exp_cipher_block((i*32 + j*8 + 7) downto (i*32 + j*8)) /= cipher(3-j,3-i)) then
succeded := false; -- check failed
all_ok := false;
end if;
end loop;
end loop;
176,17 → 195,17
-- writing the output line
for i in 3 downto 0 loop
for j in 3 downto 0 loop
hwrite(line_out, cipher(3-j,3-i));
hwrite(line_out_file, cipher(3-j,3-i));
hwrite(line_out, cipher(3-j,3-i));
end loop;
end loop;
write(line_out, ' ');
write(line_out_file, ' ');
write(line_out, ' ');
-- writing the comparison result
write(line_out_file, succeded);
write(line_out, succeded);
writeline(opfile, line_out_file);
writeline(OUTPUT, line_out);
write(line_out_file, succeded);
writeline(logfile, line_out_file);
end if;
wait for clk_period;
end process;
/trunk/doc/aes_arch.tex
67,7 → 67,7
 
The sample testbench is in \texttt{trunk/bench/vhdl}.
 
For compiling and running the testbench, the script \texttt{sim.sh} in \texttt{trunk/sim/rtl\_sim/run} directory can be used. It uses Xilinx free Isim simulator. The testbench takes in plaintext and key data from \texttt{vectors.dat} in \texttt{trunk/sim/rtl\_sim/src} directory. The expected ciphertext data should be present in \texttt{cipher.dat} in \texttt{trunk/sim/rtl\_sim/src} directory. The results are written to \texttt{output.log} in \texttt{trunk/sim/rtl\_sim/log} directory.
For compiling and running the testbench, the script \texttt{sim\_isim.sh} in \texttt{trunk/sim/rtl\_sim/run} directory can be used for Xilinx ISim simulator and \texttt{sim\_ghdl.sh} for GHDL. The testbench takes in plaintext and key data from \texttt{vectors.dat} in \texttt{trunk/sim/rtl\_sim/src} directory. The expected ciphertext data should be present in \texttt{cipher.dat} in \texttt{trunk/sim/rtl\_sim/src} directory. The results are written to \texttt{output.log} in \texttt{trunk/sim/rtl\_sim/log} directory. The final line is 'OK' if all tests pass, else it is 'FAIL'. This can be used to automate checkings over large test datasets.
 
The \texttt{trunk/syn/Xilinx/run} directory contains the \texttt{synth.sh} shell script, which will synthesize the design when run using Xilinx ISE WebPack tools.
 
/trunk/doc/aes_arch.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/sim/rtl_sim/log/output.log
1,3 → 1,4
47711816E91D6FF059BBBF2BF58E0FD3 TRUE
6DD1A447C5FA7F071774DF130EFB2E2E TRUE
6E29201190152DF4EE058139DEF610BB TRUE
OK
/trunk/sim/rtl_sim/run/sim.sh File deleted
/trunk/sim/rtl_sim/run/sim_ghdl.sh
0,0 → 1,15
#!/bin/sh
SRCROOT=../../../rtl/vhdl
TBROOT=../../../bench/vhdl
ghdl -a --ieee=synopsys $SRCROOT/aes_pkg.vhdl
ghdl -a --ieee=synopsys $SRCROOT/sbox.vhdl
ghdl -a --ieee=synopsys $SRCROOT/subsh.vhdl
ghdl -a --ieee=synopsys $SRCROOT/mixcol.vhdl
ghdl -a --ieee=synopsys $SRCROOT/colmix.vhdl
ghdl -a --ieee=synopsys $SRCROOT/keysched1.vhdl
ghdl -a --ieee=synopsys $SRCROOT/addkey.vhdl
ghdl -a --ieee=synopsys $SRCROOT/aes_top.vhdl
ghdl -a --ieee=synopsys $TBROOT/tb_aes.vhdl
ghdl -e --ieee=synopsys tb_aes
./tb_aes
ghdl --clean
trunk/sim/rtl_sim/run/sim_ghdl.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/rtl_sim/run/sim_isim.sh =================================================================== --- trunk/sim/rtl_sim/run/sim_isim.sh (nonexistent) +++ trunk/sim/rtl_sim/run/sim_isim.sh (revision 12) @@ -0,0 +1,3 @@ +#!/bin/sh +fuse -incremental -o tb.exe -prj ../src/tb_aes.prj tb_aes +./tb.exe
trunk/sim/rtl_sim/run/sim_isim.sh Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ##

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.