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URL https://opencores.org/ocsvn/aes_pipe/aes_pipe/trunk

Subversion Repositories aes_pipe

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  • This comparison shows the changes necessary to convert path 
    /aes_pipe
    from Rev 8 to Rev 9
    ↔ Reverse comparison
  •

Rev 8 → Rev 9

/trunk/bench/vhdl/tb_aes.vhdl
1,8 → 1,27
----------------------------------------------------------------------
---- ----
---- Pipelined Aes IP Core ----
---- ----
---- This file is part of the Pipelined AES project ----
---- http://www.opencores.org/cores/aes_pipe/ ----
---- ----
---- Description ----
---- Implementation of AES IP core according to ----
---- FIPS PUB 197 specification document. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Subhasis Das, subhasis256@gmail.com ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
14,18 → 33,18
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http:--www.opencores.org/lgpl.shtml ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Last Modified: 25/03/10
-- Email: subhasis256@gmail.com
--
-- TODO: Test with NIST test vectors
32,12 → 51,15
------------------------------------------------------
--
-- Description: Testbench for AESFast
-- Takes in data and keys from ../src/vectors.dat
-- Takes in true output values from ../src/cipher.dat
-- Writes all the output to ../log/output.log
------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
 
library work;
use work.aes_pkg.all;
46,16 → 68,18
end tb_aes;
 
architecture rtl of tb_aes is
signal clk: std_logic;
signal clk: std_logic; -- clock
signal plaintext: datablock;
signal key: datablock;
signal cipher: datablock;
signal start: std_logic := '0';
signal done: std_logic;
signal rst: std_logic; -- reset input
signal op_start: std_logic; -- signal that simulation ended
constant clk_period: time := 10 ns;
 
component aes_top is
port(
clk_i: in std_logic;
rst_i: in std_logic;
plaintext_i: in datablock;
keyblock_i: in datablock;
ciphertext_o: out datablock
63,43 → 87,107
end component;
 
begin
g0: for i in 3 downto 0 generate
g1: for j in 3 downto 1 generate
plaintext(i,j) <= X"00";
key(i,j) <= X"00";
end generate;
end generate;
plaintext(3,0) <= X"00";
plaintext(2,0) <= X"00";
plaintext(1,0) <= X"00";
key(3,0) <= X"00";
key(2,0) <= X"00";
key(1,0) <= X"00";
key(0,0) <= X"00";
proc0: aes_top port map(
clk_i => clk,
plaintext_i => plaintext,
keyblock_i => key,
ciphertext_o => cipher
);
-- The wiring of the top module
DUT: aes_top port map(
clk_i => clk,
rst_i => rst,
plaintext_i => plaintext,
keyblock_i => key,
ciphertext_o => cipher
);
-- Generate clock
gen_clk: process
begin
wait for 10 ns;
clk <= '1';
wait for 10 ns;
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;
-- Generate Reset
gen_rst: process
begin
rst <= '1';
wait for clk_period/2; -- generate reset
rst <= '0';
wait;
end process;
-- generate the inputs and check against expected output
gen_in: process
file testfile: text open read_mode is "../src/vectors.dat";
variable line_in: line;
variable plaintext_byte, key_byte: std_logic_vector(7 downto 0);
begin
wait for 25 ns;
plaintext(0,0) <= X"00";
wait for 20 ns;
plaintext(0,0) <= X"01";
wait for 20 ns;
plaintext(0,0) <= X"02";
wait for 40 ns;
plaintext(0,0) <= X"03";
if(endfile(testfile)) then
file_close(testfile);
wait;
end if;
readline(testfile, line_in);
for i in 3 downto 0 loop
for j in 3 downto 0 loop
hread(line_in, plaintext_byte);
plaintext(3-j,3-i) <= plaintext_byte;
end loop;
end loop;
for i in 3 downto 0 loop
for j in 3 downto 0 loop
hread(line_in, key_byte);
key(3-j,3-i) <= key_byte;
end loop;
end loop;
wait for clk_period;
end process;
-- Generate a signal to indicate that valid output has begun
op_begin: process
begin
wait for 30*clk_period;
wait for clk_period/2;
op_start <= '1';
wait;
end process;
-- Compare output with actual output file
op_chk: process
file chkfile: text open read_mode is "../src/cipher.dat";
file opfile: text open write_mode is "../log/output.log";
variable line_in, line_out_file, line_out: line;
variable exp_cipher_byte: std_logic_vector(7 downto 0);
variable succeded: boolean;
begin
-- if required cycles have passed
if(op_start = '1') then
if(endfile(chkfile)) then -- end of simulation
file_close(chkfile);
wait;
end if;
succeded := true;
readline(chkfile, line_in); -- read in one expected result
for i in 3 downto 0 loop
for j in 3 downto 0 loop
hread(line_in, exp_cipher_byte); -- read in one byte
if(exp_cipher_byte /= cipher(3-j,3-i)) then
succeded := false; -- check failed
end if;
end loop;
end loop;
-- writing the output line
for i in 3 downto 0 loop
for j in 3 downto 0 loop
hwrite(line_out_file, cipher(3-j,3-i));
hwrite(line_out, cipher(3-j,3-i));
end loop;
end loop;
write(line_out_file, ' ');
write(line_out, ' ');
-- writing the comparison result
write(line_out_file, succeded);
write(line_out, succeded);
writeline(opfile, line_out_file);
writeline(OUTPUT, line_out);
end if;
wait for clk_period;
end process;
end rtl;
/trunk/rtl/vhdl/subsh.vhdl
44,7 → 44,7
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Last Modified: 25/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
72,6 → 72,7
entity sboxshr is
port(
clk: in std_logic;
rst: in std_logic;
blockin: in datablock;
fc3: in blockcol;
c0: in blockcol;
87,6 → 88,7
component sbox is
port(
clk: in std_logic;
rst: in std_logic;
bytein: in std_logic_vector(7 downto 0);
byteout: out std_logic_vector(7 downto 0)
);
97,14 → 99,17
g1: for j in 3 downto 0 generate
sub: sbox port map(
clk => clk,
rst => rst,
bytein => blockin(i,j),
byteout => blockout(i,(j-i) mod 4)
);
end generate;
end generate;
process(clk)
process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
nextkey <= zero_data;
elsif(rising_edge(clk)) then
-- col0 of nextkey = fc3 xor col0
-- col1 of nextkey = fc3 xor col0 xor col1
-- col2 of nextkey = fc3 xor col0 xor col1 xor col2
/trunk/rtl/vhdl/aes_pkg.vhdl
44,7 → 44,7
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Last Modified: 25/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
-- Common library file containing common data path definitions
56,8 → 56,10
package aes_pkg is
-- A column of 4 bytes
type blockcol is array(3 downto 0) of std_logic_vector(7 downto 0);
constant zero_col: blockcol := (X"00", X"00", X"00", X"00");
-- A datablock of 16 bytes
type datablock is array(3 downto 0, 3 downto 0) of std_logic_vector(7 downto 0);
constant zero_data: datablock := ((X"00", X"00", X"00", X"00"),(X"00", X"00", X"00", X"00"), (X"00", X"00", X"00", X"00"), (X"00", X"00", X"00", X"00"));
-- Vector of columns
type colnet is array(natural range<>) of blockcol;
-- Vector of blocks
/trunk/rtl/vhdl/aes_top.vhdl
1,8 → 1,27
----------------------------------------------------------------------
---- ----
---- Pipelined Aes IP Core ----
---- ----
---- This file is part of the Pipelined AES project ----
---- http://www.opencores.org/cores/aes_pipe/ ----
---- ----
---- Description ----
---- Implementation of AES IP core according to ----
---- FIPS PUB 197 specification document. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Subhasis Das, subhasis256@gmail.com ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
14,7 → 33,7
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
25,7 → 44,7
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Last Modified: 25/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
48,6 → 67,7
entity aes_top is
port(
clk_i: in std_logic;
rst_i: in std_logic;
plaintext_i: in datablock;
keyblock_i: in datablock;
ciphertext_o: out datablock
63,6 → 83,7
component sboxshr is
port(
clk: in std_logic;
rst: in std_logic;
blockin: in datablock;
fc3: in blockcol;
c0: in blockcol;
76,6 → 97,7
component colmix is
port(
clk: in std_logic;
rst: in std_logic;
datain: in datablock;
inrkey: in datablock;
outrkey: out datablock;
85,6 → 107,7
component addkey is
port(
clk: in std_logic;
rst: in std_logic;
roundkey: in datablock;
datain: in datablock;
rcon: in std_logic_vector(7 downto 0);
109,6 → 132,7
proc: for i in 8 downto 0 generate
add: addkey port map(
clk => clk_i,
rst => rst_i,
roundkey => key_m(i),
datain => textnet_m_a(i),
rcon => rcon(i),
121,6 → 145,7
);
sbox: sboxshr port map(
clk => clk_i,
rst => rst_i,
blockin => textnet_a_s(i),
fc3 => fc3(i),
c0 => c0(i),
132,6 → 157,7
);
mix: colmix port map(
clk => clk_i,
rst => rst_i,
datain => textnet_s_m(i),
inrkey => key_s(i),
outrkey => key_m(i+1),
140,6 → 166,7
end generate;
add_f_1: addkey port map(
clk => clk_i,
rst => rst_i,
roundkey => key_m(9),
datain => textnet_m_a(9),
rcon => rcon(9),
152,6 → 179,7
);
sbox_f_1: sboxshr port map(
clk => clk_i,
rst => rst_i,
blockin => textnet_a_s(9),
fc3 => fc3(9),
c0 => c0(9),
163,6 → 191,7
);
add_f: addkey port map(
clk => clk_i,
rst => rst_i,
roundkey => key_s(9),
datain => textnet_s_a,
rcon => X"00",
/trunk/rtl/vhdl/colmix.vhdl
44,7 → 44,7
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Last Modified: 25/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
69,6 → 69,7
entity colmix is
port(
clk: in std_logic;
rst: in std_logic;
datain: in datablock;
inrkey: in datablock;
outrkey: out datablock;
80,6 → 81,7
component mixcol is
port(
clk: in std_logic;
rst: in std_logic;
in0: in std_logic_vector(7 downto 0);
in1: in std_logic_vector(7 downto 0);
in2: in std_logic_vector(7 downto 0);
96,6 → 98,7
g0: for i in 3 downto 0 generate
mix: mixcol port map(
clk => clk,
rst => rst,
in0 => datain(0, i),
in1 => datain(1, i),
in2 => datain(2, i),
106,9 → 109,11
out3 => dataout(3, i)
);
end generate;
process(clk)
process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
outrkey <= zero_data;
elsif(rising_edge(clk)) then
outrkey <= inrkey;
end if;
end process;
/trunk/rtl/vhdl/mixcol.vhdl
44,7 → 44,7
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Last Modified: 25/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
74,6 → 74,7
entity mixcol is
port(
clk: in std_logic;
rst: in std_logic;
in0: in std_logic_vector(7 downto 0);
in1: in std_logic_vector(7 downto 0);
in2: in std_logic_vector(7 downto 0);
125,9 → 126,14
t3 <= d3 xor in3;
xored <= in0 xor in1 xor in2 xor in3;
process(clk)
process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
out0 <= X"00";
out1 <= X"00";
out2 <= X"00";
out3 <= X"00";
elsif(rising_edge(clk)) then
out0 <= xored xor t0 xor d1;
out1 <= xored xor t1 xor d2;
out2 <= xored xor t2 xor d3;
/trunk/rtl/vhdl/sbox.vhdl
44,7 → 44,7
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Last Modified: 25/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
70,6 → 70,7
entity sbox is
port(
clk: in std_logic;
rst: in std_logic;
bytein: in std_logic_vector(7 downto 0);
byteout: out std_logic_vector(7 downto 0)
);
97,9 → 98,11
X"76", X"ab", X"d7", X"fe", X"2b", X"67", X"01", X"30", X"c5", X"6f", X"6b", X"f2", X"7b", X"77", X"7c", X"63"
);
begin
process(clk)
process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
byteout <= X"00";
elsif(rising_edge(clk)) then
byteout <= sbox_ram(conv_integer(bytein));
end if;
end process;
/trunk/rtl/vhdl/keysched1.vhdl
44,7 → 44,7
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Last Modified: 25/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
71,6 → 71,7
entity keysched1 is
port(
clk: in std_logic;
rst: in std_logic;
roundkey: in datablock;
rcon: in std_logic_vector(7 downto 0);
fc3: out blockcol;
87,6 → 88,7
component sbox is
port(
clk: in std_logic;
rst: in std_logic;
bytein: in std_logic_vector(7 downto 0);
byteout: out std_logic_vector(7 downto 0)
);
95,21 → 97,25
begin
sub0: sbox port map(
clk => clk,
rst => rst,
bytein => roundkey(0, 3),
byteout => subst(3)
);
sub1: sbox port map(
clk => clk,
rst => rst,
bytein => roundkey(1, 3),
byteout => subst(0)
);
sub2: sbox port map(
clk => clk,
rst => rst,
bytein => roundkey(2, 3),
byteout => subst(1)
);
sub3: sbox port map(
clk => clk,
rst => rst,
bytein => roundkey(3, 3),
byteout => subst(2)
);
117,9 → 123,15
fc3(1) <= subst(1);
fc3(2) <= subst(2);
fc3(3) <= subst(3);
process(clk)
process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
rcon_d <= X"00";
c0 <= zero_col;
c1 <= zero_col;
c2 <= zero_col;
c3 <= zero_col;
elsif(rising_edge(clk)) then
rcon_d <= rcon;
for j in 3 downto 0 loop
c0(j) <= roundkey(j, 0);
/trunk/rtl/vhdl/addkey.vhdl
44,7 → 44,7
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 20/03/10
-- Last Modified: 25/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
--
73,6 → 73,7
entity addkey is
port(
clk: in std_logic;
rst: in std_logic;
roundkey: in datablock;
datain: in datablock;
rcon: in std_logic_vector(7 downto 0);
89,6 → 90,7
component keysched1 is
port(
clk: in std_logic;
rst: in std_logic;
roundkey: in datablock;
rcon: in std_logic_vector(7 downto 0);
fc3: out blockcol;
102,6 → 104,7
begin
step1: keysched1 port map(
clk => clk,
rst => rst,
roundkey => roundkey,
rcon => rcon,
fc3 => fc3,
116,9 → 119,11
end generate;
end generate;
process(clk)
process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
dataout <= zero_data;
elsif(rising_edge(clk)) then
dataout <= added;
end if;
end process;
/trunk/sim/rtl_sim/log/output.log
0,0 → 1,3
47711816E91D6FF059BBBF2BF58E0FD3 TRUE
6DD1A447C5FA7F071774DF130EFB2E2E TRUE
6E29201190152DF4EE058139DEF610BB TRUE
/trunk/sim/rtl_sim/run/sim.sh
0,0 → 1,3
#!/bin/sh
fuse -incremental -o tb.exe -prj ../src/tb_aes.prj tb_aes
./tb.exe
/trunk/sim/rtl_sim/src/cipher.dat
0,0 → 1,3
47711816e91d6ff059bbbf2bf58e0fd3
6dd1a447c5fa7f071774df130efb2e2e
6e29201190152df4ee058139def610bb
/trunk/sim/rtl_sim/src/vectors.dat
0,0 → 1,3
01000000000000000000000000000000 00000000000000000000000000000000
02000000000000000000000000000000 00000000000000000000000000000001
00000000000000000000000000000000 caea65cdbb75e9169ecd22ebe6e54675

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