OpenCores
URL https://opencores.org/ocsvn/alternascope/alternascope/trunk

Subversion Repositories alternascope

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /alternascope/tags/rels2/AdcDriver
    from Rev 7 to Rev 30
    ↔ Reverse comparison
  •

Rev 7 → Rev 30

/d_Driver_RamBuffer.v
0,0 → 1,207
//==================================================================
// File: d_Driver_RamBuffer.v
// Version: 0.01
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Copyright Stephen Pickett
// April 28, 2005
//------------------------------------------------------------------
// Revisions:
// Ver 0.01 Apr 28, 2005 Initial Release
//
//==================================================================
 
module ADCDataBuffer(
CLK_64MHZ, MASTER_RST,
CLK180_64MHZ,
TIME_BASE,
RAM_ADDR, RAM_DATA, RAM_CLK,
ADC_DATA, ADC_CLK,
TRIG_ADDR,
VGA_WRITE_DONE,
TRIGGER_LEVEL
);
//==================================================================//
// PARAMETER DEFINITIONS //
//==================================================================//
parameter ss_wait_for_trig = 2'b00;
parameter ss_fill_mem_half = 2'b01;
parameter ss_write_buffer = 2'b11;
parameter ss_invalid = 2'b10;
parameter P_trigger_level = 8'h80;
 
 
//==================================================================//
// VARIABLE DEFINITIONS //
//==================================================================//
 
//----------------------//
// INPUTS / OUTPUTS //
//----------------------//
input CLK_64MHZ;
input CLK180_64MHZ;
input MASTER_RST; // Global Asyncronous Reset
input[5:0] TIME_BASE; // The selected V/Div
input[10:0] RAM_ADDR;
output[7:0] RAM_DATA;
input RAM_CLK;
input[7:0] ADC_DATA;
output ADC_CLK;
output[10:0] TRIG_ADDR;
input VGA_WRITE_DONE;
input[8:0] TRIGGER_LEVEL;
 
//----------------------//
// WIRES / NODES //
//----------------------//
wire CLK_64MHZ, MASTER_RST, CLK180_64MHZ;
wire[5:0] TIME_BASE;
wire[10:0] RAM_ADDR;
wire[7:0] RAM_DATA;
wire RAM_CLK;
wire[7:0] ADC_DATA;
wire ADC_CLK;
reg[10:0] TRIG_ADDR;
wire VGA_WRITE_DONE;
wire[8:0] TRIGGER_LEVEL;
 
//----------------------//
// VARIABLES //
//----------------------//
 
 
 
//==================================================================//
// 'SUB-ROUTINES' //
//==================================================================//
 
//------------------------------------------------------------------//
// Instanstiate the ADC //
//------------------------------------------------------------------//
wire[7:0] DATA_FROM_ADC;
Driver_ADC ADC(
.CLK_64MHZ(CLK_64MHZ),
.MASTER_RST(MASTER_RST),
.TIME_BASE(TIME_BASE),
.ADC_CLK(ADC_CLK),
.ADC_DATA(ADC_DATA),
.DATA_OUT(DATA_FROM_ADC)
);
 
//------------------------------------------------------------------//
// Initialize the RAMs WE WILL NEED MORE! //
// RAM is structured as follows: //
// Dual-Access RAM //
// 18kBits -> 2048Bytes + 1Parity/Byte //
// Access A: 8bit + 1parity (ADC_Write) //
// Access B: 8bit + 1parity (Read) //
//------------------------------------------------------------------//
reg[10:0] ADDRA;
wire VCC, GND;
assign VCC = 1'b1;
assign GND = 1'b0;
 
RAMB16_S9_S9 ADC_QuasiFifo_Buffer(
.DOA(), .DOB(RAM_DATA),
.DOPA(), .DOPB(),
.ADDRA(ADDRA), .ADDRB(RAM_ADDR),
.CLKA(CLK180_64MHZ), .CLKB(RAM_CLK),
.DIA(DATA_FROM_ADC), .DIB(8'b0),
.DIPA(GND), .DIPB(GND),
.ENA(VCC), .ENB(VCC),
.WEA(VCC), .WEB(GND),
.SSRA(GND), .SSRB(GND)
);
 
//==================================================================//
// FUNCTIONAL DEFINITIONS //
//==================================================================//
 
reg[1:0] sm_trig;
reg trigger_detected;
reg[9:0] cnt_1024bytes;
reg mem_half_full;
 
/* THE RAM WRITING TRIGGERING STATE MACHINE */
always @ (posedge CLK_64MHZ or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1)
sm_trig <= ss_wait_for_trig;
else if(sm_trig == ss_wait_for_trig && trigger_detected == 1'b1)
sm_trig <= ss_fill_mem_half;
else if(sm_trig == ss_fill_mem_half && mem_half_full == 1'b1)
sm_trig <= ss_write_buffer;
else if(sm_trig == ss_write_buffer && trigger_detected == 1'b0 && VGA_WRITE_DONE == 1'b1)
sm_trig <= ss_wait_for_trig;
else if(sm_trig == ss_invalid)
sm_trig <= ss_wait_for_trig;
else
sm_trig <= sm_trig;
end
 
 
/* THIS PART DEALS WITH THE ADDRESS OF THE ADC BUFFER */
/* Write in a Circular Buffer soft of way */
always @ (posedge ADC_CLK or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
ADDRA <= 11'b0;
end else if(sm_trig == ss_wait_for_trig || sm_trig == ss_fill_mem_half)
ADDRA <= ADDRA + 1;
else
ADDRA <= ADDRA;
end
 
/* LATCHING THE TRIGGER */
always @ (ADC_DATA) begin
// if(ADC_DATA >= P_trigger_level)
if(ADC_DATA >= TRIGGER_LEVEL)
trigger_detected = 1'b1;
else
trigger_detected = 1'b0;
end
 
/* GATHERING 1024 MORE BYTES OF MEMORY */
always @ (posedge ADC_CLK or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1)
cnt_1024bytes <= 10'b0;
else if(sm_trig == ss_fill_mem_half)
cnt_1024bytes <= cnt_1024bytes + 1;
else
cnt_1024bytes <= cnt_1024bytes;
end
 
always @ (cnt_1024bytes) begin
if(cnt_1024bytes == 10'h3FF)
mem_half_full = 1'b1;
else
mem_half_full = 1'b0;
end
 
/* STORING THE TRIGGER ADDRESS */
always @ (posedge trigger_detected or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1)
TRIG_ADDR <= 11'd0;
else
TRIG_ADDR <= ADDRA;
end
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
endmodule
/d_DCM.xaw
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.2e
$9ax4>7<8=1;"=7>;0685+5302;=+eM?813867=58;199?5<2695*6(7;`=0M_MGWHX23>GU_SUDBAWPC@Q@EAOIOVIGG<64ASUY[JHKQVIGGD@PEYVFVKGK9k1J^ZTPOONZ[AEJWZ]BXNFFNF]@HN773HX\VRAALX]G@WYD88:0M_YU_NLO]ZBCZVI:=<5NRVX\KKJ^WMNYSNBD179BVR\XGGFRSIJ]_GNJTCJHX8?0M_YU_NLO]Z@EWLR_I_@NL008EWQ]WFDGURGASU]MQHc<I[]QSB@CY^RNGA703HX\VRAALX]QAFIIN@MT\D@\149BVR\XGGFRS_K\EU]OKBOD911J^ZTPOONZ[SGKAMUOJ^QBOEGb?DUTGJU\EYF>3:CT^ZEKCK_M=RLCKOCNA43<I^PTOAEMUG3\MZUNOGKFI<;4AVX\GIME]O;TCR]FGOCNAc=F_SUH@FLZFU[SA4b<I^PTOAEBUY]J5f=F_SUM@BY[YQG;?DQ]WYKYXi5NW[]P]KRO\FEG86L@TI68FP@@:01H6QA|c]ZjhlhTMxbzh||\@f`@woqm{VoSIMB.yct0>EKC9<0OAE>81a8GIM609U=8@FU6:AOO717=2IGG?V7;BNH6]7?8<1H@F7?5:AOOAPd3JF@H[QKIWKGA0=DDBLI96MCKGZ;?FJLNQ;3<n5LLJD[5=6XJ\L:>6MCKGZ2<5YE]OMTEC][9:AOOC^XJ\Lm7NBDFY]AQCAXAGY_o6MCKGZ\@LPNLLo0OAEIX^OVHQOWDP?0OAEFN038GIMNFVNBZDJJ_C[\6g=DDBCESDLZFF33?FJLAGUBNXHH_HLPPc=DDBCESDLZFF]LQQ><KEABBRGAc:AOOLHXXLXBCIk4CMIJJZUUKV^R\H?=;BNHKPRXXAKXIR]GIGV:?FJLW?>FDWm4CMI\B@CCJHI@j6MCK^MVPUSSW]S[I45LOLOJPQCC?2IYILZJD29GGH><LJGTEC][d:FFWNCPWHNAY^Z>2:FEWZ@UMX_NBNWPMNFF57=CDEUM^H_ZEOAZ[HICM<1O_^KA149GQQ_XKPIGIRM@RSG@PLII?2NTZLBZE99F\QCUFHFj7KOLTNPZ[O@23OKG_H74FC]PKPTDM01MECQZNHVPe>@H]]U^BDZ\a:DLQQYQIE_N>6HW1:K6?LDRNN;:7GG[TDP\MKVR\V^R\Hm4JHVWAWYWC;Z@o6DFTUGQ[SGK]L<0@BOKEEa8HJEFD[E^XD@H6:NLGNCCi2FDOFKK_NWW7>JH_k1GCZ]DEVNJJ@5<EAPi7@QNNE]G[VRU?2GTZLBZE69MAQQHZB>0BB@J1:M;?J@CL[I[Io5_H@QF[VNNN]30\D@GAR@VWd=WAGCXKCJJD99SMKQNL]B37]\FMU[SA46<X[E[S]GAIRC@PLPB=2ZXOAE9;QQGKKC33YYNB55_SHL@@@E43[Y_:6\\T^KMf>UNOLR_I_@NL79PMKAKMj1XXL\[UQ]TELR13Z^JXX]>2:QZWQCJWZSEOE\@NNWP7>RHX=1_^XKi;TQFHJEFD[E^XD@Hf:WPAIIP[BO\@D@JS99VW@YE]OM37X]J_FPJ@0=QAL]:n6VNW^TFVVOHF8n0TDBFNY/[@G&7&8*XXXL/0/3#EVENA:1S_Y84Xe`\Ma773QnfS@oeosTfvvohf8:0TicPMhllvScu{`ee96U?:1_6?^6=?T>0myu3:f`ig=qm{ybcc.>.168rmbkm2rh?~<?0,6ep731uIJ{?:5O@y07>C<?28qX89477;::>456n;>j6?m934ym<6<63g2?6?5+838;4>{T<:03;766:012b72f2;i2oo5\5`8;3?>>289:j?:m:9353>U3;32<6575123e61d=08ih7^;n:959<<<6;8l98o4746;8W15=0>0357?<1g07f?>30?1X9l477;::>456n;>i6n6>a:Q77?>02131=>?i25`9g=be3m2<6=4>:0yP01<??3226<=>f36b>7e1;<1}X:k50;395??|[=>14:479;305c43i38h:>;4b6:94?6=:33p(o478:&2b?>f3-8;65l4$339<4=#?o0j7o:9:1827?6=8r.=n7::;%a96f=#l3=?7)k5249'b?423-;;6?84$03960=#9;0=:6*>3;57?!732:1/=8494:&23?2a3-;36?<4$53921=#:m0=7)=::99'73<>3-9369h4$2f93>"4m3>o7)=i:768 11=?>1/8n47;%6;>0c<,=319h5+4c84=>"3m3?0(8>5659'14<182.>>78?;%70>5=#=>0==6*92;;8 31=92.<97:i;%5`>2b<,8<18k5+43860>"21380(8654:k03?6=,?k1485+6b84=>"6l3?=76g=e;29 3g=0<1/:4489:9j34<72-<j65;4$7a93<=<a?l1<7*9a;:6?!0>2>307d9?:18'2d<?=2.=5796;:k5`?6=,?k1485+6884=>=n<h0;6)8n:978 3?=?01/:n489:9l60<72-<j65;4;n0a>5<#>h03965`2783>!0f21?07b<7:18'2d<?=21d>n4?:%4b>=3<3f826=4+6`8;1>=h:h0;6)8n:978?j4a290/:l475:&5g?1>3-;n6=5+1e86b>"6k3>;76a<0;29 3g=0<1/:n489:&2a?6<,8n19k5+1b813>=h??0;6)8n:948 3>=?010c8m50;&5e?>23-<h6:74;n4f>5<#>h03965rb2c94?4=83:p(;l5579j10<72-<j65;4$7a93<=#9k08o65`6483>!0f21?0(;m5789'5f<4121v>750;0x910=;>16?l495:&2=?5e3ty<>7>51z?72?163-=868;4}r10>5<6s4>=6?h4$6c94>"613>;7)9m:19~w67=83;p1985319'3d<73-;26?94$6`94>{t=m0;6<u24786g>"0;3<>7p}<c;295~;4i3?>7)9<:478yv27290;w)9<:778yv40290;w)9<:778yv5e290;w)9<:778yxh5=3:1=vsa2783>4}zf;=1<7?t}o0;>5<6std957>51zm6d<728qvb?l50;3xyk4d290:wp`=d;295~{zutJKOv=8:0227=7dntJKNv>r@ARxyEF
/d_Driver_ADC.v
0,0 → 1,197
//==================================================================
// File: d_Driver_ADC.v
// Version: 0.01
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Copyright Stephen Pickett
// April 28, 2005
//------------------------------------------------------------------
// Revisions:
// Ver 0.01 Apr 28, 2005 Initial Release
//
//==================================================================
 
module Driver_ADC(
CLK_64MHZ, MASTER_RST,
TIME_BASE,
ADC_CLK, ADC_DATA,
DATA_OUT
);
 
//==================================================================//
// DEFINITIONS //
//==================================================================//
parameter US1 = 5'd0;
parameter US2 = 5'd1;
parameter US4 = 5'd2;
parameter US8 = 5'd3;
parameter US16 = 5'd4;
parameter US32 = 5'd5;
parameter US64 = 5'd6;
parameter US128 = 5'd7;
parameter US512 = 5'd8;
parameter US1024 = 5'd9;
parameter US2048 = 5'd10;
parameter US4096 = 5'd11;
parameter US8192 = 5'd12;
parameter US16384 = 5'd13;
parameter US32768 = 5'd14;
parameter US65536 = 5'd15;
parameter US131072 = 5'd16;
parameter US262144 = 5'd17;
parameter US524288 = 5'd18;
parameter US1048576 = 5'd19;
parameter US2097152 = 5'd20;
parameter US4194304 = 5'd21;
parameter US8388608 = 5'd22;
 
 
//==================================================================//
// VARIABLE DEFINITIONS //
//==================================================================//
 
//----------------------//
// INPUTS / OUTPUTS //
//----------------------//
input CLK_64MHZ; // Global System Clock
input MASTER_RST; // Global Asyncronous Reset
input[5:0] TIME_BASE; // The selected V/Div
input[7:0] ADC_DATA; // Data recieved from ADC
output ADC_CLK; // Clock out to the ADC
output[7:0] DATA_OUT; // Data output (essentially buffered from ADC by one clk)
 
//----------------------//
// WIRES / NODES //
//----------------------//
wire CLK_64MHZ, MASTER_RST;
wire[5:0] TIME_BASE;
wire[7:0] ADC_DATA;
reg ADC_CLK;
wire [7:0] DATA_OUT;
 
//----------------------//
// VARIABLES //
//----------------------//
 
 
 
 
//==================================================================//
// FUNCTIONAL DEFINITIONS //
//==================================================================//
 
 
 
//------------------------------------------------------------------//
// CLOCK GENERATION AND SELECTION //
//------------------------------------------------------------------//
reg[15:0] Counter_CLK;
wire CLK_32MHZ, CLK_16MHZ, CLK_8MHZ, CLK_4MHZ, CLK_2MHZ, CLK_1MHZ, CLK_500KHZ, CLK_250KHZ, CLK_125KHZ,
CLK_62KHZ, CLK_31KHZ, CLK_16KHZ, CLK_8KHZ, CLK_4KHZ, CLK_2KHZ, CLK_1KHZ;
 
always @ (posedge CLK_64MHZ or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
Counter_CLK <= 16'b0;
end else begin
Counter_CLK <= Counter_CLK + 1;
end
end
 
assign CLK_32MHZ = Counter_CLK[0];
assign CLK_16MHZ = Counter_CLK[1];
assign CLK_8MHZ = Counter_CLK[2];
assign CLK_4MHZ = Counter_CLK[3];
assign CLK_2MHZ = Counter_CLK[4];
assign CLK_1MHZ = Counter_CLK[5];
assign CLK_500KHZ = Counter_CLK[6];
assign CLK_250KHZ = Counter_CLK[7];
assign CLK_125KHZ = Counter_CLK[8];
assign CLK_62KHZ = Counter_CLK[9];
assign CLK_31KHZ = Counter_CLK[10];
assign CLK_16KHZ = Counter_CLK[11];
assign CLK_8KHZ = Counter_CLK[12];
assign CLK_4KHZ = Counter_CLK[13];
assign CLK_2KHZ = Counter_CLK[14];
assign CLK_1KHZ = Counter_CLK[15];
//assign CLK_500HZ = Counter_CLK[16];
 
 
always @ (TIME_BASE or MASTER_RST or CLK_64MHZ or CLK_32MHZ or CLK_16MHZ or
CLK_8MHZ or CLK_4MHZ or CLK_2MHZ or CLK_1MHZ or CLK_500KHZ or CLK_250KHZ or
CLK_125KHZ or CLK_62KHZ or CLK_31KHZ or CLK_16KHZ or CLK_8KHZ or CLK_4KHZ or
CLK_2KHZ or CLK_1KHZ) begin
if(MASTER_RST == 1'b1) begin
ADC_CLK = 1'b0;
end else if(TIME_BASE == 6'd0) begin // 1us/Div, 1samp/pxl
ADC_CLK = CLK_64MHZ;
end else if(TIME_BASE == 6'd1) begin // 2us/Div, 2samp/pxl
ADC_CLK = CLK_64MHZ;
end else if(TIME_BASE == 6'd2) begin // 4us/Div, 2samp/pxl
ADC_CLK = CLK_32MHZ;
end else if(TIME_BASE == 6'd3) begin // 8us/Div, 2samp/pxl
ADC_CLK = CLK_16MHZ;
end else if(TIME_BASE == 6'd4) begin // 16us/Div, 2samp/pxl
ADC_CLK = CLK_8MHZ;
end else if(TIME_BASE == 6'd5) begin // 32us/Div, 2samp/pxl
ADC_CLK = CLK_4MHZ;
end else if(TIME_BASE == 6'd6) begin // 64us/Div, 2samp/pxl
ADC_CLK = CLK_2MHZ;
end else if(TIME_BASE == 6'd7) begin // 128us/Div, 2samp/pxl
ADC_CLK = CLK_1MHZ;
end else if(TIME_BASE == 6'd8) begin // 256us/Div, 2samp/pxl
ADC_CLK = CLK_500KHZ;
end else if(TIME_BASE == 6'd9) begin // 512us/Div, 2samp/pxl
ADC_CLK = CLK_250KHZ;
end else if(TIME_BASE == 6'd10) begin // ...
ADC_CLK = CLK_125KHZ;
end else if(TIME_BASE == 6'd11) begin
ADC_CLK = CLK_62KHZ;
end else if(TIME_BASE == 6'd12) begin
ADC_CLK = CLK_31KHZ;
end else if(TIME_BASE == 6'd13) begin
ADC_CLK = CLK_16KHZ;
end else if(TIME_BASE == 6'd14) begin
ADC_CLK = CLK_8KHZ;
end else if(TIME_BASE == 6'd15) begin
ADC_CLK = CLK_4KHZ;
end else if(TIME_BASE == 6'd16) begin
ADC_CLK = CLK_2KHZ;
end else if(TIME_BASE == 6'd17) begin
ADC_CLK = CLK_1KHZ;
// end else if(TIME_BASE == 6'd18) begin
// ADC_CLK = CLK_500HZ;
/*
end else if(TIME_BASE == 6'd19) begin
ADC_CLK = CLK_US524288;
end else if(TIME_BASE == 6'd20) begin
ADC_CLK = CLK_US1048576;
end else if(TIME_BASE == 6'd21) begin
ADC_CLK = CLK_US2097152;
end else if(TIME_BASE == 6'd22) begin
ADC_CLK = CLK_US4194304;
end else if(TIME_BASE == 6'd23) begin
ADC_CLK = CLK_US8388608;
*/
end else begin
ADC_CLK = 1'b0;
end
end
//------------------------------------------------------------------//
// ADC DATA READING //
//------------------------------------------------------------------//
/*
always @ (negedge ADC_CLK or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
DATA_OUT <= 8'b0;
end else begin
DATA_OUT <= ADC_DATA;
end
end
*/
 
assign DATA_OUT = ADC_DATA;
 
endmodule
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.