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    /altor32/trunk/rtl/cpu_lite
    from Rev 34 to Rev 36
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Rev 34 → Rev 36

/altor32_regfile_sim.v
1,9 → 1,9
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// V2.1
// Ultra-Embedded.com
// Copyright 2011 - 2013
// Copyright 2011 - 2014
//
// Email: admin@ultra-embedded.com
//
/altor32_regfile_xil.v
1,9 → 1,9
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// V2.1
// Ultra-Embedded.com
// Copyright 2011 - 2013
// Copyright 2011 - 2014
//
// Email: admin@ultra-embedded.com
//
/altor32_lite.v
1,9 → 1,9
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// V2.1
// Ultra-Embedded.com
// Copyright 2011 - 2013
// Copyright 2011 - 2014
//
// Email: admin@ultra-embedded.com
//
120,6 → 120,14
wire alu_carry_out;
wire alu_carry_update;
 
// ALU Comparisons
wire compare_equal_w;
wire compare_gts_w;
wire compare_gt_w;
wire compare_lts_w;
wire compare_lt_w;
wire alu_flag_update;
 
// ALU operation selection
reg [3:0] r_e_alu_func;
 
174,7 → 182,15
 
// Carry
.c_o(alu_carry_out),
.c_update_o(alu_carry_update)
.c_update_o(alu_carry_update),
 
// Comparisons
.equal_o(compare_equal_w),
.greater_than_signed_o(compare_gts_w),
.greater_than_o(compare_gt_w),
.less_than_signed_o(compare_lts_w),
.less_than_o(compare_lt_w),
.flag_update_o(alu_flag_update)
);
 
// Writeback result
278,7 → 294,7
 
// Sub instructions
alu_op_r = {r_opcode[9:6],r_opcode[3:0]};
sfxx_op_r = {5'b00,r_opcode[31:21]};
sfxx_op_r = {5'b00,r_opcode[31:21]} & `INST_OR32_SFMASK;
shift_op_r = r_opcode[7:6];
 
// Branch target
355,30 → 371,18
wire inst_sfxx_w = (inst_r == `INST_OR32_SFXX);
wire inst_sfxxi_w = (inst_r == `INST_OR32_SFXXI);
 
wire inst_sfeq_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFEQ); // l.sfeq
wire inst_sfges_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFGES); // l.sfges
wire inst_sfeq_w = (inst_sfxx_w || inst_sfxxi_w) & (sfxx_op_r == `INST_OR32_SFEQ); // l.sfeq
wire inst_sfges_w = (inst_sfxx_w || inst_sfxxi_w) & (sfxx_op_r == `INST_OR32_SFGES); // l.sfges
 
wire inst_sfgeu_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFGEU); // l.sfgeu
wire inst_sfgts_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFGTS); // l.sfgts
wire inst_sfgtu_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFGTU); // l.sfgtu
wire inst_sfles_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFLES); // l.sfles
wire inst_sfleu_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFLEU); // l.sfleu
wire inst_sflts_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFLTS); // l.sflts
wire inst_sfltu_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFLTU); // l.sfltu
wire inst_sfne_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFNE); // l.sfne
wire inst_sfgeu_w = (inst_sfxx_w || inst_sfxxi_w) & (sfxx_op_r == `INST_OR32_SFGEU); // l.sfgeu
wire inst_sfgts_w = (inst_sfxx_w || inst_sfxxi_w) & (sfxx_op_r == `INST_OR32_SFGTS); // l.sfgts
wire inst_sfgtu_w = (inst_sfxx_w || inst_sfxxi_w) & (sfxx_op_r == `INST_OR32_SFGTU); // l.sfgtu
wire inst_sfles_w = (inst_sfxx_w || inst_sfxxi_w) & (sfxx_op_r == `INST_OR32_SFLES); // l.sfles
wire inst_sfleu_w = (inst_sfxx_w || inst_sfxxi_w) & (sfxx_op_r == `INST_OR32_SFLEU); // l.sfleu
wire inst_sflts_w = (inst_sfxx_w || inst_sfxxi_w) & (sfxx_op_r == `INST_OR32_SFLTS); // l.sflts
wire inst_sfltu_w = (inst_sfxx_w || inst_sfxxi_w) & (sfxx_op_r == `INST_OR32_SFLTU); // l.sfltu
wire inst_sfne_w = (inst_sfxx_w || inst_sfxxi_w) & (sfxx_op_r == `INST_OR32_SFNE); // l.sfne
 
wire inst_sfeqi_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFEQI); // l.sfeqi
wire inst_sfgesi_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFGESI); // l.sfgesi
wire inst_sfgeui_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFGEUI); // l.sfgeui
wire inst_sfgtsi_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFGTSI); // l.sfgtsi
wire inst_sfgtui_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFGTUI); // l.sfgtui
wire inst_sflesi_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFLESI); // l.sflesi
 
wire inst_sfleui_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFLEUI); // l.sfleui
wire inst_sfltsi_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFLTSI); // l.sfltsi
wire inst_sfltui_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFLTUI); // l.sfltui
wire inst_sfnei_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFNEI); // l.sfnei
 
wire inst_sys_w = (inst_r == `INST_OR32_MISC) & (r_opcode[31:24] == `INST_OR32_SYS); // l.sys
wire inst_trap_w = (inst_r == `INST_OR32_MISC) & (r_opcode[31:24] == `INST_OR32_TRAP); // l.trap
 
685,6 → 689,10
begin
next_sr_r = r_sr;
 
// Update SR.F
if (alu_flag_update)
next_sr_r[`OR32_SR_F] = compare_result_r;
 
// Latch carry if updated
if (alu_carry_update)
next_sr_r[`OR32_SR_CY] = alu_carry_out;
944,6 → 952,22
write_rd_r = 1'b1;
end
 
// l.sf*i
inst_sfxxi_w:
begin
alu_func_r = `ALU_COMPARE;
alu_input_a_r = reg_ra_r;
alu_input_b_r = int32_r;
end
 
// l.sf*
inst_sfxx_w:
begin
alu_func_r = `ALU_COMPARE;
alu_input_a_r = reg_ra_r;
alu_input_b_r = reg_rb_r;
end
 
// l.lbs l.lhs l.lws l.lbz l.lhz l.lwz
inst_lbs_w,
inst_lhs_w,
968,107 → 992,39
//-----------------------------------------------------------------
// Comparisons
//-----------------------------------------------------------------
 
reg [31:0] compare_a_r;
reg [31:0] compare_b_r;
always @ *
begin
compare_a_r = reg_ra_r;
compare_b_r = reg_rb_r;
 
case (1'b1)
inst_sfeqi_w, // l.sfeqi
inst_sfgesi_w, // l.sfgesi
inst_sfgeui_w, // l.sfgeui
inst_sfgtsi_w, // l.sfgtsi
inst_sfgtui_w, // l.sfgtui
inst_sflesi_w, // l.sflesi
inst_sfleui_w, // l.sfleui
inst_sfltsi_w, // l.sfltsi
inst_sfltui_w, // l.sfltui
inst_sfnei_w: // l.sfnei
compare_b_r = int32_r;
default:
;
endcase
end
inst_sfges_w: // l.sfges
compare_result_r = compare_gts_w | compare_equal_w;
 
reg compare_equal_r;
reg compare_gts_r;
reg compare_gt_r;
reg compare_lts_r;
reg compare_lt_r;
always @ *
begin
if (compare_a_r == compare_b_r)
compare_equal_r = 1'b1;
else
compare_equal_r = 1'b0;
inst_sfgeu_w: // l.sfgeu
compare_result_r = compare_gt_w | compare_equal_w;
 
compare_lts_r = less_than_signed(compare_a_r, compare_b_r);
inst_sfgts_w: // l.sfgts
compare_result_r = compare_gts_w;
 
if (compare_a_r < compare_b_r)
compare_lt_r = 1'b1;
else
compare_lt_r = 1'b0;
inst_sfgtu_w: // l.sfgtu
compare_result_r = compare_gt_w;
 
// Greater than (signed)
compare_gts_r = ~(compare_lts_r | compare_equal_r);
inst_sfles_w: // l.sfles
compare_result_r = compare_lts_w | compare_equal_w;
 
if (compare_a_r > compare_b_r)
compare_gt_r = 1'b1;
else
compare_gt_r = 1'b0;
end
inst_sfleu_w: // l.sfleu
compare_result_r = compare_lt_w | compare_equal_w;
 
always @ *
begin
compare_result_r = 1'b0;
inst_sflts_w: // l.sflts
compare_result_r = compare_lts_w;
 
case (1'b1)
inst_sfeq_w, // l.sfeq
inst_sfeqi_w: // l.sfeqi
compare_result_r = compare_equal_r;
inst_sfltu_w: // l.sfltu
compare_result_r = compare_lt_w;
 
inst_sfges_w, // l.sfges
inst_sfgesi_w: // l.sfgesi
compare_result_r = compare_gts_r | compare_equal_r;
inst_sfne_w: // l.sfne
compare_result_r = ~compare_equal_w;
 
inst_sfgeu_w, // l.sfgeu
inst_sfgeui_w: // l.sfgeui
compare_result_r = compare_gt_r | compare_equal_r;
 
inst_sfgts_w, // l.sfgts
inst_sfgtsi_w: // l.sfgtsi
compare_result_r = compare_gts_r;
 
inst_sfgtu_w, // l.sfgtu
inst_sfgtui_w: // l.sfgtui
compare_result_r = compare_gt_r;
 
inst_sfles_w, // l.sfles
inst_sflesi_w: // l.sflesi
compare_result_r = compare_lts_r | compare_equal_r;
 
inst_sfleu_w, // l.sfleu
inst_sfleui_w: // l.sfleui
compare_result_r = compare_lt_r | compare_equal_r;
 
inst_sflts_w, // l.sflts
inst_sfltsi_w: // l.sfltsi
compare_result_r = compare_lts_r;
 
inst_sfltu_w, // l.sfltu
inst_sfltui_w: // l.sfltui
compare_result_r = compare_lt_r;
 
inst_sfne_w, // l.sfne
inst_sfnei_w: // l.sfnei
compare_result_r = ~compare_equal_r;
 
default:
;
endcase
default: // l.sfeq
compare_result_r = compare_equal_w;
endcase
end
 
//-----------------------------------------------------------------
1190,25 → 1146,15
inst_srai_w,
inst_srli_w,
inst_sfeq_w,
inst_sfeqi_w,
inst_sfges_w,
inst_sfgesi_w,
inst_sfgeu_w,
inst_sfgeui_w,
inst_sfgts_w,
inst_sfgtsi_w,
inst_sfgtu_w,
inst_sfgtui_w,
inst_sfles_w,
inst_sflesi_w,
inst_sfleu_w,
inst_sfleui_w,
inst_sflts_w,
inst_sfltsi_w,
inst_sfltu_w,
inst_sfltui_w,
inst_sfne_w,
inst_sfnei_w,
inst_sys_w,
inst_trap_w:
invalid_inst_r = 1'b0;
/altor32_regfile_alt.v
1,9 → 1,9
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// V2.1
// Ultra-Embedded.com
// Copyright 2011 - 2013
// Copyright 2011 - 2014
//
// Email: admin@ultra-embedded.com
//
51,8 → 51,8
input [4:0] rs_i /*verilator public*/,
input [4:0] rt_i /*verilator public*/,
input [4:0] rd_i /*verilator public*/,
output [31:0] reg_rs_o /*verilator public*/,
output [31:0] reg_rt_o /*verilator public*/,
output reg [31:0] reg_rs_o /*verilator public*/,
output reg [31:0] reg_rt_o /*verilator public*/,
input [31:0] reg_rd_i /*verilator public*/
);
 
64,14 → 64,11
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg clk_delayed;
wire clk_delayed;
wire [31:0] data_out1;
wire [31:0] data_out2;
reg write_enable;
 
reg [31:0] reg_rs_o;
reg [31:0] reg_rt_o;
 
reg [4:0] addr_reg;
reg [31:0] data_reg;
 
/altor32_funcs.v
1,9 → 1,9
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// V2.1
// Ultra-Embedded.com
// Copyright 2011 - 2013
// Copyright 2011 - 2014
//
// Email: admin@ultra-embedded.com
//
/altor32.v
1,9 → 1,9
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// V2.1
// Ultra-Embedded.com
// Copyright 2011 - 2013
// Copyright 2011 - 2014
//
// Email: admin@ultra-embedded.com
//
/altor32_alu.v
1,9 → 1,9
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// V2.1
// Ultra-Embedded.com
// Copyright 2011 - 2013
// Copyright 2011 - 2014
//
// Email: admin@ultra-embedded.com
//
39,6 → 39,7
// Includes
//-----------------------------------------------------------------
`include "altor32_defs.v"
`include "altor32_funcs.v"
 
//-----------------------------------------------------------------
// Module - ALU
58,7 → 59,15
 
// Carry
output reg c_o /*verilator public*/,
output reg c_update_o /*verilator public*/
output reg c_update_o /*verilator public*/,
 
// Comparison
output reg equal_o /*verilator public*/,
output reg greater_than_signed_o /*verilator public*/,
output reg greater_than_o /*verilator public*/,
output reg less_than_signed_o /*verilator public*/,
output reg less_than_o /*verilator public*/,
output flag_update_o /*verilator public*/
);
 
//-----------------------------------------------------------------
206,4 → 215,30
 
assign p_o = result;
 
//-----------------------------------------------------------------
// Comparisons
//-----------------------------------------------------------------
always @ *
begin
if (a_i == b_i)
equal_o = 1'b1;
else
equal_o = 1'b0;
 
if (a_i < b_i)
less_than_o = 1'b1;
else
less_than_o = 1'b0;
 
if (a_i > b_i)
greater_than_o = 1'b1;
else
greater_than_o = 1'b0;
 
less_than_signed_o = less_than_signed(a_i, b_i);
greater_than_signed_o = ~(less_than_signed_o | equal_o);
end
 
assign flag_update_o = (op_i == `ALU_COMPARE);
 
endmodule
/altor32_defs.v
1,9 → 1,9
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// V2.1
// Ultra-Embedded.com
// Copyright 2011 - 2013
// Copyright 2011 - 2014
//
// Email: admin@ultra-embedded.com
//
48,6 → 48,7
`define ALU_AND 4'b0111
`define ALU_OR 4'b1000
`define ALU_XOR 4'b1001
`define ALU_COMPARE 4'b1010
 
//-----------------------------------------------------------------
// ALU Instructions
106,26 → 107,17
//-----------------------------------------------------------------
`define INST_OR32_SFXX 8'h39
`define INST_OR32_SFXXI 8'h2F
`define INST_OR32_SFEQ 16'h0720
`define INST_OR32_SFEQI 16'h05E0
`define INST_OR32_SFGES 16'h072B
`define INST_OR32_SFGESI 16'h05EB
`define INST_OR32_SFGEU 16'h0723
`define INST_OR32_SFGEUI 16'h05E3
`define INST_OR32_SFGTS 16'h072A
`define INST_OR32_SFGTSI 16'h05EA
`define INST_OR32_SFGTU 16'h0722
`define INST_OR32_SFGTUI 16'h05E2
`define INST_OR32_SFLES 16'h072D
`define INST_OR32_SFLESI 16'h05ED
`define INST_OR32_SFLEU 16'h0725
`define INST_OR32_SFLEUI 16'h05E5
`define INST_OR32_SFLTS 16'h072C
`define INST_OR32_SFLTSI 16'h05EC
`define INST_OR32_SFLTU 16'h0724
`define INST_OR32_SFLTUI 16'h05E4
`define INST_OR32_SFNE 16'h0721
`define INST_OR32_SFNEI 16'h05E1
`define INST_OR32_SFMASK 16'hFD3F
`define INST_OR32_SFEQ 16'h0520
`define INST_OR32_SFGES 16'h052B
`define INST_OR32_SFGEU 16'h0523
`define INST_OR32_SFGTS 16'h052A
`define INST_OR32_SFGTU 16'h0522
`define INST_OR32_SFLES 16'h052D
`define INST_OR32_SFLEU 16'h0525
`define INST_OR32_SFLTS 16'h052C
`define INST_OR32_SFLTU 16'h0524
`define INST_OR32_SFNE 16'h0521
 
//-----------------------------------------------------------------
// Misc Instructions

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