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    /altor32/trunk/rtl/sim
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Rev 27 → Rev 32

/ram.v
1,4 → 1,41
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email: admin@ultra-embedded.com
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Module: ram - dual port block RAM
//-----------------------------------------------------------------
module ram
5,19 → 42,25
(
// Port A
input clka_i /*verilator public*/,
input ena_i /*verilator public*/,
input [3:0] wea_i /*verilator public*/,
input rsta_i /*verilator public*/,
input stba_i /*verilator public*/,
input wea_i /*verilator public*/,
input [3:0] sela_i /*verilator public*/,
input [31:2] addra_i /*verilator public*/,
input [31:0] dataa_i /*verilator public*/,
output [31:0] dataa_o /*verilator public*/,
output reg acka_o /*verilator public*/,
 
// Port B
input clkb_i /*verilator public*/,
input enb_i /*verilator public*/,
input [3:0] web_i /*verilator public*/,
input rstb_i /*verilator public*/,
input stbb_i /*verilator public*/,
input web_i /*verilator public*/,
input [3:0] selb_i /*verilator public*/,
input [31:2] addrb_i /*verilator public*/,
input [31:0] datab_i /*verilator public*/,
output [31:0] datab_o /*verilator public*/
output [31:0] datab_o /*verilator public*/,
output reg ackb_o /*verilator public*/
);
 
//-----------------------------------------------------------------
30,6 → 73,9
// Instantiation
//-----------------------------------------------------------------
 
wire [3:0] wr_a = {4{stba_i}} & {4{wea_i}} & sela_i;
wire [3:0] wr_b = {4{stbb_i}} & {4{web_i}} & selb_i;
 
ram_dp8
#(
.WIDTH(8),
41,13 → 87,13
.aadr_i(addra_i[SIZE+2-1:2]),
.adat_o(dataa_o[7:0]),
.adat_i(dataa_i[7:0]),
.awr_i(wea_i[0]),
.awr_i(wr_a[0]),
.bclk_i(clkb_i),
.badr_i(addrb_i[SIZE+2-1:2]),
.bdat_o(datab_o[7:0]),
.bdat_i(datab_i[7:0]),
.bwr_i(web_i[0])
.bwr_i(wr_b[0])
);
 
ram_dp8
61,13 → 107,13
.aadr_i(addra_i[SIZE+2-1:2]),
.adat_o(dataa_o[15:8]),
.adat_i(dataa_i[15:8]),
.awr_i(wea_i[1]),
.awr_i(wr_a[1]),
.bclk_i(clkb_i),
.badr_i(addrb_i[SIZE+2-1:2]),
.bdat_o(datab_o[15:8]),
.bdat_i(datab_i[15:8]),
.bwr_i(web_i[1])
.bwr_i(wr_b[1])
);
 
ram_dp8
81,13 → 127,13
.aadr_i(addra_i[SIZE+2-1:2]),
.adat_o(dataa_o[23:16]),
.adat_i(dataa_i[23:16]),
.awr_i(wea_i[2]),
.awr_i(wr_a[2]),
.bclk_i(clkb_i),
.badr_i(addrb_i[SIZE+2-1:2]),
.bdat_o(datab_o[23:16]),
.bdat_i(datab_i[23:16]),
.bwr_i(web_i[2])
.bwr_i(wr_b[2])
);
 
ram_dp8
101,13 → 147,39
.aadr_i(addra_i[SIZE+2-1:2]),
.adat_o(dataa_o[31:24]),
.adat_i(dataa_i[31:24]),
.awr_i(wea_i[3]),
.awr_i(wr_a[3]),
.bclk_i(clkb_i),
.badr_i(addrb_i[SIZE+2-1:2]),
.bdat_o(datab_o[31:24]),
.bdat_i(datab_i[31:24]),
.bwr_i(web_i[3])
.bwr_i(wr_b[3])
);
 
// AckA
always @(posedge clka_i or posedge rsta_i)
begin
if (rsta_i == 1'b1)
begin
acka_o <= 1'b0;
end
else
begin
acka_o <= stba_i;
end
end
 
// AckB
always @(posedge clkb_i or posedge rstb_i)
begin
if (rstb_i == 1'b1)
begin
ackb_o <= 1'b0;
end
else
begin
ackb_o <= stbb_i;
end
end
 
endmodule
/top.v
64,26 → 64,32
wire [31:0] soc_addr;
wire [31:0] soc_data_w;
wire [31:0] soc_data_r;
wire [3:0] soc_wr;
wire soc_rd;
wire soc_we;
wire soc_stb;
wire soc_ack;
wire soc_irq;
 
wire[31:0] dmem_address;
wire[31:0] dmem_data_w;
wire[31:0] dmem_data_r;
wire[3:0] dmem_wr;
wire dmem_rd;
wire dmem_burst;
wire[3:0] dmem_sel;
wire[2:0] dmem_cti;
wire dmem_we;
wire dmem_stb;
wire dmem_cyc;
wire dmem_stall;
wire dmem_ack;
reg dmem_req_r;
 
wire[31:0] imem_addr;
wire[31:0] imem_data;
wire imem_rd;
wire imem_burst;
wire[3:0] imem_sel;
wire imem_stb;
wire imem_cyc;
wire[2:0] imem_cti;
wire imem_stall;
wire imem_ack;
reg imem_req_r;
 
 
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
96,21 → 102,26
u_ram
(
.clka_i(clk_i),
.ena_i(1'b1),
.wea_i(4'b0),
.rsta_i(rst_i),
.stba_i(imem_stb),
.wea_i(1'b0),
.sela_i(imem_sel),
.addra_i(imem_addr[31:2]),
.dataa_i(32'b0),
.dataa_o(imem_data),
.acka_o(imem_ack),
 
.clkb_i(clk_i),
.enb_i(1'b1),
.web_i(dmem_wr),
.rstb_i(rst_i),
.stbb_i(dmem_stb),
.web_i(dmem_we),
.selb_i(dmem_sel),
.addrb_i(dmem_address[31:2]),
.datab_i(dmem_data_w),
.datab_o(dmem_data_r)
.datab_o(dmem_data_r),
.ackb_o(dmem_ack)
);
 
 
// CPU
cpu_if
#(
133,10 → 144,12
 
// Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
.imem0_addr_o(imem_addr),
.imem0_rd_o(imem_rd),
.imem0_burst_o(imem_burst),
.imem0_data_in_i(imem_data),
.imem0_accept_i(1'b1),
.imem0_data_i(imem_data),
.imem0_sel_o(imem_sel),
.imem0_cti_o(imem_cti),
.imem0_cyc_o(imem_cyc),
.imem0_stb_o(imem_stb),
.imem0_stall_i(1'b0),
.imem0_ack_i(imem_ack),
 
// Data Memory 0 (0x10000000 - 0x10FFFFFF)
143,20 → 156,24
.dmem0_addr_o(dmem_address),
.dmem0_data_o(dmem_data_w),
.dmem0_data_i(dmem_data_r),
.dmem0_wr_o(dmem_wr),
.dmem0_rd_o(dmem_rd),
.dmem0_accept_i(1'b1),
.dmem0_burst_o(dmem_burst),
.dmem0_sel_o(dmem_sel),
.dmem0_cti_o(dmem_cti),
.dmem0_cyc_o(dmem_cyc),
.dmem0_we_o(dmem_we),
.dmem0_stb_o(dmem_stb),
.dmem0_stall_i(1'b0),
.dmem0_ack_i(dmem_ack),
// Data Memory 1 (0x11000000 - 0x11FFFFFF)
.dmem1_addr_o(),
.dmem1_data_o(),
.dmem1_addr_o(/*open*/),
.dmem1_data_o(/*open*/),
.dmem1_data_i(32'b0),
.dmem1_wr_o(),
.dmem1_rd_o(),
.dmem1_accept_i(1'b1),
.dmem1_burst_o(/*open*/),
.dmem1_sel_o(/*open*/),
.dmem1_we_o(/*open*/),
.dmem1_stb_o(/*open*/),
.dmem1_cyc_o(/*open*/),
.dmem1_cti_o(/*open*/),
.dmem1_stall_i(1'b0),
.dmem1_ack_i(1'b1),
 
// Data Memory 2 (0x12000000 - 0x12FFFFFF)
163,11 → 180,13
.dmem2_addr_o(soc_addr),
.dmem2_data_o(soc_data_w),
.dmem2_data_i(soc_data_r),
.dmem2_wr_o(soc_wr),
.dmem2_rd_o(soc_rd),
.dmem2_accept_i(1'b1),
.dmem2_burst_o(/*open*/),
.dmem2_ack_i(1'b1)
.dmem2_sel_o(/*open*/),
.dmem2_we_o(soc_we),
.dmem2_stb_o(soc_stb),
.dmem2_cyc_o(/*open*/),
.dmem2_cti_o(/*open*/),
.dmem2_stall_i(1'b0),
.dmem2_ack_i(soc_ack)
);
 
// CPU SOC
190,38 → 209,9
.io_addr_i(soc_addr),
.io_data_i(soc_data_w),
.io_data_o(soc_data_r),
.io_wr_i(soc_wr),
.io_rd_i(soc_rd)
.io_we_i(soc_we),
.io_stb_i(soc_stb),
.io_ack_o(soc_ack)
);
 
// Ack
always @(posedge clk_i or posedge rst_i)
begin
if (rst_i == 1'b1)
begin
imem_req_r <= 1'b0;
end
else
begin
imem_req_r <= imem_rd;
end
end
 
assign imem_ack = imem_req_r;
 
// Ack
always @(posedge clk_i or posedge rst_i)
begin
if (rst_i == 1'b1)
begin
dmem_req_r <= 1'b0;
end
else
begin
dmem_req_r <= dmem_rd | (|dmem_wr);
end
end
 
assign dmem_ack = dmem_req_r;
endmodule
/ram_dp8.v
1,3 → 1,39
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email: admin@ultra-embedded.com
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Module: ram_dp8 - dual port block RAM

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