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    /altor32/trunk/rtl/soc
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Rev 27 → Rev 32

/dmem_mux3.v
1,3 → 1,39
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email: admin@ultra-embedded.com
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Module:
5,40 → 41,50
module dmem_mux3
(
// Outputs
out0_addr_o,
out0_data_o,
out0_data_i,
out0_wr_o,
out0_rd_o,
out0_burst_o,
out0_ack_i,
out0_accept_i,
out1_addr_o,
out1_data_o,
out1_data_i,
out1_wr_o,
out1_rd_o,
out1_burst_o,
out1_ack_i,
out1_accept_i,
out2_addr_o,
out2_data_o,
out2_data_i,
out2_wr_o,
out2_rd_o,
out2_burst_o,
out2_ack_i,
out2_accept_i,
output reg [31:0] out0_addr_o,
output reg [31:0] out0_data_o,
input [31:0] out0_data_i,
output reg [3:0] out0_sel_o,
output reg out0_we_o,
output reg out0_stb_o,
output reg out0_cyc_o,
output reg [2:0] out0_cti_o,
input out0_ack_i,
input out0_stall_i,
 
output reg [31:0] out1_addr_o,
output reg [31:0] out1_data_o,
input [31:0] out1_data_i,
output reg [3:0] out1_sel_o,
output reg out1_we_o,
output reg out1_stb_o,
output reg out1_cyc_o,
output reg [2:0] out1_cti_o,
input out1_ack_i,
input out1_stall_i,
 
output reg [31:0] out2_addr_o,
output reg [31:0] out2_data_o,
input [31:0] out2_data_i,
output reg [3:0] out2_sel_o,
output reg out2_we_o,
output reg out2_stb_o,
output reg out2_cyc_o,
output reg [2:0] out2_cti_o,
input out2_ack_i,
input out2_stall_i,
 
// Input
mem_addr_i,
mem_data_i,
mem_data_o,
mem_burst_i,
mem_wr_i,
mem_rd_i,
mem_ack_o,
mem_accept_o
input [31:0] mem_addr_i,
input [31:0] mem_data_i,
output reg[31:0] mem_data_o,
input [3:0] mem_sel_i,
input mem_we_i,
input mem_stb_i,
input mem_cyc_i,
input [2:0] mem_cti_i,
output reg mem_ack_o,
output reg mem_stall_o
);
 
//-----------------------------------------------------------------
47,87 → 93,32
parameter ADDR_MUX_START = 28;
 
//-----------------------------------------------------------------
// I/O
// Request
//-----------------------------------------------------------------
input [31:0] mem_addr_i /*verilator public*/;
input [31:0] mem_data_i /*verilator public*/;
output [31:0] mem_data_o /*verilator public*/;
input [3:0] mem_wr_i /*verilator public*/;
input mem_rd_i /*verilator public*/;
input mem_burst_i /*verilator public*/;
output mem_ack_o /*verilator public*/;
output mem_accept_o /*verilator public*/;
output [31:0] out0_addr_o /*verilator public*/;
output [31:0] out0_data_o /*verilator public*/;
input [31:0] out0_data_i /*verilator public*/;
output [3:0] out0_wr_o /*verilator public*/;
output out0_rd_o /*verilator public*/;
output out0_burst_o /*verilator public*/;
input out0_ack_i /*verilator public*/;
input out0_accept_i /*verilator public*/;
output [31:0] out1_addr_o /*verilator public*/;
output [31:0] out1_data_o /*verilator public*/;
input [31:0] out1_data_i /*verilator public*/;
output [3:0] out1_wr_o /*verilator public*/;
output out1_rd_o /*verilator public*/;
output out1_burst_o /*verilator public*/;
input out1_ack_i /*verilator public*/;
input out1_accept_i /*verilator public*/;
output [31:0] out2_addr_o /*verilator public*/;
output [31:0] out2_data_o /*verilator public*/;
input [31:0] out2_data_i /*verilator public*/;
output [3:0] out2_wr_o /*verilator public*/;
output out2_rd_o /*verilator public*/;
output out2_burst_o /*verilator public*/;
input out2_ack_i /*verilator public*/;
input out2_accept_i /*verilator public*/;
 
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
 
// Output Signals
reg mem_ack_o;
reg mem_accept_o;
reg [31:0] mem_data_o;
 
reg [31:0] out0_addr_o;
reg [31:0] out0_data_o;
reg [3:0] out0_wr_o;
reg out0_rd_o;
reg out0_burst_o;
reg [31:0] out1_addr_o;
reg [31:0] out1_data_o;
reg [3:0] out1_wr_o;
reg out1_rd_o;
reg out1_burst_o;
reg [31:0] out2_addr_o;
reg [31:0] out2_data_o;
reg [3:0] out2_wr_o;
reg out2_rd_o;
reg out2_burst_o;
 
//-----------------------------------------------------------------
// Memory Map
//-----------------------------------------------------------------
always @ (mem_addr_i or mem_wr_i or mem_rd_i or mem_data_i or mem_burst_i)
always @ *
begin
 
out0_addr_o = 32'h00000000;
out0_wr_o = 4'b0000;
out0_rd_o = 1'b0;
out0_data_o = 32'h00000000;
out0_burst_o = 1'b0;
out0_sel_o = 4'b0000;
out0_we_o = 1'b0;
out0_stb_o = 1'b0;
out0_cyc_o = 1'b0;
out0_cti_o = 3'b0;
out1_addr_o = 32'h00000000;
out1_wr_o = 4'b0000;
out1_rd_o = 1'b0;
out1_data_o = 32'h00000000;
out1_burst_o = 1'b0;
out1_sel_o = 4'b0000;
out1_we_o = 1'b0;
out1_stb_o = 1'b0;
out1_cyc_o = 1'b0;
out1_cti_o = 3'b0;
out2_addr_o = 32'h00000000;
out2_wr_o = 4'b0000;
out2_rd_o = 1'b0;
out2_data_o = 32'h00000000;
out2_burst_o = 1'b0;
out2_sel_o = 4'b0000;
out2_we_o = 1'b0;
out2_stb_o = 1'b0;
out2_cyc_o = 1'b0;
out2_cti_o = 3'b0;
 
case (mem_addr_i[ADDR_MUX_START+2-1:ADDR_MUX_START])
 
134,26 → 125,32
2'd0:
begin
out0_addr_o = mem_addr_i;
out0_wr_o = mem_wr_i;
out0_rd_o = mem_rd_i;
out0_data_o = mem_data_i;
out0_burst_o = mem_burst_i;
out0_sel_o = mem_sel_i;
out0_we_o = mem_we_i;
out0_stb_o = mem_stb_i;
out0_cyc_o = mem_cyc_i;
out0_cti_o = mem_cti_i;
end
2'd1:
begin
out1_addr_o = mem_addr_i;
out1_wr_o = mem_wr_i;
out1_rd_o = mem_rd_i;
out1_data_o = mem_data_i;
out1_burst_o = mem_burst_i;
out1_sel_o = mem_sel_i;
out1_we_o = mem_we_i;
out1_stb_o = mem_stb_i;
out1_cyc_o = mem_cyc_i;
out1_cti_o = mem_cti_i;
end
2'd2:
begin
out2_addr_o = mem_addr_i;
out2_wr_o = mem_wr_i;
out2_rd_o = mem_rd_i;
out2_data_o = mem_data_i;
out2_burst_o = mem_burst_i;
out2_sel_o = mem_sel_i;
out2_we_o = mem_we_i;
out2_stb_o = mem_stb_i;
out2_cyc_o = mem_cyc_i;
out2_cti_o = mem_cti_i;
end
 
default :
162,7 → 159,7
end
 
//-----------------------------------------------------------------
// Read Port
// Response
//-----------------------------------------------------------------
always @ *
begin
171,19 → 168,19
2'd0:
begin
mem_data_o = out0_data_i;
mem_accept_o = out0_accept_i;
mem_stall_o = out0_stall_i;
mem_ack_o = out0_ack_i;
end
2'd1:
begin
mem_data_o = out1_data_i;
mem_accept_o = out1_accept_i;
mem_stall_o = out1_stall_i;
mem_ack_o = out1_ack_i;
end
2'd2:
begin
mem_data_o = out2_data_i;
mem_accept_o = out2_accept_i;
mem_stall_o = out2_stall_i;
mem_ack_o = out2_ack_i;
end
 
190,7 → 187,7
default :
begin
mem_data_o = 32'h00000000;
mem_accept_o = 1'b0;
mem_stall_o = 1'b0;
mem_ack_o = 1'b0;
end
endcase
/soc.v
1,3 → 1,39
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email: admin@ultra-embedded.com
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Module:
10,20 → 46,13
ext_intr_i,
intr_o,
 
 
 
 
 
 
 
 
 
// Memory interface
io_addr_i,
io_data_i,
io_data_o,
io_wr_i,
io_rd_i
io_we_i,
io_stb_i,
io_ack_o
);
 
//-----------------------------------------------------------------
30,9 → 59,6
// Params
//-----------------------------------------------------------------
parameter [31:0] CLK_KHZ = 12288;
parameter [31:0] UART_BAUD = 115200;
parameter [31:0] SPI_FLASH_CLK_KHZ = (12288/2);
parameter SD_CLK_KHZ = 8000;
parameter [31:0] EXTERNAL_INTERRUPTS = 1;
parameter SYSTICK_INTR_MS = 1;
parameter ENABLE_SYSTICK_TIMER = "ENABLED";
46,37 → 72,22
input [(EXTERNAL_INTERRUPTS - 1):0] ext_intr_i /*verilator public*/;
output intr_o /*verilator public*/;
 
 
// Memory Port
input [31:0] io_addr_i /*verilator public*/;
input [31:0] io_data_i /*verilator public*/;
output [31:0] io_data_o /*verilator public*/;
input [3:0] io_wr_i /*verilator public*/;
input io_rd_i /*verilator public*/;
input io_we_i /*verilator public*/;
input io_stb_i /*verilator public*/;
output io_ack_o /*verilator public*/;
 
 
 
 
 
 
 
 
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
 
 
 
 
 
 
 
 
wire [7:0] timer_addr;
wire [31:0] timer_data_o;
wire [31:0] timer_data_i;
wire [3:0] timer_wr;
wire timer_rd;
wire timer_we;
wire timer_stb;
wire timer_intr_systick;
wire timer_intr_hires;
 
83,8 → 94,8
wire [7:0] intr_addr;
wire [31:0] intr_data_o;
wire [31:0] intr_data_i;
wire [3:0] intr_wr;
wire intr_rd;
wire intr_we;
wire intr_stb;
 
//-----------------------------------------------------------------
// Peripheral Interconnect
101,8 → 112,9
.io_addr_i(io_addr_i),
.io_data_i(io_data_i),
.io_data_o(io_data_o),
.io_wr_i(io_wr_i),
.io_rd_i(io_rd_i),
.io_we_i(io_we_i),
.io_stb_i(io_stb_i),
.io_ack_o(io_ack_o),
 
// Peripherals
// Unused = 0x12000000 - 0x120000FF
109,88 → 121,60
.periph0_addr_o(/*open*/),
.periph0_data_o(/*open*/),
.periph0_data_i(32'h00000000),
.periph0_wr_o(/*open*/),
.periph0_rd_o(/*open*/),
.periph0_we_o(/*open*/),
.periph0_stb_o(/*open*/),
 
// Timer = 0x12000100 - 0x120001FF
.periph1_addr_o(timer_addr),
.periph1_data_o(timer_data_o),
.periph1_data_i(timer_data_i),
.periph1_wr_o(timer_wr),
.periph1_rd_o(timer_rd),
.periph1_we_o(timer_we),
.periph1_stb_o(timer_stb),
 
// Interrupt Controller = 0x12000200 - 0x120002FF
.periph2_addr_o(intr_addr),
.periph2_data_o(intr_data_o),
.periph2_data_i(intr_data_i),
.periph2_wr_o(intr_wr),
.periph2_rd_o(intr_rd),
.periph2_we_o(intr_we),
.periph2_stb_o(intr_stb),
 
// Unused = 0x12000300 - 0x120003FF
.periph3_addr_o(/*open*/),
.periph3_data_o(/*open*/),
.periph3_data_i(32'h00000000),
.periph3_wr_o(/*open*/),
.periph3_rd_o(/*open*/),
.periph3_we_o(/*open*/),
.periph3_stb_o(/*open*/),
 
// Unused = 0x12000400 - 0x120004FF
.periph4_addr_o(/*open*/),
.periph4_data_o(/*open*/),
.periph4_data_i(32'h00000000),
.periph4_wr_o(/*open*/),
.periph4_rd_o(/*open*/),
.periph4_we_o(/*open*/),
.periph4_stb_o(/*open*/),
 
// Unused = 0x12000500 - 0x120005FF
.periph5_addr_o(/*open*/),
.periph5_data_o(/*open*/),
.periph5_data_i(32'h00000000),
.periph5_wr_o(/*open*/),
.periph5_rd_o(/*open*/),
.periph5_we_o(/*open*/),
.periph5_stb_o(/*open*/),
 
// Unused = 0x12000600 - 0x120006FF
.periph6_addr_o(/*open*/),
.periph6_data_o(/*open*/),
.periph6_data_i(32'h00000000),
.periph6_wr_o(/*open*/),
.periph6_rd_o(/*open*/),
.periph6_we_o(/*open*/),
.periph6_stb_o(/*open*/),
 
// Unused = 0x12000700 - 0x120007FF
.periph7_addr_o(/*open*/),
.periph7_data_o(/*open*/),
.periph7_data_i(32'h00000000),
.periph7_wr_o(/*open*/),
.periph7_rd_o(/*open*/)
.periph7_we_o(/*open*/),
.periph7_stb_o(/*open*/)
);
 
//-----------------------------------------------------------------
// Memory master arbiter
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// UART
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// GPIO
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// SPI Flash Master
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// DMA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// SD
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Generic Register
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Timer
//-----------------------------------------------------------------
timer_periph
209,8 → 193,8
.addr_i(timer_addr),
.data_o(timer_data_i),
.data_i(timer_data_o),
.wr_i(timer_wr),
.rd_i(timer_rd)
.we_i(timer_we),
.stb_i(timer_stb)
);
 
//-----------------------------------------------------------------
244,8 → 228,8
.addr_i(intr_addr),
.data_o(intr_data_i),
.data_i(intr_data_o),
.wr_i(intr_wr),
.rd_i(intr_rd)
.we_i(intr_we),
.stb_i(intr_stb)
);
 
//-------------------------------------------------------------------
/cpu_if.v
1,3 → 1,39
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email: admin@ultra-embedded.com
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Module:
5,126 → 41,92
module cpu_if
(
// General - Clocking & Reset
clk_i,
rst_i,
input clk_i,
input rst_i,
 
// Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
imem0_addr_o,
imem0_rd_o,
imem0_burst_o,
imem0_data_in_i,
imem0_accept_i,
imem0_ack_i,
output [31:0] imem0_addr_o,
input [31:0] imem0_data_i,
output [3:0] imem0_sel_o,
output imem0_stb_o,
output imem0_cyc_o,
output [2:0] imem0_cti_o,
input imem0_ack_i,
input imem0_stall_i,
 
// Data Memory 0 (0x10000000 - 0x10FFFFFF)
dmem0_addr_o,
dmem0_data_o,
dmem0_data_i,
dmem0_wr_o,
dmem0_rd_o,
dmem0_burst_o,
dmem0_accept_i,
dmem0_ack_i,
output [31:0] dmem0_addr_o,
output [31:0] dmem0_data_o,
input [31:0] dmem0_data_i,
output [3:0] dmem0_sel_o,
output dmem0_we_o,
output dmem0_stb_o,
output dmem0_cyc_o,
output [2:0] dmem0_cti_o,
input dmem0_ack_i,
input dmem0_stall_i,
 
// Data Memory 1 (0x11000000 - 0x11FFFFFF)
dmem1_addr_o,
dmem1_data_o,
dmem1_data_i,
dmem1_wr_o,
dmem1_rd_o,
dmem1_burst_o,
dmem1_accept_i,
dmem1_ack_i,
output [31:0] dmem1_addr_o,
output [31:0] dmem1_data_o,
input [31:0] dmem1_data_i,
output [3:0] dmem1_sel_o,
output dmem1_we_o,
output dmem1_stb_o,
output dmem1_cyc_o,
output [2:0] dmem1_cti_o,
input dmem1_ack_i,
input dmem1_stall_i,
 
// Data Memory 2 (0x12000000 - 0x12FFFFFF)
dmem2_addr_o,
dmem2_data_o,
dmem2_data_i,
dmem2_wr_o,
dmem2_rd_o,
dmem2_burst_o,
dmem2_accept_i,
dmem2_ack_i,
output [31:0] dmem2_addr_o,
output [31:0] dmem2_data_o,
input [31:0] dmem2_data_i,
output [3:0] dmem2_sel_o,
output dmem2_we_o,
output dmem2_stb_o,
output dmem2_cyc_o,
output [2:0] dmem2_cti_o,
input dmem2_ack_i,
input dmem2_stall_i,
 
fault_o,
break_o,
intr_i,
nmi_i
output fault_o,
output break_o,
input intr_i,
input nmi_i
);
 
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] CLK_KHZ = 12288;
parameter CLK_KHZ = 12288;
parameter ENABLE_ICACHE = "ENABLED";
parameter ENABLE_DCACHE = "DISABLED";
parameter ENABLE_DCACHE = "ENABLED";
parameter BOOT_VECTOR = 0;
parameter ISR_VECTOR = 0;
parameter REGISTER_FILE_TYPE = "SIMULATION";
 
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i /*verilator public*/;
input rst_i /*verilator public*/;
 
// Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
output [31:0] imem0_addr_o /*verilator public*/;
output imem0_rd_o /*verilator public*/;
output imem0_burst_o /*verilator public*/;
input [31:0] imem0_data_in_i /*verilator public*/;
input imem0_accept_i /*verilator public*/;
input imem0_ack_i /*verilator public*/;
 
// Data Memory 0 (0x10000000 - 0x10FFFFFF)
output [31:0] dmem0_addr_o /*verilator public*/;
output [31:0] dmem0_data_o /*verilator public*/;
input [31:0] dmem0_data_i /*verilator public*/;
output [3:0] dmem0_wr_o /*verilator public*/;
output dmem0_rd_o /*verilator public*/;
output dmem0_burst_o /*verilator public*/;
input dmem0_accept_i /*verilator public*/;
input dmem0_ack_i /*verilator public*/;
// Data Memory 1 (0x11000000 - 0x11FFFFFF)
output [31:0] dmem1_addr_o /*verilator public*/;
output [31:0] dmem1_data_o /*verilator public*/;
input [31:0] dmem1_data_i /*verilator public*/;
output [3:0] dmem1_wr_o /*verilator public*/;
output dmem1_rd_o /*verilator public*/;
output dmem1_burst_o /*verilator public*/;
input dmem1_accept_i /*verilator public*/;
input dmem1_ack_i /*verilator public*/;
// Data Memory 2 (0x12000000 - 0x12FFFFFF)
output [31:0] dmem2_addr_o /*verilator public*/;
output [31:0] dmem2_data_o /*verilator public*/;
input [31:0] dmem2_data_i /*verilator public*/;
output [3:0] dmem2_wr_o /*verilator public*/;
output dmem2_rd_o /*verilator public*/;
output dmem2_burst_o /*verilator public*/;
input dmem2_accept_i /*verilator public*/;
input dmem2_ack_i /*verilator public*/;
 
output fault_o /*verilator public*/;
output break_o /*verilator public*/;
input nmi_i /*verilator public*/;
input intr_i /*verilator public*/;
 
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
wire [31:0] cpu_address;
wire [3:0] cpu_wr;
wire cpu_rd;
wire cpu_burst;
wire [31:0] cpu_data_w;
wire [31:0] cpu_data_r;
wire cpu_accept;
wire cpu_ack;
wire [31:0] dmem_addr;
wire [31:0] dmem_data_w;
wire [31:0] dmem_data_r;
wire [3:0] dmem_sel;
wire [2:0] dmem_cti;
wire dmem_cyc;
wire dmem_we;
wire dmem_stb;
wire dmem_stall;
wire dmem_ack;
wire [31:0] imem_address;
wire [31:0] imem_data;
wire imem_rd;
wire imem_burst;
wire [2:0] imem_cti;
wire imem_cyc;
wire imem_stb;
wire imem_stall;
wire imem_ack;
wire imem_accept;
 
//-----------------------------------------------------------------
// CPU core
151,21 → 153,24
// Instruction memory
.imem_addr_o(imem_address),
.imem_rd_o(imem_rd),
.imem_burst_o(imem_burst),
.imem_data_in_i(imem_data),
.imem_accept_i(imem_accept),
.imem_ack_i(imem_ack),
.imem_dat_i(imem_data),
.imem_cti_o(imem_cti),
.imem_cyc_o(imem_cyc),
.imem_stb_o(imem_stb),
.imem_stall_i(imem_stall),
.imem_ack_i(imem_ack),
// Data memory
.dmem_addr_o(cpu_address),
.dmem_data_out_o(cpu_data_w),
.dmem_data_in_i(cpu_data_r),
.dmem_wr_o(cpu_wr),
.dmem_rd_o(cpu_rd),
.dmem_burst_o(cpu_burst),
.dmem_accept_i(cpu_accept),
.dmem_ack_i(cpu_ack)
.dmem_addr_o(dmem_addr),
.dmem_dat_o(dmem_data_w),
.dmem_dat_i(dmem_data_r),
.dmem_sel_o(dmem_sel),
.dmem_cti_o(dmem_cti),
.dmem_cyc_o(dmem_cyc),
.dmem_we_o(dmem_we),
.dmem_stb_o(dmem_stb),
.dmem_stall_i(dmem_stall),
.dmem_ack_i(dmem_ack)
);
 
//-----------------------------------------------------------------
173,10 → 178,12
//-----------------------------------------------------------------
 
assign imem0_addr_o = imem_address;
assign imem0_rd_o = imem_rd;
assign imem0_burst_o = imem_burst;
assign imem_data = imem0_data_in_i;
assign imem_accept = imem0_accept_i;
assign imem0_sel_o = 4'b1111;
assign imem0_stb_o = imem_stb;
assign imem0_cyc_o = imem_cyc;
assign imem0_cti_o = imem_cti;
assign imem_data = imem0_data_i;
assign imem_stall = imem0_stall_i;
assign imem_ack = imem0_ack_i;
 
 
194,39 → 201,49
.out0_addr_o(dmem0_addr_o),
.out0_data_o(dmem0_data_o),
.out0_data_i(dmem0_data_i),
.out0_wr_o(dmem0_wr_o),
.out0_rd_o(dmem0_rd_o),
.out0_burst_o(dmem0_burst_o),
.out0_sel_o(dmem0_sel_o),
.out0_we_o(dmem0_we_o),
.out0_stb_o(dmem0_stb_o),
.out0_cyc_o(dmem0_cyc_o),
.out0_cti_o(dmem0_cti_o),
.out0_ack_i(dmem0_ack_i),
.out0_accept_i(dmem0_accept_i),
.out0_stall_i(dmem0_stall_i),
 
// 0x11000000 - 0x11FFFFFF
.out1_addr_o(dmem1_addr_o),
.out1_data_o(dmem1_data_o),
.out1_data_i(dmem1_data_i),
.out1_wr_o(dmem1_wr_o),
.out1_rd_o(dmem1_rd_o),
.out1_burst_o(dmem1_burst_o),
.out1_sel_o(dmem1_sel_o),
.out1_we_o(dmem1_we_o),
.out1_stb_o(dmem1_stb_o),
.out1_cyc_o(dmem1_cyc_o),
.out1_cti_o(dmem1_cti_o),
.out1_ack_i(dmem1_ack_i),
.out1_accept_i(dmem1_accept_i),
.out1_stall_i(dmem1_stall_i),
 
// 0x12000000 - 0x12FFFFFF
.out2_addr_o(dmem2_addr_o),
.out2_data_o(dmem2_data_o),
.out2_data_i(dmem2_data_i),
.out2_wr_o(dmem2_wr_o),
.out2_rd_o(dmem2_rd_o),
.out2_burst_o(dmem2_burst_o),
.out2_sel_o(dmem2_sel_o),
.out2_we_o(dmem2_we_o),
.out2_stb_o(dmem2_stb_o),
.out2_cyc_o(dmem2_cyc_o),
.out2_cti_o(dmem2_cti_o),
.out2_ack_i(dmem2_ack_i),
.out2_accept_i(dmem2_accept_i),
.out2_stall_i(dmem2_stall_i),
 
// Input - CPU core bus
.mem_addr_i(cpu_address),
.mem_data_i(cpu_data_w),
.mem_data_o(cpu_data_r),
.mem_wr_i(cpu_wr),
.mem_rd_i(cpu_rd),
.mem_burst_i(cpu_burst),
.mem_ack_o(cpu_ack),
.mem_accept_o(cpu_accept)
.mem_addr_i(dmem_addr),
.mem_data_i(dmem_data_w),
.mem_data_o(dmem_data_r),
.mem_sel_i(dmem_sel),
.mem_we_i(dmem_we),
.mem_stb_i(dmem_stb),
.mem_cyc_i(dmem_cyc),
.mem_cti_i(dmem_cti),
.mem_ack_o(dmem_ack),
.mem_stall_o(dmem_stall)
);
 
endmodule
/soc_pif8.v
1,3 → 1,39
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email: admin@ultra-embedded.com
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Module:
5,190 → 41,109
module soc_pif8
(
// General - Clocking & Reset
clk_i,
rst_i,
input clk_i,
input rst_i,
 
// Peripherals
periph0_addr_o,
periph0_data_o,
periph0_data_i,
periph0_wr_o,
periph0_rd_o,
periph1_addr_o,
periph1_data_o,
periph1_data_i,
periph1_wr_o,
periph1_rd_o,
periph2_addr_o,
periph2_data_o,
periph2_data_i,
periph2_wr_o,
periph2_rd_o,
periph3_addr_o,
periph3_data_o,
periph3_data_i,
periph3_wr_o,
periph3_rd_o,
periph4_addr_o,
periph4_data_o,
periph4_data_i,
periph4_wr_o,
periph4_rd_o,
periph5_addr_o,
periph5_data_o,
periph5_data_i,
periph5_wr_o,
periph5_rd_o,
periph6_addr_o,
periph6_data_o,
periph6_data_i,
periph6_wr_o,
periph6_rd_o,
periph7_addr_o,
periph7_data_o,
periph7_data_i,
periph7_wr_o,
periph7_rd_o,
output [7:0] periph0_addr_o,
output [31:0] periph0_data_o,
input [31:0] periph0_data_i,
output reg periph0_we_o,
output reg periph0_stb_o,
 
// I/O bus
io_addr_i,
io_data_i,
io_data_o,
io_wr_i,
io_rd_i
);
output [7:0] periph1_addr_o,
output [31:0] periph1_data_o,
input [31:0] periph1_data_i,
output reg periph1_we_o,
output reg periph1_stb_o,
 
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i /*verilator public*/;
input rst_i /*verilator public*/;
output [7:0] periph2_addr_o,
output [31:0] periph2_data_o,
input [31:0] periph2_data_i,
output reg periph2_we_o,
output reg periph2_stb_o,
 
input [31:0] io_addr_i /*verilator public*/;
output [31:0] io_data_o /*verilator public*/;
input [31:0] io_data_i /*verilator public*/;
input [3:0] io_wr_i /*verilator public*/;
input io_rd_i /*verilator public*/;
output [7:0] periph3_addr_o,
output [31:0] periph3_data_o,
input [31:0] periph3_data_i,
output reg periph3_we_o,
output reg periph3_stb_o,
 
output [7:0] periph0_addr_o /*verilator public*/;
output [31:0] periph0_data_o /*verilator public*/;
input [31:0] periph0_data_i /*verilator public*/;
output [3:0] periph0_wr_o /*verilator public*/;
output periph0_rd_o /*verilator public*/;
output [7:0] periph1_addr_o /*verilator public*/;
output [31:0] periph1_data_o /*verilator public*/;
input [31:0] periph1_data_i /*verilator public*/;
output [3:0] periph1_wr_o /*verilator public*/;
output periph1_rd_o /*verilator public*/;
output [7:0] periph2_addr_o /*verilator public*/;
output [31:0] periph2_data_o /*verilator public*/;
input [31:0] periph2_data_i /*verilator public*/;
output [3:0] periph2_wr_o /*verilator public*/;
output periph2_rd_o /*verilator public*/;
output [7:0] periph3_addr_o /*verilator public*/;
output [31:0] periph3_data_o /*verilator public*/;
input [31:0] periph3_data_i /*verilator public*/;
output [3:0] periph3_wr_o /*verilator public*/;
output periph3_rd_o /*verilator public*/;
output [7:0] periph4_addr_o /*verilator public*/;
output [31:0] periph4_data_o /*verilator public*/;
input [31:0] periph4_data_i /*verilator public*/;
output [3:0] periph4_wr_o /*verilator public*/;
output periph4_rd_o /*verilator public*/;
output [7:0] periph5_addr_o /*verilator public*/;
output [31:0] periph5_data_o /*verilator public*/;
input [31:0] periph5_data_i /*verilator public*/;
output [3:0] periph5_wr_o /*verilator public*/;
output periph5_rd_o /*verilator public*/;
output [7:0] periph6_addr_o /*verilator public*/;
output [31:0] periph6_data_o /*verilator public*/;
input [31:0] periph6_data_i /*verilator public*/;
output [3:0] periph6_wr_o /*verilator public*/;
output periph6_rd_o /*verilator public*/;
output [7:0] periph7_addr_o /*verilator public*/;
output [31:0] periph7_data_o /*verilator public*/;
input [31:0] periph7_data_i /*verilator public*/;
output [3:0] periph7_wr_o /*verilator public*/;
output periph7_rd_o /*verilator public*/;
output [7:0] periph4_addr_o,
output [31:0] periph4_data_o,
input [31:0] periph4_data_i,
output reg periph4_we_o,
output reg periph4_stb_o,
 
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [3:0] r_mem_sel;
output [7:0] periph5_addr_o,
output [31:0] periph5_data_o,
input [31:0] periph5_data_i,
output reg periph5_we_o,
output reg periph5_stb_o,
 
reg [31:0] io_data_o;
output [7:0] periph6_addr_o,
output [31:0] periph6_data_o,
input [31:0] periph6_data_i,
output reg periph6_we_o,
output reg periph6_stb_o,
 
reg [7:0] periph0_addr_o;
reg [31:0] periph0_data_o;
reg [3:0] periph0_wr_o;
reg periph0_rd_o;
reg [7:0] periph1_addr_o;
reg [31:0] periph1_data_o;
reg [3:0] periph1_wr_o;
reg periph1_rd_o;
reg [7:0] periph2_addr_o;
reg [31:0] periph2_data_o;
reg [3:0] periph2_wr_o;
reg periph2_rd_o;
reg [7:0] periph3_addr_o;
reg [31:0] periph3_data_o;
reg [3:0] periph3_wr_o;
reg periph3_rd_o;
reg [7:0] periph4_addr_o;
reg [31:0] periph4_data_o;
reg [3:0] periph4_wr_o;
reg periph4_rd_o;
reg [7:0] periph5_addr_o;
reg [31:0] periph5_data_o;
reg [3:0] periph5_wr_o;
reg periph5_rd_o;
reg [7:0] periph6_addr_o;
reg [31:0] periph6_data_o;
reg [3:0] periph6_wr_o;
reg periph6_rd_o;
reg [7:0] periph7_addr_o;
reg [31:0] periph7_data_o;
reg [3:0] periph7_wr_o;
reg periph7_rd_o;
output [7:0] periph7_addr_o,
output [31:0] periph7_data_o,
input [31:0] periph7_data_i,
output reg periph7_we_o,
output reg periph7_stb_o,
 
// I/O bus
input [31:0] io_addr_i,
input [31:0] io_data_i,
output reg [31:0] io_data_o,
input io_we_i,
input io_stb_i,
output reg io_ack_o
);
 
//-----------------------------------------------------------------
// Memory Map
//-----------------------------------------------------------------
always @ (io_addr_i or io_wr_i or io_rd_i or io_data_i)
 
// Route data / address to all peripherals
assign periph0_addr_o = io_addr_i[7:0];
assign periph0_data_o = io_data_i;
assign periph1_addr_o = io_addr_i[7:0];
assign periph1_data_o = io_data_i;
assign periph2_addr_o = io_addr_i[7:0];
assign periph2_data_o = io_data_i;
assign periph3_addr_o = io_addr_i[7:0];
assign periph3_data_o = io_data_i;
assign periph4_addr_o = io_addr_i[7:0];
assign periph4_data_o = io_data_i;
assign periph5_addr_o = io_addr_i[7:0];
assign periph5_data_o = io_data_i;
assign periph6_addr_o = io_addr_i[7:0];
assign periph6_data_o = io_data_i;
assign periph7_addr_o = io_addr_i[7:0];
assign periph7_data_o = io_data_i;
 
// Select correct target
always @ *
begin
 
periph0_addr_o = 8'h00;
periph0_wr_o = 4'b0000;
periph0_rd_o = 1'b0;
periph0_data_o = 32'h00000000;
periph1_addr_o = 8'h00;
periph1_wr_o = 4'b0000;
periph1_rd_o = 1'b0;
periph1_data_o = 32'h00000000;
periph2_addr_o = 8'h00;
periph2_wr_o = 4'b0000;
periph2_rd_o = 1'b0;
periph2_data_o = 32'h00000000;
periph3_addr_o = 8'h00;
periph3_wr_o = 4'b0000;
periph3_rd_o = 1'b0;
periph3_data_o = 32'h00000000;
periph4_addr_o = 8'h00;
periph4_wr_o = 4'b0000;
periph4_rd_o = 1'b0;
periph4_data_o = 32'h00000000;
periph5_addr_o = 8'h00;
periph5_wr_o = 4'b0000;
periph5_rd_o = 1'b0;
periph5_data_o = 32'h00000000;
periph6_addr_o = 8'h00;
periph6_wr_o = 4'b0000;
periph6_rd_o = 1'b0;
periph6_data_o = 32'h00000000;
periph7_addr_o = 8'h00;
periph7_wr_o = 4'b0000;
periph7_rd_o = 1'b0;
periph7_data_o = 32'h00000000;
periph0_we_o = 1'b0;
periph0_stb_o = 1'b0;
periph1_we_o = 1'b0;
periph1_stb_o = 1'b0;
periph2_we_o = 1'b0;
periph2_stb_o = 1'b0;
periph3_we_o = 1'b0;
periph3_stb_o = 1'b0;
periph4_we_o = 1'b0;
periph4_stb_o = 1'b0;
periph5_we_o = 1'b0;
periph5_stb_o = 1'b0;
periph6_we_o = 1'b0;
periph6_stb_o = 1'b0;
periph7_we_o = 1'b0;
periph7_stb_o = 1'b0;
 
// Decode 4-bit peripheral select
case (io_addr_i[11:8])
196,66 → 151,50
// Peripheral 0
4'd 0 :
begin
periph0_addr_o = io_addr_i[7:0];
periph0_wr_o = io_wr_i;
periph0_rd_o = io_rd_i;
periph0_data_o = io_data_i;
periph0_we_o = io_we_i;
periph0_stb_o = io_stb_i;
end
// Peripheral 1
4'd 1 :
begin
periph1_addr_o = io_addr_i[7:0];
periph1_wr_o = io_wr_i;
periph1_rd_o = io_rd_i;
periph1_data_o = io_data_i;
periph1_we_o = io_we_i;
periph1_stb_o = io_stb_i;
end
// Peripheral 2
4'd 2 :
begin
periph2_addr_o = io_addr_i[7:0];
periph2_wr_o = io_wr_i;
periph2_rd_o = io_rd_i;
periph2_data_o = io_data_i;
periph2_we_o = io_we_i;
periph2_stb_o = io_stb_i;
end
// Peripheral 3
4'd 3 :
begin
periph3_addr_o = io_addr_i[7:0];
periph3_wr_o = io_wr_i;
periph3_rd_o = io_rd_i;
periph3_data_o = io_data_i;
periph3_we_o = io_we_i;
periph3_stb_o = io_stb_i;
end
// Peripheral 4
4'd 4 :
begin
periph4_addr_o = io_addr_i[7:0];
periph4_wr_o = io_wr_i;
periph4_rd_o = io_rd_i;
periph4_data_o = io_data_i;
periph4_we_o = io_we_i;
periph4_stb_o = io_stb_i;
end
// Peripheral 5
4'd 5 :
begin
periph5_addr_o = io_addr_i[7:0];
periph5_wr_o = io_wr_i;
periph5_rd_o = io_rd_i;
periph5_data_o = io_data_i;
periph5_we_o = io_we_i;
periph5_stb_o = io_stb_i;
end
// Peripheral 6
4'd 6 :
begin
periph6_addr_o = io_addr_i[7:0];
periph6_wr_o = io_wr_i;
periph6_rd_o = io_rd_i;
periph6_data_o = io_data_i;
periph6_we_o = io_we_i;
periph6_stb_o = io_stb_i;
end
// Peripheral 7
4'd 7 :
begin
periph7_addr_o = io_addr_i[7:0];
periph7_wr_o = io_wr_i;
periph7_rd_o = io_rd_i;
periph7_data_o = io_data_i;
periph7_we_o = io_we_i;
periph7_stb_o = io_stb_i;
end
 
default :
266,67 → 205,42
//-----------------------------------------------------------------
// Read Port
//-----------------------------------------------------------------
always @ *
always @ (posedge clk_i or posedge rst_i)
begin
case (r_mem_sel)
 
// Peripheral 0
4'd 0 :
if (rst_i == 1'b1)
begin
io_data_o = periph0_data_i;
io_data_o <= 32'b0;
io_ack_o <= 1'b0;
end
// Peripheral 1
4'd 1 :
else
begin
io_data_o = periph1_data_i;
end
// Peripheral 2
4'd 2 :
begin
io_data_o = periph2_data_i;
end
// Peripheral 3
4'd 3 :
begin
io_data_o = periph3_data_i;
end
// Peripheral 4
4'd 4 :
begin
io_data_o = periph4_data_i;
end
// Peripheral 5
4'd 5 :
begin
io_data_o = periph5_data_i;
end
// Peripheral 6
4'd 6 :
begin
io_data_o = periph6_data_i;
end
// Peripheral 7
4'd 7 :
begin
io_data_o = periph7_data_i;
end
if (io_stb_i)
begin
// Decode 4-bit peripheral select
case (io_addr_i[11:8])
// Peripheral 0
4'd 0 : io_data_o <= periph0_data_i;
// Peripheral 1
4'd 1 : io_data_o <= periph1_data_i;
// Peripheral 2
4'd 2 : io_data_o <= periph2_data_i;
// Peripheral 3
4'd 3 : io_data_o <= periph3_data_i;
// Peripheral 4
4'd 4 : io_data_o <= periph4_data_i;
// Peripheral 5
4'd 5 : io_data_o <= periph5_data_i;
// Peripheral 6
4'd 6 : io_data_o <= periph6_data_i;
// Peripheral 7
4'd 7 : io_data_o <= periph7_data_i;
 
default :
begin
io_data_o = 32'h00000000;
default : io_data_o <= 32'h00000000;
endcase
end
 
io_ack_o <= io_stb_i;
end
endcase
end
 
//-----------------------------------------------------------------
// Registered peripheral select
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i == 1'b1)
r_mem_sel <= 4'h0;
else
r_mem_sel <= io_addr_i[11:8];
end
 
endmodule

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