OpenCores
URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /altor32/trunk/rtl
    from Rev 27 to Rev 30
    ↔ Reverse comparison
  •

Rev 27 → Rev 30

/cpu/altor32_icache.v
60,10 → 60,10
output busy_o /*verilator public*/,
 
// Memory interface (slave)
output [31:0] mem_addr_o /*verilator public*/,
output reg [31:0] mem_addr_o /*verilator public*/,
input [31:0] mem_data_i /*verilator public*/,
output mem_burst_o /*verilator public*/,
output mem_rd_o /*verilator public*/,
output reg mem_burst_o /*verilator public*/,
output reg mem_rd_o /*verilator public*/,
input mem_accept_i/*verilator public*/,
input mem_ack_i/*verilator public*/
);
116,16 → 116,9
reg [31:0] last_pc;
reg [31:0] miss_pc;
 
wire busy_o;
wire miss_o;
 
reg initial_fetch;
reg flush_req;
 
reg [31:0] mem_addr_o;
reg mem_rd_o;
reg mem_burst_o;
 
reg [CACHE_LINE_ADDR_WIDTH-1:0] flush_addr;
reg flush_wr;
 
144,7 → 137,7
 
assign miss_o = (!tag_data_out[CACHE_TAG_VALID_BIT] || (last_pc[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] != tag_data_out[14:0])) ? 1'b1: 1'b0;
 
wire valid_o = !miss_o && !busy_o;
assign valid_o = !miss_o && !busy_o;
 
//-----------------------------------------------------------------
// Control logic
/cpu/altor32_ram_sp.v
38,7 → 38,11
//-----------------------------------------------------------------
// Module: altor32_ram_sp - Single port RAM (used in cache)
//-----------------------------------------------------------------
module altor32_ram_sp
module altor32_ram_sp
#(
parameter [31:0] WIDTH = 8,
parameter [31:0] SIZE = 14
)
(
input clk_i /*verilator public*/,
output [(WIDTH - 1):0] dat_o /*verilator public*/,
48,12 → 52,6
);
 
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] WIDTH = 8;
parameter [31:0] SIZE = 14;
 
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [(WIDTH - 1):0] ram [((2<< (SIZE-1)) - 1):0] /*verilator public*/;
/cpu/altor32_dcache_mem_if.v
40,35 → 40,35
//-----------------------------------------------------------------
module altor32_dcache_mem_if
(
input clk_i /*verilator public*/,
input rst_i /*verilator public*/,
input clk_i /*verilator public*/,
input rst_i /*verilator public*/,
// Cache interface
input [31:0] address_i /*verilator public*/,
input [31:0] data_i /*verilator public*/,
output [31:0] data_o /*verilator public*/,
input fill_i /*verilator public*/,
input evict_i /*verilator public*/,
input [31:0] evict_addr_i /*verilator public*/,
input rd_single_i /*verilator public*/,
input [3:0] wr_single_i /*verilator public*/,
output done_o /*verilator public*/,
input [31:0] address_i /*verilator public*/,
input [31:0] data_i /*verilator public*/,
output reg [31:0] data_o /*verilator public*/,
input fill_i /*verilator public*/,
input evict_i /*verilator public*/,
input [31:0] evict_addr_i /*verilator public*/,
input rd_single_i /*verilator public*/,
input [3:0] wr_single_i /*verilator public*/,
output reg done_o /*verilator public*/,
 
// Cache memory (fill/evict)
output [31:2] cache_addr_o /*verilator public*/,
output [31:0] cache_data_o /*verilator public*/,
input [31:0] cache_data_i /*verilator public*/,
output cache_wr_o /*verilator public*/,
output reg [31:2] cache_addr_o /*verilator public*/,
output reg [31:0] cache_data_o /*verilator public*/,
input [31:0] cache_data_i /*verilator public*/,
output reg cache_wr_o /*verilator public*/,
// Memory interface (slave)
output [31:0] mem_addr_o /*verilator public*/,
input [31:0] mem_data_i /*verilator public*/,
output [31:0] mem_data_o /*verilator public*/,
output mem_burst_o /*verilator public*/,
output mem_rd_o /*verilator public*/,
output [3:0] mem_wr_o /*verilator public*/,
input mem_accept_i/*verilator public*/,
input mem_ack_i/*verilator public*/
output reg [31:0] mem_addr_o /*verilator public*/,
input [31:0] mem_data_i /*verilator public*/,
output reg [31:0] mem_data_o /*verilator public*/,
output reg mem_burst_o /*verilator public*/,
output reg mem_rd_o /*verilator public*/,
output reg [3:0] mem_wr_o /*verilator public*/,
input mem_accept_i/*verilator public*/,
input mem_ack_i/*verilator public*/
);
 
//-----------------------------------------------------------------
81,22 → 81,9
// Registers / Wires
//-----------------------------------------------------------------
 
reg [31:2] cache_addr_o;
reg [31:0] cache_data_o;
reg cache_wr_o;
reg [31:CACHE_LINE_SIZE_WIDTH] line_address;
reg [CACHE_LINE_SIZE_WIDTH-3:0] line_word;
 
reg [31:0] data_o;
reg done_o;
 
reg [31:0] mem_addr_o;
reg [31:0] mem_data_o;
reg mem_rd_o;
reg [3:0] mem_wr_o;
reg mem_burst_o;
 
// Current state
parameter STATE_IDLE = 0;
parameter STATE_FETCH = 1;
/cpu/altor32_ram_dp.v
39,6 → 39,10
// Module: altor32_ram_dp - Dual port RAM (used in cache)
//-----------------------------------------------------------------
module altor32_ram_dp
#(
parameter WIDTH = 8,
parameter SIZE = 14
)
(
input aclk_i /*verilator public*/,
output [(WIDTH - 1):0] adat_o /*verilator public*/,
54,12 → 58,6
);
 
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] WIDTH = 8;
parameter [31:0] SIZE = 14;
 
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
/* verilator lint_off MULTIDRIVEN */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.