OpenCores
URL https://opencores.org/ocsvn/alu_with_selectable_inputs_and_outputs/alu_with_selectable_inputs_and_outputs/trunk

Subversion Repositories alu_with_selectable_inputs_and_outputs

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /alu_with_selectable_inputs_and_outputs/tags/arelease/rtl
    from Rev 3 to Rev 4
    ↔ Reverse comparison
  •

Rev 3 → Rev 4

/dut.v
0,0 → 1,92
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//DUT
 
module DUT(dut_clk, dut_res, dut_stb,
dut_sel,
dut_data_in_0, dut_data_in_1, dut_data_in_2,
dut_data_valid_in,
dut_valid_0, dut_valid_1,
dut_out_0, dut_out_1,
dut_parity_0, dut_parity_1);
 
input dut_clk, dut_res, dut_stb;
input [1:0] dut_sel;
input [7:0] dut_data_in_0, dut_data_in_1, dut_data_in_2;
input dut_data_valid_in;
output dut_valid_0, dut_valid_1;
output [15:0] dut_out_0, dut_out_1;
output dut_parity_0, dut_parity_1;
 
wire [7:0] dut_data_out;
wire dut_data_valid_out;
wire dut_selector_alu_stb;
wire dut_alu_dmux_stb;
wire [15:0] dut_alu_result;
wire dut_parity;
wire dut_output_channel;
wire dut_parity_0, dut_parity_1;
 
//Modules' instantiations
 
SELECTOR selector(.clk(dut_clk), .res(dut_res), .stb(dut_stb),
.sel(dut_sel),
.data_in_0(dut_data_in_0), .data_in_1(dut_data_in_1), .data_in_2(dut_data_in_2),
.data_valid_in(dut_data_valid_in),
.data_out(dut_data_out), .data_valid_out(dut_data_valid_out),
.stb_out(dut_selector_alu_stb));
 
ALU alu(.clk(dut_clk), .res(dut_res), .alu_stb_in(dut_selector_alu_stb),
.alu_data_in(dut_data_out), .alu_data_valid_in(dut_data_valid_out),
.alu_result(dut_alu_result), .result_parity(dut_parity),
.output_channel(dut_output_channel),
.alu_stb_out(dut_alu_dmux_stb));
 
DMUX dmux(.clk(dut_clk), .res(dut_res), .dmux_stb_in(dut_alu_dmux_stb),
.alu_result(dut_alu_result), .result_parity(dut_parity),
.output_channel(dut_output_channel),
.valid_0(dut_valid_0), .valid_1(dut_valid_1),
.out_0(dut_out_0), .out_1(dut_out_1),
.parity_0(dut_parity_0), .parity_1(dut_parity_1));
 
endmodule
/dmux.v
0,0 → 1,118
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//DMUX
 
module DMUX(clk, res, dmux_stb_in,
alu_result, result_parity,
output_channel,
valid_0, valid_1,
out_0, out_1,
parity_0, parity_1);
 
input clk, res, dmux_stb_in;
input [15:0] alu_result;
input result_parity;
input output_channel;
output valid_0, valid_1;
output [15:0] out_0, out_1;
output parity_0, parity_1;
 
reg valid_0, valid_1;
reg [15:0] out_0, out_1;
reg parity_0, parity_1;
 
reg dmux_stb_in_was_1;
integer i;
 
always @ (posedge clk or posedge res)
begin
if(res)
begin
valid_0 = 0;
valid_1 = 0;
out_0 = 16'b0;
out_1 = 16'b0;
parity_0 = 0;
parity_1 = 0;
dmux_stb_in_was_1 = 0;
i = 0;
end
else
begin
if(valid_0 === 1)
valid_0 = 0;
if(valid_1 === 1)
valid_1 = 0;
end
end
 
always @ (posedge clk)
begin
if(dmux_stb_in === 1)
dmux_stb_in_was_1 = 1;
if(dmux_stb_in_was_1 === 1)
i = i + 1;
end
 
always @ (i)
if (i === 5)
begin
case(output_channel)
1'b0:
begin
out_0 = alu_result;
parity_0 = result_parity;
valid_0 = 1;
end
1'b1:
begin
out_1 = alu_result;
parity_1 = result_parity;
valid_1 = 1;
end
endcase
i = 0;
dmux_stb_in_was_1 = 0;
end
endmodule
/selector.v
0,0 → 1,88
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//SELECTOR
 
module SELECTOR(clk, res, stb,
sel,
data_in_0, data_in_1, data_in_2,
data_valid_in,
data_out, data_valid_out,
stb_out);
 
input clk, res, stb;
input [1:0] sel;
input [7:0] data_in_0, data_in_1, data_in_2;
input data_valid_in;
output [7:0] data_out;
output data_valid_out;
output stb_out;
 
reg [1:0] reg_sel;
reg [7:0] data_out;
reg data_valid_out;
reg stb_out;
 
always @ (posedge clk or posedge res)
begin
if(res)
begin
reg_sel = 1'b0;
data_out = 8'b0;
data_valid_out = 1'b0;
stb_out = 1'b0;
end
else
begin
if(stb)
reg_sel = sel;
case(reg_sel[1:0])
2'b00: data_out = data_in_0;
2'b01: data_out = data_in_1;
2'b10: data_out = data_in_2;
endcase
data_valid_out = data_valid_in;
stb_out = stb;
end
end
 
endmodule
/alu.v
0,0 → 1,379
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//ALU
 
module ALU(clk, res, alu_stb_in,
alu_data_in, alu_data_valid_in,
alu_result, result_parity,
output_channel,
alu_stb_out);
 
input clk, res, alu_stb_in;
input [7:0] alu_data_in;
input alu_data_valid_in;
output [15:0] alu_result;
output result_parity;
output output_channel;
output alu_stb_out;
 
reg [15:0] alu_result;
reg result_parity;
reg [3:0] operator_type;
reg [2:0] operator_symbol;
reg output_channel;
reg [7:0] alu_memory [0:15];
reg alu_stb_out;
 
integer i;
integer j;
reg executed_case_once;
always @ (posedge clk or posedge res)
if(res)
begin
alu_result = 16'b0;
result_parity = 1'b0;
operator_type = 4'b1111;
operator_symbol = 3'b111;
output_channel = 1'b0;
for(i = 0; i < 15; i = i + 1)
alu_memory[i] = 8'b0;
i = 0;
j = 0;
executed_case_once = 1'b0;
end
else
begin
if(alu_stb_in)
begin
operator_type = alu_data_in[7:4];
operator_symbol = alu_data_in[3:1];
output_channel = alu_data_in[0];
executed_case_once = 1'b0;
end
if((alu_data_valid_in) && (! alu_stb_in))
begin
alu_memory[i] = alu_data_in;
i = i + 1;
end
if((! alu_data_valid_in) && (! alu_stb_in) && (! executed_case_once))
begin
executed_case_once = 1'b1;
if(i !== 0)
for(j=i;j<16; j=j+1)
alu_memory[j] = 8'b0;
i = 0;
case (operator_type)
'd0: //Arithmetic
begin
$display("Arithmetic operator");
case(operator_symbol)
'd0: //Multiply
begin
alu_result = (alu_memory[0] * alu_memory[1]);
$display("OPERATION * (Multiply): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd1: //Divide
begin
alu_result = (alu_memory[0] / alu_memory[1]);
$display("OPERATION / (Divide): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd2: //Add
begin
alu_result = (alu_memory[0] + alu_memory[1]);
$display("OPERATION + (Add): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd3: //Substract
begin
alu_result = (alu_memory[0] - alu_memory[1]);
$display("OPERATION - (Substract): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd4: //Modulus
begin
alu_result = (alu_memory[0] % alu_memory[1]);
$display("OPERATION (Modulus): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
endcase
end
'd1: //Logical
begin
$display("Logical operator");
case(operator_symbol)
'd0: //Logical negation
begin
alu_result = (!alu_memory[0]);
$display("OPERATION ! (Logical negation): alu_memory[0]=%b, alu_result=%b",
alu_memory[0], alu_result);
end
'd1: //Logical and
begin
alu_result = (alu_memory[0] && alu_memory[1]);
$display("OPERATION && (Logical and): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd2: //Logical or
begin
alu_result = (alu_memory[0] || alu_memory[1]);
$display("OPERATION || (Logical or): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
endcase
end
'd2: //Relational
begin
$display("Relational operator");
case(operator_symbol)
'd0: //Greater than
begin
alu_result = (alu_memory[0] > alu_memory[1]);
$display("OPERATION > (Greater than): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd1: //Less than
begin
alu_result = (alu_memory[0] < alu_memory[1]);
$display("OPERATION < (Less than): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd2: //Greater than or equal
begin
alu_result = (alu_memory[0] >= alu_memory[1]);
$display("OPERATION >= (Greater than or equal): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd3: //Less than or equal
begin
alu_result = (alu_memory[0] <= alu_memory[1]);
$display("OPERATION <= (Less than or equal): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
endcase
end
'd3: //Equality
begin
$display("Equality operator");
case(operator_symbol)
'd0: //Equality
begin
alu_result = (alu_memory[0] == alu_memory[1]);
$display("OPERATION == (Equality): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd1: //Inequality
begin
alu_result = (alu_memory[0] != alu_memory[1]);
$display("OPERATION != (Inequality): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd2: //Case equality
begin
alu_result = (alu_memory[0] === alu_memory[1]);
$display("OPERATION === (Case equality): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd3: //Case inequality
begin
alu_result = (alu_memory[0] !== alu_memory[1]);
$display("OPERATION !== (Case inequality): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
endcase
end
'd4: //Bitwise
begin
$display("Bitwise operator");
case(operator_symbol)
'd0: //Bitwise negation
begin
alu_result = (~ alu_memory[0]);
$display("OPERATION ~ (Bitwise negation): alu_memory[0]=%b, alu_result=%b",
alu_memory[0], alu_result);
end
'd1: //Bitwise and
begin
alu_result = (alu_memory[0] & alu_memory[1]);
$display("OPERATION & (Bitwise and): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd2: //Bitwise or
begin
alu_result = (alu_memory[0] | alu_memory[1]);
$display("OPERATION | (Bitwise or): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd3: //Bitwise xor
begin
alu_result = (alu_memory[0] ^ alu_memory[1]);
$display("OPERATION ^ (Bitwise xor): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd4: //Bitwise xnor (1st operator symbol)
begin
alu_result = (alu_memory[0] ^~ alu_memory[1]);
$display("OPERATION ^~ (Bitwise xnor (1st operator symbol)): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd5: //Bitwise xnor (2nd operator symbol)
begin
alu_result = (alu_memory[0] ~^ alu_memory[1]);
$display("OPERATION ~^ (Bitwise xnor (2nd operator symbol)): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
endcase
end
'd5: //Reduction
begin
$display("Reduction operator");
case(operator_symbol)
'd0: //Reduction and
begin
alu_result = (& alu_memory[0]);
$display("OPERATION & (Reduction and): alu_memory[0]=%b, alu_result=%b",
alu_memory[0], alu_result);
end
'd1: //Reduction nand
begin
alu_result = (~& alu_memory[0]);
$display("OPERATION ~& (Reduction nand): alu_memory[0]=%b, alu_result=%b",
alu_memory[0], alu_result);
end
'd2: //Reduction or
begin
alu_result = (| alu_memory[0]);
$display("OPERATION | (Reduction or): alu_memory[0]=%b, alu_result=%b",
alu_memory[0], alu_result);
end
'd3: //Reduction nor
begin
alu_result = (~| alu_memory[0]);
$display("OPERATION ~| (Reduction nor): alu_memory[0]=%b, alu_result=%b",
alu_memory[0], alu_result);
end
'd4: //Reduction xor
begin
alu_result = (^ alu_memory[0]);
$display("OPERATION ^ (Reduction xor): alu_memory[0]=%b, alu_result=%b",
alu_memory[0], alu_result);
end
'd5: //Reduction xnor (1st operator symbol)
begin
alu_result = (^~ alu_memory[0]);
$display("OPERATION ^~ (Reduction xnor (1st operator symbol)): alu_memory[0]=%b, alu_result=%b",
alu_memory[0], alu_result);
end
'd6: //Reduction xnor (2nd operator symbol)
begin
alu_result = (~^ alu_memory[0]);
$display("OPERATION ~^ (Reduction xnor (2nd operator symbol)): alu_memory[0]=%b, alu_result=%b",
alu_memory[0], alu_result);
end
endcase
end
'd6: //Shift
begin
$display("Shift operator");
case(operator_symbol)
'd0: //Right shift
begin
alu_result = (alu_memory[0] >> alu_memory[1]);
$display("OPERATION >> (Right shift): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd1: //Left shift
begin
alu_result = (alu_memory[0] << alu_memory[1]);
$display("OPERATION << (Left shift): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
endcase
end
'd7: //Concatenation
begin
//$display("Concatenation operator");
case(operator_symbol)
'd0: //Concatenation
begin
alu_result = {alu_memory[0], alu_memory[1]};
$display("OPERATION {} (Concatenation): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
endcase
end
'd8: //Replication
begin
$display("Replication operator");
case(operator_symbol)
'd0: //Replication
begin
alu_result = { 2 {alu_memory[0]} };
$display("OPERATION { { } } (Replication): alu_memory[0]=%b - replicated twice: alu_result=%b",
alu_memory[0], alu_result);
end
endcase
end
'd9: //Conditional
begin
$display("Conditional operator");
case(operator_symbol)
'd0: //Conditional
begin
alu_result = (alu_memory[0] ? alu_memory[1] : alu_memory[2]);
$display("OPERATION ?: (Conditional): alu_memory[0]=%b, alu_memory[1]=%b, alu_memory[2]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_memory[2], alu_result);
end
endcase
end
endcase
result_parity = ^alu_result; //Parity = XOR of all result's bits
end
end
 
always @ (posedge clk)
alu_stb_out = alu_stb_in;
 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.