URL
https://opencores.org/ocsvn/am9080_cpu_based_on_microcoded_am29xx_bit-slices/am9080_cpu_based_on_microcoded_am29xx_bit-slices/trunk
Subversion Repositories am9080_cpu_based_on_microcoded_am29xx_bit-slices
Compare Revisions
- This comparison shows the changes necessary to convert path
/am9080_cpu_based_on_microcoded_am29xx_bit-slices/trunk
- from Rev 9 to Rev 10
- ↔ Reverse comparison
Rev 9 → Rev 10
/Am9080/Am29XX/Old/q_reg.vhd
File deleted
Am9080/Am29XX/Old/q_reg.vhd
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-CRLF
\ No newline at end of property
Index: Am9080/Am29XX/Old/am2901_comps.vhd
===================================================================
--- Am9080/Am29XX/Old/am2901_comps.vhd (revision 9)
+++ Am9080/Am29XX/Old/am2901_comps.vhd (nonexistent)
@@ -1,67 +0,0 @@
--- Package File Template
---
--- Purpose: This package defines supplemental types, subtypes,
--- constants, and functions
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.numeric_std.all;
-package am2901_comps is
- component ram_regs is
- Port ( clk : in STD_LOGIC;
- rst : in STD_LOGIC;
- a : in std_logic_vector (3 downto 0);
- b : in std_logic_vector (3 downto 0);
- f : in std_logic_vector (3 downto 0);
- dest_ctl : in STD_LOGIC_VECTOR (2 downto 0);
- ram0 : inout STD_LOGIC;
- ram3 : inout STD_LOGIC;
- ad : buffer std_logic_vector (3 downto 0);
- bd : buffer std_logic_vector (3 downto 0));
-end component;
- component q_reg is
- Port ( clk : in STD_LOGIC;
- rst : in STD_LOGIC;
- f : in std_logic_vector (3 downto 0);
- dest_ctl : in STD_LOGIC_VECTOR (2 downto 0);
- qs0 : inout STD_LOGIC;
- qs3 : inout STD_LOGIC;
- q : out std_logic_vector (3 downto 0));
-end component;
-
-component src_op is
- Port ( d : in std_logic_vector (3 downto 0);
- ad : in std_logic_vector (3 downto 0);
- bd : in std_logic_vector (3 downto 0);
- q : in std_logic_vector (3 downto 0);
- src_ctl : in STD_LOGIC_VECTOR (2 downto 0);
- r : buffer std_logic_vector (3 downto 0);
- s : buffer std_logic_vector (3 downto 0));
-end component;
-
-
- component alu is
- Port ( r : in STD_LOGIC_VECTOR (3 downto 0);
- s : in STD_LOGIC_VECTOR (3 downto 0);
- c_n : in STD_LOGIC;
- alu_ctl : in STD_LOGIC_VECTOR (2 downto 0);
- f : out STD_LOGIC_VECTOR (3 downto 0);
- g_bar : out STD_LOGIC;
- p_bar : out STD_LOGIC;
- c_n4 : out STD_LOGIC;
- ovr : out STD_LOGIC);
-end component;
-
-
- component out_mux is
- Port ( ad : in STD_LOGIC_VECTOR (3 downto 0);
- f : in STD_LOGIC_VECTOR (3 downto 0);
- dest_ctl : in STD_LOGIC_VECTOR (2 downto 0);
- oe : in STD_LOGIC;
- y : inout STD_LOGIC_VECTOR (3 downto 0));
-end component;
-
-
-
-end am2901_comps;
Am9080/Am29XX/Old/am2901_comps.vhd
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-CRLF
\ No newline at end of property
Index: Am9080/Am29XX/Old/mnemonics.vhd
===================================================================
--- Am9080/Am29XX/Old/mnemonics.vhd (revision 9)
+++ Am9080/Am29XX/Old/mnemonics.vhd (nonexistent)
@@ -1,50 +0,0 @@
--- Package File Template
---
--- Purpose: This package defines supplemental types, subtypes,
--- constants, and functions
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-package mnemonics is
-
-
- ---ALU source operand control mnemonics
-
-
- constant aq: std_logic_vector(2 downto 0) :="000";
- constant ab: std_logic_vector(2 downto 0) :="001";
- constant zq: std_logic_vector(2 downto 0) :="010";
- constant zb: std_logic_vector(2 downto 0) :="011";
- constant za: std_logic_vector(2 downto 0) :="100";
- constant da: std_logic_vector(2 downto 0) :="101";
- constant dq: std_logic_vector(2 downto 0) :="110";
- constant dz: std_logic_vector(2 downto 0) :="111";
-
- ----ALU function control mnemonics
-
- constant add: std_logic_vector(2 downto 0) :="000";
- constant subr: std_logic_vector(2 downto 0) :="001";
- constant subs: std_logic_vector(2 downto 0) :="010";
- constant orrs: std_logic_vector(2 downto 0) :="011";
- constant andrs: std_logic_vector(2 downto 0) :="100";
- constant notrs: std_logic_vector(2 downto 0) :="101";
- constant exor : std_logic_vector(2 downto 0) :="110";
- constant exnor: std_logic_vector(2 downto 0) :="111";
-
-
- ---ALU destination control mnemonics
-
- constant qreg: std_logic_vector(2 downto 0) :="000";
- constant nop : std_logic_vector(2 downto 0) :="001";
- constant rama: std_logic_vector(2 downto 0) :="010";
- constant ramf: std_logic_vector(2 downto 0) :="011";
- constant ramqd: std_logic_vector(2 downto 0) :="100";
- constant ramd : std_logic_vector(2 downto 0) :="101";
- constant ramqu: std_logic_vector(2 downto 0) :="110";
- constant ramu : std_logic_vector(2 downto 0) :="111";
-
- end mnemonics;
-
-
\ No newline at end of file
Am9080/Am29XX/Old/mnemonics.vhd
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-CRLF
\ No newline at end of property
Index: Am9080/Am29XX/Old/out_mux.vhd
===================================================================
--- Am9080/Am29XX/Old/out_mux.vhd (revision 9)
+++ Am9080/Am29XX/Old/out_mux.vhd (nonexistent)
@@ -1,47 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 14:46:36 04/26/2010
--- Design Name:
--- Module Name: out_mux - out_mux
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use work.mnemonics.all;
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity out_mux is
- Port ( ad : in STD_LOGIC_VECTOR (3 downto 0);
- f : in STD_LOGIC_VECTOR (3 downto 0);
- dest_ctl : in STD_LOGIC_VECTOR (2 downto 0);
- oe : in STD_LOGIC;
- y : inout STD_LOGIC_VECTOR (3 downto 0));
-end out_mux;
-
-architecture out_mux of out_mux is
- signal y_int: STD_LOGIC_VECTOR(3 downto 0); ---output before tri-state
- ---- buffer
-begin
- y_int <= ad when dest_ctl = rama else f;
- y <= y_int when oe='0' else "ZZZZ";
-
-end out_mux;
-
Am9080/Am29XX/Old/out_mux.vhd
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-CRLF
\ No newline at end of property
Index: Am9080/Am29XX/Old/src_op.vhd
===================================================================
--- Am9080/Am29XX/Old/src_op.vhd (revision 9)
+++ Am9080/Am29XX/Old/src_op.vhd (nonexistent)
@@ -1,58 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 13:00:06 04/26/2010
--- Design Name:
--- Module Name: src_op - src_op
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use WORK.MNEMONICS.ALL;
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity src_op is
- Port ( d : in std_logic_vector (3 downto 0);
- ad : in std_logic_vector (3 downto 0);
- bd : in std_logic_vector (3 downto 0);
- q : in std_logic_vector (3 downto 0);
- src_ctl : in STD_LOGIC_VECTOR (2 downto 0);
- r : buffer std_logic_vector (3 downto 0);
- s : buffer std_logic_vector (3 downto 0));
-end src_op;
-
-architecture src_op of src_op is
-
-begin
- ---decode alu operand r:
-
- with src_ctl select
- r<= ad when aq |ab,
- "0000" when zq|zb|za,
- d when others;
-
- with src_ctl select
- s<=q when aq|zq|dq,
- bd when ab|zb,
- ad when za|da,
- "0000" when others;
-
-end src_op;
-
Am9080/Am29XX/Old/src_op.vhd
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-CRLF
\ No newline at end of property
Index: Am9080/Am29XX/Old/ureg.vhd
===================================================================
--- Am9080/Am29XX/Old/ureg.vhd (revision 9)
+++ Am9080/Am29XX/Old/ureg.vhd (nonexistent)
@@ -1,67 +0,0 @@
------Set of registers (unsigned)
------ Sizes : (1,size)
------
-
------clk ---posedge clock input
------reset -----asynchronous reset
------load -----active high input loads rregister
------d -----register input
------q -----register output
-
-
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 10:52:23 04/26/2010
--- Design Name:
--- Module Name: ureg - archureg
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use IEEE.NUMERIC_STD.ALL;
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity ureg is
- Port ( clk : in STD_LOGIC;
- reset : in STD_LOGIC;
- load : in STD_LOGIC;
- d : in std_logic_vector (3 downto 0);
- q : out std_logic_vector (3 downto 0));
-end ureg;
-
-architecture archureg of ureg is
-signal q_temp: std_logic_vector(3 downto 0);
-begin
-
- p1: process(reset,clk)
- begin
- if reset ='1' then
- q_temp<=(others =>'0');
- elsif (clk'event and clk='1') then
- if load='1' then
- q_temp<=d;
- else
- q_temp<=q_temp;
- end if;
- end if;
- end process;
-q <= q_temp;
-end archureg;
-
Am9080/Am29XX/Old/ureg.vhd
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-CRLF
\ No newline at end of property
Index: Am9080/Am29XX/Old/am2901.vhd
===================================================================
--- Am9080/Am29XX/Old/am2901.vhd (revision 9)
+++ Am9080/Am29XX/Old/am2901.vhd (nonexistent)
@@ -1,92 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 14:59:18 04/26/2010
--- Design Name:
--- Module Name: am2901 - am2901
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
---use IEEE.STD_LOGIC_ARITH.ALL;
---use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use work.am2901_comps.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity am2901 is
- Port ( clk : in STD_LOGIC;
- rst : in STD_LOGIC;
- a : in std_logic_vector (3 downto 0);----address inputs
- b : in STD_LOGIC_VECTOR (3 downto 0);----address inputs
- d : in STD_LOGIC_VECTOR (3 downto 0);----direct data
- i : in STD_LOGIC_VECTOR (8 downto 0);---micro instruction
- c_n : in STD_LOGIC;---------------------carry in
- oe : in STD_LOGIC;----------------------output enable
- ram0 : inout STD_LOGIC;-----------------shift lines to ram
- ram3 : inout STD_LOGIC;-----------------shift lines to ram
- qs0 : inout STD_LOGIC;------------------shift lines to q
- qs3 : inout STD_LOGIC;------------------shift lines to q
- y : inout STD_LOGIC_VECTOR (3 downto 0);-------data outputs(3-state)
- g_bar : out STD_LOGIC;---------------carry generate
- p_bar : out STD_LOGIC;---------------carry propagate
- ovr : out STD_LOGIC;-----------------overflow
- c_n4 : out STD_LOGIC;----------------carry out
- f_0 : out STD_LOGIC;-----------------f = 0
- f3 : out STD_LOGIC);-----------------f(3) w/o 3-state
-end am2901;
-
-architecture am2901 of am2901 is
-
- alias dest_ctl: std_logic_vector(2 downto 0) is i(8 downto 6);
- alias alu_ctl : std_logic_vector(2 downto 0) is i(5 downto 3);
- alias src_ctl : std_logic_vector(2 downto 0) is i(2 downto 0);
-
- signal ad,bd: STD_LOGIC_VECTOR (3 downto 0);
- signal q : std_logic_vector (3 downto 0);
- signal r,s : std_logic_vector (3 downto 0);
- signal f : STD_LOGIC_VECTOR (3 downto 0);
-
-begin
------instantiate and connect components
-
-u1: ram_regs port map(clk=>clk,rst=>rst,a=>a,b=>b,f=>f,
- dest_ctl=>dest_ctl,ram0=>ram0,ram3=>ram3,
- ad=>ad,bd=>bd);
-
-u2: q_reg port map(clk=>clk,rst=>rst,f=>f,dest_ctl=>dest_ctl,
- qs0=>qs0,qs3=>qs3,q=>q);
-
-u3: src_op port map(d=>d,ad=>ad,bd=>bd,q=>q,
- src_ctl=>src_ctl,r=>r,s=>s);
-
-u4: alu port map(r=>r, s=>s,c_n=>c_n,alu_ctl=>alu_ctl,
- f=>f, g_bar => g_bar, p_bar=>p_bar,
- c_n4=>c_n4, ovr=>ovr);
-
-u5: out_mux port map(ad=>ad,f=>f,dest_ctl=>dest_ctl,
- oe=>oe,y=>y);
-
-
-------define f_0 and f3 outputs
-
-f_0 <= '1' when f = "0000" else '0'; -- not that these are "strong" signals, not open collector
-f3 <= f(3);
-
-end am2901;
-
Am9080/Am29XX/Old/am2901.vhd
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-CRLF
\ No newline at end of property
Index: Am9080/Am29XX/Old/ram_regs.vhd
===================================================================
--- Am9080/Am29XX/Old/ram_regs.vhd (revision 9)
+++ Am9080/Am29XX/Old/ram_regs.vhd (nonexistent)
@@ -1,113 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 13:16:34 04/08/2010
--- Design Name:
--- Module Name: ram_regs - ram_regs
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;--, basic;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use work.mnemonics.all;
---use basic.regs_pkg.all;
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity ram_regs is
- Port ( clk : in STD_LOGIC;
- rst : in STD_LOGIC;
- a : in std_logic_vector (3 downto 0);
- b : in std_logic_vector (3 downto 0);
- f : in std_logic_vector (3 downto 0);
- dest_ctl : in STD_LOGIC_VECTOR (2 downto 0);
- ram0 : inout STD_LOGIC;
- ram3 : inout STD_LOGIC;
- ad : buffer std_logic_vector (3 downto 0);
- bd : buffer std_logic_vector (3 downto 0));
-end ram_regs;
-
-architecture ram_regs of ram_regs is
-
-
- component ureg is
- Port ( clk : in STD_LOGIC;
- reset : in STD_LOGIC;
- load : in STD_LOGIC;
- d : in std_logic_vector (3 downto 0);
- q : out std_logic_vector (3 downto 0));
-end component;
-
-
-
-
-
-
-
-
- signal ram_en: std_logic;
- signal data: std_logic_vector (3 downto 0);
- signal en : std_logic_vector(15 downto 0);
- type ram_array is array(15 downto 0) of std_logic_vector (3 downto 0);
- signal ab_data: ram_array;
-
-begin
-
- --define register array:
-
- gen : for i in 15 downto 0 generate
- ram : ureg
- port map(clk,rst,en(i),data,ab_data(i));
- end generate;
-
- ---decode b to determine which register is enabled:
-
- with dest_ctl select
- ram_en <='0' when qreg |nop,
- '1' when others;
-
- decode_b: process(b, ram_en)
- begin
- for i in 0 to 15 loop
- if CONV_INTEGER(b) = i then en(i) <= ram_en;
- else en(i) <='0';
- end if;
- end loop;
- end process;
-
- ----define data input to register array:
-
- with dest_ctl select
- data<=(f(2),f(1),f(0),ram0) when ramqu|ramu , --shift up
- (ram3,f(3),f(2),f(1)) when ramqd| ramd , --shift down
- f when rama|ramf,
- "----" when others;
-
- --define reg_array output for a and b regs:
-
- ad<= ab_data(CONV_INTEGER(a)); --- to_integer defined in
- bd<= ab_data(CONV_INTEGER(b)); --- numeric_std (See Chapter 7)
-
- ----define ram0 and ram3 inouts:
- ram3 <= f(3) when (dest_ctl = ramu or dest_ctl = ramqu ) else 'Z';
- ram0 <= f(0) when (dest_ctl = ramd or dest_ctl = ramqd) else 'Z';
-
-
-
-end ram_regs;
-
Am9080/Am29XX/Old/ram_regs.vhd
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-CRLF
\ No newline at end of property