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/Am9080/Am29XX/Old/am2901.vhd
0,0 → 1,92
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:59:18 04/26/2010
-- Design Name:
-- Module Name: am2901 - am2901
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.am2901_comps.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity am2901 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
a : in std_logic_vector (3 downto 0);----address inputs
b : in STD_LOGIC_VECTOR (3 downto 0);----address inputs
d : in STD_LOGIC_VECTOR (3 downto 0);----direct data
i : in STD_LOGIC_VECTOR (8 downto 0);---micro instruction
c_n : in STD_LOGIC;---------------------carry in
oe : in STD_LOGIC;----------------------output enable
ram0 : inout STD_LOGIC;-----------------shift lines to ram
ram3 : inout STD_LOGIC;-----------------shift lines to ram
qs0 : inout STD_LOGIC;------------------shift lines to q
qs3 : inout STD_LOGIC;------------------shift lines to q
y : inout STD_LOGIC_VECTOR (3 downto 0);-------data outputs(3-state)
g_bar : out STD_LOGIC;---------------carry generate
p_bar : out STD_LOGIC;---------------carry propagate
ovr : out STD_LOGIC;-----------------overflow
c_n4 : out STD_LOGIC;----------------carry out
f_0 : out STD_LOGIC;-----------------f = 0
f3 : out STD_LOGIC);-----------------f(3) w/o 3-state
end am2901;
 
architecture am2901 of am2901 is
alias dest_ctl: std_logic_vector(2 downto 0) is i(8 downto 6);
alias alu_ctl : std_logic_vector(2 downto 0) is i(5 downto 3);
alias src_ctl : std_logic_vector(2 downto 0) is i(2 downto 0);
signal ad,bd: STD_LOGIC_VECTOR (3 downto 0);
signal q : std_logic_vector (3 downto 0);
signal r,s : std_logic_vector (3 downto 0);
signal f : STD_LOGIC_VECTOR (3 downto 0);
 
begin
-----instantiate and connect components
 
u1: ram_regs port map(clk=>clk,rst=>rst,a=>a,b=>b,f=>f,
dest_ctl=>dest_ctl,ram0=>ram0,ram3=>ram3,
ad=>ad,bd=>bd);
 
u2: q_reg port map(clk=>clk,rst=>rst,f=>f,dest_ctl=>dest_ctl,
qs0=>qs0,qs3=>qs3,q=>q);
 
u3: src_op port map(d=>d,ad=>ad,bd=>bd,q=>q,
src_ctl=>src_ctl,r=>r,s=>s);
 
u4: alu port map(r=>r, s=>s,c_n=>c_n,alu_ctl=>alu_ctl,
f=>f, g_bar => g_bar, p_bar=>p_bar,
c_n4=>c_n4, ovr=>ovr);
 
u5: out_mux port map(ad=>ad,f=>f,dest_ctl=>dest_ctl,
oe=>oe,y=>y);
 
 
------define f_0 and f3 outputs
 
f_0 <= '1' when f = "0000" else '0'; -- not that these are "strong" signals, not open collector
f3 <= f(3);
 
end am2901;
 
Am9080/Am29XX/Old/am2901.vhd Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/Am29XX/Old/am2901_comps.vhd =================================================================== --- Am9080/Am29XX/Old/am2901_comps.vhd (nonexistent) +++ Am9080/Am29XX/Old/am2901_comps.vhd (revision 5) @@ -0,0 +1,67 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.numeric_std.all; +package am2901_comps is + component ram_regs is + Port ( clk : in STD_LOGIC; + rst : in STD_LOGIC; + a : in std_logic_vector (3 downto 0); + b : in std_logic_vector (3 downto 0); + f : in std_logic_vector (3 downto 0); + dest_ctl : in STD_LOGIC_VECTOR (2 downto 0); + ram0 : inout STD_LOGIC; + ram3 : inout STD_LOGIC; + ad : buffer std_logic_vector (3 downto 0); + bd : buffer std_logic_vector (3 downto 0)); +end component; + component q_reg is + Port ( clk : in STD_LOGIC; + rst : in STD_LOGIC; + f : in std_logic_vector (3 downto 0); + dest_ctl : in STD_LOGIC_VECTOR (2 downto 0); + qs0 : inout STD_LOGIC; + qs3 : inout STD_LOGIC; + q : out std_logic_vector (3 downto 0)); +end component; + +component src_op is + Port ( d : in std_logic_vector (3 downto 0); + ad : in std_logic_vector (3 downto 0); + bd : in std_logic_vector (3 downto 0); + q : in std_logic_vector (3 downto 0); + src_ctl : in STD_LOGIC_VECTOR (2 downto 0); + r : buffer std_logic_vector (3 downto 0); + s : buffer std_logic_vector (3 downto 0)); +end component; + + + component alu is + Port ( r : in STD_LOGIC_VECTOR (3 downto 0); + s : in STD_LOGIC_VECTOR (3 downto 0); + c_n : in STD_LOGIC; + alu_ctl : in STD_LOGIC_VECTOR (2 downto 0); + f : out STD_LOGIC_VECTOR (3 downto 0); + g_bar : out STD_LOGIC; + p_bar : out STD_LOGIC; + c_n4 : out STD_LOGIC; + ovr : out STD_LOGIC); +end component; + + + component out_mux is + Port ( ad : in STD_LOGIC_VECTOR (3 downto 0); + f : in STD_LOGIC_VECTOR (3 downto 0); + dest_ctl : in STD_LOGIC_VECTOR (2 downto 0); + oe : in STD_LOGIC; + y : inout STD_LOGIC_VECTOR (3 downto 0)); +end component; + + + +end am2901_comps;
Am9080/Am29XX/Old/am2901_comps.vhd Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/Am29XX/Old/mnemonics.vhd =================================================================== --- Am9080/Am29XX/Old/mnemonics.vhd (nonexistent) +++ Am9080/Am29XX/Old/mnemonics.vhd (revision 5) @@ -0,0 +1,50 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package mnemonics is + + + ---ALU source operand control mnemonics + + + constant aq: std_logic_vector(2 downto 0) :="000"; + constant ab: std_logic_vector(2 downto 0) :="001"; + constant zq: std_logic_vector(2 downto 0) :="010"; + constant zb: std_logic_vector(2 downto 0) :="011"; + constant za: std_logic_vector(2 downto 0) :="100"; + constant da: std_logic_vector(2 downto 0) :="101"; + constant dq: std_logic_vector(2 downto 0) :="110"; + constant dz: std_logic_vector(2 downto 0) :="111"; + + ----ALU function control mnemonics + + constant add: std_logic_vector(2 downto 0) :="000"; + constant subr: std_logic_vector(2 downto 0) :="001"; + constant subs: std_logic_vector(2 downto 0) :="010"; + constant orrs: std_logic_vector(2 downto 0) :="011"; + constant andrs: std_logic_vector(2 downto 0) :="100"; + constant notrs: std_logic_vector(2 downto 0) :="101"; + constant exor : std_logic_vector(2 downto 0) :="110"; + constant exnor: std_logic_vector(2 downto 0) :="111"; + + + ---ALU destination control mnemonics + + constant qreg: std_logic_vector(2 downto 0) :="000"; + constant nop : std_logic_vector(2 downto 0) :="001"; + constant rama: std_logic_vector(2 downto 0) :="010"; + constant ramf: std_logic_vector(2 downto 0) :="011"; + constant ramqd: std_logic_vector(2 downto 0) :="100"; + constant ramd : std_logic_vector(2 downto 0) :="101"; + constant ramqu: std_logic_vector(2 downto 0) :="110"; + constant ramu : std_logic_vector(2 downto 0) :="111"; + + end mnemonics; + + \ No newline at end of file
Am9080/Am29XX/Old/mnemonics.vhd Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/Am29XX/Old/out_mux.vhd =================================================================== --- Am9080/Am29XX/Old/out_mux.vhd (nonexistent) +++ Am9080/Am29XX/Old/out_mux.vhd (revision 5) @@ -0,0 +1,47 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 14:46:36 04/26/2010 +-- Design Name: +-- Module Name: out_mux - out_mux +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.mnemonics.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity out_mux is + Port ( ad : in STD_LOGIC_VECTOR (3 downto 0); + f : in STD_LOGIC_VECTOR (3 downto 0); + dest_ctl : in STD_LOGIC_VECTOR (2 downto 0); + oe : in STD_LOGIC; + y : inout STD_LOGIC_VECTOR (3 downto 0)); +end out_mux; + +architecture out_mux of out_mux is + signal y_int: STD_LOGIC_VECTOR(3 downto 0); ---output before tri-state + ---- buffer +begin + y_int <= ad when dest_ctl = rama else f; + y <= y_int when oe='0' else "ZZZZ"; + +end out_mux; +
Am9080/Am29XX/Old/out_mux.vhd Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/Am29XX/Old/q_reg.vhd =================================================================== --- Am9080/Am29XX/Old/q_reg.vhd (nonexistent) +++ Am9080/Am29XX/Old/q_reg.vhd (revision 5) @@ -0,0 +1,81 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 11:13:03 04/26/2010 +-- Design Name: +-- Module Name: q_reg - q_reg +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE;--,basic; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.mnemonics.all; +--use basic.regs_pkg.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity q_reg is + Port ( clk : in STD_LOGIC; + rst : in STD_LOGIC; + f : in std_logic_vector (3 downto 0); + dest_ctl : in STD_LOGIC_VECTOR (2 downto 0); + qs0 : inout STD_LOGIC; + qs3 : inout STD_LOGIC; + q : out std_logic_vector (3 downto 0)); +end q_reg; + +architecture q_reg of q_reg is + + component ureg is + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + load : in STD_LOGIC; + d : in std_logic_vector (3 downto 0); + q : out std_logic_vector (3 downto 0)); +end component; + + signal q_en: std_logic; + signal data: std_logic_vector(3 downto 0); + + + +begin + + ---define q register: + u1: ureg port map (clk,rst,q_en,data,q); + + ---- define q_en: + with dest_ctl select + q_en <='1' when qreg|ramqd|ramqu, + '0' when others; + + ----define data input to q register: + + with dest_ctl select + data<=(f(2),f(1),f(0),qs0) when ramqu , --- shift up + (qs3,f(3),f(2),f(1)) when ramqd, --- shift down + f when qreg, + "----" when others; + + ----define qs0 and qs3 inouts: + + qs3 <=f(3) when (dest_ctl = ramu or dest_ctl = ramqu) else 'Z'; + qs0 <=f(0) when (dest_ctl = ramd or dest_ctl = ramqd) else 'Z'; + +end q_reg; +
Am9080/Am29XX/Old/q_reg.vhd Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/Am29XX/Old/ram_regs.vhd =================================================================== --- Am9080/Am29XX/Old/ram_regs.vhd (nonexistent) +++ Am9080/Am29XX/Old/ram_regs.vhd (revision 5) @@ -0,0 +1,113 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:16:34 04/08/2010 +-- Design Name: +-- Module Name: ram_regs - ram_regs +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE;--, basic; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.mnemonics.all; +--use basic.regs_pkg.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ram_regs is + Port ( clk : in STD_LOGIC; + rst : in STD_LOGIC; + a : in std_logic_vector (3 downto 0); + b : in std_logic_vector (3 downto 0); + f : in std_logic_vector (3 downto 0); + dest_ctl : in STD_LOGIC_VECTOR (2 downto 0); + ram0 : inout STD_LOGIC; + ram3 : inout STD_LOGIC; + ad : buffer std_logic_vector (3 downto 0); + bd : buffer std_logic_vector (3 downto 0)); +end ram_regs; + +architecture ram_regs of ram_regs is + + + component ureg is + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + load : in STD_LOGIC; + d : in std_logic_vector (3 downto 0); + q : out std_logic_vector (3 downto 0)); +end component; + + + + + + + + + signal ram_en: std_logic; + signal data: std_logic_vector (3 downto 0); + signal en : std_logic_vector(15 downto 0); + type ram_array is array(15 downto 0) of std_logic_vector (3 downto 0); + signal ab_data: ram_array; + +begin + + --define register array: + + gen : for i in 15 downto 0 generate + ram : ureg + port map(clk,rst,en(i),data,ab_data(i)); + end generate; + + ---decode b to determine which register is enabled: + + with dest_ctl select + ram_en <='0' when qreg |nop, + '1' when others; + + decode_b: process(b, ram_en) + begin + for i in 0 to 15 loop + if CONV_INTEGER(b) = i then en(i) <= ram_en; + else en(i) <='0'; + end if; + end loop; + end process; + + ----define data input to register array: + + with dest_ctl select + data<=(f(2),f(1),f(0),ram0) when ramqu|ramu , --shift up + (ram3,f(3),f(2),f(1)) when ramqd| ramd , --shift down + f when rama|ramf, + "----" when others; + + --define reg_array output for a and b regs: + + ad<= ab_data(CONV_INTEGER(a)); --- to_integer defined in + bd<= ab_data(CONV_INTEGER(b)); --- numeric_std (See Chapter 7) + + ----define ram0 and ram3 inouts: + ram3 <= f(3) when (dest_ctl = ramu or dest_ctl = ramqu ) else 'Z'; + ram0 <= f(0) when (dest_ctl = ramd or dest_ctl = ramqd) else 'Z'; + + + +end ram_regs; +
Am9080/Am29XX/Old/ram_regs.vhd Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/Am29XX/Old/src_op.vhd =================================================================== --- Am9080/Am29XX/Old/src_op.vhd (nonexistent) +++ Am9080/Am29XX/Old/src_op.vhd (revision 5) @@ -0,0 +1,58 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:00:06 04/26/2010 +-- Design Name: +-- Module Name: src_op - src_op +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use WORK.MNEMONICS.ALL; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity src_op is + Port ( d : in std_logic_vector (3 downto 0); + ad : in std_logic_vector (3 downto 0); + bd : in std_logic_vector (3 downto 0); + q : in std_logic_vector (3 downto 0); + src_ctl : in STD_LOGIC_VECTOR (2 downto 0); + r : buffer std_logic_vector (3 downto 0); + s : buffer std_logic_vector (3 downto 0)); +end src_op; + +architecture src_op of src_op is + +begin + ---decode alu operand r: + + with src_ctl select + r<= ad when aq |ab, + "0000" when zq|zb|za, + d when others; + + with src_ctl select + s<=q when aq|zq|dq, + bd when ab|zb, + ad when za|da, + "0000" when others; + +end src_op; +
Am9080/Am29XX/Old/src_op.vhd Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/Am29XX/Old/ureg.vhd =================================================================== --- Am9080/Am29XX/Old/ureg.vhd (nonexistent) +++ Am9080/Am29XX/Old/ureg.vhd (revision 5) @@ -0,0 +1,67 @@ +-----Set of registers (unsigned) +----- Sizes : (1,size) +----- + +-----clk ---posedge clock input +-----reset -----asynchronous reset +-----load -----active high input loads rregister +-----d -----register input +-----q -----register output + + +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10:52:23 04/26/2010 +-- Design Name: +-- Module Name: ureg - archureg +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ureg is + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + load : in STD_LOGIC; + d : in std_logic_vector (3 downto 0); + q : out std_logic_vector (3 downto 0)); +end ureg; + +architecture archureg of ureg is +signal q_temp: std_logic_vector(3 downto 0); +begin + + p1: process(reset,clk) + begin + if reset ='1' then + q_temp<=(others =>'0'); + elsif (clk'event and clk='1') then + if load='1' then + q_temp<=d; + else + q_temp<=q_temp; + end if; + end if; + end process; +q <= q_temp; +end archureg; +
Am9080/Am29XX/Old/ureg.vhd Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/Am29XX/Am2918.vhd =================================================================== --- Am9080/Am29XX/Am2918.vhd (nonexistent) +++ Am9080/Am29XX/Am2918.vhd (revision 5) @@ -0,0 +1,55 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09/20/2017 11:29:08 PM +-- Design Name: +-- Module Name: Am2918 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Am2918 is + Port ( clk : in STD_LOGIC; + nOE : in STD_LOGIC; + d : in STD_LOGIC_VECTOR (3 downto 0); + o : buffer STD_LOGIC_VECTOR (3 downto 0); + y : out STD_LOGIC_VECTOR (3 downto 0)); +end Am2918; + +architecture Behavioral of Am2918 is + +begin + +y <= o when (nOE = '0') else "ZZZZ"; + +load_q: process(clk, d) +begin + if (rising_edge(clk)) then + o <= d; + end if; +end process; + +end Behavioral;
Am9080/Am29XX/Am2918.vhd Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/Am29XX/Am2920.vhd =================================================================== --- Am9080/Am29XX/Am2920.vhd (nonexistent) +++ Am9080/Am29XX/Am2920.vhd (revision 5) @@ -0,0 +1,62 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09/20/2017 11:10:09 PM +-- Design Name: +-- Module Name: Am2920 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Am2920 is + Port ( clk : in STD_LOGIC; + nE : in STD_LOGIC; + nCLR : in STD_LOGIC; + nOE : in STD_LOGIC; + d : in STD_LOGIC_VECTOR (7 downto 0); + y : out STD_LOGIC_VECTOR (7 downto 0)); +end Am2920; + +architecture Behavioral of Am2920 is + +signal q: std_logic_vector(7 downto 0); + +begin + +y <= q when (nOE = '0') else "ZZZZZZZZ"; + +load_q: process(clk, d, nE, nCLR) +begin + if (nCLR = '0') then + q <= "00000000"; + else + if (rising_edge(clk) and (nE = '0')) then + q <= d; + end if; + end if; +end process; + +end Behavioral;
Am9080/Am29XX/Am2920.vhd Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/Am29XX/Am2922.vhd =================================================================== --- Am9080/Am29XX/Am2922.vhd (nonexistent) +++ Am9080/Am29XX/Am2922.vhd (revision 5) @@ -0,0 +1,79 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09/20/2017 10:32:16 PM +-- Design Name: +-- Module Name: Am2922 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Am2922 is + Port ( clk : in STD_LOGIC; + a : in STD_LOGIC; + b : in STD_LOGIC; + c : in STD_LOGIC; + pol : in STD_LOGIC; + nME : in STD_LOGIC; + nRE : in STD_LOGIC; + nCLR : in STD_LOGIC; + nOE : in STD_LOGIC; + d : in STD_LOGIC_VECTOR (7 downto 0); + y : out STD_LOGIC); +end Am2922; + +architecture Behavioral of Am2922 is + +signal mux, muxen: std_logic; +signal q: std_logic_vector(3 downto 0) := "0000"; + +begin + +muxen <= not nME; +mux <= not ( + (muxen and q(2) and q(1) and q(0) and d(7)) or + (muxen and q(2) and q(1) and (not q(0)) and d(6)) or + (muxen and q(2) and (not q(1)) and q(0) and d(5)) or + (muxen and q(2) and (not q(1)) and (not q(0)) and d(4)) or + (muxen and (not q(2)) and q(1) and q(0) and d(3)) or + (muxen and (not q(2)) and q(1) and (not q(0)) and d(2)) or + (muxen and (not q(2)) and (not q(1)) and q(0) and d(1)) or + (muxen and (not q(2)) and (not q(1)) and (not q(0)) and d(0)) + ); +y <= (q(3) xor mux) when (nOE = '0') else 'Z'; + +load_q: process(clk, a, b, c, pol, nCLR, nRE) +begin + if (nCLR = '0') then + q <= "0000"; + else + if (rising_edge(clk) and (nRE = '0')) then + q <= pol & c & b & a; + end if; + end if; +end process; + +end Behavioral;
Am9080/Am29XX/Am2922.vhd Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/Am29XX/am2909.vhd =================================================================== --- Am9080/Am29XX/am2909.vhd (nonexistent) +++ Am9080/Am29XX/am2909.vhd (revision 5) @@ -0,0 +1,104 @@ +-- VERSION: 1.0 +-- MODULE: am2909 +-- 13/1/2010 +-- ************************************************************ +-- Copyright (C) Stanisalw Deniziak + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity am2909 is + port + ( + -- Input ports + S : in std_logic_vector(1 downto 0); + R,D : in std_logic_vector(3 downto 0); + ORi : in std_logic_vector(3 downto 0); + nFE, PUP, nRE , nZERO, nOE, CN : in std_logic; + CLK : in std_logic; + -- Output ports + Y : out std_logic_vector(3 downto 0); + C4 : out std_logic + ); +end am2909; + +architecture RTL of am2909 is +signal XX, AR, F, PC, YY : std_logic_vector(3 downto 0); +begin + +Sel: process (S, AR, F, PC, D) +begin +case S(1 downto 0) is + when "00" => + XX <= PC; + when "01" => + XX <= AR; + when "10" => + XX <= F; + when "11" => + XX <= D; + when others => + null; + end case; +end process; + +stos: process (CLK) +variable STK0, STK1, STK2, STK3: std_logic_vector(3 downto 0); +begin +if (rising_edge(clk)) then + if (nFE = '0') then + if PUP = '0' then + STK0 := STK1; + STK1 := STK2; + STK2 := STK3; + else + STK3 := STK2; + STK2 := STK1; + STK1 := STK0; + STK0 := PC; + end if; + end if; + end if; + F <= STK0; +end process; + +AReg: process (clk) +begin +if (rising_edge(clk)) then + if nRE = '0' then + AR <= R; + end if; + end if; +end process; + +uPC: process (CLK, YY, CN) +variable res : std_logic_vector(5 downto 0); +variable PCint : std_logic_vector(5 downto 0); +begin + PCint := '0' & YY & CN; + res := std_logic_vector(unsigned(PCint) + 1); + C4 <= res(5); + if (rising_edge(clk)) then + PC <= res(4 downto 1); + end if; +end process; + +output: process (nOE, nZERO, XX, ORi, YY) +begin + if (nZERO = '0') then + YY <= "0000"; + else + YY <= XX or ORi; + end if; + + if (nOE = '0') then + Y <= YY; + else + Y <= "ZZZZ"; + end if; + +end process; + +end RTL; +
Am9080/Am29XX/am2909.vhd Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/prom/desktop.ini =================================================================== --- Am9080/prom/desktop.ini (nonexistent) +++ Am9080/prom/desktop.ini (revision 5) @@ -0,0 +1,4 @@ +[LocalizedFileNames] +testprog3.mif=@testprog3.mif,0 +testprog2.mif=@testprog2.mif,0 +testprog1.mif=@testprog1.mif,0
Am9080/prom/desktop.ini Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/prom/mapper.hex =================================================================== --- Am9080/prom/mapper.hex (nonexistent) +++ Am9080/prom/mapper.hex (revision 5) @@ -0,0 +1,17 @@ +: 10 0000 00 086 022 0DF 06D 0AB 0AA 01B 05A 000 071 0DC 06F 0AB 0AA 01B 05D B9 +: 10 0010 00 000 0E5 0DF 0F1 0AB 0AA 01B 05F 000 073 156 0F6 0AB 0AA 01B 060 ED +: 10 0020 00 000 0E9 0D3 0F3 0AB 0AA 01B 13F 000 074 0C9 0F8 0AB 0AA 01B 0C8 35 +: 10 0030 00 000 0ED 02D 0F5 0A6 0A2 01E 09C 000 075 026 0FA 0AB 0AA 01B 09D 4D +: 10 0040 00 014 014 014 014 014 014 018 014 014 014 014 014 014 014 018 014 B8 +: 10 0050 00 014 014 014 014 014 014 018 014 014 014 014 014 014 014 018 014 B8 +: 10 0060 00 014 014 014 014 014 014 018 014 014 014 014 014 014 014 018 014 B8 +: 10 0070 00 015 015 015 015 015 015 082 015 014 014 014 014 014 014 018 014 47 +: 10 0080 00 034 034 034 034 034 034 035 034 03A 03A 03A 03A 03A 03A 08C 03A 3D +: 10 0090 00 0AC 0AC 0AC 0AC 0AC 0AC 0AD 0AC 0B2 0B2 0B2 0B2 0B2 0B2 0B4 0B2 0D +: 10 00A0 00 09F 09F 09F 09F 09F 09F 0B9 09F 0A0 0A0 0A0 0A0 0A0 0A0 0BC 0A0 D2 +: 10 00B0 00 0A1 0A1 0A1 0A1 0A1 0A1 0BF 0A1 076 076 076 076 086 076 079 076 17 +: 10 00C0 00 10D 07C 107 042 10A 064 038 055 114 050 10E 000 111 047 03F 055 D5 +: 10 00D0 00 11B 0FB 115 08B 118 064 0B0 055 122 000 11C 087 11F 000 0B7 055 D9 +: 10 00E0 00 129 101 123 092 126 064 0C2 055 130 09B 12A 159 12D 000 0C4 055 EC +: 10 00F0 00 137 150 131 090 134 068 0C6 055 13E 091 138 08F 13B 000 077 055 64 +: 00 0000 01 FF
Am9080/prom/mapper.hex Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/prom/mapper.mif =================================================================== --- Am9080/prom/mapper.mif (nonexistent) +++ Am9080/prom/mapper.mif (revision 5) @@ -0,0 +1,265 @@ +; http://www.pastraiser.com/cpu/i8080/i8080_opcodes.html +;PC MICROWORD IN HEX SOURCE CODE +; +0000 086 NOP: FF H#086 +0001 022 LXIB: FF H#022 +0002 0DF STAXB: FF H#0DF +0003 06D INXB: FF H#06D +0004 0AB INRB: FF H#0AB +0005 0AA DCRB: FF H#0AA +0006 01B MVIB: FF H#01B +0007 05A RLC: FF H#05A +0008 000 FF 12X +0009 071 DADB: FF H#071 +000A 0DC LDAXB: FF H#0DC +000B 06F DCXB: FF H#06F +000C 0AB INRC: FF H#0AB +000D 0AA DCRC: FF H#0AA +000E 01B MVIC: FF H#01B +000F 05D RRC: FF H#05D +0010 000 FF 12X +0011 0E5 LXID: FF H#0E5 +0012 0DF STAXD: FF H#0DF +0013 0F1 INXD: FF H#0FI +0014 0AB INRD: FF H#0AB +0015 0AA DCRD: FF H#0AA +0016 01B MVID: FF H#01B +0017 05F RAL: FF H#05F +0018 000 FF 12X +0019 073 DADD: FF H#073 +001A 156 LDAXD: FF H#156 +001B 0F6 DCXD: FF H#0F6 +001C 0AB INRE: FF H#0AB +001D 0AA DCRE: FF H#0AA +001E 01B MVIE: FF H#01B +001F 060 RAR: FF H#060 +0020 000 FF 12X +0021 0E9 LXIH: FF H#0E9 +0022 0D3 SHLD: FF H#0D3 +0023 0F3 INXH: FF H#0F3 +0024 0AB INRH: FF H#0AB +0025 0AA DCRH: FF H#0AA +0026 01B MVIH: FF H#01B +0027 13F DAA: FF H#13F +0028 000 FF 12X +0029 074 DADH: FF H#074 +002A 0C9 LHLD: FF H#0C9 +002B 0F8 DCXH: FF H#0F8 +002C 0AB INRL: FF H#0AB +002D 0AA DCRL: FF H#0AA +002E 01B MVIL: FF H#01B +002F 0C8 CMA: FF H#0C8 +0030 000 FF 12X +0031 0ED LXISP: FF H#0ED +0032 02D STA: FF H#02D +0033 0F5 INXSP: FF H#0F5 +0034 0A6 INRM: FF H#0A6 +0035 0A2 DCRM: FF H#0A2 +0036 01E MVIM: FF H#01E +0037 09C STC: FF H#09C +0038 000 FF 12X +0039 075 DADSP: FF H#075 +003A 026 LDA: FF H#026 +003B 0FA DCXSP: FF H#0FA +003C 0AB INRA: FF H#0AB +003D 0AA DCRA: FF H#0AA +003E 01B MVIA: FF H#01B +003F 09D CMC: FF H#09D +0040 014 MOVB.R FF H#014 +0041 014 MOVB.R FF H#014 +0042 014 MOVB.R FF H#014 +0043 014 MOVB.R FF H#014 +0044 014 NOVB.R FF H#014 +0045 014 MOVB.R FF H#014 +0046 018 MOVB.M FF H#018 +0047 014 MOVB.A FF H#014 +0048 014 MOVC.R FF H#014 +0049 014 MOVC.R FF H#014 +004A 014 MOVC.R FF H#014 +004B 014 MOVC.R FF H#014 +004C 014 MOVC.R FF H#014 +004D 014 MOVC.R FF H#014 +004E 018 MOVC.M FF H#018 +004F 014 MOVX.R FF H#014 +0050 014 MOVX.R FF H#014 +0051 014 MOVX.R FF H#014 +0052 014 MOVX.R FF H#014 +0053 014 MOVX.R FF H#014 +0054 014 MOVX.R FF H#014 +0055 014 NOVX.R FF H#014 +0056 018 MOVD.M FF H#018 +0057 014 MOVY.R FF H#014 +0058 014 MOVY.R FF H#014 +0059 014 MOVY.R FF H#014 +005A 014 MOVY.R FF H#014 +005B 014 MOVY.R FF H#014 +005C 014 MOVY.R FF H#014 +005D 014 MOVY.R FF H#014 +005E 018 MOVE.M FF H#018 +005F 014 MOVZ.R FF H#014 +0060 014 MOVZ.R FF H#014 +0061 014 MOVZ.R FF H#014 +0062 014 MOVZ.R FF H#014 +0063 014 MOVZ.R FF H#014 +0064 014 MOVZ.R FF H#014 +0065 014 MOVZ.R FF H#014 +0066 018 MOVH.M FF H#018 +0067 014 MOVW.R FF H#014 +0068 014 MOVW.R FF H#014 +0069 014 MOVW.R FF H#014 +006A 014 MOVW.R FF H#014 +006B 014 MOVM.R FF H#014 +006C 014 MOVM.R FF H#014 +006D 014 MOVW.R FF H#014 +006E 018 MOVL.M FF H#018 +006F 014 MOVL.A FF H#014 +0070 015 MOVM.R FF H#015 +0071 015 MOVM.R FF H#015 +0072 015 MOVM.R FF H#015 +0073 015 MOVM.R FF H#015 +0074 015 MOVM.R FF H#015 +0075 015 MOVM.R FF H#015 +0076 082 HLT: FF H#082 +0077 015 MOVM.A: FF H#015 +0078 014 MOVA.R: FF H#014 +0079 014 MOVA.R: FF H#014 +007A 014 MOVA.R: FF H#014 +007B 014 MOVA.R: FF H#014 +007C 014 MOVA.R: FF H#014 +007D 014 MOVA.R: FF H#014 +007E 018 MOVA.M: FF H#018 +007F 014 MOVA.A: FF H#014 +0080 034 ADDR: FF H#034 +0081 034 ADDR: FF H#034 +0082 034 ADDR: FF H#034 +0083 034 ADDR: FF H#034 +0084 034 ADDR: FF H#034 +0085 034 ADDR: FF H#034 +0086 035 ADDM: FF H#035 +0087 034 ADDA: FF H#034 +0088 03A ADCR: FF H#03A +0089 03A ADCR: FF H#03A +008A 03A ADCR: FF H#03A +008B 03A ADCR: FF H#03A +008C 03A ADCR: FF H#03A +008D 03A ADCR: FF H#03A +008E 08C ADCM: FF H#03C +008F 03A ADCA: FF H#03A +0090 0AC SUBR: FF H#0AC +0091 0AC SUBR: FF H#0AC +0092 0AC SUBR: FF H#0AC +0093 0AC SUBR: FF H#0AC +0094 0AC SUBR: FF H#0AC +0095 0AC SUBR: FF H#0AC +0096 0AD SUBN: FF H#0AD +0097 0AC SUBA: FF H#0AC +0098 0B2 SBBR: FF H#0B2 +0099 0B2 SBBR: FF H#0B2 +009A 0B2 SBBR: FF H#0B2 +009B 0B2 SBBR: FF H#0B2 +009C 0B2 SBBR: FF H#0B2 +009D 0B2 SBBR: FF H#0B2 +009E 0B4 SBBM: FF H#0B4 +009F 0B2 SBBA: FF H#0B2 +00A0 09F ANAR: FF H#09F +00A1 09F ANAR: FF H#09F +00A2 09F ANAR: FF H#09F +00A3 09F ANAR: FF H#09F +00A4 09F RNAR: FF H#09F +00A5 09F RNAR: FF H#09F +00A6 0B9 ANAM: FF H#089 +00A7 09F ANAA: FF H#09F +00A8 0A0 XRAR: FF H#0A0 +00A9 0A0 XRAR: FF H#0A0 +00AA 0A0 XRAR: FF H#0A0 +00AB 0A0 XRAR: FF H#0A0 +00AC 0A0 XRAR: FF H#0A0 +00AD 0A0 XRAR: FF H#0A0 +00AE 0BC XRAM: FF H#0BC +00AF 0A0 XRAA: FF H#0A0 +00B0 0A1 ORAR: FF H#0A1 +00B1 0A1 ORAR: FF H#0A1 +00B2 0A1 ORAR: FF H#0A1 +00B3 0A1 ORAR: FF H#0A1 +00B4 0A1 ORAR: FF H#0A1 +00B5 0A1 ORAR: FF H#0A1 +00B6 0BF ORAM: FF H#0BF +00B7 0A1 ORAA: FF H#0A1 +00B8 076 CMPR: FF H#076 +00B9 076 CMPR: FF H#076 +00BA 076 CMPR: FF H#076 +00BB 076 CMPR FF H#076 +00BE 076 CMPR FF H#076 +00BD 076 CMPR FF H#076 +00BE 079 CMPM FF H#079 +00BF 076 CMPA FF H#076 +00C0 10D RNZ: FF H#100 +00C1 07C POPB: FF H#07C +00C2 107 JNZ: FF H#107 +00C3 042 JMP: FF H#042 +00C4 10A CNZ: FF H#10A +00C5 064 PUSHB: FF H#064 +00C6 038 ADI: FF H#038 +00C7 055 RST0: FF H#055 +00C8 114 RZ: FF H#114 +00C9 050 RET: FF H#050 +00CA 10E JZ: FF H#10E +00CB 000 FF 12X +00CC 111 CZ: FF H#111 +00CD 047 CALL: FF H#047 +00CE 03F ACI: FF H#03F +00CF 055 RST1: FF H#055 +00D0 11B RNC: FF H#11B +00D1 0FB POPD: FF H#0FB +00D2 115 JNC: FF H#115 +00D3 08B OUT.: FF H#08B +00D4 118 CNC: FF H#118 +00D5 064 PUSHD: FF H0064 +00D6 0B0 SUI: FF H#0B0 +00D7 055 RST2: FF H#055 +00D8 122 RC: FF H#122 +00D9 000 FF 12X +00DA 11C JC: FF H#11C +00DB 087 IN.: FF H#087 +00DC 11F CC: FF H#11F +00DD 000 FF 12X +00DE 0B7 SBI: FF H#0B7 +00DF 055 RST3: FF H#055 +00E0 129 RPO: FF H#129 +00E1 101 POPH: FF H#101 +00E2 123 JPO: FF H#123 +00E3 092 XTHL: FF H#092 +00E4 126 CPD: FF H#126 +00E5 064 PUSHH: FF H#064 +00E6 0C2 ANI: FF H#0C2 +00E7 055 RST4: FF H#055 +00E8 130 RPE: FF H#130 +00E9 09B PCHL: FF H#09B +00EA 12A JPE: FF H#12A +00EB 159 XCHG: FF H#159 +00EC 12D CPE: FF H#12D +00ED 000 FF 12X +00EE 0C4 XRI: FF H#0C4 +00EF 055 RST5: FF H#055 +00F0 137 RP: FF H#037 +00F1 150 P0PPSW: FF H#150 +00F2 131 JP: FF H#131 +00F3 090 DI: FF H#090 +00F4 134 CP: FF H#134 +00F5 068 PUSHPSW: FF H#068 +00F6 0C6 ORI: FF H#0C6 +00F7 055 RST6: FF H#055 +00F8 13E RM: FF H#13E +00F9 091 SPHL: FF H#091 +00FA 138 JM: FF H#138 +00FB 08F EI: FF H#08F +00FC 13B CM: FF H#13B +00FD 000 FF 12X +00FE 077 CPI: FF H#077 +00FF 055 RST7: FF H#055 +; END + + + + +
Am9080/prom/mapper.mif Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/prom/microcode.hex =================================================================== --- Am9080/prom/microcode.hex (nonexistent) +++ Am9080/prom/microcode.hex (revision 5) @@ -0,0 +1,560 @@ +-------------------------------------------------------------------------------- + I D DIRECT-VALUE NXT P COND B SYSCTL OE OS A UK S C W AADR BADR DST FCT SRC +-------------------------------------------------------------------------------- +0000 1 0 000000111000 000 0 1111 0 111110 00 11 0 11 0 1 1 1111 1111 011 100 100 +0001 1 1 000000000000 000 0 1111 0 111110 00 00 0 11 0 1 0 1010 1101 011 011 111 +0002 1 1 000000000000 000 0 1111 0 111110 00 00 0 11 0 1 0 1010 1100 011 100 100 +0003 1 1 000000000000 110 1 1111 0 111110 00 10 0 11 0 1 0 1010 1010 011 100 100 +0004 0 1 000000000100 000 0 1001 0 111010 00 10 0 11 0 1 1 1111 1111 011 011 100 +0005 1 1 000000001100 001 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0000 0000 000 000 000 +01FC 0 0 000000000000 000 0 0000 0 000000 00 00 0 00 0 0 0 0000 0000 000 000 000 +01FD 0 0 000000000000 000 0 0000 0 000000 00 00 0 00 0 0 0 0000 0000 000 000 000 +01FE 0 0 000000000000 000 0 0000 0 000000 00 00 0 00 0 0 0 0000 0000 000 000 000 +01FF 1 1 000010000100 000 1 1111 0 111110 00 00 0 11 0 1 0 1010 1010 001 000 000
Am9080/prom/microcode.hex Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/prom/microcode.lst =================================================================== --- Am9080/prom/microcode.lst (nonexistent) +++ Am9080/prom/microcode.lst (revision 5) @@ -0,0 +1,561 @@ +----------------------------------------------------------------------------------------- + I D DIRECT-VALUE NXT P COND B SYSCTL OE OS A UK S C W AADR BADR DST FCT SRC +----------------------------------------------------------------------------------------- +0000 - m 000000111000 C/R - TRUE 0 NOC -- INTE 0 11 0 1 16 R_PC R_PC RAMF AND ZA +0001 - - 000000000000 C/R - TRUE 0 NOC -- ---- 0 11 0 1 8 RAS1 R38Z RAMF OR DZ +0002 - - 000000000000 C/R - TRUE 0 NOC -- ---- 0 11 0 1 8 RAS1 RZ38 RAMF AND ZA +0003 - - 000000000000 R/PUSH ! TRUE 0 NOC -- ADDR 0 11 0 1 8 RAS1 RAS1 RAMF AND ZA +0004 i - = location = C/R - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF OR ZA +0005 - - 000000001100 D/R ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0006 (uninitialized) +0007 (uninitialized) +0008 (uninitialized) +0009 (uninitialized) +000A - - = location = R/RTN - HOLD 0 HLDA -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +000B - - = location = R/F - HOLD 0 HLDA -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +000C - - = location = D/R ! HOLD 0 HLDA -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +000D - - = location = R/RTN ! RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF OR ZA +000E - - = location = R/RTN ! RDY 0 MEMW YH ADDR 0 11 0 1 16 R_PC R_PC RAMF OR ZA +000F - - = location = R/F ! RDY 0 MEMW YH ADDR 0 11 0 1 16 R_PC R_PC RAMF OR ZA +0010 - - = location = R/F ! RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF OR ZA +0011 - - = location = R/RTN ! RDY 0 MEMR -- ADDR 0 11 0 1 16 R_SP R_SP RAMF OR ZA +0012 - - = location = R/RTN ! RDY 0 MEMW YH ADDR 0 11 0 1 16 R_SP R_SP RAMF OR ZA +0013 - - = location = R/RTN ! RDY 0 MEMW YL ADDR 0 11 0 1 16 R_SP R_SP RAMF OR ZA +0014 - - 000000001011 R/F - HOLD 1 NOC -- ---- 1 11 0 1 8 RAS1 RAS1 RAMF OR ZA +0015 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_HL RAS1 NOP OR ZA +0016 - - 000000001010 C/SBR ! HOLD 0 NOC -- DATA 1 11 0 1 8 RAS1 RAS1 NOP OR ZA +0017 - - = location = R/F ! RDY 0 MEMW YH ADDR 0 11 0 1 16 R_PC R_PC RAMF OR ZA +0018 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_HL RAS1 NOP OR ZA +0019 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF OR ZA +001A - - 000000001011 R/F - HOLD 1 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 RAMF OR DZ +001B - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +001C - - 000000001011 R/F - HOLD 1 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 RAMF OR DZ +001D - - 111111111111 R/F ! TRUE 0 HLDA FL INTE 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +001E - - 000000001101 C/SBR - RDY 0 MEMR -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +001F - - 000000001010 C/SBR ! HOLD 0 NOC -- DATA 0 11 0 1 8 RAS1 RAS1 RAMF OR DZ +----------------------------------------------------------------------------------------- + I D DIRECT-VALUE NXT P COND B SYSCTL OE OS A UK S C W AADR BADR DST FCT SRC +----------------------------------------------------------------------------------------- +0020 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_HL RAS1 NOP OR ZA +0021 - - 000000001111 R/F ! RDY 0 MEMW YH ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0022 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0023 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_CB RAMF OR DZ +0024 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0025 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_BC RAMF OR DZ +0026 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0027 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 16 RAS1 RAS1 RAMF OR DZ +0028 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0029 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 RAMF OR DZ +002A - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 RAS1 RAS1 NOP OR ZA +002B - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF OR ZA +002C - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 0 1 8 R_A? R_A? RAMF OR DZ +002D - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +002E - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 16 RAS1 RAS1 RAMF OR DZ +002F - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0030 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 RAMF OR DZ +0031 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 RAS1 RAS1 RAMF OR ZA +0032 - - 000000001010 C/SBR ! HOLD 0 NOC -- DATA 0 11 0 1 8 R_A? R_A? RAMF OR ZA +0033 - - 000000001111 R/F ! RDY 0 MEMW YH ADDR 0 11 0 1 16 R_PC R_PC RAMF OR ZA +0034 - - 000000001011 R/F - HOLD 0 NOC -- ---- 1 00 0 0 8 RAS1 R_A? RAMF ADD AB +0035 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_HL RAS1 NOP OR ZA +0036 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF OR ZA +0037 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 00 0 0 8 R_A? R_A? RAMF ADD DA +0038 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0039 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 00 0 0 8 R_A? R_A? RAMF ADD DA +003A - - 000000110100 C/R - CY 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +003B - - 000000001011 R/F - HOLD 0 NOC -- ---- 1 00 0 1 8 RAS1 R_A? RAMF ADD AB +003C - - 000000110110 C/R - CY 0 NOC -- ADDR 0 11 0 1 16 R_HL RAS1 NOP OR ZA +003D - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF OR ZA +003E - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 00 0 1 8 R_A? R_A? RAMF ADD DA +003F - - 000000111000 C/R - CY 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +----------------------------------------------------------------------------------------- + I D DIRECT-VALUE NXT P COND B SYSCTL OE OS A UK S C W AADR BADR DST FCT SRC +----------------------------------------------------------------------------------------- +0040 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0041 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 00 0 1 8 R_A? R_A? RAMF ADD DA +0042 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0043 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 16 RAS1 RAS1 RAMF OR DZ +0044 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0045 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 RAMF OR DZ +0046 - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 RAS1 R_PC RAMA OR ZA +0047 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0048 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 16 RAS1 RAS1 RAMF OR DZ +0049 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +004A - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 RAMF OR DZ +004B - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 0 16 R_SP R_SP RAMF SUBR ZA +004C - - 000000001010 C/SBR ! HOLD 0 NOC -- DATA 0 11 0 1 16 R_PC RAS1 NOP OR ZA +004D - - 000000010010 C/SBR - RDY 0 MEMW YH ADDR 0 11 0 0 16 R_SP R_SP RAMF SUBR ZA +004E - - = location = R/F ! RDY 0 MEMW YL ADDR 0 11 0 1 16 RAS1 R_PC RAMF OR ZA +004F - - 111111111111 R/F ! TRUE 0 HLDA FL INTE 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0050 - - 000000010001 C/SBR ! TRUE 0 NOC -- ADDR 0 11 0 1 16 R_SP R_SP RAMA ADD ZA +0051 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 16 R_PC R_PC RAMF OR DZ +0052 - - 000000010001 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_SP R_SP RAMA ADD ZA +0053 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 R_PC R_PC RAMF OR DZ +0054 - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC NOP OR ZA +0055 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 16 RZ38 RAS1 RAMF AND DA +0056 - - 000000001010 C/SBR ! HOLD 0 NOC -- DATA 0 11 0 1 16 R_PC RAS1 NOP OR ZA +0057 - - 000000010010 C/SBR ! TRUE 0 NOC -- ADDR 0 11 0 0 16 R_SP R_SP RAMF SUBR ZA +0058 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 0 16 R_SP R_SP RAMF SUBR ZA +0059 - - = location = R/F ! RDY 0 MEMW YL ADDR 0 11 0 1 16 RAS1 R_PC RAMF OR ZA +005A - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 01 0 1 8 R_A? R_A? RAMU OR ZA +005B - - 000010011100 R/F - F3 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +005C - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 01 0 1 8 RAS1 RAS1 NOP OR DZ +005D - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 01 0 1 8 R_A? R_A? RAMD OR ZA +005E - - 000001011011 C/R ! TRUE 0 NOC -- ---- 0 11 0 1 8 R_A? RAS1 NOP OR ZA +005F - - 000001011011 C/R ! TRUE 0 NOC -- ---- 0 01 1 1 8 R_A? R_A? RAMU OR ZA +----------------------------------------------------------------------------------------- + I D DIRECT-VALUE NXT P COND B SYSCTL OE OS A UK S C W AADR BADR DST FCT SRC +----------------------------------------------------------------------------------------- +0060 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 R_A? R_A? RAMD OR ZA +0061 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 R_A? R_A? RAMU OR ZA +0062 - - 000010011100 R/F - F3 0 NOC -- ---- 0 01 1 1 8 R_A? R_A? RAMD OR ZA +0063 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 01 0 1 8 RAS1 RAS1 NOP OR DZ +0064 - - 000000001010 C/SBR ! HOLD 1 NOC -- DATA 0 11 0 1 16 RAS1 RAS1 NOP OR ZB +0065 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 0 16 R_SP R_SP RAMF SUBR ZA +0066 - - 000000010010 C/SBR - RDY 0 MEMW YH ADDR 0 11 0 0 16 R_SP R_SP RAMF SUBR ZA +0067 - - = location = R/F ! RDY 0 MEMW YL ADDR 0 11 0 1 16 R_PC R_PC RAMF OR ZA +0068 - - 000000001010 C/SBR ! HOLD 0 NOC -- DATA 0 11 0 1 8 R_A? RAS1 NOP OR ZA +0069 - - 000000010010 C/SBR ! TRUE 0 NOC -- ADDR 0 11 0 0 16 R_SP R_SP RAMF SUBR ZA +006A - - 000001101011 R/F - TRUE 0 NOC -- ADDR 0 11 0 0 16 R_SP R_SP RAMF SUBR ZA +006B - - 000000010010 C/SBR - RDY 0 MEMW FL ---- 0 11 0 0 8 RAS1 RAS1 NOP EXNOR DZ +006C - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF OR ZA +006D - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 16 RAS1 R_BC RAMF ADD ZB +006E - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 1 1 16 R_BC R_CB RAMA OR DZ +006F - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 0 16 RAS1 R_BC RAMF SUBR ZB +0070 - - 000000001011 R/F - HOLD 1 NOC -- ---- 1 11 1 1 16 R_BC R_CB RAMA OR DZ +0071 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 01 0 0 16 R_BC R_HL RAMF ADD AB +0072 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 1 1 16 R_HL R_LH RAMA OR DZ +0073 - - 000001110010 C/R ! TRUE 0 NOC -- ---- 0 01 0 0 16 R_DE R_HL RAMF ADD AB +0074 - - 000001110010 C/R ! TRUE 0 NOC -- ---- 0 01 0 0 16 R_HL R_HL RAMF ADD AB +0075 - - 000001110010 C/R ! TRUE 0 NOC -- ---- 0 01 0 0 16 R_SP R_HL RAMF ADD AB +0076 - - 000000001011 R/F - HOLD 0 NOC -- ---- 1 00 0 1 8 RAS1 R_A? NOP SUBR AB +0077 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0078 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 00 0 1 8 R_A? RAS1 NOP SUBR DA +0079 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_HL RAS1 NOP OR ZA +007A - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC RAS1 NOP OR ZA +007B - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 00 0 1 8 R_A? RAS1 NOP SUBR DA +007C - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_SP R_SP RAMA OR ZA +007D - - 000000010001 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_SP R_SP RAMF ADD ZA +007E - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_CB RAMF OR DZ +007F - - 000000010001 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_SP R_SP RAMF ADD ZA +----------------------------------------------------------------------------------------- + I D DIRECT-VALUE NXT P COND B SYSCTL OE OS A UK S C W AADR BADR DST FCT SRC +----------------------------------------------------------------------------------------- +0080 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_BC RAMF OR DZ +0081 - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC RAS1 NOP OR ZA +0082 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0083 - - 000010000010 C/R - INT 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0084 - - 000000000000 C/R - TRUE 0 INTA -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0085 - - 000001010110 C/R ! TRUE 0 INTA -- ---- 0 11 0 1 16 RZ38 RAS1 RAMA AND DA +0086 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0087 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0088 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 8 RAS1 RAS1 NOP OR DZ +0089 - - = location = C/R - RDY 0 IOR -- ADDR 0 11 0 1 16 R_PC RAS1 NOP OR ZA +008A - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_A? RAMF OR DZ +008B - - 000000001010 C/SBR ! HOLD 0 NOC -- DATA 0 11 0 1 8 R_A? RAS1 NOP OR ZA +008C - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +008D - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 8 RAS1 RAS1 NOP OR DZ +008E - - = location = R/F ! RDY 0 IOW YH ADDR 0 11 0 1 16 R_PC RAS1 NOP OR ZA +008F - - 000000001011 R/F - HOLD 0 NOC -- INTE 0 11 0 1 8 RZ38 RAS1 NOP EXNOR ZA +0090 - - 000000001011 R/F - HOLD 0 NOC -- INTE 0 11 0 1 8 RAS1 RAS1 NOP AND ZA +0091 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 0 1 16 R_HL R_SP RAMF OR ZA +0092 - - 000000001010 C/SBR ! HOLD 0 NOC -- DATA 0 11 0 1 16 R_HL RAS1 NOP OR ZA +0093 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_SP RAS1 NOP OR ZA +0094 - - = location = C/R - RDY 0 MEMR -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0095 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_LH RAMF OR DZ +0096 - - 000000010011 C/SBR - RDY 0 MEMW YL ADDR 0 11 0 1 16 R_SP R_SP RAMF ADD ZA +0097 - - = location = C/R - RDY 0 MEMR -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0098 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_HL RAMF OR DZ +0099 - - = location = C/R - RDY 0 MEMW YH ADDR 0 11 0 1 16 R_PC RAS1 NOP OR ZA +009A - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 0 0 16 R_SP R_SP RAMF SUBR ZA +009B - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_HL R_PC RAMF OR ZA +009C - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 01 0 0 8 RZ38 RAS1 NOP SUBR ZA +009D - - 000010011100 R/F ! CY 0 NOC -- ---- 0 01 0 1 8 RAS1 RAS1 NOP AND ZA +009E - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 01 0 0 8 RAS1 RAS1 NOP AND ZA +009F - - 000000001011 R/F - HOLD 0 NOC -- ---- 1 00 0 1 8 RAS1 R_A? RAMF AND AB +----------------------------------------------------------------------------------------- + I D DIRECT-VALUE NXT P COND B SYSCTL OE OS A UK S C W AADR BADR DST FCT SRC +----------------------------------------------------------------------------------------- +00A0 - - 000000001011 R/F - HOLD 0 NOC -- ---- 1 00 0 1 8 RAS1 R_A? RAMF EXOR AB +00A1 - - 000000001011 R/F - HOLD 0 NOC -- ---- 1 00 0 1 8 RAS1 R_A? RAMF OR AB +00A2 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_HL RAS1 NOP OR ZA +00A3 - - = location = C/R - RDY 0 MEMR -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +00A4 - - 000000001010 C/SBR ! HOLD 0 NOC -- DATA 0 10 0 0 8 RAS1 RAS1 NOP SUBS DZ +00A5 - - = location = R/F ! RDY 0 MEMW YH ADDR 0 11 0 1 16 R_PC RAS1 NOP OR ZA +00A6 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_HL RAS1 NOP OR ZA +00A7 - - = location = C/R - RDY 0 MEMR -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +00A8 - - 000000001010 C/SBR ! HOLD 0 NOC -- DATA 0 10 0 1 8 RAS1 RAS1 NOP ADD DZ +00A9 - - = location = R/F ! RDY 0 MEMW YH ADDR 0 11 0 1 16 R_PC RAS1 NOP OR ZA +00AA - - 000000001011 R/F - HOLD 1 NOC -- ---- 0 10 0 0 8 RAS1 RAS1 RAMF SUBR ZB +00AB - - 000000001011 R/F - HOLD 1 NOC -- ---- 0 10 0 1 8 RAS1 RAS1 RAMF ADD ZB +00AC - - 000000001011 R/F - HOLD 0 NOC -- ---- 1 00 0 1 8 RAS1 R_A? RAMF SUBR AB +00AD - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_HL RAS1 NOP OR ZA +00AE - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC RAS1 NOP OR ZA +00AF - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 00 0 1 8 R_A? R_A? RAMF SUBR DA +00B0 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +00B1 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 00 0 1 8 R_A? R_A? RAMF SUBR DA +00B2 - - 000010101100 C/R - CY 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +00B3 - - 000000001011 R/F - HOLD 0 NOC -- ---- 1 00 0 0 8 RAS1 R_A? RAMF SUBR AB +00B4 - - 000010101110 C/R - CY 0 NOC -- ADDR 0 11 0 1 16 R_HL RAS1 NOP OR ZA +00B5 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC RAS1 NOP OR ZA +00B6 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 00 0 0 8 R_A? R_A? RAMF SUBR DA +00B7 - - 000010110000 C/R - CY 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +00B8 - - 000101011101 C/R ! TRUE 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +00B9 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_HL RAS1 NOP OR ZA +00BA - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC RAS1 NOP OR ZA +00BB - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 00 0 1 8 R_A? R_A? RAMF AND DA +00BC - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_HL RAS1 NOP OR ZA +00BD - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC RAS1 NOP OR ZA +00BE - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 00 0 1 8 R_A? R_A? RAMF EXOR DA +00BF - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_HL RAS1 NOP OR ZA +----------------------------------------------------------------------------------------- + I D DIRECT-VALUE NXT P COND B SYSCTL OE OS A UK S C W AADR BADR DST FCT SRC +----------------------------------------------------------------------------------------- +00C0 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC RAS1 NOP OR ZA +00C1 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 00 0 1 8 R_A? R_A? RAMF OR DA +00C2 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +00C3 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 00 0 1 8 R_A? R_A? RAMF AND DA +00C4 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +00C5 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 00 0 1 8 R_A? R_A? RAMF EXOR DA +00C6 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +00C7 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 00 0 1 8 R_A? R_A? RAMF OR DA +00C8 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 0 1 8 R_A? R_A? RAMF EXNOR ZA +00C9 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +00CA - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 16 RAS1 RAS1 RAMF OR DZ +00CB - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +00CC - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 RAMF OR DZ +00CD - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 RAS1 RAS1 RAMF OR ZA +00CE - - = location = C/R - RDY 0 MEMR -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +00CF - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_LH RAMF OR DZ +00D0 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 RAS1 RAS1 RAMF ADD ZA +00D1 - - = location = C/R - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC RAS1 NOP OR ZA +00D2 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_HL RAMF OR DZ +00D3 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +00D4 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 16 RAS1 RAS1 RAMF OR DZ +00D5 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +00D6 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 RAMF OR DZ +00D7 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 RAS1 RAS1 RAMF OR ZA +00D8 - - 000000001010 C/SBR ! HOLD 0 NOC -- DATA 0 11 0 1 16 R_HL RAS1 NOP OR ZA +00D9 - - = location = C/R - RDY 0 MEMW YL ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +00DA - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 RAS1 RAS1 RAMF ADD ZA +00DB - - = location = R/F ! RDY 0 MEMW YH ADDR 0 11 0 1 16 R_PC RAS1 NOP OR ZA +00DC - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_BC RAS1 NOP OR ZA +00DD - - = location = C/R - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC RAS1 NOP OR ZA +00DE - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_A? RAMF OR DZ +00DF - - 000000001010 C/SBR ! HOLD 1 NOC -- ADDR 0 11 0 1 16 RAS1 RAS1 NOP OR ZB +----------------------------------------------------------------------------------------- + I D DIRECT-VALUE NXT P COND B SYSCTL OE OS A UK S C W AADR BADR DST FCT SRC +----------------------------------------------------------------------------------------- +00E0 - - 000000001010 C/SBR ! HOLD 0 NOC -- DATA 0 11 0 1 8 R_A? RAS1 NOP OR ZA +00E1 - - 000000001011 R/F - HOLD 0 MEMW YH ADDR 0 11 0 1 16 R_PC RAS1 NOP OR ZA +00E2 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 16 R_DE RAS1 RAMF OR ZA +00E3 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 16 R_HL R_DE RAMF OR ZA +00E4 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 0 1 16 RAS1 R_HL RAMF OR ZA +00E5 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +00E6 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_ED RAMF OR DZ +00E7 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +00E8 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_DE RAMF OR DZ +00E9 - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +00EA - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_LH RAMF OR DZ +00EB - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +00EC - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_HL RAMF OR DZ +00ED - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +00EE - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 16 RAS1 R_SP RAMF OR DZ +00EF - - 000000011101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +00F0 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_SP RAMF OR DZ +00F1 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 16 RAS1 R_DE RAMF ADD ZB +00F2 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 1 1 16 R_DE R_ED RAMA OR DZ +00F3 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 16 RAS1 R_HL RAMF ADD ZB +00F4 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 1 1 16 R_HL R_LH RAMA OR DZ +00F5 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 0 1 16 RAS1 R_SP RAMF ADD ZB +00F6 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 0 16 RAS1 R_DE RAMF SUBR ZB +00F7 - - 000000001011 R/F - HOLD 1 NOC -- ---- 1 11 1 1 16 R_DE R_ED RAMA OR DZ +00F8 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 0 16 RAS1 R_HL RAMF SUBR ZB +00F9 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 1 1 16 R_HL R_LH RAMA OR DZ +00FA - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 0 0 16 RAS1 R_SP RAMF SUBR ZB +00FB - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_SP R_SP RAMA OR ZA +00FC - - 000000010001 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_SP R_SP RAMF ADD ZA +00FD - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_ED RAMF OR DZ +00FE - - 000000010001 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_SP R_SP RAMF ADD ZA +00FF - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_DE RAMF OR DZ +----------------------------------------------------------------------------------------- + I D DIRECT-VALUE NXT P COND B SYSCTL OE OS A UK S C W AADR BADR DST FCT SRC +----------------------------------------------------------------------------------------- +0100 - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC RAS1 NOP OR ZA +0101 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_SP R_SP RAMA OR ZA +0102 - - 000000010001 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_SP R_SP RAMF ADD ZA +0103 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_LH RAMF OR DZ +0104 - - 000000010001 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_SP R_SP RAMF ADD ZA +0105 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_HL RAMF OR DZ +0106 - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC RAS1 NOP OR ZA +0107 - - 000001000010 C/R - Z 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0108 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0109 - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +010A - - 000001000111 C/R - Z 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +010B - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +010C - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +010D - - 000001010000 R/F ! Z 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +010E - - 000001000010 C/R ! Z 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +010F - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0110 - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0111 - - 000001000111 C/R ! Z 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0112 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0113 - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0114 - - 000001010000 R/F - Z 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0115 - - 000001000010 C/R - CY 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0116 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0117 - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0118 - - 000001000111 C/R - CY 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0119 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +011A - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +011B - - 000001010000 R/F ! CY 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +011C - - 000001000010 C/R ! CY 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +011D - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +011E - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +011F - - 000001000111 C/R ! CY 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +----------------------------------------------------------------------------------------- + I D DIRECT-VALUE NXT P COND B SYSCTL OE OS A UK S C W AADR BADR DST FCT SRC +----------------------------------------------------------------------------------------- +0120 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0121 - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0122 - - 000001010000 R/F - CY 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0123 - - 000001000010 C/R - P 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0124 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0125 - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0126 - - 000001000111 C/R - P 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0127 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0128 - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0129 - - 000001010000 R/F ! P 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +012A - - 000001000010 C/R ! P 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +012B - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +012C - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +012D - - 000001000111 C/R ! P 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +012E - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +012F - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0130 - - 000001010000 R/F - P 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0131 - - 000001000010 C/R - S 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0132 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0133 - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0134 - - 000001000111 R/F ! S 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0135 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0136 - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +0137 - - 000001010000 C/R - S 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0138 - - 000001000010 C/R ! S 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0139 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +013A - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +013B - - 000001000111 C/R ! S 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +013C - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +013D - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +013E - - 000001010000 R/F - S 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +013F - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +----------------------------------------------------------------------------------------- + I D DIRECT-VALUE NXT P COND B SYSCTL OE OS A UK S C W AADR BADR DST FCT SRC +----------------------------------------------------------------------------------------- +0140 - m 000000000110 C/R - TRUE 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0141 - - 000101000110 C/R ! AC 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 RAMF OR DZ +0142 - m 000000001111 C/R - TRUE 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0143 - m 000000001010 C/R - TRUE 0 NOC -- ---- 0 11 0 1 8 R_A? RAS1 QREG AND DA +0144 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP SUBR DQ +0145 - - 000101000111 C/R - CN4 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0146 - - 000101011111 C/SBR ! CY 0 NOC -- ---- 0 00 0 0 8 RAS1 R_A? RAMF ADD AB +0147 - m 000001100000 C/R - TRUE 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +0148 - - 000101001111 C/R ! CY 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 RAMF OR DZ +0149 - m 000011110000 C/R - TRUE 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +014A - m 000010100000 C/R - TRUE 0 NOC -- ---- 0 11 0 1 8 R_A? RAS1 QREG AND DA +014B - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP SUBR DQ +014C - - 000101001110 C/R - CN4 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +014D - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 00 0 0 8 RAS1 R_A? RAMF ADD AB +014E - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ +014F - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 10 0 0 8 RAS1 R_A? RAMF ADD AB +0150 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_SP R_SP RAMA OR ZA +0151 - - 000000010001 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_SP R_SP RAMF ADD ZA +0152 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP NOTRS DZ +0153 - - 000000010001 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_SP R_SP RAMF ADD ZA +0154 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_A? RAMF OR DZ +0155 - - 000000001011 R/F - HOLD 0 NOC -- ADDR 0 11 0 1 16 R_PC RAS1 NOP OR ZA +0156 - - 000000001010 C/SBR ! HOLD 0 NOC -- ADDR 0 11 0 1 16 R_DE RAS1 NOP OR ZA +0157 - - = location = C/R - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC RAS1 NOP OR ZA +0158 - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 0 1 8 RAS1 R_A? RAMF OR DZ +0159 - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 1 1 16 R_DE R_LH RAMA OR DZ +015A - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 0 1 16 R_HL R_DE RAMA OR ZA +015B - - 000000001010 C/SBR ! HOLD 0 NOC -- ---- 0 11 1 1 16 R_LH R_HL RAMA OR DZ +015C - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 11 1 1 16 R_DE R_ED RAMA OR DZ +015D - - 000000001101 C/SBR - RDY 0 MEMR -- ADDR 0 11 0 1 16 R_PC R_PC RAMF ADD ZA +015E - - 000000001011 R/F - HOLD 0 NOC -- ---- 0 00 0 0 8 R_A? R_A? RAMF SUBR DA +015F - - 000000000000 R/RTN ! TRUE 0 NOC -- ---- 0 01 0 0 8 RZ38 RAS1 NOP SUBR ZA +----------------------------------------------------------------------------------------- + I D DIRECT-VALUE NXT P COND B SYSCTL OE OS A UK S C W AADR BADR DST FCT SRC +----------------------------------------------------------------------------------------- +0160 (uninitialized) +0161 (uninitialized) +0162 (uninitialized) +0163 (uninitialized) +0164 (uninitialized) +0165 (uninitialized) +0166 (uninitialized) +0167 (uninitialized) +0168 (uninitialized) +0169 (uninitialized) +016A (uninitialized) +016B (uninitialized) +016C (uninitialized) +016D (uninitialized) +016E (uninitialized) +016F (uninitialized) +0170 (uninitialized) +0171 (uninitialized) +0172 (uninitialized) +0173 (uninitialized) +0174 (uninitialized) +0175 (uninitialized) +0176 (uninitialized) +0177 (uninitialized) +0178 (uninitialized) +0179 (uninitialized) +017A (uninitialized) +017B (uninitialized) +017C (uninitialized) +017D (uninitialized) +017E (uninitialized) +017F (uninitialized) +----------------------------------------------------------------------------------------- + I D DIRECT-VALUE NXT P COND B SYSCTL OE OS A UK S C W AADR BADR DST FCT SRC +----------------------------------------------------------------------------------------- +0180 (uninitialized) +0181 (uninitialized) +0182 (uninitialized) +0183 (uninitialized) +0184 (uninitialized) +0185 (uninitialized) +0186 (uninitialized) +0187 (uninitialized) +0188 (uninitialized) +0189 (uninitialized) +018A (uninitialized) +018B (uninitialized) +018C (uninitialized) +018D (uninitialized) +018E (uninitialized) +018F (uninitialized) +0190 (uninitialized) +0191 (uninitialized) +0192 (uninitialized) +0193 (uninitialized) +0194 (uninitialized) +0195 (uninitialized) +0196 (uninitialized) +0197 (uninitialized) +0198 (uninitialized) +0199 (uninitialized) +019A (uninitialized) +019B (uninitialized) +019C (uninitialized) +019D (uninitialized) +019E (uninitialized) +019F (uninitialized) +----------------------------------------------------------------------------------------- + I D DIRECT-VALUE NXT P COND B SYSCTL OE OS A UK S C W AADR BADR DST FCT SRC +----------------------------------------------------------------------------------------- +01A0 (uninitialized) +01A1 (uninitialized) +01A2 (uninitialized) +01A3 (uninitialized) +01A4 (uninitialized) +01A5 (uninitialized) +01A6 (uninitialized) +01A7 (uninitialized) +01A8 (uninitialized) +01A9 (uninitialized) +01AA (uninitialized) +01AB (uninitialized) +01AC (uninitialized) +01AD (uninitialized) +01AE (uninitialized) +01AF (uninitialized) +01B0 (uninitialized) +01B1 (uninitialized) +01B2 (uninitialized) +01B3 (uninitialized) +01B4 (uninitialized) +01B5 (uninitialized) +01B6 (uninitialized) +01B7 (uninitialized) +01B8 (uninitialized) +01B9 (uninitialized) +01BA (uninitialized) +01BB (uninitialized) +01BC (uninitialized) +01BD (uninitialized) +01BE (uninitialized) +01BF (uninitialized) +----------------------------------------------------------------------------------------- + I D DIRECT-VALUE NXT P COND B SYSCTL OE OS A UK S C W AADR BADR DST FCT SRC +----------------------------------------------------------------------------------------- +01C0 (uninitialized) +01C1 (uninitialized) +01C2 (uninitialized) +01C3 (uninitialized) +01C4 (uninitialized) +01C5 (uninitialized) +01C6 (uninitialized) +01C7 (uninitialized) +01C8 (uninitialized) +01C9 (uninitialized) +01CA (uninitialized) +01CB (uninitialized) +01CC (uninitialized) +01CD (uninitialized) +01CE (uninitialized) +01CF (uninitialized) +01D0 (uninitialized) +01D1 (uninitialized) +01D2 (uninitialized) +01D3 (uninitialized) +01D4 (uninitialized) +01D5 (uninitialized) +01D6 (uninitialized) +01D7 (uninitialized) +01D8 (uninitialized) +01D9 (uninitialized) +01DA (uninitialized) +01DB (uninitialized) +01DC (uninitialized) +01DD (uninitialized) +01DE (uninitialized) +01DF (uninitialized) +----------------------------------------------------------------------------------------- + I D DIRECT-VALUE NXT P COND B SYSCTL OE OS A UK S C W AADR BADR DST FCT SRC +----------------------------------------------------------------------------------------- +01E0 (uninitialized) +01E1 (uninitialized) +01E2 (uninitialized) +01E3 (uninitialized) +01E4 (uninitialized) +01E5 (uninitialized) +01E6 (uninitialized) +01E7 (uninitialized) +01E8 (uninitialized) +01E9 (uninitialized) +01EA (uninitialized) +01EB (uninitialized) +01EC (uninitialized) +01ED (uninitialized) +01EE (uninitialized) +01EF (uninitialized) +01F0 (uninitialized) +01F1 (uninitialized) +01F2 (uninitialized) +01F3 (uninitialized) +01F4 (uninitialized) +01F5 (uninitialized) +01F6 (uninitialized) +01F7 (uninitialized) +01F8 (uninitialized) +01F9 (uninitialized) +01FA (uninitialized) +01FB (uninitialized) +01FC (uninitialized) +01FD (uninitialized) +01FE (uninitialized) +01FF - - 000010000100 C/R ! TRUE 0 NOC -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ + -- ---- 0 11 0 1 8 RAS1 RAS1 NOP EXNOR DZ
Am9080/prom/microcode.lst Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/prom/microcode.mif =================================================================== --- Am9080/prom/microcode.mif (nonexistent) +++ Am9080/prom/microcode.mif (revision 5) @@ -0,0 +1,1072 @@ +;EMULATOR ASSEMBLY (MARCH 1977) +;07/06/77 +; +;PC SOURCE AND/OR OBJECT CODE. x = DONT CARE +;0000 ;INITIALIZATION: +; +;0000 RESET: ALU DOUBLE, PC,PC.FTOB.F & AND & ZA :\, ALUC s, BASW & /lOC,, TO. INTE a IF.INY, & NUM DBUS, Hc:3&& NOC +0000 1000000011100000 0011110111110001 1011011111111110 11100100; +; +;0001 ALU,H#D,FTOB.F & DR & D2 & ALUC & BASW & 10C & /NOC & IF,INV & NUM +0001 1100000000000000 0011110111110000 0011010101011010 11011111; +; +;0002 ALU,H#C,FTOB.F & ANII *' 2Ft a, ALUC s, BASW & IOC & /NOC & IF,INV & NUM +0002 1100000000000000 0011110111110000 0011010101011000 11100100; +; +;0003 ALU,,,FTOB.F & AND :\, ZA & st.uc & BASLJ & IOC,,TO.A & /NOC & IF R.PUSH & NUM +0003 1100000000000011 0111110111110001 0011010101010100 11100100; +; +;0004 FETCH: ALU DOUBLE,PC,PC,FTOB.F & OR & ZA & ALUC & BASW & /IOC IN,,TO.A & MEMR & IF .INV,READY & NUM, $ +0004 0100000000010000 0010010111010001 0011011111111110 11011100; +; +;0005 INCPC & IF D.R. ,HOLD & NUM,HLDD & NOC +0005 1100000000110000 1110100111110001 0011011111111110 11000100; +; +;0000 +;0000 ;HOLD AND MEMORY REFERENCE SUBROUTINES AND HANDLERS: +;0000 +; +;0000 ORG 10 +; +;000A HLDSB: NALU & IOC & HLDA & IF R.RTN, INV, HOLD & NUM. $ +000A 1100000000101001 1010100111111000 0011010101010100 01XXXXXX +; +;000B HLDF: NALU & IOC & HLDA & IF R.F, INV,HOLD & NUM, $ +000B 1100000000101111 1010100111111000 0011010101010100 01XXXXXX +; +;000C HLDD: NALU & IOC & HLDA & IF D.R.,,HOLD & NUM, $ +000C 1100000000110000 1110100111111000 0011010101010100 01XXXXXX +; +;000D MMRSB: ALU DOUBLE,PC,PC,FTOB.F & OR & ZA & IOC,,TO.A & /ALUC & MEMR & IF R.RTN, ,READY & NUM, $ & BASW +000D 1100000000110101 1110010111010001 0011011111111110 11011100 +; +;000E MMWSB: ALU DOUBLE,PC,PC,FTOB.F & OR & ZA & ALUC & /IOC, DH, TO.A & NUM, $ & IF R.RT,,READY & BASW & MEMW +000E 1100000000111001 1110010111100101 0011011111111110 11011100 +; +;000F MMWF: ALU DOUBLE.PC.PC.FTOB.F & DR & ZA & ALue & BASW & /MEMW & IF R.F,,READY *' IOC. DH.TO.A & NUM, $ +000F 1100000000111111 1110010111100101 0011011111111110 11011100 +; +;0010 MMRF: ALU DOUELE.PC,PC,FTOB.F & DR & ZA & ALUC & BASW :\, MEMR & /IOC,,TO.A ~ IF R.F ,,READY ~ NUM , $ +0010 1100000001000011 1110010111010001 0011011111111110 11011100 +; +;0011 MMRSP: ALU DOUBLE,SP,SP,FTOB.F ~ OR ~ 2A & IOC,,TO.A & BASW & /ALUC & MEMR & IF R.RTN.,READY & NUM, $ +0011 1100000001000101 1110010111010001 0011011100010000 11011100 +; +;0012 MMWSPH: ALU DOUBLE,SP,SP',FTOB.F s, DR & 2A & ALUC 3. BASbJ & /IOC,DH,TO.A & MEMW 3. IF R.RTN, ,READY 3. NUM, $ +0012 1100000001001001 1110010111100101 0011011100010000 11011100 +; +;0013 MMWSPL: ALU DOUBLE, Sp, Sp, F TOB. F 3. DR & ZA & ALUC & BASW & /IOC,DL,TO.A & MEMW & IF R.RTN,,READY & NUM, $ +0013 1100000001001101 1110010111100011 0011011100010000 11011100 +; +;0000 +;0000 ;MACROCODES: +;0000 +; +;0014 MOVRR: ftLU, ,,FTOB.F & ALUC & BASW SW,SW & OR & 2A & IOC & /IF R.F, INV,HOLD 3. NUM, HLDF & NOC +0014 1100000000101111 1010101111110000 0111010101010100 11011100 +; +;0015 MOVMR: ALU DOUBLE, H 3. ftLUC & DR & 2ft 3. BASW 3. IDC,,TO.A & HLD +0015 1100000000101001 0110100111110001 0011011010010100 01011100 +; +;0016 ALU.& OR & 2A & BASW, SW ~< ftLUC & IOC,,TD.D 3. HLD +0016 1100000000101001 0110100111110000 1111010101010100 01011100 +; +;0017 ALU DOUBLE,PC.PC,FTOB.F & ALUC & OR & ZA & BASW & /MEMW & IF R.F,,READY & NUM, s & . IOC, DH, TO.A +0017 1100000001011111 1110010111100101 0011011111111110 11011100 +; +;0018 MOVRM: ALU DOUBLE, H & ALUC & OR & ZA & BASW & IOC,,TO.A & HLD +0018 1100000000101001 0110100111110001 0011011010010100 01011100 +; +;0019 ALU DOUBLE,PC,PC,FTOB.F & OR & ZA & ALUC & BASW & MMR & /IOC,,TO.A +0019 1100000000110101 0010010111010001 0011011111111110 11011100 +; +;001A ALU,,,FTOB.F & OR & DZ & BASW SW & ALUC & IOC & /NOC & IF R.F, INV, HOLD & NUM, HLDF +001A 1100000000101111 1010101111110000 0011010101010100 11011111 +; +;001B MVIR: INCPC & MMR +001B 1100000000110101 0010010111010001 0011011111111110 11000100 +; +;001C ALIJ, , ,FTOB. F & OR & DZ & ALUC & BASI.o.I SW & IDC / 3. NOC & IF R.F, INV, HOLD & NUM. HLDF +001C 1100000000101111 1010101111110000 0011010101010100 11011111 +; +;001D NALU +001D XXXXXXXXXXXXXXXX XXXXXX0XXXXXXXXX X011010101010100 01XXXXXX +; +;001E MVIM: NALU & MMR & IDe +001E 1100000000110101 0010010111010000 0011010101010100 01XXXXXX +; +;001F ALU,,,FTOB.F &. BASW & OR &. DZ & ALUC & IOC ,,TO.D s, HLD +001F 1100000000101001 0110100111110000 1011010101010100 11011111 +; +;0020 ALU DOUBLE,H & DR & ZA & ALUC & BASW & IOC,,TO.A & HLD +0020 1100000000101001 0110100111110001 0011011010010100 01011100 +; +;0021 ALU DOUBLE,PC,PC,FTOB.F & PLUS & ZA & ALUC & BASW & /MEMW & IF R.F,,READY & NUM, MMWF & IOC,DH,TO.A +0021 1100000000111111 1110010111100101 0011011111111110 11000100 +; +;0022 LXIB: INCPC & MMR +0022 1100000000110101 0010010111010001 0011011111111110 11000100 +; +;0023 ALU,,C,FTOB.F & OR & DZ & ALUC & BASW & HLD & IOC +0023 1100000000101001 0110100111110000 0011010101000010 11011111 +; +;0024 INCPC & MMR +0024 1100000000110101 0010010111010001 0011011111111110 11000100 +; +;0025 ALU,,B,FTOB.F, & OR & D2 & ALUC &. BASW &. NOC & /IF R.F,INY,HOLD & NUM,HLDF & IOC +0025 1100000000101111 1010100111110000 0011010101000000 11011111 +; +;0026 LDA: INCPC & MMR +0026 1100000000110101 0010010111010001 0011011111111110 11000100 +; +;0027 ALU DOUBLE,,jFTOB.F & OR & DZ & ALUC & BASW & HLD & lOC +0027 1100000000101001 0110100111110000 0011011101010100 11011111 +; +;0028 INCPC & MMR +0028 1100000000110101 0010010111010001 0011011111111110 11000100 +; +;0029 ALU,,,FTOB.F &. DR &. DZ &. ALUC 3, BASI.
Am9080/prom/microcode.mif Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/Am25139.vhd =================================================================== --- Am9080/Am25139.vhd (nonexistent) +++ Am9080/Am25139.vhd (revision 5) @@ -0,0 +1,94 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09/20/2017 11:51:21 PM +-- Design Name: +-- Module Name: Am25139 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Am25139 is + Port ( nG1 : in STD_LOGIC; + B1 : in STD_LOGIC; + A1 : in STD_LOGIC; + nY1 : out STD_LOGIC_VECTOR (3 downto 0); + nG2 : in STD_LOGIC; + B2 : in STD_LOGIC; + A2 : in STD_LOGIC; + nY2 : out STD_LOGIC_VECTOR (3 downto 0)); +end Am25139; + +architecture Behavioral of Am25139 is + +signal sel1, sel2: std_logic_vector(1 downto 0); + +begin + +sel1 <= B1 & A1; +sel2 <= B2 & A2; + +decoder1: process(nG1, sel1) +begin + if (nG1 = '0') then + case sel1 is + when "00" => + nY1 <= "1110"; -- 0 + when "01" => + nY1 <= "1101"; -- 1 + when "10" => + nY1 <= "1011"; -- 2 + when "11" => + nY1 <= "0111"; -- 3 + when others => + null; + end case; + else + nY1 <= "1111"; + end if; +end process; + +decoder2: process(nG2, sel2) +begin + if (nG2 = '0') then + case sel2 is + when "00" => + nY2 <= "1110"; -- 0 + when "01" => + nY2 <= "1101"; -- 1 + when "10" => + nY2 <= "1011"; -- 2 + when "11" => + nY2 <= "0111"; -- 3 + when others => + null; + end case; + else + nY2 <= "1111"; + end if; +end process; + +end Behavioral;
Am9080/Am25139.vhd Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/Am25LS153.vhd =================================================================== --- Am9080/Am25LS153.vhd (nonexistent) +++ Am9080/Am25LS153.vhd (revision 5) @@ -0,0 +1,73 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09/24/2017 10:11:13 AM +-- Design Name: +-- Module Name: Am25LS153 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Am25LS153 is + Port ( sel : in STD_LOGIC_VECTOR (1 downto 0); + n1G : in STD_LOGIC; + n2G : in STD_LOGIC; + in1 : in STD_LOGIC_VECTOR (3 downto 0); + in2 : in STD_LOGIC_VECTOR (3 downto 0); + out1 : out STD_LOGIC; + out2 : out STD_LOGIC); +end Am25LS153; + +architecture Behavioral of Am25LS153 is + +signal y1, y2: std_logic; + +begin + +selection: process(sel, in1, in2) +begin + case sel is + when "00" => + y1 <= in1(0); + y2 <= in2(0); + when "01" => + y1 <= in1(1); + y2 <= in2(1); + when "10" => + y1 <= in1(2); + y2 <= in2(2); + when "11" => + y1 <= in1(3); + y2 <= in2(3); + when others => + null; + end case; +end process; + +out1 <= y1 when (n1G = '0') else '0'; +out2 <= y2 when (n2G = '0') else '0'; + +end Behavioral;
Am9080/Am25LS153.vhd Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/Am25LS157.vhd =================================================================== --- Am9080/Am25LS157.vhd (nonexistent) +++ Am9080/Am25LS157.vhd (revision 5) @@ -0,0 +1,51 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09/24/2017 10:11:13 AM +-- Design Name: +-- Module Name: Am25LS157 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Am25LS157 is + Port ( a : in STD_LOGIC_VECTOR (3 downto 0); + b : in STD_LOGIC_VECTOR (3 downto 0); + s : in STD_LOGIC; + nG : in STD_LOGIC; + y : out STD_LOGIC_VECTOR (3 downto 0)); +end Am25LS157; + +architecture Behavioral of Am25LS157 is + +signal y_internal: std_logic_vector(3 downto 0); + +begin + +y_internal <= a when (s = '0') else b; +y <= y_internal when (nG = '0') else "0000"; + +end Behavioral;
Am9080/Am25LS157.vhd Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/Am25LS257.vhd =================================================================== --- Am9080/Am25LS257.vhd (nonexistent) +++ Am9080/Am25LS257.vhd (revision 5) @@ -0,0 +1,52 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09/24/2017 10:11:13 AM +-- Design Name: +-- Module Name: Am25LS257 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Am25LS257 is + Port ( a : in STD_LOGIC_VECTOR (3 downto 0); + b : in STD_LOGIC_VECTOR (3 downto 0); + s : in STD_LOGIC; + nOE : in STD_LOGIC; + y : out STD_LOGIC_VECTOR (3 downto 0)); +end Am25LS257; + +architecture Behavioral of Am25LS257 is + +signal y_internal: std_logic_vector(3 downto 0); + +begin + +y_internal <= a when (s = '0') else b; +y <= y_internal when (nOE = '0') else "ZZZZ"; + +end Behavioral; +
Am9080/Am25LS257.vhd Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/Am82S62.vhd =================================================================== --- Am9080/Am82S62.vhd (nonexistent) +++ Am9080/Am82S62.vhd (revision 5) @@ -0,0 +1,51 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09/24/2017 09:28:27 AM +-- Design Name: +-- Module Name: Am82S62 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Am82S62 is + Port ( p : in STD_LOGIC_VECTOR (8 downto 0); + inhibit : in STD_LOGIC; + even : out STD_LOGIC; + odd : out STD_LOGIC); +end Am82S62; + +architecture Behavioral of Am82S62 is + +signal odd_internal: std_logic; + +begin + +odd_internal <= p(0) xor p(1) xor p(2) xor p(3) xor p(4) xor p(5) xor p(6) xor p(7) xor p(8); +even <= '0' when (inhibit = '1') else not odd_internal; +odd <= '0' when (inhibit = '1') else odd_internal; + +end Behavioral;
Am9080/Am82S62.vhd Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/rom256x12.vhd =================================================================== --- Am9080/rom256x12.vhd (nonexistent) +++ Am9080/rom256x12.vhd (revision 5) @@ -0,0 +1,182 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 16:51:58 02/19/2017 +-- Design Name: +-- Module Name: tinyrom - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- http://www.pastraiser.com/cpu/i8080/i8080_opcodes.html +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use STD.textio.all; +use ieee.std_logic_textio.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +--use work.tinycpu_common.all; + +entity rom256x12 is + Port ( address : in STD_LOGIC_VECTOR (7 downto 0); + data : out STD_LOGIC_VECTOR (11 downto 0)); +end rom256x12; + +architecture Behavioral of rom256x12 is + +constant uPrgAddress_nop: std_logic_vector(11 downto 0) := X"086"; +constant uPrgAddress_hlt: std_logic_vector(11 downto 0) := X"082"; + +alias a8: std_logic_vector(7 downto 0) is address(7 downto 0); + +type rom_array is array(0 to 255) of std_logic_vector(11 downto 0); + +impure function char2hex(char: in character) return integer is +begin + case char is + when '0' to '9' => + return character'pos(char) - character'pos('0'); + when 'a' to 'f' => + return character'pos(char) - character'pos('a') + 10; + when 'A' to 'F' => + return character'pos(char) - character'pos('A') + 10; + when others => + assert false report "char2hex(): unexcpected character '" & char & "'" severity failure; + end case; + return 0; +end char2hex; + +impure function init_wordmemory(mif_file_name : in string; hex_file_name: in string; depth: in integer; default_value: std_logic_vector(11 downto 0)) return rom_array is + variable temp_mem : rom_array;-- := (others => (others => default)); + -- mif file variables + file mif_file : text open read_mode is mif_file_name; + variable mif_line : line; + variable char: character; + variable line_cnt: integer := 1; + variable isOk: boolean; + variable word_address: std_logic_vector(15 downto 0); + variable word_value: std_logic_vector(11 downto 0); + variable word_offset: integer; + variable hex_cnt: integer; + -- hex file variables + file hex_file : text open write_mode is hex_file_name; + variable hex_line : line; + variable checksum: integer; + +begin + -- fill with default value + for i in 0 to depth - 1 loop + temp_mem(i) := default_value; + end loop; + report "init_bytememory(): initialized " & integer'image(depth) & " bytes of memory to " & integer'image(to_integer(unsigned(default_value))) severity note; + -- parse the file for the data + report "init_bytememory(): loading memory from file " & mif_file_name severity note; + while not endfile(mif_file) loop --till the end of file is reached continue. + readline (mif_file, mif_line); + --next when mif_line'length = 0; -- Skip empty lines + report "init_mem(): line " & integer'image(line_cnt) & " read"; + isOk := true; + hex_cnt := 0; + word_offset := 0; + while isOk and (line_cnt < 1024) loop -- TODO: remove this hack + read(mif_line, char, isOk); + if (isOk) then + case char is + when ' ' => + report "init_wordmemory(): space detected"; + if (hex_cnt > 6) then + isOk := false; + end if; + when ';' => + report "init_wordmemory(): comment detected, rest of line is ignored"; + exit; + when '0' to '9'|'a' to 'f'|'A' to 'F' => + --report "init_mem(): hex char detected"; + case hex_cnt is + when 0 => + word_address := x"000" & std_logic_vector(to_unsigned(char2hex(char), 4)); + when 1|2 => + word_address := word_address(11 downto 0) & std_logic_vector(to_unsigned(char2hex(char), 4)); + when 3 => + word_address := word_address(11 downto 0) & std_logic_vector(to_unsigned(char2hex(char), 4)); + report "init_wordmemory(): address parsed"; + --assert unsigned(word_address) < depth; + when 4 => + word_value := x"00" & std_logic_vector(to_unsigned(char2hex(char), 4)); + when 5 => + word_value := word_value(7 downto 0) & std_logic_vector(to_unsigned(char2hex(char), 4)); + when 6 => + word_value := word_value(7 downto 0) & std_logic_vector(to_unsigned(char2hex(char), 4)); + temp_mem(to_integer(unsigned(word_address)) + word_offset) := word_value; + report "init_wordmemory(): word " & integer'image(word_offset) & " set."; + word_offset := word_offset + 1; + when others => + assert false report "init_wordmemory(): too many bytes specified in line" severity note; + exit; + end case; + hex_cnt := hex_cnt + 1; + when others => + assert false report "init_wordmemory(): unexpected char in line " & integer'image(line_cnt) severity note; + exit; + end case; + else + report "init_bytememory(): end of line " & integer'image(line_cnt) & " reached"; + end if; + end loop; + + line_cnt := line_cnt + 1; + end loop; -- next line in file + + file_close(mif_file); + + -- dump memory content to Intel hex-format like file + for i in 0 to (depth - 1) / 16 loop + write(hex_line, string'(": 10 ")); -- 16 bytes per line + hwrite(hex_line, std_logic_vector(to_unsigned(i * 16, 16)), RIGHT, 4); + write(hex_line, string'(" 00 ")); -- regular data line marker + checksum := 0; + for j in 0 to 15 loop + hwrite(hex_line, temp_mem(i * 16 + j), RIGHT, 3); + checksum := checksum + to_integer(unsigned(temp_mem(i * 16 + j))); + write(hex_line, string'(" ")); + end loop; + hwrite(hex_line, std_logic_vector(to_unsigned(0 - checksum, 8)), RIGHT, 2); + writeline(hex_file, hex_line); + end loop; + write(hex_line, string'(": 00 0000 01 FF")); -- last line marker + writeline(hex_file, hex_line); -- write last line + file_close(hex_file); + + return temp_mem; + +end init_wordmemory; + +constant data_from_file: rom_array := init_wordmemory("./prom/mapper.mif", "./prom/mapper.hex", 256, uPrgAddress_nop); + +constant data_from_inline: rom_array := +( + 0 => uPrgAddress_hlt, + others => uPrgAddress_nop +); + +begin + data <= data_from_file(to_integer(unsigned(a8))); + +end Behavioral; +
Am9080/rom256x12.vhd Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/rom32x8.vhd =================================================================== --- Am9080/rom32x8.vhd (nonexistent) +++ Am9080/rom32x8.vhd (revision 5) @@ -0,0 +1,88 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09/24/2017 01:49:44 PM +-- Design Name: +-- Module Name: rom32x8 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity rom32x8 is + Port ( nCS : in STD_LOGIC; + address : in STD_LOGIC_VECTOR (3 downto 0); + data : out STD_LOGIC_VECTOR (4 downto 0)); +end rom32x8; + +architecture Behavioral of rom32x8 is + +signal data_int: std_logic_vector(4 downto 0); + +begin + +sequence: process(address) +begin + case address is + when "0000" => + data_int <= "01000"; -- C + when "0001" => + data_int <= "01001"; -- R + when "0010" => + data_int <= "01011"; -- D + when "0011" => + data_int <= "01001"; -- R + when "0100" => + data_int <= "01000"; -- C + when "0101" => + data_int <= "00101"; -- SBR + when "0110" => + data_int <= "01001"; -- R + when "0111" => + data_int <= "00010"; -- RTN + when "1000" => + data_int <= "11010"; -- F + when "1001" => + data_int <= "00101"; -- SBR + when "1010" => + data_int <= "00000"; -- POP + when "1011" => + data_int <= "00001"; -- PR + when "1100" => + data_int <= "01001"; -- R + when "1101" => + data_int <= "00100"; -- PUSH + when "1110" => + data_int <= "01001"; -- R + when "1111" => + data_int <= "11010"; -- F + when others => + data_int <= "11111"; + end case; +end process; + +data <= data_int when (nCS = '0') else "ZZZZZ"; + +end Behavioral;
Am9080/rom32x8.vhd Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property Index: Am9080/rom512x56.vhd =================================================================== --- Am9080/rom512x56.vhd (nonexistent) +++ Am9080/rom512x56.vhd (revision 5) @@ -0,0 +1,366 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 16:51:58 02/19/2017 +-- Design Name: +-- Module Name: tinyrom - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use STD.textio.all; +use ieee.std_logic_textio.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +--use work.tinycpu_common.all; + +entity rom512x56 is + Port ( address : in STD_LOGIC_VECTOR (8 downto 0); + data : out STD_LOGIC_VECTOR (55 downto 0)); +end rom512x56; + +architecture Behavioral of rom512x56 is + +--type t_uinstruction is array (55 downto 0) of std_logic; +type t_word is array(15 downto 0) of std_logic; +type t_byte is array(7 downto 0) of std_logic; +type t_uinstruction512 is array(0 to 511) of std_logic_vector(55 downto 0); +constant uCode_nop: std_logic_vector(55 downto 0) := "11000000001011111010100111110000001101010101010001000000"; +constant uCode_default: std_logic_vector(55 downto 0) := "11111111111111111111111111111111111111111111111111111111"; + +type t_string16x4 is array(0 to 15) of string(1 to 4); +type t_string8x3 is array(0 to 7) of string(1 to 3); +type t_string8x5 is array(0 to 7) of string(1 to 5); +type t_string8x6 is array(0 to 7) of string(1 to 6); +type t_string4x4 is array(0 to 3) of string(1 to 4); +type t_string4x2 is array(0 to 3) of string(1 to 2); +type t_string2x2 is array(0 to 1) of string(1 to 2); +type t_string2x1 is array(0 to 1) of string(1 to 1); +constant cond_decode: t_string16x4 := ("Z ", "CY ", "P ", "S ", "AC ", "?(5)", "?(6)", "?(7)", "INT ", "RDY ", "HOLD", "?(B)", "F3 ", "F=0 ", "CN4 ", "TRUE"); +constant reg_decode: t_string16x4 := ("R_BC", "R_CB", "R_DE", "R_ED", "R_HL", "R_LH", "R_?A", "R_A?", "R_SP", "R_9?", "RAS1", "RBS2", "RZ38", "R38Z", "RES3", "R_PC"); +constant src_decode: t_string8x3 := ("AQ ", "AB ", "ZQ ", "ZB ", "ZA ", "DA ", "DQ ", "DZ "); +constant fct_decode: t_string8x5 := ("ADD ", "SUBR ", "SUBS ", "OR ", "AND ", "NOTRS", "EXOR ", "EXNOR"); +constant dst_decode: t_string8x5 := ("QREG ", "NOP ", "RAMA ", "RAMF ", "RAMQD", "RAMD ", "RAMQU", "RAMU "); +constant next_decode: t_string8x6 := ("C/R ", "D/R ", "C/SBR ", "R/RTN ", "F/SBR ", "POP/PR", "R/PUSH", "R/F "); +constant databusenable_decode: t_string4x2 := ("--", "YL", "YH", "FL"); +constant outputsteer_decode: t_string4x4 := ("----", "DATA", "ADDR", "INTE"); +constant immediatedatabus_decode: t_string2x1 := ("m", "-"); +constant size_decode: t_string2x2 := ("8 ", "16"); +constant instregenable_decode: t_string2x1 := ("i", "-"); +constant condpolarity_decode: t_string2x1 := ("-", "!"); + +alias a8: std_logic_vector(8 downto 0) is address(8 downto 0); + + +impure function char2hex(char: in character) return integer is +begin + case char is + when '0' to '9' => + return character'pos(char) - character'pos('0'); + when 'a' to 'f' => + return character'pos(char) - character'pos('a') + 10; + when 'A' to 'F' => + return character'pos(char) - character'pos('A') + 10; + when others => + assert false report "char2hex(): unexpected character '" & char & "'" severity failure; + end case; + return 0; +end char2hex; + +impure function decode_buscontrol(buscontrol: in std_logic_vector(5 downto 0)) return string is +begin + case buscontrol is + when "111110" => return "NOC "; + when "111100" => return "MEMW "; + when "111010" => return "MEMR "; + when "110110" => return "IOW "; + when "101110" => return "IOR "; + when "011110" => return "INTA "; + when "111111" => return "HLDA "; + when others => + return "??????"; + end case; +end decode_buscontrol; + +impure function decode_reg(reg: in std_logic_vector(3 downto 0)) return string is +begin + return reg_decode(to_integer(unsigned(reg))); +end decode_reg; + +impure function decode_cond(cond: in std_logic_vector(3 downto 0)) return string is +begin + return cond_decode(to_integer(unsigned(cond))); +end decode_cond; + +impure function decode_src(src: in std_logic_vector(2 downto 0)) return string is +begin + return src_decode(to_integer(unsigned(src))); +end decode_src; + +impure function decode_fct(fct: in std_logic_vector(2 downto 0)) return string is +begin + return fct_decode(to_integer(unsigned(fct))); +end decode_fct; + +impure function decode_dst(dst: in std_logic_vector(2 downto 0)) return string is +begin + return dst_decode(to_integer(unsigned(dst))); +end decode_dst; + +impure function decode_next(nxt: in std_logic_vector(2 downto 0)) return string is +begin + return next_decode(to_integer(unsigned(nxt))); +end decode_next; + +impure function decode_databusenable(busenable: in std_logic_vector(1 downto 0)) return string is +begin + return databusenable_decode(to_integer(unsigned(busenable))); +end decode_databusenable; + +impure function decode_outputsteer(outputsteer: in std_logic_vector(1 downto 0)) return string is +begin + return outputsteer_decode(to_integer(unsigned(outputsteer))); +end decode_outputsteer; + +impure function decode_immediatedatabus(immediatedatabus: in std_logic) return string is +begin + return immediatedatabus_decode(to_integer(unsigned'("" & immediatedatabus))); +end decode_immediatedatabus; + +impure function decode_size(size: in std_logic) return string is +begin + return size_decode(to_integer(unsigned'("" & size))); +end decode_size; + +impure function decode_instregenable(instregenable: in std_logic) return string is +begin + return instregenable_decode(to_integer(unsigned'("" & instregenable))); +end decode_instregenable; + +impure function decode_condpolarity(condpolarity: in std_logic) return string is +begin + return condpolarity_decode(to_integer(unsigned'("" & condpolarity))); +end decode_condpolarity; + +procedure dump_wordmemory(out_file_name: in string; depth: in integer; temp_mem: in t_uinstruction512; base: in integer) is + file out_file : text open write_mode is out_file_name; + variable out_line : line; + +begin + -- dump memory content in
format for verification + for i in 0 to (depth - 1) loop + + if ((i mod 32 = 0) and not ((base = 8) or (base = 16))) then + write(out_line, string'("-----------------------------------------------------------------------------------------"));writeline(out_file, out_line); + write(out_line, string'(" I D DIRECT-VALUE NXT P COND B SYSCTL OE OS A UK S C W AADR BADR DST FCT SRC"));writeline(out_file, out_line); + write(out_line, string'("-----------------------------------------------------------------------------------------"));writeline(out_file, out_line); + end if; + + hwrite(out_line, std_logic_vector(to_unsigned(i, 16))); + write(out_line, string'(" ")); + if (temp_mem(i) = ucode_default) then + write(out_line, string'("(uninitialized)")); + else + case base is + when 2 => + write(out_line, temp_mem(i)(55));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(54));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(53 downto 42));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(41 downto 39));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(38));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(37 downto 34));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(33));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(32 downto 27));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(26 downto 25));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(24 downto 23));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(22));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(21 downto 20));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(19));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(18));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(17));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(16 downto 13));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(12 downto 9));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(8 downto 6));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(5 downto 3));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(2 downto 0)); + when 8 => + owrite(out_line, temp_mem(i)); + when 16 => + hwrite(out_line, temp_mem(i)); + when others => -- any other value will dump microcode "mnemonics" + write(out_line, decode_instregenable(temp_mem(i)(55)));write(out_line, string'(" ")); + write(out_line, decode_immediatedatabus(temp_mem(i)(54)));write(out_line, string'(" ")); + if (unsigned(temp_mem(i)(53 downto 42)) = i) then + write(out_line, string'("= location = ")); + else + write(out_line, temp_mem(i)(53 downto 42));write(out_line, string'(" ")); + end if; + write(out_line, decode_next(temp_mem(i)(41 downto 39)));write(out_line, string'(" ")); + write(out_line, decode_condpolarity(temp_mem(i)(38)));write(out_line, string'(" ")); + write(out_line, decode_cond(temp_mem(i)(37 downto 34)));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(33));write(out_line, string'(" ")); + write(out_line, decode_buscontrol(temp_mem(i)(32 downto 27)));write(out_line, string'(" ")); + write(out_line, decode_databusenable(temp_mem(i)(26 downto 25)));write(out_line, string'(" ")); + write(out_line, decode_outputsteer(temp_mem(i)(24 downto 23)));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(22));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(21 downto 20));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(19));write(out_line, string'(" ")); + write(out_line, temp_mem(i)(18));write(out_line, string'(" ")); + write(out_line, decode_size(temp_mem(i)(17)));write(out_line, string'(" ")); + write(out_line, decode_reg(temp_mem(i)(16 downto 13)));write(out_line, string'(" ")); + write(out_line, decode_reg(temp_mem(i)(12 downto 9)));write(out_line, string'(" ")); + write(out_line, decode_dst(temp_mem(i)(8 downto 6)));write(out_line, string'(" ")); + write(out_line, decode_fct(temp_mem(i)(5 downto 3)));write(out_line, string'(" ")); + write(out_line, decode_src(temp_mem(i)(2 downto 0))); + end case; + end if; + writeline(out_file, out_line); + end loop; + file_close(out_file); +end dump_wordmemory; + +impure function parseHex16(hex_str: in string) return std_logic_vector is + variable intVal: integer := 0; +begin + --report "parseHex16(" & hex_str & ")" severity note; + + for i in hex_str'left to hex_str'right loop + intVal := 16 * intVal + char2hex(hex_str(i)); + end loop; + return std_logic_vector(to_unsigned(intVal, 16)); +end parseHex16; + +impure function parseBinary8(bin_str: in string) return std_logic_vector is + variable val: std_logic_vector(7 downto 0) := "00000000"; +begin + --report "parseBinary8(" & bin_str & ")" severity note; + for i in bin_str'left to bin_str'right loop + case bin_str(i) is + when '0' => + val := val(6 downto 0) & "0"; + when '1'|'X' => -- interpret X as '1' due to bus signal being low active - this way is undefined microinstruction is executed, bus won't short! + val := val(6 downto 0) & "1"; + when others => + assert false report "parseBinary8(): unexpected character '" & bin_str(i) & "'" severity failure; + end case; + end loop; + + return val; +end parseBinary8; + +impure function parseBinary16(bin_str: in string) return std_logic_vector is +begin + --report "parseBinary16(" & bin_str & ")" severity note; + return parseBinary8(bin_str(1 to 8)) & parseBinary8(bin_str(9 to 16)); +end parseBinary16; + + +impure function init_wordmemory(input_file_name : in string; dump_file_name: in string; dump_file_base: in integer; depth: in integer; default_value: std_logic_vector(55 downto 0)) return t_uinstruction512 is + variable temp_mem : t_uinstruction512;-- := (others => (others => default_value)); + -- mif file variables + file input_file : text open read_mode is input_file_name; + variable input_line : line; + variable line_current: integer := 0; + variable line_cnt_accepted, line_cnt_ignored: integer := 0; + variable address: std_logic_vector(15 downto 0); + variable word: std_logic_vector(55 downto 0); + variable addr_str: string(1 to 3); + variable data16_str1, data16_str2, data16_str3: string(1 to 16); + variable data8_str: string(1 to 8); + variable addr_ok, data16_ok1, data16_ok2, data16_ok3, data8_ok : boolean; + variable firstChar: character; + +begin + -- fill with default value + for i in 0 to depth - 1 loop + temp_mem(i) := default_value; + --temp_mem(i) := std_logic_vector(to_unsigned(i, 9)) & "00000000000000000000000000000000000000000000000"; + end loop; + assert false report "init_bytememory(): initialized " & integer'image(depth) & " words of memory to default value " severity note; + + -- parse the file for the data + assert false report "init_bytememory(): loading memory from file " & input_file_name severity note; + loop + exit when endfile(input_file); --till the end of file is reached continue. + line_current := line_current + 1; + readline (input_file, input_line); + --next when input_line'length = 0; -- Skip empty lines + report "init_mem(): parsing line " & integer'image(line_current) severity note; + --report "[" & integer'image(input_line'left) & "]" severity note; + address := X"0000"; + word := X"00000000000000"; + + read(input_line, firstChar); + --exit when endline(input_line); + addr_ok := true; + report "addr_str='" & firstChar & "'" severity note; + case firstChar is + when ';' => + --report "Semicolon detected, line is treated as comment" severity note; + line_cnt_ignored := line_cnt_ignored + 1; + when '0' to '9' | 'A' to 'F' => + read(input_line, addr_str, addr_ok); + read(input_line, data16_str1, data16_ok1); + read(input_line, data16_str2, data16_ok2); + read(input_line, data16_str3, data16_ok3); + read(input_line, data8_str, data8_ok); + --if (addr_ok and data16_ok1 and data16_ok2 and data16_ok3 and data8_ok) then + address := parseHex16(firstChar & addr_str); + word := parseBinary16(data16_str1) & parseBinary16(data16_str2) & parseBinary16(data16_str3) & parseBinary8(data8_str); + + temp_mem(to_integer(unsigned(address))) := word; + line_cnt_accepted := line_cnt_accepted + 1; + report "init_bytememory(): line " & integer'image(line_current) & " parsed and accepted for address " & integer'image(to_integer(unsigned(address))) severity note; + --else + -- report "init_bytememory(): line " & integer'image(line_current) & " is ignored due to missing data" severity note; + -- line_cnt_ignored := line_cnt_ignored + 1; + --end if; + when others => + report "init_bytememory(): line " & integer'image(line_current) & " is ignored due to unrecognized 1st char" severity note; + line_cnt_ignored := line_cnt_ignored + 1; + end case; + end loop; -- next line in file + + file_close(input_file); + + report "init_bytememory(): " & integer'image(line_cnt_accepted) & " total lines parsed and accepted from file " & input_file_name severity note; + report "init_bytememory(): " & integer'image(line_cnt_ignored) & " total lines parsed and ignored from file " & input_file_name severity note; + + dump_wordmemory(dump_file_name, depth, temp_mem, dump_file_base); + + return temp_mem; +end init_wordmemory; + +constant data_from_file: t_uinstruction512 := init_wordmemory("./prom/microcode.mif", "./prom/microcode.lst", 0, 512, uCode_default); +--constant data_from_file: rom_array := init_wordmemory("./prom/microcode.mif", "./prom/microcode.hex", 2, 512, uCode_default); + +constant data_from_inline: t_uinstruction512 := +( + 0 => uCode_nop, + others => uCode_nop +); + +begin + data <= data_from_file(to_integer(unsigned(a8))); + +end Behavioral; +
Am9080/rom512x56.vhd Property changes : Added: svn:eol-style ## -0,0 +1 ## +CRLF \ No newline at end of property

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