URL
https://opencores.org/ocsvn/amber/amber/trunk
Subversion Repositories amber
Compare Revisions
- This comparison shows the changes necessary to convert path
/amber/trunk/hw/fpga/bin
- from Rev 77 to Rev 78
- ↔ Reverse comparison
Rev 77 → Rev 78
/Makefile
38,9 → 38,9
# // |
# ---------------------------------------------------------------- |
|
# ---------------------------------------------------- |
# ---------------------------------------------------- |
# Environment Configuration |
# ---------------------------------------------------- |
# ---------------------------------------------------- |
|
# Directories |
BIN_FOLDER = ../bin |
61,7 → 61,7
BOOT_LOADER_DEF = BOOT_LOADER_ETHMAC |
else |
BOOT_LOADER_DIR = ../../../sw/boot-loader-serial |
BOOT_LOADER_DEF = |
BOOT_LOADER_DEF = |
endif |
|
VERILOG_INCLUDE_PATH = ../../vlog/lib ../../vlog/tb $(BOOT_LOADER_DIR) |
71,9 → 71,9
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# ---------------------------------------------------- |
# ---------------------------------------------------- |
# Build Configuration |
# ---------------------------------------------------- |
# ---------------------------------------------------- |
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# AMBER_CLK_DIVIDER |
# Sets the system clock frequency |
86,7 → 86,7
ifdef A25 |
AMBER_CORE = AMBER_A25_CORE |
else |
AMBER_CORE = AMBER_A23_CORE |
AMBER_CORE = AMBER_A23_CORE |
endif |
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|
93,7 → 93,7
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# The spartan6 device used on SP605 Development board |
XILINX_FPGA = xc6slx45tfgg484-3 |
XST_DEFINES = XILINX_FPGA XILINX_SPARTAN6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=20 $(BOOT_LOADER_DEF) |
XST_DEFINES = XILINX_FPGA XILINX_SPARTAN6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=21 $(BOOT_LOADER_DEF) |
# Xilinx placement and timing constraints |
XST_CONST_FILE = xs6_constraints.ucf |
# List of verilog source files for Xilinx Spartan-6 device |
101,14 → 101,14
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# ---------------------------------------------------- |
# Focus on speed or area |
# ---------------------------------------------------- |
# ---------------------------------------------------- |
# Focus on speed or area |
# ---------------------------------------------------- |
#OPT = area |
OPT = speed |
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# ---------------------------------------------------- |
# ---------------------------------------------------- |
# Xilinx XST Compile Options |
# ---------------------------------------------------- |
|
203,10 → 203,10
cd $(WORK_FOLDER); \ |
trce -v 5 -l 5 -n 5 -xml $(RTL_TOP) $(RTL_TOP).ncd \ |
-o $(WORK_FOLDER)/$(RTL_TOP).trc.twr \ |
$(RTL_TOP).pcf |
$(RTL_TOP).pcf |
cp $(WORK_FOLDER)/$(RTL_TOP).trc.twr $(LOG_FOLDER)/$(RTL_TOP).trc.$(RUN_ID).twr |
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# ---------------------------------------------------- |
# bitgen |
# ---------------------------------------------------- |
252,8 → 252,8
$(RTL_TOP).ngd \ |
$(RTL_TOP).pcf |
cp $(WORK_FOLDER)/$(RTL_TOP).map.mrp $(LOG_FOLDER)/$(RTL_TOP).map.$(RUN_ID).mrp |
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# ---------------------------------------------------- |
# ngdbuild |
# ---------------------------------------------------- |
261,7 → 261,7
cd $(WORK_FOLDER); \ |
ngdbuild -intstyle xflow -verbose -p $(XILINX_FPGA) \ |
-dd _ngo -nt on \ |
-uc $(BIN_FOLDER)/$(XST_CONST_FILE) $(RTL_TOP).ngc $(RTL_TOP).ngd |
-uc $(BIN_FOLDER)/$(XST_CONST_FILE) $(RTL_TOP).ngc $(RTL_TOP).ngd |
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# ---------------------------------------------------- |