URL
https://opencores.org/ocsvn/amber/amber/trunk
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- This comparison shows the changes necessary to convert path
/amber/trunk/hw/tests
- from Rev 70 to Rev 82
- ↔ Reverse comparison
Rev 70 → Rev 82
/teq.S
0,0 → 1,84
/***************************************************************** |
// // |
// Amber 2 Core Instruction Test // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Tests add with carry // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
*****************************************************************/ |
|
// Test "Strange issue with r12 after TEQLSP" |
// Tests for bug where testlsp command would switch the core |
// from supervisor into FIRQ mode if it were executed. However the condition is not |
// met so it is not executed. Thje bug is the next instrument works in FIRQ mode anyway. |
// This was caused because the mode bits used in the ececute stage were not conditional on the |
// teq instrumention being executed. |
|
#include "amber_registers.h" |
#include "amber_macros.h" |
|
.section .text |
.globl main |
main: |
|
// Test "Strange issue with r12 after TEQLSP" |
mov r1, #0x0 |
mov r2, #0x1 |
mov r6, #10 |
mov r12, #100 |
nop |
|
// this next instrument does not get executed because 'ls' condition is false |
teqlsp r1, r2 // r1 XOR r2 = 0x1 -> sets the mode bits of the PC to 1 |
mov r12, r6 // user r12 or FIRQ r12 ? |
|
cmp r12, r6 // error if user mode r12 was not updated with new value |
bne testfail |
|
b testpass |
|
testfail: |
ldr r11, AdrTestStatus |
str r10, [r11] |
b testfail |
|
testpass: |
ldr r11, AdrTestStatus |
mov r10, #17 |
str r10, [r11] |
b testpass |
|
|
AdrTestStatus: .word ADR_AMBER_TEST_STATUS |
|
/and.S
0,0 → 1,89
/***************************************************************** |
// // |
// Amber 2 Core Instruction Test // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Tests add with carry // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
*****************************************************************/ |
|
#include "amber_registers.h" |
#include "amber_macros.h" |
|
.section .text |
.globl main |
main: |
// sets all four flags |
// Cant use p version of instrustion in 32-bit CPU because it writes the upper 4 bits of PC |
teqp pc, #0xf0000000 |
|
// |
// Check that they are set |
bvc testfail // V flag |
bpl testfail // N flag |
bne testfail // Z flag |
bcc testfail // C flag |
|
mov r1, #0x0000005a |
|
// should not unset the V flag value |
ands r2, r1, #0x00000055 |
|
// Check the V flag is still set, the Z flag is clear the C flag |
// gets the carry out value from the barrel shifter, which is |
// the C flag in this case, and the N flag gets cleared |
bvc testfail |
beq testfail |
bcc testfail |
bmi testfail |
|
tst r2, #0x00000050 |
beq testfail |
|
b testpass |
|
testfail: |
ldr r11, AdrTestStatus |
str r10, [r11] |
b testfail |
|
testpass: |
ldr r11, AdrTestStatus |
mov r10, #17 |
str r10, [r11] |
b testpass |
|
|
AdrTestStatus: .word ADR_AMBER_TEST_STATUS |
|
/ldrt.S
0,0 → 1,86
/***************************************************************** |
// // |
// Amber 2 Core Instruction Test // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Tests lrd and ldrb // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
*****************************************************************/ |
|
#include "amber_registers.h" |
|
.section .text |
.globl main |
main: |
|
/* Load Byte 0 */ |
ldr r0, AdrData1 |
ldrb r1, [r0] |
ldr r2, Data2 |
cmp r1, r2 |
movne r10, #10 |
bne testfail |
|
b testpass |
|
testfail: |
ldr r11, AdrTestStatus |
str r10, [r11] |
b testfail |
|
testpass: |
ldr r11, AdrTestStatus |
mov r10, #17 |
str r10, [r11] |
b testpass |
|
|
/* Write 17 to this address to generate a Test Passed message */ |
AdrTestStatus: .word ADR_AMBER_TEST_STATUS |
AdrData1: .word Data1 |
AdrData8: .word Data8 |
Data1: .word 0x12345678 |
Data2: .word 0x00000078 |
Data3: .word 0x00000056 |
Data4: .word 0x00000034 |
Data5: .word 0x00000012 |
Data6: .word 0xfecba987 |
Data7: .word 0x78123456 |
Data8: .word 0x34567812 |
Data9: .word 0x33221100 |
|
/* ========================================================================= */ |
/* ========================================================================= */ |
|
|
/tst.S
0,0 → 1,103
/***************************************************************** |
// // |
// Amber 2 Core Instruction Test // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Tests add with carry // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
*****************************************************************/ |
|
#include "amber_registers.h" |
#include "amber_macros.h" |
|
.section .text |
.globl main |
main: |
// sets all four flags |
// Cant use p version of instrustion in 32-bit CPU because it writes the upper 4 bits of PC |
teqp pc, #0xf0000000 |
|
// |
// Check that they are set |
bvc testfail // V flag |
bpl testfail // N flag |
bne testfail // Z flag |
bcc testfail // C flag |
|
mov r1, #0 |
|
// should not unset the V flag value |
tst r1, #0 |
|
// Check the V flag and Z flag are still set, the C flag |
// gets the carry out value from the barrel shifter, which is |
// the C flag in this case, and the N flag gets cleared |
bvc testfail |
bne testfail |
bcc testfail |
bmi testfail |
|
// Test "Strange issue with r12 after TEQLSP" |
mov r1, #0x1 |
mov r2, #0x1 |
mov r8, #0 |
mov r6, #10 |
mov r10, #13 |
mov r12, #100 |
nop |
|
add r6, r6,#1 |
cmp r6, r8 |
ldrls r3, [r9,r6,lsl #2] |
movls r4, r11 |
movhi r3, #0 |
teqp r1, r2 // r1 XOR r2 = 0x1 -> sets the mode bits of the PC to 1 |
mov r12, r6 // normal r12 or FIRQ r12 ? |
|
b testpass |
|
testfail: |
ldr r11, AdrTestStatus |
str r10, [r11] |
b testfail |
|
testpass: |
ldr r11, AdrTestStatus |
mov r10, #17 |
str r10, [r11] |
b testpass |
|
|
AdrTestStatus: .word ADR_AMBER_TEST_STATUS |
|
/ethmac_reg.S
72,7 → 72,9
@ Set MII address - device [4:0], register [12:8] |
ldr r4, AdrEthMacMIIAddress |
mov r5, #0x07 |
orr r5, r5, #0x1600 |
|
@ MII_BMSR register in eth_test.v has reg address of 1 |
orr r5, r5, #0x0100 |
str r5, [r4] |
|
@ receive (read PHY register) Command |
130,7 → 132,7
AdrEthMacMIIStatus: .word ADR_ETHMAC_MIISTATUS |
|
EthMacModerDefault: .word 0x0000a000 |
ExpectedMIIReadBack: .word 0x0000ffff |
ExpectedMIIReadBack: .word 0x0000fe04 @ value from eth_test.v, state MD_TURN1 |
|
|
/* ========================================================================= */ |
/ldm5.S
0,0 → 1,93
/***************************************************************** |
// // |
// Amber 2 Core Instruction Test // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
|
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
*****************************************************************/ |
|
#include "amber_registers.h" |
|
.section .text |
.globl main |
main: |
mov r14, #100 |
ldr r13, Data1Base |
ldmia r13!,{r1-r14}^ // load into user mode registers |
|
// supervisor r14 value should be unchanged |
nop |
nop |
mov r0, r14 |
cmp r0, #100 |
beq testpass |
|
testfail: |
ldr r11, AdrTestStatus |
str r10, [r11] |
b testfail |
|
testpass: |
ldr r11, AdrTestStatus |
mov r10, #17 |
str r10, [r11] |
b testpass |
|
|
/* Write 17 to this address to generate a Test Passed message */ |
AdrTestStatus: .word ADR_AMBER_TEST_STATUS |
Data1Base: .word Data1 |
Data1: .word 0x00 |
.word 0x01 |
.word 0x02 |
.word 0x03 |
.word 0x04 |
.word 0x05 |
.word 0x06 |
.word 0x07 |
.word 0x08 |
.word 0x09 |
.word 0x0a |
.word 0x0b |
.word 0x0c |
.word 0x0d |
.word 0x0e |
.word 0x0f |
.word 0x10 |
|
/* ========================================================================= */ |
/* ========================================================================= */ |
|
|