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  • This comparison shows the changes necessary to convert path 
    /amber/trunk/hw/vlog/amber23
    from Rev 15 to Rev 42
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  •

Rev 15 → Rev 42

/a23_wishbone.v
104,13 → 104,22
reg exclusive_access = 'd0;
wire read_ack;
wire wait_write_ack;
wire wb_wait;
 
// Write buffer
reg [31:0] wbuf_data_r = 'd0;
reg [31:0] wbuf_addr_r = 'd0;
reg [3:0] wbuf_sel_r = 'd0;
reg wbuf_busy_r = 'd0;
 
 
assign read_ack = !o_wb_we && i_wb_ack;
assign o_stall = ( core_read_request && !read_ack ) ||
( core_read_request && servicing_cache ) ||
( core_write_request && servicing_cache ) ;
( core_write_request && servicing_cache ) ||
( core_write_request && wishbone_st == WB_WAIT_ACK) ||
( cache_write_request && wishbone_st == WB_WAIT_ACK) ||
wbuf_busy_r;
 
// Don't stall on writes
// Wishbone is doing burst read so make core wait to execute the write
122,13 → 131,33
assign cache_read_request = i_cache_req && !i_write_enable;
assign cache_write_request = i_cache_req && i_write_enable;
 
assign start_access = core_read_request || core_write_request || i_cache_req ;
assign wb_wait = o_wb_stb && !i_wb_ack;
assign start_access = (core_read_request || core_write_request || i_cache_req) && !wb_wait ;
 
// For writes the byte enable is always 4'hf
assign byte_enable = ( core_write_request || cache_write_request ) ? i_byte_enable : 4'hf;
assign byte_enable = wbuf_busy_r ? wbuf_sel_r :
( core_write_request || cache_write_request ) ? i_byte_enable :
4'hf ;
 
 
// ======================================
// Write buffer
// ======================================
 
 
always @( posedge i_clk )
if ( wb_wait && !wbuf_busy_r && (core_write_request || cache_write_request) )
begin
wbuf_data_r <= i_write_data;
wbuf_addr_r <= i_address;
wbuf_sel_r <= i_byte_enable;
wbuf_busy_r <= 1'd1;
end
else if (!o_wb_stb)
wbuf_busy_r <= 1'd0;
// ======================================
// Register Accesses
// ======================================
always @( posedge i_clk )
170,12 → 199,12
// do a burst of 4 read to fill a cache line
else if ( cache_read_request )
begin
wishbone_st <= WB_BURST1;
wishbone_st <= WB_BURST1;
exclusive_access <= 1'd0;
end
else if ( core_read_request )
begin
wishbone_st <= WB_WAIT_ACK;
wishbone_st <= WB_WAIT_ACK;
exclusive_access <= i_exclusive;
end
// The core does not currently issue exclusive write requests
187,9 → 216,18
if ( start_access )
begin
o_wb_we <= core_write_request || cache_write_request;
// only update these on new wb access to make debug easier
o_wb_adr[31:2] <= i_address[31:2];
if (wbuf_busy_r)
begin
o_wb_we <= 1'd1;
o_wb_adr[31:2] <= wbuf_addr_r[31:2];
end
else
begin
o_wb_we <= core_write_request || cache_write_request;
// only update these on new wb access to make debug easier
o_wb_adr[31:2] <= i_address[31:2];
end
o_wb_adr[1:0] <= byte_enable == 4'b0001 ? 2'd0 :
byte_enable == 4'b0010 ? 2'd1 :
byte_enable == 4'b0100 ? 2'd2 :

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