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    /amber/trunk/hw/vlog/amber23
    from Rev 74 to Rev 82
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Rev 74 → Rev 82

/a23_config_defines.v File deleted
/a23_localparams.v File deleted
/a23_functions.v File deleted
/a23_localparams.vh
0,0 → 1,117
//////////////////////////////////////////////////////////////////
// //
// Parameters file for Amber 2 Core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Holds general parameters that are used is several core //
// modules //
// //
// Author(s): //
// - Conor Santifort, csantifort.amber@gmail.com //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
 
 
// Instruction Types
localparam [3:0] REGOP = 4'h0, // Data processing
MULT = 4'h1, // Multiply
SWAP = 4'h2, // Single Data Swap
TRANS = 4'h3, // Single data transfer
MTRANS = 4'h4, // Multi-word data transfer
BRANCH = 4'h5, // Branch
CODTRANS = 4'h6, // Co-processor data transfer
COREGOP = 4'h7, // Co-processor data operation
CORTRANS = 4'h8, // Co-processor register transfer
SWI = 4'h9; // software interrupt
 
 
// Opcodes
localparam [3:0] AND = 4'h0, // Logical AND
EOR = 4'h1, // Logical Exclusive OR
SUB = 4'h2, // Subtract
RSB = 4'h3, // Reverse Subtract
ADD = 4'h4, // Add
ADC = 4'h5, // Add with Carry
SBC = 4'h6, // Subtract with Carry
RSC = 4'h7, // Reverse Subtract with Carry
TST = 4'h8, // Test (using AND operator)
TEQ = 4'h9, // Test Equivalence (using EOR operator)
CMP = 4'ha, // Compare (using Subtract operator)
CMN = 4'hb, // Compare Negated
ORR = 4'hc, // Logical OR
MOV = 4'hd, // Move
BIC = 4'he, // Bit Clear (using AND & NOT operators)
MVN = 4'hf; // Move NOT
// Condition Encoding
localparam [3:0] EQ = 4'h0, // Equal / Z set
NE = 4'h1, // Not equal / Z clear
CS = 4'h2, // Carry set / C set
CC = 4'h3, // Carry clear / C clear
MI = 4'h4, // Minus / N set
PL = 4'h5, // Plus / N clear
VS = 4'h6, // Overflow / V set
VC = 4'h7, // No overflow / V clear
HI = 4'h8, // Unsigned higher / C set and Z clear
LS = 4'h9, // Unsigned lower
// or same / C clear or Z set
GE = 4'ha, // Signed greater
// than or equal / N == V
LT = 4'hb, // Signed less than / N != V
GT = 4'hc, // Signed greater
// than / Z == 0, N == V
LE = 4'hd, // Signed less than
// or equal / Z == 1, N != V
AL = 4'he, // Always
NV = 4'hf; // Never
 
// Any instruction with a condition field of 0b1111 is UNPREDICTABLE.
// Shift Types
localparam [1:0] LSL = 2'h0,
LSR = 2'h1,
ASR = 2'h2,
RRX = 2'h3,
ROR = 2'h3;
// Modes
localparam [1:0] SVC = 2'b11, // Supervisor
IRQ = 2'b10, // Interrupt
FIRQ = 2'b01, // Fast Interrupt
USR = 2'b00; // User
 
// One-Hot Mode encodings
localparam [5:0] OH_USR = 0,
OH_IRQ = 1,
OH_FIRQ = 2,
OH_SVC = 3;
 
 
/a23_config_defines.vh
0,0 → 1,81
//////////////////////////////////////////////////////////////////
// //
// Amber Configuration and Debug for the AMber 2 Core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Contains a set of defines used to configure and debug //
// the Amber core //
// //
// Author(s): //
// - Conor Santifort, csantifort.amber@gmail.com //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
 
`ifndef _A23_CONFIG_DEFINES
`define _A23_CONFIG_DEFINES
 
// Cache Ways
// Changing this parameter is the recommended
// way to change the Amber cache size; 2, 3, 4 and 8 ways are supported.
// 2 ways -> 8KB cache
// 3 ways -> 12KB cache
// 4 ways -> 16KB cache
// 8 ways -> 32KB cache
`define A23_CACHE_WAYS 4
 
// Use ram-based register bank implementation
// `define A23_RAM_REGISTER_BANK
 
// --------------------------------------------------------------------
// Debug switches
// --------------------------------------------------------------------
 
// Enable the decompiler. The default output file is amber.dis
`define A23_DECOMPILE
 
// Co-processor 15 debug. Registers in here control the cache
//`define A23_COPRO15_DEBUG
 
// Cache debug
//`define A23_CACHE_DEBUG
 
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
// File Names
// --------------------------------------------------------------------
`ifndef A23_DECOMPILE_FILE
`define A23_DECOMPILE_FILE "amber.dis"
`endif
 
`endif
 
/makefile.inc
0,0 → 1,17
INCDIR += +$(IPVLOG)/amber23
SRC += $(IPVLOG)/amber23/a23_alu.v
SRC += $(IPVLOG)/amber23/a23_barrel_shift.v
SRC += $(IPVLOG)/amber23/a23_cache.v
SRC += $(IPVLOG)/amber23/a23_coprocessor.v
SRC += $(IPVLOG)/amber23/a23_core.v
SRC += $(IPVLOG)/amber23/a23_decode.v
SRC += $(IPVLOG)/amber23/a23_decompile.v
SRC += $(IPVLOG)/amber23/a23_execute.v
SRC += $(IPVLOG)/amber23/a23_fetch.v
SRC += $(IPVLOG)/amber23/a23_multiply.v
SRC += $(IPVLOG)/amber23/a23_register_bank.v
SRC += $(IPVLOG)/amber23/a23_wishbone.v
 
DEP += $(IPVLOG)/amber23/a23_config_defines.vh
DEP += $(IPVLOG)/amber23/a23_functions.vh
DEP += $(IPVLOG)/amber23/a23_localparams.vh
/a23_ram_register_bank.v
74,8 → 74,8
 
);
 
`include "a23_localparams.v"
`include "a23_functions.v"
`include "a23_localparams.vh"
`include "a23_functions.vh"
 
wire [1:0] mode_idec;
wire [1:0] mode_exec;
/a23_register_bank.v
76,8 → 76,8
 
);
 
`include "a23_localparams.v"
`include "a23_functions.v"
`include "a23_localparams.vh"
`include "a23_functions.vh"
 
 
// User Mode Registers
/a23_functions.vh
0,0 → 1,174
//////////////////////////////////////////////////////////////////
// //
// Functions for Amber 2 Core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Functions used in more than one module //
// //
// Author(s): //
// - Conor Santifort, csantifort.amber@gmail.com //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
 
 
// ========================================================
// PC Filter - Remove the status bits
// ========================================================
function [31:0] pcf;
input [31:0] pc_reg;
begin
pcf = {6'd0, pc_reg[25:2], 2'd0};
end
endfunction
 
 
// ========================================================
// 4-bit to 16-bit 1-hot decode
// ========================================================
function [14:0] decode;
input [3:0] reg_sel;
begin
case ( reg_sel )
4'h0: decode = 15'h0001;
4'h1: decode = 15'h0002;
4'h2: decode = 15'h0004;
4'h3: decode = 15'h0008;
4'h4: decode = 15'h0010;
4'h5: decode = 15'h0020;
4'h6: decode = 15'h0040;
4'h7: decode = 15'h0080;
4'h8: decode = 15'h0100;
4'h9: decode = 15'h0200;
4'ha: decode = 15'h0400;
4'hb: decode = 15'h0800;
4'hc: decode = 15'h1000;
4'hd: decode = 15'h2000;
4'he: decode = 15'h4000;
default: decode = 15'h0000;
endcase
end
endfunction
 
 
// ========================================================
// Convert Stats Bits Mode to one-hot encoded version
// ========================================================
function [3:0] oh_status_bits_mode;
input [1:0] fn_status_bits_mode;
begin
oh_status_bits_mode =
fn_status_bits_mode == SVC ? 1'd1 << OH_SVC :
fn_status_bits_mode == IRQ ? 1'd1 << OH_IRQ :
fn_status_bits_mode == FIRQ ? 1'd1 << OH_FIRQ :
1'd1 << OH_USR ;
end
endfunction
 
// ========================================================
// Convert mode into ascii name
// ========================================================
function [(14*8)-1:0] mode_name;
input [4:0] mode;
begin
 
mode_name = mode == USR ? "User " :
mode == SVC ? "Supervisor " :
mode == IRQ ? "Interrupt " :
mode == FIRQ ? "Fast Interrupt" :
"UNKNOWN " ;
end
endfunction
 
 
// ========================================================
// Conditional Execution Function
// ========================================================
// EQ Z set
// NE Z clear
// CS C set
// CC C clear
// MI N set
// PL N clear
// VS V set
// VC V clear
// HI C set and Z clear
// LS C clear or Z set
// GE N == V
// LT N != V
// GT Z == 0,N == V
// LE Z == 1 or N != V
// AL Always (unconditional)
// NV Never
 
function conditional_execute;
input [3:0] condition;
input [3:0] flags;
begin
conditional_execute
= ( condition == AL ) ||
( condition == EQ && flags[2] ) ||
( condition == NE && !flags[2] ) ||
( condition == CS && flags[1] ) ||
( condition == CC && !flags[1] ) ||
( condition == MI && flags[3] ) ||
( condition == PL && !flags[3] ) ||
( condition == VS && flags[0] ) ||
( condition == VC && !flags[0] ) ||
( condition == HI && flags[1] && !flags[2] ) ||
( condition == LS && (!flags[1] || flags[2]) ) ||
( condition == GE && flags[3] == flags[0] ) ||
( condition == LT && flags[3] != flags[0] ) ||
 
( condition == GT && !flags[2] && flags[3] == flags[0] ) ||
( condition == LE && (flags[2] || flags[3] != flags[0])) ;
end
endfunction
 
 
// ========================================================
// Log 2
// ========================================================
 
function [31:0] log2;
input [31:0] num;
integer i;
integer out;
begin
out = 32'd0;
for (i=0; i<30; i=i+1)
if ((2**i > num) && (out == 0))
out = i-1;
log2 = out;
end
endfunction
/a23_decode.v
39,7 → 39,7
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`include "global_defines.v"
`include "global_defines.vh"
 
module a23_decode
(
130,8 → 130,8
 
);
 
`include "a23_localparams.v"
`include "a23_functions.v"
`include "a23_localparams.vh"
`include "a23_functions.vh"
 
localparam [4:0] RST_WAIT1 = 5'd0,
RST_WAIT2 = 5'd1,
666,7 → 666,12
if ( !immediate_shifter_operand && !instruction[4] )
barrel_shift_amount_sel_nxt = 2'd2; // Shift immediate amount
// regops that do not change the overflow flag
if ( opcode == AND || opcode == EOR || opcode == TST || opcode == TEQ ||
opcode == ORR || opcode == MOV || opcode == BIC || opcode == MVN )
status_bits_sel_nxt = 3'd5;
 
if ( opcode == ADD || opcode == CMN ) // CMN is just like an ADD
begin
alu_out_sel_nxt = 4'd1; // Add
852,12 → 857,12
write_data_wen_nxt = 1'd1;
// LDM: load into user mode registers, when in priviledged mode
// DOnt use mtrans_r15 here because its not loaded yet
if ( {instruction[22:20],instruction[15]} == 4'b1010 )
// Don't use mtrans_r15 here because its not loaded yet
if ( {instruction[22],instruction[20],instruction[15]} == 3'b110 )
user_mode_regs_load_nxt = 1'd1;
// SDM: store the user mode registers, when in priviledged mode
if ( {instruction[22:20]} == 3'b100 )
if ( {instruction[22],instruction[20]} == 3'b10 )
o_user_mode_regs_store_nxt = 1'd1;
// update the base register ?
1054,11 → 1059,11
write_data_wen_nxt = 1'd1;
// LDM: load into user mode registers, when in priviledged mode
if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
if ( {instruction[22],instruction[20],mtrans_r15} == 3'b110 )
user_mode_regs_load_nxt = 1'd1;
// SDM: store the user mode registers, when in priviledged mode
if ( {instruction[22:20]} == 3'b100 )
if ( {instruction[22],instruction[20]} == 2'b10 )
o_user_mode_regs_store_nxt = 1'd1;
end
end
1085,11 → 1090,11
write_data_wen_nxt = 1'd1;
// LDM: load into user mode registers, when in priviledged mode
if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
if ( {instruction[22],instruction[20],mtrans_r15} == 3'b110 )
user_mode_regs_load_nxt = 1'd1;
// SDM: store the user mode registers, when in priviledged mode
if ( {instruction[22:20]} == 3'b100 )
if ( {instruction[22],instruction[20]} == 2'b10 )
o_user_mode_regs_store_nxt = 1'd1;
end
1107,11 → 1112,12
reg_bank_wsel_nxt = mtrans_reg_d2;
// LDM: load into user mode registers, when in priviledged mode
if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
if ( {instruction[22],instruction[20],mtrans_r15} == 3'b110 )
user_mode_regs_load_nxt = 1'd1;
// SDM: store the user mode registers, when in priviledged mode
if ( {instruction[22:20]} == 3'b100 )
//if ( {instruction[22:20]} == 3'b100 )
if ( {instruction[22],instruction[20]} == 2'b10 )
o_user_mode_regs_store_nxt = 1'd1;
end
 
1126,11 → 1132,11
pc_wen_nxt = 1'd0; // hold current PC value
// LDM: load into user mode registers, when in priviledged mode
if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
if ( {instruction[22],instruction[20],mtrans_r15} == 3'b110 )
user_mode_regs_load_nxt = 1'd1;
// SDM: store the user mode registers, when in priviledged mode
if ( {instruction[22:20]} == 3'b100 )
if ( {instruction[22],instruction[20]} == 2'b10 )
o_user_mode_regs_store_nxt = 1'd1;
end
1180,11 → 1186,11
end
// LDM: load into user mode registers, when in priviledged mode
if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
if ( {instruction[22],instruction[20],mtrans_r15} == 3'b110 )
user_mode_regs_load_nxt = 1'd1;
// SDM: store the user mode registers, when in priviledged mode
if ( {instruction[22:20]} == 3'b100 )
if ( {instruction[22],instruction[20]} == 2'b10 )
o_user_mode_regs_store_nxt = 1'd1;
end
1635,7 → 1641,7
// ========================================================
//synopsys translate_off
 
`include "debug_functions.v"
`include "debug_functions.vh"
 
a23_decompile u_decompile (
.i_clk ( i_clk ),
/a23_fetch.v
77,7 → 77,7
 
);
 
`include "memory_configuration.v"
`include "memory_configuration.vh"
 
wire cache_stall;
wire wb_stall;
/a23_barrel_shift_fpga.v
56,7 → 56,7
 
);
 
`include "a23_localparams.v"
`include "a23_localparams.vh"
 
wire [31:0] rot_prod; // Input rotated by the shift amount
 
/a23_decompile.v
39,9 → 39,11
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`include "global_defines.v"
`include "a23_config_defines.v"
 
`include "global_timescale.vh"
`include "global_defines.vh"
`include "a23_config_defines.vh"
 
module a23_decompile
(
input i_clk,
58,7 → 60,7
 
);
 
`include "a23_localparams.v"
`include "a23_localparams.vh"
`ifdef A23_DECOMPILE
 
/a23_execute.v
41,7 → 41,7
// //
//////////////////////////////////////////////////////////////////
 
`include "a23_config_defines.v"
`include "a23_config_defines.vh"
 
module a23_execute (
 
106,7 → 106,6
input i_user_mode_regs_load,
input i_user_mode_regs_store_nxt,
input i_firq_not_user_mode,
input i_firq_not_user_mode_nxt,
 
input i_write_data_wen,
input i_base_address_wen, // save LDM base address register,
122,8 → 121,8
 
);
 
`include "a23_localparams.v"
`include "a23_functions.v"
`include "a23_localparams.vh"
`include "a23_functions.vh"
 
// ========================================================
// Internal signals
192,6 → 191,7
wire status_bits_mode_update;
wire status_bits_irq_mask_update;
wire status_bits_firq_mask_update;
wire [1:0] status_bits_out;
 
wire [31:0] alu_out_pc_filtered;
wire adex_nxt;
199,8 → 199,7
// ========================================================
// Status Bits in PC register
// ========================================================
wire [1:0] status_bits_out;
assign status_bits_out = (i_status_bits_mode_wen && i_status_bits_sel == 3'd1) ?
assign status_bits_out = (i_status_bits_mode_wen && i_status_bits_sel == 3'd1 && execute) ?
alu_out[1:0] : status_bits_mode ;
 
 
216,10 → 215,14
assign status_bits_flags_nxt = i_status_bits_sel == 3'd0 ? alu_flags :
i_status_bits_sel == 3'd1 ? alu_out [31:28] :
i_status_bits_sel == 3'd3 ? i_copro_read_data[31:28] :
// 4 = update flags after a multiply operation
{ multiply_flags, status_bits_flags[1:0] } ;
// update flags after a multiply operation
i_status_bits_sel == 3'd4 ? { multiply_flags, status_bits_flags[1:0] } :
// regops that do not change the overflow flag
i_status_bits_sel == 3'd5 ? { alu_flags[3:1], status_bits_flags[0] } :
4'b1111 ;
 
assign status_bits_mode_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_mode :
i_status_bits_sel == 3'd5 ? i_status_bits_mode :
i_status_bits_sel == 3'd1 ? alu_out [1:0] :
i_copro_read_data [1:0] ;
 
240,10 → 243,12
 
 
assign status_bits_irq_mask_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_irq_mask :
i_status_bits_sel == 3'd5 ? i_status_bits_irq_mask :
i_status_bits_sel == 3'd1 ? alu_out [27] :
i_copro_read_data [27] ;
assign status_bits_firq_mask_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_firq_mask :
i_status_bits_sel == 3'd5 ? i_status_bits_firq_mask :
i_status_bits_sel == 3'd1 ? alu_out [26] :
i_copro_read_data [26] ;
 
263,7 → 268,7
// ========================================================
// An immediate shift value of 0 is translated into 32
assign shift_amount = i_barrel_shift_amount_sel == 2'd0 ? 8'd0 :
i_barrel_shift_amount_sel == 2'd1 ? rs[7:0] :
i_barrel_shift_amount_sel == 2'd1 ? rs[7:0] :
i_barrel_shift_amount_sel == 2'd2 ? {3'd0, i_imm_shift_amount } :
{3'd0, i_read_data_alignment } ;
 
/a23_cache.v
42,8 → 42,8
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`include "global_defines.v"
`include "a23_config_defines.v"
`include "global_defines.vh"
`include "a23_config_defines.vh"
 
module a23_cache
#(
105,8 → 105,8
input i_wb_stall // wb_stb && !wb_ack
);
 
`include "a23_localparams.v"
`include "a23_functions.v"
`include "a23_localparams.vh"
`include "a23_functions.vh"
 
// One-hot encoded
localparam C_INIT = 0,
/a23_barrel_shift.v
52,7 → 52,7
 
);
 
`include "a23_localparams.v"
`include "a23_localparams.vh"
 
// MSB is carry out
wire [32:0] lsl_out;

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