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URL https://opencores.org/ocsvn/amber/amber/trunk

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  • This comparison shows the changes necessary to convert path 
    /amber/trunk/hw/vlog/amber25
    from Rev 58 to Rev 60
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  •

Rev 58 → Rev 60

/a25_dcache.v
474,13 → 474,14
data_wdata_r[127: 96] ;
 
 
assign con_write_data_word = i_byte_enable == 4'b0001 ? { con_read_data_word[31: 8], i_write_data[ 7: 0] } :
i_byte_enable == 4'b0010 ? { con_read_data_word[31:16], i_write_data[15: 8], con_read_data_word[ 7:0]} :
i_byte_enable == 4'b0100 ? { con_read_data_word[31:24], i_write_data[23:16], con_read_data_word[15:0]} :
i_byte_enable == 4'b1000 ? { i_write_data[31:24], con_read_data_word[23:0]} :
i_byte_enable == 4'b0011 ? { con_read_data_word[31:16], i_write_data[15: 0] } :
i_byte_enable == 4'b1100 ? { i_write_data[31:16], con_read_data_word[15:0]} :
i_write_data ;
assign con_write_data_word =
i_byte_enable == 4'b0001 ? { con_read_data_word[31: 8], i_write_data[ 7: 0] } :
i_byte_enable == 4'b0010 ? { con_read_data_word[31:16], i_write_data[15: 8], con_read_data_word[ 7:0]} :
i_byte_enable == 4'b0100 ? { con_read_data_word[31:24], i_write_data[23:16], con_read_data_word[15:0]} :
i_byte_enable == 4'b1000 ? { i_write_data[31:24], con_read_data_word[23:0]} :
i_byte_enable == 4'b0011 ? { con_read_data_word[31:16], i_write_data[15: 0] } :
i_byte_enable == 4'b1100 ? { i_write_data[31:16], con_read_data_word[15:0]} :
i_write_data ;
 
 
/a25_mem.v
114,8 → 114,8
assign address_cachable = in_cachable_mem( i_daddress ) && i_cacheable_area[i_daddress[25:21]];
assign sel_cache_p = daddress_valid_p && address_cachable && i_cache_enable && !i_exclusive;
assign sel_cache = i_daddress_valid && address_cachable && i_cache_enable && !i_exclusive;
assign uncached_data_access = i_daddress_valid && !sel_cache && !(cache_stall);
assign uncached_data_access_p = daddress_valid_p && !sel_cache && !(cache_stall);
assign uncached_data_access = i_daddress_valid && !sel_cache && !cache_stall;
assign uncached_data_access_p = daddress_valid_p && !sel_cache;
 
assign use_mem_reg = wb_stop && !mem_stall_r;
assign o_mem_read_data = use_mem_reg ? mem_read_data_r : mem_read_data_c;
170,7 → 170,7
 
always @( posedge i_clk )
begin
uncached_wb_stop_r <= (uncached_wb_stop_r || uncached_data_access_p) && (i_fetch_stall || o_mem_stall);
uncached_wb_stop_r <= (uncached_wb_stop_r || (uncached_data_access_p&&!cache_stall)) && (i_fetch_stall || o_mem_stall);
cached_wb_stop_r <= (cached_wb_stop_r || cached_wb_req) && (i_fetch_stall || o_mem_stall);
daddress_valid_stop_r <= (daddress_valid_stop_r || daddress_valid_p) && (i_fetch_stall || o_mem_stall);
// hold this until the mem access completes
/a25_decode.v
288,6 → 288,7
wire use_hold_instruction;
wire use_pre_fetch_instruction;
wire interrupt;
wire interrupt_or_conflict;
wire [1:0] interrupt_mode;
wire [2:0] next_interrupt;
reg irq = 'd0;
457,7 → 458,12
(type == MULT &&
(control_state == MULT_PROC1 ||
control_state == MULT_PROC2 ||
instruction_valid && !interrupt )) ;
// instruction_valid && !interrupt )) ;
// remove the '!conflict' term from the interrupt logic used here
// to break a combinational loop
(instruction_valid && !interrupt_or_conflict))) ;
 
 
assign branch = type == BRANCH;
assign opcode_compare = opcode == CMP || opcode == CMN || opcode == TEQ || opcode == TST ;
assign mem_op = type == TRANS;
687,9 → 693,10
swi_request ? 3'd7 : // SWI
3'd0 ; // none
 
// SWI and undefined instructions do not cause an interrupt in the decode
// stage. They only trigger interrupts if they arfe executed, so the
// interrupt is triggered if the execute condition is met in the execute stage
 
// SWI and undefined instructions do not cause an interrupt in the decode
// stage. They only trigger interrupts if they arfe executed, so the
// interrupt is triggered if the execute condition is met in the execute stage
assign interrupt = next_interrupt != 3'd0 &&
next_interrupt != 3'd7 && // SWI
next_interrupt != 3'd6 && // undefined interrupt
696,6 → 703,14
!conflict ; // Wait for conflicts to resolve before
// triggering int
 
 
// Added to use in rds_use_rs logic to break a combinational loop invloving
// the conflict signal
assign interrupt_or_conflict
= next_interrupt != 3'd0 &&
next_interrupt != 3'd7 && // SWI
next_interrupt != 3'd6 ; // undefined interrupt
 
assign interrupt_mode = next_interrupt == 3'd2 ? FIRQ :
next_interrupt == 3'd3 ? IRQ :
next_interrupt == 3'd4 ? SVC :
706,8 → 721,6
USR ;
 
 
 
 
// ========================================================
// Generate control signals
// ========================================================

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