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  • This comparison shows the changes necessary to convert path 
    /amber/trunk/hw/vlog/system
    from Rev 78 to Rev 82
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  •

Rev 78 → Rev 82

/register_addresses.v File deleted
/system_functions.v File deleted
/system_config_defines.v File deleted
/memory_configuration.v File deleted
/uart.v
51,8 → 51,8
// //
//////////////////////////////////////////////////////////////////
 
`include "system_config_defines.v"
`include "global_defines.v"
`include "system_config_defines.vh"
`include "global_defines.vh"
 
// Normally AMBER_UART_BAUD is defined in the system_config_defines.v file.
`ifndef AMBER_UART_BAUD
85,7 → 85,7
);
 
 
`include "register_addresses.v"
`include "register_addresses.vh"
 
 
localparam [3:0] TXD_IDLE = 4'd0,
/system_config_defines.vh
0,0 → 1,146
//////////////////////////////////////////////////////////////////
// //
// System Configuration and Debug //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Contains a set of defines used to configure and debug //
// the Amber peripherals. //
// //
// Author(s): //
// - Conor Santifort, csantifort.amber@gmail.com //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
 
`ifndef _SYSTEM_CONFIG_DEFINES
`define _SYSTEM_CONFIG_DEFINES
 
// Select the A23 or A25 version of the core
// You can also select the A25 core on the command line using the run script
//`define AMBER_A25_CORE
 
 
// Frequency = 800 / AMBER_CLK_DIVIDER
// 20 = 40.00 MHz
// 24 = 33.33 MHz
// 29 = 27.58 MHz
// 40 = 20.00 MHz
//
// Note that for FPGA synthesis this value is overridden
// by a value specified in $AMBER_BASE/hw/fpga/bin/Makefile
`ifdef XILINX_VIRTEX6_FPGA
`define AMBER_CLK_DIVIDER 13
`else
`define AMBER_CLK_DIVIDER 20
`endif
 
// Specify a device, if none defined then the
// generic library is used which is the fastest for simulations
// `define XILINX_SPARTAN6_FPGA
// `define XILINX_VIRTEX6_FPGA
 
// UART Baud rate for both uarts
// e.g. 921600, 460800, 230400, 57600
// `define AMBER_UART_BAUD 921600
`define AMBER_UART_BAUD 921600
 
 
// --------------------------------------------------------------------
// Debug switches
// --------------------------------------------------------------------
 
// Add jitter to wishbone accesses
//`define AMBER_WISHBONE_DEBUG
 
// Print UART debug messages
//`define AMBER_UART_DEBUG
 
// Print Interrupt Controller debug messages
//`define AMBER_IC_DEBUG
 
// Debug the loading of the memory file into memory
//`define AMBER_LOAD_MEM_DEBUG
 
// Debug main memory interface
// `define AMBER_MEMIF_DEBUG
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
// Waveform dumping
// --------------------------------------------------------------------
 
// Normally these defines are fed in via the simulator command line
 
// Create a VCD Dump File
// `define AMBER_DUMP_VCD
// Measured in system clock ticks
//`define AMBER_DUMP_START 25348000
`define AMBER_DUMP_LENGTH 150000
 
// --------------------------------------------------------------------
// Xilinx FPGA ?
// --------------------------------------------------------------------
`ifdef XILINX_SPARTAN6_FPGA
`define XILINX_FPGA
`endif
`ifdef XILINX_VIRTEX6_FPGA
`define XILINX_FPGA
`endif
 
// --------------------------------------------------------------------
// File Names
// --------------------------------------------------------------------
`ifndef AMBER_TEST_NAME
`define AMBER_TEST_NAME "add"
`endif
`ifndef MAIN_MEM_FILE
`define MAIN_MEM_FILE "not-defined"
`endif
`ifndef BOOT_MEM_FILE
`define BOOT_MEM_FILE "../tests/add.mem"
`endif
`ifndef BOOT_MEM32_PARAMS_FILE
`define BOOT_MEM32_PARAMS_FILE "not-defined"
`endif
`ifndef BOOT_MEM128_PARAMS_FILE
`define BOOT_MEM128_PARAMS_FILE "not-defined"
`endif
`ifndef AMBER_LOG_FILE
`define AMBER_LOG_FILE "tests.log"
`endif
`ifndef AMBER_VCD_FILE
`define AMBER_VCD_FILE "sim.vcd"
`endif
 
 
`endif
 
/makefile.inc
0,0 → 1,16
INCDIR += +$(IPVLOG)/system
SRC += $(IPVLOG)/system/boot_mem32.v
SRC += $(IPVLOG)/system/boot_mem128.v
SRC += $(IPVLOG)/system/clocks_resets.v
SRC += $(IPVLOG)/system/ethmac_wb.v
SRC += $(IPVLOG)/system/interrupt_controller.v
SRC += $(IPVLOG)/system/main_mem.v
SRC += $(IPVLOG)/system/system.v
SRC += $(IPVLOG)/system/test_module.v
SRC += $(IPVLOG)/system/timer_module.v
SRC += $(IPVLOG)/system/uart.v
SRC += $(IPVLOG)/system/wishbone_arbiter.v
DEP += $(IPVLOG)/system/memory_configuration.vh
DEP += $(IPVLOG)/system/register_addresses.vh
DEP += $(IPVLOG)/system/system_config_defines.vh
DEP += $(IPVLOG)/system/system_functions.vh
/main_mem.v
62,7 → 62,7
 
);
 
`include "memory_configuration.v"
`include "memory_configuration.vh"
 
reg [127:0] ram [2**(MAIN_MSB-2)-1:0];
wire start_write;
/system_functions.vh
0,0 → 1,61
//////////////////////////////////////////////////////////////////
// //
// Functions for Amber 2 System //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Functions used in more than one module //
// //
// Author(s): //
// - Conor Santifort, csantifort.amber@gmail.com //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
 
 
// ========================================================
// 32-bit Endian switch
// ========================================================
function [31:0] endian_x32;
input [31:0] data;
begin
endian_x32 = {data[7:0], data[15:8], data[23:16], data[31:24]};
end
endfunction
 
 
// ========================================================
// 4-bit Endian switch
// ========================================================
function [3:0] endian_x4;
input [3:0] data;
begin
endian_x4 = {data[0], data[1], data[2], data[3]};
end
endfunction
/test_module.v
64,7 → 64,7
 
);
 
`include "register_addresses.v"
`include "register_addresses.vh"
 
reg [7:0] firq_timer = 'd0;
/timer_module.v
38,7 → 38,7
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`include "global_defines.v"
`include "global_defines.vh"
 
module timer_module #(
parameter WB_DWIDTH = 32,
61,7 → 61,7
);
 
 
`include "register_addresses.v"
`include "register_addresses.vh"
 
// Wishbone registers
reg [15:0] timer0_load_reg = 'd0; // initial count value
/wishbone_arbiter.v
169,7 → 169,8
input i_s7_wb_err
);
 
`include "memory_configuration.v"
`include "memory_configuration.vh"
 
reg m0_wb_hold_r = 'd0;
reg m1_wb_hold_r = 'd0;
// wire m0_in_cycle;
/register_addresses.vh
0,0 → 1,140
//////////////////////////////////////////////////////////////////
// //
// Register Addresses //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Parameters that define the 16 lower bits of the address //
// of every register in the system. The upper 16 bits is //
// defined by which module the register is in. //
// //
// Author(s): //
// - Conor Santifort, csantifort.amber@gmail.com //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
 
 
// ======================================
// Register Addresses
// ======================================
 
// Test Module
localparam AMBER_TEST_STATUS = 16'h0000;
localparam AMBER_TEST_FIRQ_TIMER = 16'h0004;
localparam AMBER_TEST_IRQ_TIMER = 16'h0008;
localparam AMBER_TEST_UART_CONTROL = 16'h0010;
localparam AMBER_TEST_UART_STATUS = 16'h0014;
localparam AMBER_TEST_UART_TXD = 16'h0018;
localparam AMBER_TEST_SIM_CTRL = 16'h001c;
localparam AMBER_TEST_MEM_CTRL = 16'h0020;
localparam AMBER_TEST_CYCLES = 16'h0024;
localparam AMBER_TEST_LED = 16'h0028;
localparam AMBER_TEST_PHY_RST = 16'h002c;
 
localparam AMBER_TEST_RANDOM_NUM = 16'h0100;
localparam AMBER_TEST_RANDOM_NUM00 = 16'h0100;
localparam AMBER_TEST_RANDOM_NUM01 = 16'h0104;
localparam AMBER_TEST_RANDOM_NUM02 = 16'h0108;
localparam AMBER_TEST_RANDOM_NUM03 = 16'h010c;
localparam AMBER_TEST_RANDOM_NUM04 = 16'h0110;
localparam AMBER_TEST_RANDOM_NUM05 = 16'h0114;
localparam AMBER_TEST_RANDOM_NUM06 = 16'h0118;
localparam AMBER_TEST_RANDOM_NUM07 = 16'h011c;
localparam AMBER_TEST_RANDOM_NUM08 = 16'h0120;
localparam AMBER_TEST_RANDOM_NUM09 = 16'h0124;
localparam AMBER_TEST_RANDOM_NUM10 = 16'h0128;
localparam AMBER_TEST_RANDOM_NUM11 = 16'h012c;
localparam AMBER_TEST_RANDOM_NUM12 = 16'h0130;
localparam AMBER_TEST_RANDOM_NUM13 = 16'h0134;
localparam AMBER_TEST_RANDOM_NUM14 = 16'h0138;
localparam AMBER_TEST_RANDOM_NUM15 = 16'h013c;
 
 
// Interrupt Controller
localparam AMBER_IC_IRQ0_STATUS = 16'h0000;
localparam AMBER_IC_IRQ0_RAWSTAT = 16'h0004;
localparam AMBER_IC_IRQ0_ENABLESET = 16'h0008;
localparam AMBER_IC_IRQ0_ENABLECLR = 16'h000c;
localparam AMBER_IC_INT_SOFTSET_0 = 16'h0010;
localparam AMBER_IC_INT_SOFTCLEAR_0 = 16'h0014;
localparam AMBER_IC_FIRQ0_STATUS = 16'h0020;
localparam AMBER_IC_FIRQ0_RAWSTAT = 16'h0024;
localparam AMBER_IC_FIRQ0_ENABLESET = 16'h0028;
localparam AMBER_IC_FIRQ0_ENABLECLR = 16'h002c;
localparam AMBER_IC_IRQ1_STATUS = 16'h0040;
localparam AMBER_IC_IRQ1_RAWSTAT = 16'h0044;
localparam AMBER_IC_IRQ1_ENABLESET = 16'h0048;
localparam AMBER_IC_IRQ1_ENABLECLR = 16'h004c;
localparam AMBER_IC_INT_SOFTSET_1 = 16'h0050;
localparam AMBER_IC_INT_SOFTCLEAR_1 = 16'h0054;
localparam AMBER_IC_FIRQ1_STATUS = 16'h0060;
localparam AMBER_IC_FIRQ1_RAWSTAT = 16'h0064;
localparam AMBER_IC_FIRQ1_ENABLESET = 16'h0068;
localparam AMBER_IC_FIRQ1_ENABLECLR = 16'h006c;
localparam AMBER_IC_INT_SOFTSET_2 = 16'h0090;
localparam AMBER_IC_INT_SOFTCLEAR_2 = 16'h0094;
localparam AMBER_IC_INT_SOFTSET_3 = 16'h00d0;
localparam AMBER_IC_INT_SOFTCLEAR_3 = 16'h00d4;
 
 
// Timer Module
localparam AMBER_TM_TIMER0_LOAD = 16'h0000;
localparam AMBER_TM_TIMER0_VALUE = 16'h0004;
localparam AMBER_TM_TIMER0_CTRL = 16'h0008;
localparam AMBER_TM_TIMER0_CLR = 16'h000c;
localparam AMBER_TM_TIMER1_LOAD = 16'h0100;
localparam AMBER_TM_TIMER1_VALUE = 16'h0104;
localparam AMBER_TM_TIMER1_CTRL = 16'h0108;
localparam AMBER_TM_TIMER1_CLR = 16'h010c;
localparam AMBER_TM_TIMER2_LOAD = 16'h0200;
localparam AMBER_TM_TIMER2_VALUE = 16'h0204;
localparam AMBER_TM_TIMER2_CTRL = 16'h0208;
localparam AMBER_TM_TIMER2_CLR = 16'h020c;
 
 
// UART 0 and 1
localparam AMBER_UART_PID0 = 16'h0fe0;
localparam AMBER_UART_PID1 = 16'h0fe4;
localparam AMBER_UART_PID2 = 16'h0fe8;
localparam AMBER_UART_PID3 = 16'h0fec;
localparam AMBER_UART_CID0 = 16'h0ff0;
localparam AMBER_UART_CID1 = 16'h0ff4;
localparam AMBER_UART_CID2 = 16'h0ff8;
localparam AMBER_UART_CID3 = 16'h0ffc;
localparam AMBER_UART_DR = 16'h0000;
localparam AMBER_UART_RSR = 16'h0004;
localparam AMBER_UART_LCRH = 16'h0008;
localparam AMBER_UART_LCRM = 16'h000c;
localparam AMBER_UART_LCRL = 16'h0010;
localparam AMBER_UART_CR = 16'h0014;
localparam AMBER_UART_FR = 16'h0018;
localparam AMBER_UART_IIR = 16'h001c;
localparam AMBER_UART_ICR = 16'h001c;
 
/ethmac_wb.v
92,7 → 92,7
 
);
 
`include "system_functions.v"
`include "system_functions.vh"
 
 
// =========================
/boot_mem128.v
129,8 → 129,8
// and ISE, which I couldn't get to work with giving it the
// file name as a define.
 
`ifdef BOOT_MEM_PARAMS_FILE
`include `BOOT_MEM_PARAMS_FILE
`ifdef BOOT_MEM128_PARAMS_FILE
`include `BOOT_MEM128_PARAMS_FILE
`else
`ifdef BOOT_LOADER_ETHMAC
`include "boot-loader-ethmac_memparams128.v"
169,9 → 169,9
 
//synopsys translate_off
`ifdef XILINX_SPARTAN6_FPGA
`ifdef BOOT_MEM_PARAMS_FILE
`ifdef BOOT_MEM128_PARAMS_FILE
initial
$display("Boot mem file is %s", `BOOT_MEM_PARAMS_FILE );
$display("Boot mem file is %s", `BOOT_MEM128_PARAMS_FILE );
`endif
`endif
//synopsys translate_on
/interrupt_controller.v
69,7 → 69,7
);
 
 
`include "register_addresses.v"
`include "register_addresses.vh"
 
 
// Wishbone registers
/wb_xs6_ddr3_bridge.v
41,7 → 41,7
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`include "global_defines.v"
`include "global_defines.vh"
 
module wb_xs6_ddr3_bridge #(
parameter WB_DWIDTH = 32,
/clocks_resets.v
38,7 → 38,8
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`include "system_config_defines.v"
`include "system_config_defines.vh"
`include "global_timescale.vh"
 
 
//
/boot_mem32.v
126,8 → 126,8
// and ISE, which I couldn't get to work with giving it the
// file name as a define.
 
`ifdef BOOT_MEM_PARAMS_FILE
`include `BOOT_MEM_PARAMS_FILE
`ifdef BOOT_MEM32_PARAMS_FILE
`include `BOOT_MEM32_PARAMS_FILE
`else
`ifdef BOOT_LOADER_ETHMAC
`include "boot-loader-ethmac_memparams32.v"
166,9 → 166,9
 
//synopsys translate_off
`ifdef XILINX_SPARTAN6_FPGA
`ifdef BOOT_MEM_PARAMS_FILE
`ifdef BOOT_MEM32_PARAMS_FILE
initial
$display("Boot mem file is %s", `BOOT_MEM_PARAMS_FILE );
$display("Boot mem file is %s", `BOOT_MEM32_PARAMS_FILE );
`endif
`endif
//synopsys translate_on
/memory_configuration.vh
0,0 → 1,159
//////////////////////////////////////////////////////////////////
// //
// Memory configuration and Wishbone address decoding //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// This module provides a set of functions that are used to //
// decode memory addresses so other modules know if an address //
// is for example in main memory, or boot memory, or a UART //
// //
// Author(s): //
// - Conor Santifort, csantifort.amber@gmail.com //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
 
// e.g. 24 for 32MBytes, 26 for 128MBytes
localparam MAIN_MSB = 26;
 
// e.g. 13 for 4k words
localparam BOOT_MSB = 13;
 
localparam MAIN_BASE = 32'h0000_0000; /* Main Memory */
localparam BOOT_BASE = 32'h0000_0000; /* Cachable Boot Memory */
localparam AMBER_TM_BASE = 16'h1300; /* Timers Module */
localparam AMBER_IC_BASE = 16'h1400; /* Interrupt Controller */
localparam AMBER_UART0_BASE = 16'h1600; /* UART 0 */
localparam AMBER_UART1_BASE = 16'h1700; /* UART 1 */
localparam ETHMAC_BASE = 16'h2000; /* Ethernet MAC */
localparam HIBOOT_BASE = 32'h2800_0000; /* Uncachable Boot Memory */
localparam TEST_BASE = 16'hf000; /* Test Module */
 
 
 
function in_loboot_mem;
input [31:0] address;
begin
in_loboot_mem = (address >= BOOT_BASE &&
address < (BOOT_BASE + 2**(BOOT_MSB+1)-1));
end
endfunction
 
 
function in_hiboot_mem;
input [31:0] address;
begin
in_hiboot_mem = (address[31:BOOT_MSB+1] == HIBOOT_BASE[31:BOOT_MSB+1]);
end
endfunction
 
 
function in_boot_mem;
input [31:0] address;
begin
in_boot_mem = in_loboot_mem(address) || in_hiboot_mem(address);
end
endfunction
 
 
function in_main_mem;
input [31:0] address;
begin
in_main_mem = (address >= MAIN_BASE &&
address < (MAIN_BASE + 2**(MAIN_MSB+1)-1)) &&
!in_boot_mem ( address );
end
endfunction
 
 
// UART 0 address space
function in_uart0;
input [31:0] address;
begin
in_uart0 = address [31:16] == AMBER_UART0_BASE;
end
endfunction
 
 
// UART 1 address space
function in_uart1;
input [31:0] address;
begin
in_uart1 = address [31:16] == AMBER_UART1_BASE;
end
endfunction
 
 
// Interrupt Controller address space
function in_ic;
input [31:0] address;
begin
in_ic = address [31:16] == AMBER_IC_BASE;
end
endfunction
 
 
// Timer Module address space
function in_tm;
input [31:0] address;
begin
in_tm = address [31:16] == AMBER_TM_BASE;
end
endfunction
 
 
// Test module
function in_test;
input [31:0] address;
begin
in_test = address [31:16] == TEST_BASE;
end
endfunction
 
 
// Ethernet MAC
function in_ethmac;
input [31:0] address;
begin
in_ethmac = address [31:16] == ETHMAC_BASE;
end
endfunction
 
 
// Used in fetch.v and l2cache.v to allow accesses to these addresses
// to be cached
function in_cachable_mem;
input [31:0] address;
begin
in_cachable_mem = in_loboot_mem ( address ) ||
in_main_mem ( address ) ;
end
endfunction
 

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