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  • This comparison shows the changes necessary to convert path 
    /amber/trunk/hw/vlog/xs6_ddr3
    from Rev 52 to Rev 64
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  •

Rev 52 → Rev 64

/ddr3.xco
0,0 → 1,49
##############################################################
#
# Xilinx Core Generator version 14.5
# Date: Sun Apr 28 12:02:09 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:mig:3.92
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT MIG_Virtex-6_and_Spartan-6 family Xilinx,_Inc. 3.92
# END Select
# BEGIN Parameters
CSET component_name=ddr3
CSET xml_input_file=./ddr3/user_design/mig.prj
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-03-27T03:45:13Z
# END Extra information
GENERATE
# CRC: 75718c29
/coregen_sp605.cgp
0,0 → 1,22
# Date: Sun Apr 28 11:01:18 2013
 
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
SET workingdirectory = ./tmp/
 
# CRC: 78bed5b0
/README.txt
1,7 → 1,15
*** Steps to create the Spartan-6 DDR3 memory interface for the SP605 development board.
These instructions are based on using Xilinx ISE 11.5
These instructions are based on using Xilinx ISE 14.5
 
Use Coregen/MIG 3.3 to create the controller.
Run coregen
Open the project hw/vlog/xs6_ddr3/coregen_sp605.cgp
Under Project IP, select the Core Name "MIG Virtex-6 and Spartan-6",
right mouse on it and select Regenerate 9Under Original Project Settings)
Answer Yes to 'Do you wish to continue?' twice. The core generation process then runs in a few seconds.
Exit coregen.
 
 
This is the controller configuration, for reference.
- Component Name: ddr3
- Bank 3 Memory Type DDR3 SDRAM
- Frequency: 400MHz
10,30 → 18,39
- Memory Address Mapping Selection: Row, Bank, Column
 
 
Once the controller is generated copy all the Verilog files from the user_design/rtl directory to $AMBER_BASE/hw/vlog/xs6_ddr3.
Once the controller is generated copy all the Verilog files from the
hw/vlog/xs6_ddr3/user_design/rtl and hw/vlog/xs6_ddr3/user_design/rtl/mcb_controller
directories to $AMBER_BASE/hw/vlog/xs6_ddr3. Then make the following modifications
 
Then make the following modifications
1. ddr3
line 167 change
localparam C3_CLKFBOUT_MULT = 2;
to
localparam C3_CLKFBOUT_MULT = 4;
2. infrastructure.v
Comment out line 126, (* KEEP = "TRUE" *) wire sys_clk_ibufg;
Comment out the IBUFG instance u_ibufg_sys_clk on lines 156 to 160.
Change the CLKIN1 signal on line 202 from sys_clk_ibufg to sys_clk.
 
1. ddr3.v
Rename this module to mcb_ddr3.v.
Replace the inputs c3_sys_clk_p, c3_sys_clk_n with sys_clk_ibufg.
Delete the outputs c3_clk0 and c3_rst0.
There is already an IBUFGDS on that signal in clocks_resets.v so the
one in infrastructure.v is not needed.
 
2. memc3_infrastructure.v
Replace the inputs sys_clk_p, sys_clk_n with sys_clk_ibufg.
Delete the outputs clk0 and rst0.
Delete the line with (* KEEP = "TRUE" *) wire sys_clk_ibufg;
 
Change the localparam from
localparam CLK_PERIOD_NS = C_MEMCLK_PERIOD / 1000.0;
to
localparam CLK_PERIOD_NS = C_MEMCLK_PERIOD / 500.0;
In order to use Impact on CentOS 6, you need to install a USB driver.
sudo yum install libusb-devel
Then download and make the usb driver from http://rmdir.de/~michael/xilinx/
Once its successfully compiled run setup_pcusb to add the device IDs to the Xilinx installation.
 
Delete the generate statement from lines 124 to 154
You also need to install the fxload package
sudo rpm -i fxload-2008_10_13-3.el6.i686.rpm
And reboot after installing it.
 
On the PLL_ADV instantiation,
Change the parameter CLKFBOUT_MULT from 2 to 4.
Disconnect the CLKOUT2 output
Then power on the SP605 board and connect its USB-JTAG port to your PC.
Then run impact as follows
export LD_PRELOAD=/your-path/libusb-driver.so
impact
Impact should now be able to auto-detect the FPFA card. Right click on the FPGA and select the bitfile to load into it.
 
Delete the U_BUFG_CLK0 instantiation.
Delete the rst0_sync_r logic.
 
/ddr3/user_design/mig.prj
0,0 → 1,63
<?xml version="1.0" encoding="UTF-8"?>
<Project NoOfControllers="1" >
<ModuleName>ddr3</ModuleName>
<TargetFPGA>xc6slx45t-fgg484/-3</TargetFPGA>
<Version>3.92</Version>
<Controller number="3" >
<MemoryDevice>DDR3_SDRAM/Components/MT41J64M16XX-187E</MemoryDevice>
<TimePeriod>2500</TimePeriod>
<EnableVoltageRange>0</EnableVoltageRange>
<DataMask>1</DataMask>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>13</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<TimingParameters>
<Parameters twtr="7.5" trefi="7.8" twr="15" trtp="7.5" trfc="110" trp="13.13" tras="37.5" trcd="13.13" />
</TimingParameters>
<mrBurstLength name="Burst Length" >8(00)</mrBurstLength>
<mrCasLatency name="CAS Latency" >6</mrCasLatency>
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
<emrRTT name="RTT (nominal) - ODT" >RZQ/4</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
<emrDQS name="TDQS enable" >Disabled</emrDQS>
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
<mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
<PortInterface>NATIVE</PortInterface>
<Class>Class II</Class>
<DataClass>Class II</DataClass>
<InputPinTermination>UNCALIB_TERM</InputPinTermination>
<DataTermination>50 Ohms</DataTermination>
<CalibrationRowAddress></CalibrationRowAddress>
<CalibrationColumnAddress></CalibrationColumnAddress>
<CalibrationBankAddress></CalibrationBankAddress>
<SystemClock>Single-Ended</SystemClock>
<BypassCalibration>1</BypassCalibration>
<DebugSignals>Disable</DebugSignals>
<SystemClock>Single-Ended</SystemClock>
<Configuration>One 128-bit bi-directional port</Configuration>
<RzqPin>R7</RzqPin>
<ZioPin>W4</ZioPin>
<PortsSelected>Port0</PortsSelected>
<PortDirections>Bi-directional</PortDirections>
<UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap>
<ArbitrationAlgorithm>Round Robin</ArbitrationAlgorithm>
<TimeSlot0>0</TimeSlot0>
<TimeSlot1>0</TimeSlot1>
<TimeSlot2>0</TimeSlot2>
<TimeSlot3>0</TimeSlot3>
<TimeSlot4>0</TimeSlot4>
<TimeSlot5>0</TimeSlot5>
<TimeSlot6>0</TimeSlot6>
<TimeSlot7>0</TimeSlot7>
<TimeSlot8>0</TimeSlot8>
<TimeSlot9>0</TimeSlot9>
<TimeSlot10>0</TimeSlot10>
<TimeSlot11>0</TimeSlot11>
</Controller>
</Project>
/ddr3/user_design
ddr3/user_design Property changes : Added: svn:ignore ## -0,0 +1,5 ## +datasheet.txt +rtl +par +synth +sim Index: ddr3 =================================================================== --- ddr3 (nonexistent) +++ ddr3 (revision 64)
ddr3 Property changes : Added: svn:ignore ## -0,0 +1,2 ## +example_design +docs Index: . =================================================================== --- . (revision 52) +++ . (revision 64)
. Property changes : Modified: svn:ignore ## -6,3 +6,16 ## memc3_infrastructure.v mcb_soft_calibration_top.v mcb_raw_wrapper.v +ddr3.gise +ddr3.veo +mcb_ui_top.v +infrastructure.v +memc_wrapper.v +ddr3_readme.txt +ddr3_xmdf.tcl +ddr3.v +tmp +coregen.log +ddr3.xise +coregen_sp605.cgc +ddr3_flist.txt

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