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    /amber/trunk/hw/vlog
    from Rev 10 to Rev 11
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Rev 10 → Rev 11

/xv6_ddr3
xv6_ddr3 Property changes : Added: svn:ignore ## -0,0 +1,53 ## +arb_mux.v +arb_row_col.v +arb_select.v +bank_cntrl.v +bank_common.v +bank_compare.v +bank_mach.v +bank_queue.v +bank_state.v +circ_buffer.v +clk_ibuf.v +col_mach.v +ddr2_ddr3_chipscope.v +ecc_buf.v +ecc_dec_fix.v +ecc_gen.v +ecc_merge_enc.v +infrastructure.v +iodelay_ctrl.v +mc.v +memc_ui_top.v +mem_intfc.v +phy_ck_iob.v +phy_clock_io.v +phy_control_io.v +phy_data_io.v +phy_dly_ctrl.v +phy_dm_iob.v +phy_dq_iob.v +phy_dqs_iob.v +phy_init.v +phy_ocb_mon_top.v +phy_ocb_mon.v +phy_pd_top.v +phy_pd.v +phy_rdclk_gen.v +phy_rdctrl_sync.v +phy_rddata_sync.v +phy_rdlvl.v +phy_read.v +phy_top.v +phy_write.v +phy_wrlvl.v +rank_cntrl.v +rank_common.v +rank_mach.v +rd_bitslip.v +round_robin_arb.v +ui_cmd.v +ui_rd_data.v +ui_top.v +ui_wr_data.v +xv6_ddr3.v Index: system/register_addresses.v =================================================================== --- system/register_addresses.v (revision 10) +++ system/register_addresses.v (revision 11) @@ -53,6 +53,7 @@ localparam AMBER_TEST_UART_STATUS = 16'h0014; localparam AMBER_TEST_UART_TXD = 16'h0018; localparam AMBER_TEST_SIM_CTRL = 16'h001c; +localparam AMBER_TEST_MEM_CTRL = 16'h0020; localparam AMBER_TEST_RANDOM_NUM = 16'h0100; localparam AMBER_TEST_RANDOM_NUM00 = 16'h0100;
/system/main_mem.v
46,7 → 46,7
module main_mem
(
input i_clk,
 
input i_mem_ctrl, // 0=128MB, 1=32MB
// Wishbone Bus
input [31:0] i_wb_adr,
input [3:0] i_wb_sel,
96,7 → 96,9
i_wb_adr[3:2] == 2'd2 ? { 4'hf, ~i_wb_sel, 8'hff } :
{ ~i_wb_sel, 12'hfff } ;
wr_data <= {4{i_wb_dat}};
addr_d1 <= i_wb_adr[29:2];
 
// Wrap the address at 32 MB, or full width
addr_d1 <= i_mem_ctrl ? {5'd0, i_wb_adr[24:2]} : i_wb_adr[29:2];
if ( wr_en )
ram [addr_d1[27:2]] <= masked_wdata;
/system/system.v
121,6 → 121,7
`endif
 
wire phy_init_done;
wire test_mem_ctrl;
 
// ======================================
// Xilinx Virtex-6 DDR3 Controller connections
382,6 → 383,7
.o_irq ( test_reg_irq ),
.o_firq ( test_reg_firq ),
.o_mem_ctrl ( test_mem_ctrl ),
.i_wb_adr ( s_wb_adr [5] ),
.i_wb_sel ( s_wb_sel [5] ),
.i_wb_we ( s_wb_we [5] ),
458,6 → 460,7
main_mem u_main_mem (
.i_clk ( sys_clk ),
.i_mem_ctrl ( test_mem_ctrl ),
.i_wb_adr ( s_wb_adr [2] ),
.i_wb_sel ( s_wb_sel [2] ),
.i_wb_we ( s_wb_we [2] ),
491,6 → 494,7
.i_rd_data ( c3_p0_rd_data ),
.i_rd_empty ( c3_p0_rd_empty ),
.i_mem_ctrl ( test_mem_ctrl ),
.i_wb_adr ( s_wb_adr [2] ),
.i_wb_sel ( s_wb_sel [2] ),
.i_wb_we ( s_wb_we [2] ),
594,6 → 598,7
.i_phy_init_done ( phy_init_done1 ),
.o_phy_init_done ( phy_init_done ), // delayed version
.i_mem_ctrl ( test_mem_ctrl ),
.i_wb_adr ( s_wb_adr [2] ),
.i_wb_sel ( s_wb_sel [2] ),
.i_wb_we ( s_wb_we [2] ),
/system/test_module.v
46,7 → 46,7
 
output o_irq,
output o_firq,
 
output o_mem_ctrl, // 0=128MB, 1=32MB
input [31:0] i_wb_adr,
input [3:0] i_wb_sel,
input i_wb_we,
74,7 → 74,8
reg [7:0] tb_uart_txd_reg = 'd0;
//synopsys translate_on
 
reg [1:0] sim_ctrl_reg = 'd0; // 1,2 = simulation, 0 = fpga
reg [2:0] sim_ctrl_reg = 'd0; // 0 = fpga, other values for simulations
reg mem_ctrl_reg = 'd0; // 0 = 128MB, 1 = 32MB main memory
reg [31:0] test_status_reg = 'd0;
reg test_status_set = 'd0; // used to terminate tests
91,11 → 92,11
always @( posedge i_clk )
wb_start_read_d1 <= wb_start_read;
 
assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
assign o_wb_err = 1'd0;
assign o_wb_dat = wb_rdata;
assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
assign o_wb_err = 1'd0;
assign o_wb_dat = wb_rdata;
assign o_mem_ctrl = mem_ctrl_reg;
 
 
// ========================================================
// Register Reads
// ========================================================
103,7 → 104,7
if ( wb_start_read )
case ( i_wb_adr[15:0] )
AMBER_TEST_STATUS: wb_rdata <= test_status_reg;
AMBER_TEST_FIRQ_TIMER: wb_rdata <= {24'd0, firq_timer};
AMBER_TEST_FIRQ_TIMER: wb_rdata <= {24'd0, firq_timer};
AMBER_TEST_IRQ_TIMER: wb_rdata <= {24'd0, irq_timer};
AMBER_TEST_RANDOM_NUM: wb_rdata <= {24'd0, random_num};
133,7 → 134,8
AMBER_TEST_UART_TXD: wb_rdata <= {24'd0, tb_uart_txd_reg};
//synopsys translate_on
AMBER_TEST_SIM_CTRL: wb_rdata <= {30'd0, sim_ctrl_reg};
AMBER_TEST_SIM_CTRL: wb_rdata <= {29'd0, sim_ctrl_reg};
AMBER_TEST_MEM_CTRL: wb_rdata <= {31'd0, mem_ctrl_reg};
default: wb_rdata <= 32'haabbccdd;
endcase
154,7 → 156,7
always @( posedge i_clk )
begin
// Value reads as 1 in simulation, and zero in the FPGA
sim_ctrl_reg <= 2'd `AMBER_SIM_CTRL ;
sim_ctrl_reg <= 3'd `AMBER_SIM_CTRL ;
end
//synopsys translate_on
 
231,6 → 233,14
 
 
// ======================================
// Memory Configuration Register Write
// ======================================
always @( posedge i_clk )
if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_MEM_CTRL )
mem_ctrl_reg <= i_wb_dat[0];
 
 
// ======================================
// Test UART registers
// ======================================
// These control the testbench UART, not the real
/system/wb_xs6_ddr3_bridge.v
47,6 → 47,8
(
input i_clk,
 
input i_mem_ctrl, // 0=128MB, 1=32MB
 
// Wishbone Bus
input [31:0] i_wb_adr,
input [3:0] i_wb_sel,
77,7 → 79,7
reg start_write_d1;
reg start_read_d1;
reg start_read_hold = 'd0;
reg [31:0] wb_adr_d1;
reg [29:0] wb_adr_d1;
wire ddr3_busy;
reg read_ack = 'd0;
reg read_ready = 1'd1;
130,7 → 132,7
start_write_d1 <= start_write;
start_read_d1 <= start_read;
wb_adr_d1 <= i_wb_adr;
wb_adr_d1 <= i_mem_ctrl ? {5'd0, i_wb_adr[24:0]} : i_wb_adr[29:0];
if ( start_read )
start_read_hold <= 1'd1;
/system/wb_xv6_ddr3_bridge.v
48,7 → 48,9
input i_sys_clk,
input i_ddr_clk,
 
// MBus Ports
input i_mem_ctrl, // 0=128MB, 1=32MB
 
// Wishbone Ports
input [31:0] i_wb_adr,
input [3:0] i_wb_sel,
input i_wb_we,
125,7 → 127,7
 
assign cmd_en = start_write || start_read;
assign cmd_instr = start_write ? 3'd0 : 3'd1;
assign cmd_addr = i_wb_adr[26:0];
assign cmd_addr = i_mem_ctrl ? {2'd0, i_wb_adr[24:0]} : i_wb_adr[26:0];
 
assign ddr_rd_valid = i_ddr_rd_valid && !ddr_rd_valid_r;
assign ddr_rd_data = ddr_addr2_r ? i_ddr_rd_data[63:32] : i_ddr_rd_data[31:00];
/tb/tb.v
189,9 → 189,9
.dm_tdqs ( ddr3_dm ),
.ba ( ddr3_ba ),
.addr ( {1'd0, ddr3_addr} ),
.dq ( ddr3_dq ),
.dqs ( ddr3_dqs_p ),
.dqs_n ( ddr3_dqs_n ),
.dq ( ddr3_dq ),
.dqs ( ddr3_dqs_p ),
.dqs_n ( ddr3_dqs_n ),
.tdqs_n ( ),
.odt ( ddr3_odt ),
.rst_n ( ddr3_reset_n )
391,14 → 391,14
`ifdef XILINX_FPGA
mm_ddr3_addr = {main_mem_file_address[13:11], main_mem_file_address[26:14], main_mem_file_address[10:4]};
main_mem_file_data_128 = tb.u_ddr3_model_c3.memory [mm_ddr3_addr];
tb.u_ddr3_model_c3.memory [mm_ddr3_addr] =
main_mem_file_data_128 = tb.u_ddr3_model.memory [mm_ddr3_addr];
tb.u_ddr3_model.memory [mm_ddr3_addr] =
insert_32_into_128 ( main_mem_file_address[3:2],
main_mem_file_data_128,
main_mem_file_data );
`ifdef AMBER_LOAD_MEM_DEBUG
main_mem_file_data_128 = tb.u_ddr3_model_c3.memory [mm_ddr3_addr];
main_mem_file_data_128 = tb.u_ddr3_model.memory [mm_ddr3_addr];
$display ("Load DDR3: PAddr: 0x%08x, DDR3 Addr 0x%08h, Data 0x%032x",
main_mem_file_address, mm_ddr3_addr, main_mem_file_data_128);
`endif
/tb
tb Property changes : Added: svn:ignore ## -0,0 +1,2 ## +ddr3_model_parameters_c3.vh +ddr3_model_c3.v Index: xs6_ddr3 =================================================================== --- xs6_ddr3 (revision 10) +++ xs6_ddr3 (revision 11)
xs6_ddr3 Property changes : Added: svn:ignore ## -0,0 +1,8 ## +mcb_ddr3.v +iodrp_controller.v +iodrp_mcb_controller.v +mcb_soft_calibration.v +memc3_wrapper.v +memc3_infrastructure.v +mcb_soft_calibration_top.v +mcb_raw_wrapper.v

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