URL
https://opencores.org/ocsvn/amber/amber/trunk
Subversion Repositories amber
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- This comparison shows the changes necessary to convert path
/amber/trunk/hw/vlog
- from Rev 78 to Rev 82
- ↔ Reverse comparison
Rev 78 → Rev 82
/ethmac/makefile.inc
0,0 → 1,28
INCDIR += +$(IPVLOG)/ethmac |
SRC += $(IPVLOG)/ethmac/eth_clockgen.v |
SRC += $(IPVLOG)/ethmac/eth_cop.v |
SRC += $(IPVLOG)/ethmac/eth_crc.v |
SRC += $(IPVLOG)/ethmac/eth_fifo.v |
SRC += $(IPVLOG)/ethmac/eth_maccontrol.v |
SRC += $(IPVLOG)/ethmac/eth_macstatus.v |
SRC += $(IPVLOG)/ethmac/eth_miim.v |
SRC += $(IPVLOG)/ethmac/eth_outputcontrol.v |
SRC += $(IPVLOG)/ethmac/eth_random.v |
SRC += $(IPVLOG)/ethmac/eth_receivecontrol.v |
SRC += $(IPVLOG)/ethmac/eth_registers.v |
SRC += $(IPVLOG)/ethmac/eth_register.v |
SRC += $(IPVLOG)/ethmac/eth_rxaddrcheck.v |
SRC += $(IPVLOG)/ethmac/eth_rxcounters.v |
SRC += $(IPVLOG)/ethmac/eth_rxethmac.v |
SRC += $(IPVLOG)/ethmac/eth_rxstatem.v |
SRC += $(IPVLOG)/ethmac/eth_shiftreg.v |
SRC += $(IPVLOG)/ethmac/eth_spram_256x32.v |
SRC += $(IPVLOG)/ethmac/eth_top.v |
SRC += $(IPVLOG)/ethmac/eth_transmitcontrol.v |
SRC += $(IPVLOG)/ethmac/eth_txcounters.v |
SRC += $(IPVLOG)/ethmac/eth_txethmac.v |
SRC += $(IPVLOG)/ethmac/eth_txstatem.v |
SRC += $(IPVLOG)/ethmac/eth_wishbone.v |
|
DEP += $(IPVLOG)/ethmac/eth_defines.v |
DEP += $(IPVLOG)/ethmac/timescale.v |
/system/register_addresses.v
File deleted
/system/system_functions.v
File deleted
/system/system_config_defines.v
File deleted
/system/memory_configuration.v
File deleted
/system/uart.v
51,8 → 51,8
// // |
////////////////////////////////////////////////////////////////// |
|
`include "system_config_defines.v" |
`include "global_defines.v" |
`include "system_config_defines.vh" |
`include "global_defines.vh" |
|
// Normally AMBER_UART_BAUD is defined in the system_config_defines.v file. |
`ifndef AMBER_UART_BAUD |
85,7 → 85,7
); |
|
|
`include "register_addresses.v" |
`include "register_addresses.vh" |
|
|
localparam [3:0] TXD_IDLE = 4'd0, |
/system/system_config_defines.vh
0,0 → 1,146
////////////////////////////////////////////////////////////////// |
// // |
// System Configuration and Debug // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Contains a set of defines used to configure and debug // |
// the Amber peripherals. // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
|
`ifndef _SYSTEM_CONFIG_DEFINES |
`define _SYSTEM_CONFIG_DEFINES |
|
// Select the A23 or A25 version of the core |
// You can also select the A25 core on the command line using the run script |
//`define AMBER_A25_CORE |
|
|
// Frequency = 800 / AMBER_CLK_DIVIDER |
// 20 = 40.00 MHz |
// 24 = 33.33 MHz |
// 29 = 27.58 MHz |
// 40 = 20.00 MHz |
// |
// Note that for FPGA synthesis this value is overridden |
// by a value specified in $AMBER_BASE/hw/fpga/bin/Makefile |
`ifdef XILINX_VIRTEX6_FPGA |
`define AMBER_CLK_DIVIDER 13 |
`else |
`define AMBER_CLK_DIVIDER 20 |
`endif |
|
// Specify a device, if none defined then the |
// generic library is used which is the fastest for simulations |
// `define XILINX_SPARTAN6_FPGA |
// `define XILINX_VIRTEX6_FPGA |
|
// UART Baud rate for both uarts |
// e.g. 921600, 460800, 230400, 57600 |
// `define AMBER_UART_BAUD 921600 |
`define AMBER_UART_BAUD 921600 |
|
|
// -------------------------------------------------------------------- |
// Debug switches |
// -------------------------------------------------------------------- |
|
// Add jitter to wishbone accesses |
//`define AMBER_WISHBONE_DEBUG |
|
// Print UART debug messages |
//`define AMBER_UART_DEBUG |
|
// Print Interrupt Controller debug messages |
//`define AMBER_IC_DEBUG |
|
// Debug the loading of the memory file into memory |
//`define AMBER_LOAD_MEM_DEBUG |
|
// Debug main memory interface |
// `define AMBER_MEMIF_DEBUG |
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// Waveform dumping |
// -------------------------------------------------------------------- |
|
// Normally these defines are fed in via the simulator command line |
|
// Create a VCD Dump File |
// `define AMBER_DUMP_VCD |
// Measured in system clock ticks |
//`define AMBER_DUMP_START 25348000 |
`define AMBER_DUMP_LENGTH 150000 |
|
// -------------------------------------------------------------------- |
// Xilinx FPGA ? |
// -------------------------------------------------------------------- |
`ifdef XILINX_SPARTAN6_FPGA |
`define XILINX_FPGA |
`endif |
`ifdef XILINX_VIRTEX6_FPGA |
`define XILINX_FPGA |
`endif |
|
|
// -------------------------------------------------------------------- |
// File Names |
// -------------------------------------------------------------------- |
`ifndef AMBER_TEST_NAME |
`define AMBER_TEST_NAME "add" |
`endif |
`ifndef MAIN_MEM_FILE |
`define MAIN_MEM_FILE "not-defined" |
`endif |
`ifndef BOOT_MEM_FILE |
`define BOOT_MEM_FILE "../tests/add.mem" |
`endif |
`ifndef BOOT_MEM32_PARAMS_FILE |
`define BOOT_MEM32_PARAMS_FILE "not-defined" |
`endif |
`ifndef BOOT_MEM128_PARAMS_FILE |
`define BOOT_MEM128_PARAMS_FILE "not-defined" |
`endif |
`ifndef AMBER_LOG_FILE |
`define AMBER_LOG_FILE "tests.log" |
`endif |
`ifndef AMBER_VCD_FILE |
`define AMBER_VCD_FILE "sim.vcd" |
`endif |
|
|
`endif |
|
/system/makefile.inc
0,0 → 1,16
INCDIR += +$(IPVLOG)/system |
SRC += $(IPVLOG)/system/boot_mem32.v |
SRC += $(IPVLOG)/system/boot_mem128.v |
SRC += $(IPVLOG)/system/clocks_resets.v |
SRC += $(IPVLOG)/system/ethmac_wb.v |
SRC += $(IPVLOG)/system/interrupt_controller.v |
SRC += $(IPVLOG)/system/main_mem.v |
SRC += $(IPVLOG)/system/system.v |
SRC += $(IPVLOG)/system/test_module.v |
SRC += $(IPVLOG)/system/timer_module.v |
SRC += $(IPVLOG)/system/uart.v |
SRC += $(IPVLOG)/system/wishbone_arbiter.v |
DEP += $(IPVLOG)/system/memory_configuration.vh |
DEP += $(IPVLOG)/system/register_addresses.vh |
DEP += $(IPVLOG)/system/system_config_defines.vh |
DEP += $(IPVLOG)/system/system_functions.vh |
/system/main_mem.v
62,7 → 62,7
|
); |
|
`include "memory_configuration.v" |
`include "memory_configuration.vh" |
|
reg [127:0] ram [2**(MAIN_MSB-2)-1:0]; |
wire start_write; |
/system/system_functions.vh
0,0 → 1,61
////////////////////////////////////////////////////////////////// |
// // |
// Functions for Amber 2 System // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Functions used in more than one module // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
|
|
// ======================================================== |
// 32-bit Endian switch |
// ======================================================== |
function [31:0] endian_x32; |
input [31:0] data; |
begin |
endian_x32 = {data[7:0], data[15:8], data[23:16], data[31:24]}; |
end |
endfunction |
|
|
// ======================================================== |
// 4-bit Endian switch |
// ======================================================== |
function [3:0] endian_x4; |
input [3:0] data; |
begin |
endian_x4 = {data[0], data[1], data[2], data[3]}; |
end |
endfunction |
/system/test_module.v
64,7 → 64,7
|
); |
|
`include "register_addresses.v" |
`include "register_addresses.vh" |
|
|
reg [7:0] firq_timer = 'd0; |
/system/timer_module.v
38,7 → 38,7
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
`include "global_defines.v" |
`include "global_defines.vh" |
|
module timer_module #( |
parameter WB_DWIDTH = 32, |
61,7 → 61,7
); |
|
|
`include "register_addresses.v" |
`include "register_addresses.vh" |
|
// Wishbone registers |
reg [15:0] timer0_load_reg = 'd0; // initial count value |
/system/wishbone_arbiter.v
169,7 → 169,8
input i_s7_wb_err |
); |
|
`include "memory_configuration.v" |
`include "memory_configuration.vh" |
|
reg m0_wb_hold_r = 'd0; |
reg m1_wb_hold_r = 'd0; |
// wire m0_in_cycle; |
/system/register_addresses.vh
0,0 → 1,140
////////////////////////////////////////////////////////////////// |
// // |
// Register Addresses // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Parameters that define the 16 lower bits of the address // |
// of every register in the system. The upper 16 bits is // |
// defined by which module the register is in. // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
|
|
// ====================================== |
// Register Addresses |
// ====================================== |
|
// Test Module |
localparam AMBER_TEST_STATUS = 16'h0000; |
localparam AMBER_TEST_FIRQ_TIMER = 16'h0004; |
localparam AMBER_TEST_IRQ_TIMER = 16'h0008; |
localparam AMBER_TEST_UART_CONTROL = 16'h0010; |
localparam AMBER_TEST_UART_STATUS = 16'h0014; |
localparam AMBER_TEST_UART_TXD = 16'h0018; |
localparam AMBER_TEST_SIM_CTRL = 16'h001c; |
localparam AMBER_TEST_MEM_CTRL = 16'h0020; |
localparam AMBER_TEST_CYCLES = 16'h0024; |
localparam AMBER_TEST_LED = 16'h0028; |
localparam AMBER_TEST_PHY_RST = 16'h002c; |
|
localparam AMBER_TEST_RANDOM_NUM = 16'h0100; |
localparam AMBER_TEST_RANDOM_NUM00 = 16'h0100; |
localparam AMBER_TEST_RANDOM_NUM01 = 16'h0104; |
localparam AMBER_TEST_RANDOM_NUM02 = 16'h0108; |
localparam AMBER_TEST_RANDOM_NUM03 = 16'h010c; |
localparam AMBER_TEST_RANDOM_NUM04 = 16'h0110; |
localparam AMBER_TEST_RANDOM_NUM05 = 16'h0114; |
localparam AMBER_TEST_RANDOM_NUM06 = 16'h0118; |
localparam AMBER_TEST_RANDOM_NUM07 = 16'h011c; |
localparam AMBER_TEST_RANDOM_NUM08 = 16'h0120; |
localparam AMBER_TEST_RANDOM_NUM09 = 16'h0124; |
localparam AMBER_TEST_RANDOM_NUM10 = 16'h0128; |
localparam AMBER_TEST_RANDOM_NUM11 = 16'h012c; |
localparam AMBER_TEST_RANDOM_NUM12 = 16'h0130; |
localparam AMBER_TEST_RANDOM_NUM13 = 16'h0134; |
localparam AMBER_TEST_RANDOM_NUM14 = 16'h0138; |
localparam AMBER_TEST_RANDOM_NUM15 = 16'h013c; |
|
|
// Interrupt Controller |
localparam AMBER_IC_IRQ0_STATUS = 16'h0000; |
localparam AMBER_IC_IRQ0_RAWSTAT = 16'h0004; |
localparam AMBER_IC_IRQ0_ENABLESET = 16'h0008; |
localparam AMBER_IC_IRQ0_ENABLECLR = 16'h000c; |
localparam AMBER_IC_INT_SOFTSET_0 = 16'h0010; |
localparam AMBER_IC_INT_SOFTCLEAR_0 = 16'h0014; |
localparam AMBER_IC_FIRQ0_STATUS = 16'h0020; |
localparam AMBER_IC_FIRQ0_RAWSTAT = 16'h0024; |
localparam AMBER_IC_FIRQ0_ENABLESET = 16'h0028; |
localparam AMBER_IC_FIRQ0_ENABLECLR = 16'h002c; |
localparam AMBER_IC_IRQ1_STATUS = 16'h0040; |
localparam AMBER_IC_IRQ1_RAWSTAT = 16'h0044; |
localparam AMBER_IC_IRQ1_ENABLESET = 16'h0048; |
localparam AMBER_IC_IRQ1_ENABLECLR = 16'h004c; |
localparam AMBER_IC_INT_SOFTSET_1 = 16'h0050; |
localparam AMBER_IC_INT_SOFTCLEAR_1 = 16'h0054; |
localparam AMBER_IC_FIRQ1_STATUS = 16'h0060; |
localparam AMBER_IC_FIRQ1_RAWSTAT = 16'h0064; |
localparam AMBER_IC_FIRQ1_ENABLESET = 16'h0068; |
localparam AMBER_IC_FIRQ1_ENABLECLR = 16'h006c; |
localparam AMBER_IC_INT_SOFTSET_2 = 16'h0090; |
localparam AMBER_IC_INT_SOFTCLEAR_2 = 16'h0094; |
localparam AMBER_IC_INT_SOFTSET_3 = 16'h00d0; |
localparam AMBER_IC_INT_SOFTCLEAR_3 = 16'h00d4; |
|
|
// Timer Module |
localparam AMBER_TM_TIMER0_LOAD = 16'h0000; |
localparam AMBER_TM_TIMER0_VALUE = 16'h0004; |
localparam AMBER_TM_TIMER0_CTRL = 16'h0008; |
localparam AMBER_TM_TIMER0_CLR = 16'h000c; |
localparam AMBER_TM_TIMER1_LOAD = 16'h0100; |
localparam AMBER_TM_TIMER1_VALUE = 16'h0104; |
localparam AMBER_TM_TIMER1_CTRL = 16'h0108; |
localparam AMBER_TM_TIMER1_CLR = 16'h010c; |
localparam AMBER_TM_TIMER2_LOAD = 16'h0200; |
localparam AMBER_TM_TIMER2_VALUE = 16'h0204; |
localparam AMBER_TM_TIMER2_CTRL = 16'h0208; |
localparam AMBER_TM_TIMER2_CLR = 16'h020c; |
|
|
// UART 0 and 1 |
localparam AMBER_UART_PID0 = 16'h0fe0; |
localparam AMBER_UART_PID1 = 16'h0fe4; |
localparam AMBER_UART_PID2 = 16'h0fe8; |
localparam AMBER_UART_PID3 = 16'h0fec; |
localparam AMBER_UART_CID0 = 16'h0ff0; |
localparam AMBER_UART_CID1 = 16'h0ff4; |
localparam AMBER_UART_CID2 = 16'h0ff8; |
localparam AMBER_UART_CID3 = 16'h0ffc; |
localparam AMBER_UART_DR = 16'h0000; |
localparam AMBER_UART_RSR = 16'h0004; |
localparam AMBER_UART_LCRH = 16'h0008; |
localparam AMBER_UART_LCRM = 16'h000c; |
localparam AMBER_UART_LCRL = 16'h0010; |
localparam AMBER_UART_CR = 16'h0014; |
localparam AMBER_UART_FR = 16'h0018; |
localparam AMBER_UART_IIR = 16'h001c; |
localparam AMBER_UART_ICR = 16'h001c; |
|
/system/ethmac_wb.v
92,7 → 92,7
|
); |
|
`include "system_functions.v" |
`include "system_functions.vh" |
|
|
// ========================= |
/system/boot_mem128.v
129,8 → 129,8
// and ISE, which I couldn't get to work with giving it the |
// file name as a define. |
|
`ifdef BOOT_MEM_PARAMS_FILE |
`include `BOOT_MEM_PARAMS_FILE |
`ifdef BOOT_MEM128_PARAMS_FILE |
`include `BOOT_MEM128_PARAMS_FILE |
`else |
`ifdef BOOT_LOADER_ETHMAC |
`include "boot-loader-ethmac_memparams128.v" |
169,9 → 169,9
|
//synopsys translate_off |
`ifdef XILINX_SPARTAN6_FPGA |
`ifdef BOOT_MEM_PARAMS_FILE |
`ifdef BOOT_MEM128_PARAMS_FILE |
initial |
$display("Boot mem file is %s", `BOOT_MEM_PARAMS_FILE ); |
$display("Boot mem file is %s", `BOOT_MEM128_PARAMS_FILE ); |
`endif |
`endif |
//synopsys translate_on |
/system/interrupt_controller.v
69,7 → 69,7
); |
|
|
`include "register_addresses.v" |
`include "register_addresses.vh" |
|
|
// Wishbone registers |
/system/wb_xs6_ddr3_bridge.v
41,7 → 41,7
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
`include "global_defines.v" |
`include "global_defines.vh" |
|
module wb_xs6_ddr3_bridge #( |
parameter WB_DWIDTH = 32, |
/system/clocks_resets.v
38,7 → 38,8
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
`include "system_config_defines.v" |
`include "system_config_defines.vh" |
`include "global_timescale.vh" |
|
|
// |
/system/boot_mem32.v
126,8 → 126,8
// and ISE, which I couldn't get to work with giving it the |
// file name as a define. |
|
`ifdef BOOT_MEM_PARAMS_FILE |
`include `BOOT_MEM_PARAMS_FILE |
`ifdef BOOT_MEM32_PARAMS_FILE |
`include `BOOT_MEM32_PARAMS_FILE |
`else |
`ifdef BOOT_LOADER_ETHMAC |
`include "boot-loader-ethmac_memparams32.v" |
166,9 → 166,9
|
//synopsys translate_off |
`ifdef XILINX_SPARTAN6_FPGA |
`ifdef BOOT_MEM_PARAMS_FILE |
`ifdef BOOT_MEM32_PARAMS_FILE |
initial |
$display("Boot mem file is %s", `BOOT_MEM_PARAMS_FILE ); |
$display("Boot mem file is %s", `BOOT_MEM32_PARAMS_FILE ); |
`endif |
`endif |
//synopsys translate_on |
/system/memory_configuration.vh
0,0 → 1,159
////////////////////////////////////////////////////////////////// |
// // |
// Memory configuration and Wishbone address decoding // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// This module provides a set of functions that are used to // |
// decode memory addresses so other modules know if an address // |
// is for example in main memory, or boot memory, or a UART // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
|
// e.g. 24 for 32MBytes, 26 for 128MBytes |
localparam MAIN_MSB = 26; |
|
// e.g. 13 for 4k words |
localparam BOOT_MSB = 13; |
|
localparam MAIN_BASE = 32'h0000_0000; /* Main Memory */ |
localparam BOOT_BASE = 32'h0000_0000; /* Cachable Boot Memory */ |
localparam AMBER_TM_BASE = 16'h1300; /* Timers Module */ |
localparam AMBER_IC_BASE = 16'h1400; /* Interrupt Controller */ |
localparam AMBER_UART0_BASE = 16'h1600; /* UART 0 */ |
localparam AMBER_UART1_BASE = 16'h1700; /* UART 1 */ |
localparam ETHMAC_BASE = 16'h2000; /* Ethernet MAC */ |
localparam HIBOOT_BASE = 32'h2800_0000; /* Uncachable Boot Memory */ |
localparam TEST_BASE = 16'hf000; /* Test Module */ |
|
|
|
function in_loboot_mem; |
input [31:0] address; |
begin |
in_loboot_mem = (address >= BOOT_BASE && |
address < (BOOT_BASE + 2**(BOOT_MSB+1)-1)); |
end |
endfunction |
|
|
function in_hiboot_mem; |
input [31:0] address; |
begin |
in_hiboot_mem = (address[31:BOOT_MSB+1] == HIBOOT_BASE[31:BOOT_MSB+1]); |
end |
endfunction |
|
|
function in_boot_mem; |
input [31:0] address; |
begin |
in_boot_mem = in_loboot_mem(address) || in_hiboot_mem(address); |
end |
endfunction |
|
|
function in_main_mem; |
input [31:0] address; |
begin |
in_main_mem = (address >= MAIN_BASE && |
address < (MAIN_BASE + 2**(MAIN_MSB+1)-1)) && |
!in_boot_mem ( address ); |
end |
endfunction |
|
|
// UART 0 address space |
function in_uart0; |
input [31:0] address; |
begin |
in_uart0 = address [31:16] == AMBER_UART0_BASE; |
end |
endfunction |
|
|
// UART 1 address space |
function in_uart1; |
input [31:0] address; |
begin |
in_uart1 = address [31:16] == AMBER_UART1_BASE; |
end |
endfunction |
|
|
// Interrupt Controller address space |
function in_ic; |
input [31:0] address; |
begin |
in_ic = address [31:16] == AMBER_IC_BASE; |
end |
endfunction |
|
|
// Timer Module address space |
function in_tm; |
input [31:0] address; |
begin |
in_tm = address [31:16] == AMBER_TM_BASE; |
end |
endfunction |
|
|
// Test module |
function in_test; |
input [31:0] address; |
begin |
in_test = address [31:16] == TEST_BASE; |
end |
endfunction |
|
|
// Ethernet MAC |
function in_ethmac; |
input [31:0] address; |
begin |
in_ethmac = address [31:16] == ETHMAC_BASE; |
end |
endfunction |
|
|
// Used in fetch.v and l2cache.v to allow accesses to these addresses |
// to be cached |
function in_cachable_mem; |
input [31:0] address; |
begin |
in_cachable_mem = in_loboot_mem ( address ) || |
in_main_mem ( address ) ; |
end |
endfunction |
|
/tb/global_defines.v
File deleted
/tb/debug_functions.v
File deleted
/tb/global_timescale.vh
0,0 → 1,159
`timescale 1 ps / 1 ps |
/tb/eth_test.v
39,9 → 39,8
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
`timescale 1 ps / 1 ps |
`include "global_timescale.vh" |
|
|
module eth_test |
( |
// MD interface - serial configuration of PHY |
60,8 → 59,8
input mrxdv_i |
); |
|
`include "debug_functions.v" |
`include "system_functions.v" |
`include "debug_functions.vh" |
`include "system_functions.vh" |
|
// mxt state machine |
localparam IDLE = 4'd0; |
/tb/tb_uart.v
38,9 → 38,9
// // |
////////////////////////////////////////////////////////////////// |
|
`timescale 1 ps / 1 ps |
`include "system_config_defines.v" |
`include "global_defines.v" |
`include "global_timescale.vh" |
`include "system_config_defines.vh" |
`include "global_defines.vh" |
|
|
module tb_uart ( |
/tb/dumpvcd.v
40,8 → 40,7
// // |
////////////////////////////////////////////////////////////////// |
|
`timescale 1 ns / 1 ps |
`include "global_defines.v" |
`include "global_defines.vh" |
|
module dumpvcd(); |
|
/tb/tb.v
38,17 → 38,16
// // |
////////////////////////////////////////////////////////////////// |
|
`timescale 1 ps / 1 ps |
`include "global_timescale.vh" |
`include "system_config_defines.vh" |
`include "global_defines.vh" |
|
`include "system_config_defines.v" |
`include "global_defines.v" |
|
|
module tb(); |
|
`include "debug_functions.v" |
`include "system_functions.v" |
`include "memory_configuration.v" |
`include "debug_functions.vh" |
`include "system_functions.vh" |
`include "memory_configuration.vh" |
|
reg sysrst; |
`ifdef XILINX_VIRTEX6_FPGA |
114,6 → 113,7
wire [3:0] eth_mrxd; |
wire eth_mrxdv; |
|
reg [7*8-1:0] core_str; |
|
|
// ====================================== |
313,6 → 313,7
begin |
`TB_ERROR_MESSAGE |
$display("ERROR: Can't open input file %s", `BOOT_MEM_FILE); |
$finish; |
end |
|
if (boot_mem_file != 0) |
363,8 → 364,13
`endif |
|
// Grab the test name from memory |
timeout = `AMBER_TIMEOUT ; |
$display("log file %s, timeout %0d, test name %0s ", `AMBER_LOG_FILE, timeout, `AMBER_TEST_NAME ); |
timeout = `AMBER_TIMEOUT ; |
`ifdef AMBER_A25_CORE |
core_str = "amber25"; |
`else |
core_str = "amber23"; |
`endif |
$display("Core %s, log file %s, timeout %0d, test name %0s ", core_str, `AMBER_LOG_FILE, timeout, `AMBER_TEST_NAME ); |
log_file = $fopen(`AMBER_LOG_FILE, "a"); |
end |
|
470,11 → 476,11
// Terminate Test |
// ====================================== |
`ifdef AMBER_A25_CORE |
`include "a25_localparams.v" |
`include "a25_functions.v" |
`include "a25_localparams.vh" |
`include "a25_functions.vh" |
`else |
`include "a23_localparams.v" |
`include "a23_functions.v" |
`include "a23_localparams.vh" |
`include "a23_functions.vh" |
`endif |
|
reg testfail; |
/tb/global_defines.vh
0,0 → 1,93
////////////////////////////////////////////////////////////////// |
// // |
// Global testbench defines // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Contains a set of defines for each module so if the module // |
// hierarchy changes, hierarchical references to signals // |
// will still work as long as this file is updated. // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
|
// --------------------------------------------------------------- |
// Module hierarchy defines |
// --------------------------------------------------------------- |
`ifndef _GLOBAL_DEFINES |
`define _GLOBAL_DEFINES |
|
`ifndef AMBER_TIMEOUT |
`define AMBER_TIMEOUT 0 |
`endif |
|
`define U_TB tb |
`define U_SYSTEM `U_TB.u_system |
|
`define U_AMBER `U_SYSTEM.u_amber |
`define U_FETCH `U_AMBER.u_fetch |
`define U_MMU `U_FETCH.u_mmu |
`define U_CACHE `U_FETCH.u_cache |
`define U_COPRO15 `U_AMBER.u_coprocessor |
`define U_EXECUTE `U_AMBER.u_execute |
`define U_WB `U_AMBER.u_write_back |
`define U_REGISTER_BANK `U_EXECUTE.u_register_bank |
`define U_DECODE `U_AMBER.u_decode |
`define U_DECOMPILE `U_DECODE.u_decompile |
`define U_L2CACHE `U_SYSTEM.u_l2cache |
`define U_TEST_MODULE `U_SYSTEM.u_test_module |
|
`ifdef AMBER_A25_CORE |
`define U_MEM `U_AMBER.u_mem |
`define U_DCACHE `U_MEM.u_dcache |
`define U_WISHBONE `U_AMBER.u_wishbone |
`define U_BOOT_MEM `U_SYSTEM.boot_mem128.u_boot_mem |
`else |
`define U_WISHBONE `U_FETCH.u_wishbone |
`define U_BOOT_MEM `U_SYSTEM.boot_mem32.u_boot_mem |
`endif |
// --------------------------------------------------------------- |
|
`define TB_DEBUG_MESSAGE $display("\nDEBUG in %m @ tick %8d ", `U_TB.clk_count ); |
`define TB_WARNING_MESSAGE $display("\nWARNING in %m @ tick %8d", `U_TB.clk_count ); |
`define TB_ERROR_MESSAGE $display("\nFATAL ERROR in %m @ tick %8d", `U_TB.clk_count ); force `U_TB.testfail = 1'd1; |
|
|
`ifdef XILINX_FPGA |
// Full DDR3 memory Model |
`define U_RAM tb.u_ddr3_model_c3.memory |
`else |
// Simplified Main Memory Model |
`define U_RAM tb.u_system.u_main_mem.ram |
`endif |
|
`endif |
/tb/debug_functions.vh
0,0 → 1,228
////////////////////////////////////////////////////////////////// |
// // |
// Debug Functions // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// A bunch of non-synthesizable testbench functions // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
|
// Testbench Functions used in more than one module |
|
|
function [31:0] hex_chars_to_32bits; |
input [8*8-1:0] hex_chars; |
begin |
hex_chars_to_32bits[31:28] = hex_chars_to_4bits (hex_chars[8*8-1:7*8]); |
hex_chars_to_32bits[27:24] = hex_chars_to_4bits (hex_chars[7*8-1:6*8]); |
hex_chars_to_32bits[23:20] = hex_chars_to_4bits (hex_chars[6*8-1:5*8]); |
hex_chars_to_32bits[19:16] = hex_chars_to_4bits (hex_chars[5*8-1:4*8]); |
hex_chars_to_32bits[15:12] = hex_chars_to_4bits (hex_chars[4*8-1:3*8]); |
hex_chars_to_32bits[11: 8] = hex_chars_to_4bits (hex_chars[3*8-1:2*8]); |
hex_chars_to_32bits[ 7: 4] = hex_chars_to_4bits (hex_chars[2*8-1:1*8]); |
hex_chars_to_32bits[ 3: 0] = hex_chars_to_4bits (hex_chars[1*8-1: 0]); |
end |
endfunction |
|
|
function [7:0] hex_chars_to_8bits; |
input [8*2-1:0] hex_chars; |
begin |
hex_chars_to_8bits[ 7: 4] = hex_chars_to_4bits (hex_chars[2*8-1:1*8]); |
hex_chars_to_8bits[ 3: 0] = hex_chars_to_4bits (hex_chars[1*8-1: 0]); |
end |
endfunction |
|
|
function [3:0] hex_chars_to_4bits; |
input [7:0] hex_chars; |
begin |
case (hex_chars) |
"0" : hex_chars_to_4bits = 4'h0; |
"1" : hex_chars_to_4bits = 4'h1; |
"2" : hex_chars_to_4bits = 4'h2; |
"3" : hex_chars_to_4bits = 4'h3; |
"4" : hex_chars_to_4bits = 4'h4; |
"5" : hex_chars_to_4bits = 4'h5; |
"6" : hex_chars_to_4bits = 4'h6; |
"7" : hex_chars_to_4bits = 4'h7; |
"8" : hex_chars_to_4bits = 4'h8; |
"9" : hex_chars_to_4bits = 4'h9; |
"a" : hex_chars_to_4bits = 4'ha; |
"b" : hex_chars_to_4bits = 4'hb; |
"c" : hex_chars_to_4bits = 4'hc; |
"d" : hex_chars_to_4bits = 4'hd; |
"e" : hex_chars_to_4bits = 4'he; |
"f" : hex_chars_to_4bits = 4'hf; |
"A" : hex_chars_to_4bits = 4'ha; |
"B" : hex_chars_to_4bits = 4'hb; |
"C" : hex_chars_to_4bits = 4'hc; |
"D" : hex_chars_to_4bits = 4'hd; |
"E" : hex_chars_to_4bits = 4'he; |
"F" : hex_chars_to_4bits = 4'hf; |
endcase |
end |
endfunction |
|
|
function [120*8-1:0] align_line; |
input [120*8-1:0] line; |
begin |
case (1'd1) |
line[1 *8-1: 0] == 8'd0 : align_line = 960'd0; |
line[2 *8-1:1 *8] == 8'd0 : align_line = {line[1 *8-1: 0], 952'd0}; |
line[3 *8-1:2 *8] == 8'd0 : align_line = {line[2 *8-1: 0], 944'd0}; |
line[4 *8-1:3 *8] == 8'd0 : align_line = {line[3 *8-1: 0], 936'd0}; |
line[5 *8-1:4 *8] == 8'd0 : align_line = {line[4 *8-1: 0], 928'd0}; |
line[6 *8-1:5 *8] == 8'd0 : align_line = {line[5 *8-1: 0], 920'd0}; |
line[7 *8-1:6 *8] == 8'd0 : align_line = {line[6 *8-1: 0], 912'd0}; |
line[8 *8-1:7 *8] == 8'd0 : align_line = {line[7 *8-1: 0], 904'd0}; |
line[9 *8-1:8 *8] == 8'd0 : align_line = {line[8 *8-1: 0], 896'd0}; |
line[10 *8-1:9 *8] == 8'd0 : align_line = {line[9 *8-1: 0], 888'd0}; |
line[11 *8-1:10 *8] == 8'd0 : align_line = {line[10 *8-1: 0], 880'd0}; |
line[12 *8-1:11 *8] == 8'd0 : align_line = {line[11 *8-1: 0], 872'd0}; |
line[13 *8-1:12 *8] == 8'd0 : align_line = {line[12 *8-1: 0], 864'd0}; |
line[14 *8-1:13 *8] == 8'd0 : align_line = {line[13 *8-1: 0], 856'd0}; |
line[15 *8-1:14 *8] == 8'd0 : align_line = {line[14 *8-1: 0], 848'd0}; |
line[16 *8-1:15 *8] == 8'd0 : align_line = {line[15 *8-1: 0], 840'd0}; |
line[17 *8-1:16 *8] == 8'd0 : align_line = {line[16 *8-1: 0], 832'd0}; |
line[18 *8-1:17 *8] == 8'd0 : align_line = {line[17 *8-1: 0], 824'd0}; |
line[19 *8-1:18 *8] == 8'd0 : align_line = {line[18 *8-1: 0], 816'd0}; |
line[20 *8-1:19 *8] == 8'd0 : align_line = {line[19 *8-1: 0], 808'd0}; |
line[21 *8-1:20 *8] == 8'd0 : align_line = {line[20 *8-1: 0], 800'd0}; |
line[22 *8-1:21 *8] == 8'd0 : align_line = {line[21 *8-1: 0], 792'd0}; |
line[23 *8-1:22 *8] == 8'd0 : align_line = {line[22 *8-1: 0], 784'd0}; |
line[24 *8-1:23 *8] == 8'd0 : align_line = {line[23 *8-1: 0], 776'd0}; |
line[25 *8-1:24 *8] == 8'd0 : align_line = {line[24 *8-1: 0], 768'd0}; |
line[26 *8-1:25 *8] == 8'd0 : align_line = {line[25 *8-1: 0], 760'd0}; |
line[27 *8-1:26 *8] == 8'd0 : align_line = {line[26 *8-1: 0], 752'd0}; |
line[28 *8-1:27 *8] == 8'd0 : align_line = {line[27 *8-1: 0], 744'd0}; |
line[29 *8-1:28 *8] == 8'd0 : align_line = {line[28 *8-1: 0], 736'd0}; |
line[30 *8-1:29 *8] == 8'd0 : align_line = {line[29 *8-1: 0], 728'd0}; |
line[31 *8-1:30 *8] == 8'd0 : align_line = {line[30 *8-1: 0], 720'd0}; |
line[32 *8-1:31 *8] == 8'd0 : align_line = {line[31 *8-1: 0], 712'd0}; |
line[33 *8-1:32 *8] == 8'd0 : align_line = {line[32 *8-1: 0], 704'd0}; |
line[34 *8-1:33 *8] == 8'd0 : align_line = {line[33 *8-1: 0], 696'd0}; |
line[35 *8-1:34 *8] == 8'd0 : align_line = {line[34 *8-1: 0], 688'd0}; |
line[36 *8-1:35 *8] == 8'd0 : align_line = {line[35 *8-1: 0], 680'd0}; |
line[37 *8-1:36 *8] == 8'd0 : align_line = {line[36 *8-1: 0], 672'd0}; |
line[38 *8-1:37 *8] == 8'd0 : align_line = {line[37 *8-1: 0], 664'd0}; |
line[39 *8-1:38 *8] == 8'd0 : align_line = {line[38 *8-1: 0], 656'd0}; |
line[40 *8-1:39 *8] == 8'd0 : align_line = {line[39 *8-1: 0], 648'd0}; |
line[41 *8-1:40 *8] == 8'd0 : align_line = {line[40 *8-1: 0], 640'd0}; |
line[42 *8-1:41 *8] == 8'd0 : align_line = {line[41 *8-1: 0], 632'd0}; |
line[43 *8-1:42 *8] == 8'd0 : align_line = {line[42 *8-1: 0], 624'd0}; |
line[44 *8-1:43 *8] == 8'd0 : align_line = {line[43 *8-1: 0], 616'd0}; |
line[45 *8-1:44 *8] == 8'd0 : align_line = {line[44 *8-1: 0], 608'd0}; |
line[46 *8-1:45 *8] == 8'd0 : align_line = {line[45 *8-1: 0], 600'd0}; |
line[47 *8-1:46 *8] == 8'd0 : align_line = {line[46 *8-1: 0], 592'd0}; |
line[48 *8-1:47 *8] == 8'd0 : align_line = {line[47 *8-1: 0], 584'd0}; |
line[49 *8-1:48 *8] == 8'd0 : align_line = {line[48 *8-1: 0], 576'd0}; |
line[50 *8-1:49 *8] == 8'd0 : align_line = {line[49 *8-1: 0], 568'd0}; |
line[51 *8-1:50 *8] == 8'd0 : align_line = {line[50 *8-1: 0], 560'd0}; |
line[52 *8-1:51 *8] == 8'd0 : align_line = {line[51 *8-1: 0], 552'd0}; |
line[53 *8-1:52 *8] == 8'd0 : align_line = {line[52 *8-1: 0], 544'd0}; |
line[54 *8-1:53 *8] == 8'd0 : align_line = {line[53 *8-1: 0], 536'd0}; |
line[55 *8-1:54 *8] == 8'd0 : align_line = {line[54 *8-1: 0], 528'd0}; |
line[56 *8-1:55 *8] == 8'd0 : align_line = {line[55 *8-1: 0], 520'd0}; |
line[57 *8-1:56 *8] == 8'd0 : align_line = {line[56 *8-1: 0], 512'd0}; |
line[58 *8-1:57 *8] == 8'd0 : align_line = {line[57 *8-1: 0], 504'd0}; |
line[59 *8-1:58 *8] == 8'd0 : align_line = {line[58 *8-1: 0], 496'd0}; |
line[60 *8-1:59 *8] == 8'd0 : align_line = {line[59 *8-1: 0], 488'd0}; |
line[61 *8-1:60 *8] == 8'd0 : align_line = {line[60 *8-1: 0], 480'd0}; |
line[62 *8-1:61 *8] == 8'd0 : align_line = {line[61 *8-1: 0], 472'd0}; |
line[63 *8-1:62 *8] == 8'd0 : align_line = {line[62 *8-1: 0], 464'd0}; |
line[64 *8-1:63 *8] == 8'd0 : align_line = {line[63 *8-1: 0], 456'd0}; |
line[65 *8-1:64 *8] == 8'd0 : align_line = {line[64 *8-1: 0], 448'd0}; |
line[66 *8-1:65 *8] == 8'd0 : align_line = {line[65 *8-1: 0], 440'd0}; |
line[67 *8-1:66 *8] == 8'd0 : align_line = {line[66 *8-1: 0], 432'd0}; |
line[68 *8-1:67 *8] == 8'd0 : align_line = {line[67 *8-1: 0], 424'd0}; |
line[69 *8-1:68 *8] == 8'd0 : align_line = {line[68 *8-1: 0], 416'd0}; |
line[70 *8-1:69 *8] == 8'd0 : align_line = {line[69 *8-1: 0], 408'd0}; |
line[71 *8-1:70 *8] == 8'd0 : align_line = {line[70 *8-1: 0], 400'd0}; |
line[72 *8-1:71 *8] == 8'd0 : align_line = {line[71 *8-1: 0], 392'd0}; |
line[73 *8-1:72 *8] == 8'd0 : align_line = {line[72 *8-1: 0], 384'd0}; |
line[74 *8-1:73 *8] == 8'd0 : align_line = {line[73 *8-1: 0], 376'd0}; |
line[75 *8-1:74 *8] == 8'd0 : align_line = {line[74 *8-1: 0], 368'd0}; |
line[76 *8-1:75 *8] == 8'd0 : align_line = {line[75 *8-1: 0], 360'd0}; |
line[77 *8-1:76 *8] == 8'd0 : align_line = {line[76 *8-1: 0], 352'd0}; |
line[78 *8-1:77 *8] == 8'd0 : align_line = {line[77 *8-1: 0], 344'd0}; |
line[79 *8-1:78 *8] == 8'd0 : align_line = {line[78 *8-1: 0], 336'd0}; |
line[80 *8-1:79 *8] == 8'd0 : align_line = {line[79 *8-1: 0], 328'd0}; |
line[81 *8-1:80 *8] == 8'd0 : align_line = {line[80 *8-1: 0], 320'd0}; |
line[82 *8-1:81 *8] == 8'd0 : align_line = {line[81 *8-1: 0], 312'd0}; |
line[83 *8-1:82 *8] == 8'd0 : align_line = {line[82 *8-1: 0], 304'd0}; |
line[84 *8-1:83 *8] == 8'd0 : align_line = {line[83 *8-1: 0], 296'd0}; |
line[85 *8-1:84 *8] == 8'd0 : align_line = {line[84 *8-1: 0], 288'd0}; |
line[86 *8-1:85 *8] == 8'd0 : align_line = {line[85 *8-1: 0], 280'd0}; |
line[87 *8-1:86 *8] == 8'd0 : align_line = {line[86 *8-1: 0], 272'd0}; |
line[88 *8-1:87 *8] == 8'd0 : align_line = {line[87 *8-1: 0], 264'd0}; |
line[89 *8-1:88 *8] == 8'd0 : align_line = {line[88 *8-1: 0], 256'd0}; |
line[90 *8-1:89 *8] == 8'd0 : align_line = {line[89 *8-1: 0], 248'd0}; |
line[91 *8-1:90 *8] == 8'd0 : align_line = {line[90 *8-1: 0], 240'd0}; |
line[92 *8-1:91 *8] == 8'd0 : align_line = {line[91 *8-1: 0], 232'd0}; |
line[93 *8-1:92 *8] == 8'd0 : align_line = {line[92 *8-1: 0], 224'd0}; |
line[94 *8-1:93 *8] == 8'd0 : align_line = {line[93 *8-1: 0], 216'd0}; |
line[95 *8-1:94 *8] == 8'd0 : align_line = {line[94 *8-1: 0], 208'd0}; |
line[96 *8-1:95 *8] == 8'd0 : align_line = {line[95 *8-1: 0], 200'd0}; |
line[97 *8-1:96 *8] == 8'd0 : align_line = {line[96 *8-1: 0], 192'd0}; |
line[98 *8-1:97 *8] == 8'd0 : align_line = {line[97 *8-1: 0], 184'd0}; |
line[99 *8-1:98 *8] == 8'd0 : align_line = {line[98 *8-1: 0], 176'd0}; |
line[100*8-1:99 *8] == 8'd0 : align_line = {line[99 *8-1: 0], 168'd0}; |
line[101*8-1:100*8] == 8'd0 : align_line = {line[100*8-1: 0], 160'd0}; |
line[102*8-1:101*8] == 8'd0 : align_line = {line[101*8-1: 0], 152'd0}; |
line[103*8-1:102*8] == 8'd0 : align_line = {line[102*8-1: 0], 144'd0}; |
line[104*8-1:103*8] == 8'd0 : align_line = {line[103*8-1: 0], 136'd0}; |
line[105*8-1:104*8] == 8'd0 : align_line = {line[104*8-1: 0], 128'd0}; |
line[106*8-1:105*8] == 8'd0 : align_line = {line[105*8-1: 0], 120'd0}; |
line[107*8-1:106*8] == 8'd0 : align_line = {line[106*8-1: 0], 112'd0}; |
line[108*8-1:107*8] == 8'd0 : align_line = {line[107*8-1: 0], 104'd0}; |
line[109*8-1:108*8] == 8'd0 : align_line = {line[108*8-1: 0], 96'd0}; |
line[110*8-1:109*8] == 8'd0 : align_line = {line[109*8-1: 0], 88'd0}; |
line[111*8-1:110*8] == 8'd0 : align_line = {line[110*8-1: 0], 80'd0}; |
line[112*8-1:111*8] == 8'd0 : align_line = {line[111*8-1: 0], 72'd0}; |
line[113*8-1:112*8] == 8'd0 : align_line = {line[112*8-1: 0], 64'd0}; |
line[114*8-1:113*8] == 8'd0 : align_line = {line[113*8-1: 0], 56'd0}; |
line[115*8-1:114*8] == 8'd0 : align_line = {line[114*8-1: 0], 48'd0}; |
line[116*8-1:115*8] == 8'd0 : align_line = {line[115*8-1: 0], 40'd0}; |
line[117*8-1:116*8] == 8'd0 : align_line = {line[116*8-1: 0], 32'd0}; |
line[118*8-1:117*8] == 8'd0 : align_line = {line[117*8-1: 0], 24'd0}; |
line[119*8-1:118*8] == 8'd0 : align_line = {line[118*8-1: 0], 16'd0}; |
line[120*8-1:119*8] == 8'd0 : align_line = {line[119*8-1: 0], 8'd0}; |
|
default: align_line = 960'd0; |
endcase |
end |
endfunction |
|
/amber23/a23_config_defines.v
File deleted
/amber23/a23_localparams.v
File deleted
/amber23/a23_functions.v
File deleted
/amber23/a23_localparams.vh
0,0 → 1,117
////////////////////////////////////////////////////////////////// |
// // |
// Parameters file for Amber 2 Core // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Holds general parameters that are used is several core // |
// modules // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
|
|
// Instruction Types |
localparam [3:0] REGOP = 4'h0, // Data processing |
MULT = 4'h1, // Multiply |
SWAP = 4'h2, // Single Data Swap |
TRANS = 4'h3, // Single data transfer |
MTRANS = 4'h4, // Multi-word data transfer |
BRANCH = 4'h5, // Branch |
CODTRANS = 4'h6, // Co-processor data transfer |
COREGOP = 4'h7, // Co-processor data operation |
CORTRANS = 4'h8, // Co-processor register transfer |
SWI = 4'h9; // software interrupt |
|
|
// Opcodes |
localparam [3:0] AND = 4'h0, // Logical AND |
EOR = 4'h1, // Logical Exclusive OR |
SUB = 4'h2, // Subtract |
RSB = 4'h3, // Reverse Subtract |
ADD = 4'h4, // Add |
ADC = 4'h5, // Add with Carry |
SBC = 4'h6, // Subtract with Carry |
RSC = 4'h7, // Reverse Subtract with Carry |
TST = 4'h8, // Test (using AND operator) |
TEQ = 4'h9, // Test Equivalence (using EOR operator) |
CMP = 4'ha, // Compare (using Subtract operator) |
CMN = 4'hb, // Compare Negated |
ORR = 4'hc, // Logical OR |
MOV = 4'hd, // Move |
BIC = 4'he, // Bit Clear (using AND & NOT operators) |
MVN = 4'hf; // Move NOT |
|
// Condition Encoding |
localparam [3:0] EQ = 4'h0, // Equal / Z set |
NE = 4'h1, // Not equal / Z clear |
CS = 4'h2, // Carry set / C set |
CC = 4'h3, // Carry clear / C clear |
MI = 4'h4, // Minus / N set |
PL = 4'h5, // Plus / N clear |
VS = 4'h6, // Overflow / V set |
VC = 4'h7, // No overflow / V clear |
HI = 4'h8, // Unsigned higher / C set and Z clear |
LS = 4'h9, // Unsigned lower |
// or same / C clear or Z set |
GE = 4'ha, // Signed greater |
// than or equal / N == V |
LT = 4'hb, // Signed less than / N != V |
GT = 4'hc, // Signed greater |
// than / Z == 0, N == V |
LE = 4'hd, // Signed less than |
// or equal / Z == 1, N != V |
AL = 4'he, // Always |
NV = 4'hf; // Never |
|
// Any instruction with a condition field of 0b1111 is UNPREDICTABLE. |
|
// Shift Types |
localparam [1:0] LSL = 2'h0, |
LSR = 2'h1, |
ASR = 2'h2, |
RRX = 2'h3, |
ROR = 2'h3; |
|
// Modes |
localparam [1:0] SVC = 2'b11, // Supervisor |
IRQ = 2'b10, // Interrupt |
FIRQ = 2'b01, // Fast Interrupt |
USR = 2'b00; // User |
|
// One-Hot Mode encodings |
localparam [5:0] OH_USR = 0, |
OH_IRQ = 1, |
OH_FIRQ = 2, |
OH_SVC = 3; |
|
|
/amber23/a23_config_defines.vh
0,0 → 1,81
////////////////////////////////////////////////////////////////// |
// // |
// Amber Configuration and Debug for the AMber 2 Core // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Contains a set of defines used to configure and debug // |
// the Amber core // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
|
`ifndef _A23_CONFIG_DEFINES |
`define _A23_CONFIG_DEFINES |
|
// Cache Ways |
// Changing this parameter is the recommended |
// way to change the Amber cache size; 2, 3, 4 and 8 ways are supported. |
// 2 ways -> 8KB cache |
// 3 ways -> 12KB cache |
// 4 ways -> 16KB cache |
// 8 ways -> 32KB cache |
`define A23_CACHE_WAYS 4 |
|
// Use ram-based register bank implementation |
// `define A23_RAM_REGISTER_BANK |
|
// -------------------------------------------------------------------- |
// Debug switches |
// -------------------------------------------------------------------- |
|
// Enable the decompiler. The default output file is amber.dis |
`define A23_DECOMPILE |
|
// Co-processor 15 debug. Registers in here control the cache |
//`define A23_COPRO15_DEBUG |
|
// Cache debug |
//`define A23_CACHE_DEBUG |
|
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// File Names |
// -------------------------------------------------------------------- |
`ifndef A23_DECOMPILE_FILE |
`define A23_DECOMPILE_FILE "amber.dis" |
`endif |
|
`endif |
|
/amber23/makefile.inc
0,0 → 1,17
INCDIR += +$(IPVLOG)/amber23 |
SRC += $(IPVLOG)/amber23/a23_alu.v |
SRC += $(IPVLOG)/amber23/a23_barrel_shift.v |
SRC += $(IPVLOG)/amber23/a23_cache.v |
SRC += $(IPVLOG)/amber23/a23_coprocessor.v |
SRC += $(IPVLOG)/amber23/a23_core.v |
SRC += $(IPVLOG)/amber23/a23_decode.v |
SRC += $(IPVLOG)/amber23/a23_decompile.v |
SRC += $(IPVLOG)/amber23/a23_execute.v |
SRC += $(IPVLOG)/amber23/a23_fetch.v |
SRC += $(IPVLOG)/amber23/a23_multiply.v |
SRC += $(IPVLOG)/amber23/a23_register_bank.v |
SRC += $(IPVLOG)/amber23/a23_wishbone.v |
|
DEP += $(IPVLOG)/amber23/a23_config_defines.vh |
DEP += $(IPVLOG)/amber23/a23_functions.vh |
DEP += $(IPVLOG)/amber23/a23_localparams.vh |
/amber23/a23_ram_register_bank.v
74,8 → 74,8
|
); |
|
`include "a23_localparams.v" |
`include "a23_functions.v" |
`include "a23_localparams.vh" |
`include "a23_functions.vh" |
|
wire [1:0] mode_idec; |
wire [1:0] mode_exec; |
/amber23/a23_register_bank.v
76,8 → 76,8
|
); |
|
`include "a23_localparams.v" |
`include "a23_functions.v" |
`include "a23_localparams.vh" |
`include "a23_functions.vh" |
|
|
// User Mode Registers |
/amber23/a23_functions.vh
0,0 → 1,174
////////////////////////////////////////////////////////////////// |
// // |
// Functions for Amber 2 Core // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Functions used in more than one module // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
|
|
// ======================================================== |
// PC Filter - Remove the status bits |
// ======================================================== |
function [31:0] pcf; |
input [31:0] pc_reg; |
begin |
pcf = {6'd0, pc_reg[25:2], 2'd0}; |
end |
endfunction |
|
|
// ======================================================== |
// 4-bit to 16-bit 1-hot decode |
// ======================================================== |
function [14:0] decode; |
input [3:0] reg_sel; |
begin |
case ( reg_sel ) |
4'h0: decode = 15'h0001; |
4'h1: decode = 15'h0002; |
4'h2: decode = 15'h0004; |
4'h3: decode = 15'h0008; |
4'h4: decode = 15'h0010; |
4'h5: decode = 15'h0020; |
4'h6: decode = 15'h0040; |
4'h7: decode = 15'h0080; |
4'h8: decode = 15'h0100; |
4'h9: decode = 15'h0200; |
4'ha: decode = 15'h0400; |
4'hb: decode = 15'h0800; |
4'hc: decode = 15'h1000; |
4'hd: decode = 15'h2000; |
4'he: decode = 15'h4000; |
default: decode = 15'h0000; |
endcase |
end |
endfunction |
|
|
// ======================================================== |
// Convert Stats Bits Mode to one-hot encoded version |
// ======================================================== |
function [3:0] oh_status_bits_mode; |
input [1:0] fn_status_bits_mode; |
begin |
oh_status_bits_mode = |
fn_status_bits_mode == SVC ? 1'd1 << OH_SVC : |
fn_status_bits_mode == IRQ ? 1'd1 << OH_IRQ : |
fn_status_bits_mode == FIRQ ? 1'd1 << OH_FIRQ : |
1'd1 << OH_USR ; |
end |
endfunction |
|
// ======================================================== |
// Convert mode into ascii name |
// ======================================================== |
function [(14*8)-1:0] mode_name; |
input [4:0] mode; |
begin |
|
mode_name = mode == USR ? "User " : |
mode == SVC ? "Supervisor " : |
mode == IRQ ? "Interrupt " : |
mode == FIRQ ? "Fast Interrupt" : |
"UNKNOWN " ; |
end |
endfunction |
|
|
// ======================================================== |
// Conditional Execution Function |
// ======================================================== |
// EQ Z set |
// NE Z clear |
// CS C set |
// CC C clear |
// MI N set |
// PL N clear |
// VS V set |
// VC V clear |
// HI C set and Z clear |
// LS C clear or Z set |
// GE N == V |
// LT N != V |
// GT Z == 0,N == V |
// LE Z == 1 or N != V |
// AL Always (unconditional) |
// NV Never |
|
function conditional_execute; |
input [3:0] condition; |
input [3:0] flags; |
begin |
conditional_execute |
= ( condition == AL ) || |
( condition == EQ && flags[2] ) || |
( condition == NE && !flags[2] ) || |
( condition == CS && flags[1] ) || |
( condition == CC && !flags[1] ) || |
( condition == MI && flags[3] ) || |
( condition == PL && !flags[3] ) || |
( condition == VS && flags[0] ) || |
( condition == VC && !flags[0] ) || |
|
( condition == HI && flags[1] && !flags[2] ) || |
( condition == LS && (!flags[1] || flags[2]) ) || |
|
( condition == GE && flags[3] == flags[0] ) || |
( condition == LT && flags[3] != flags[0] ) || |
|
( condition == GT && !flags[2] && flags[3] == flags[0] ) || |
( condition == LE && (flags[2] || flags[3] != flags[0])) ; |
|
end |
endfunction |
|
|
// ======================================================== |
// Log 2 |
// ======================================================== |
|
function [31:0] log2; |
input [31:0] num; |
integer i; |
integer out; |
begin |
out = 32'd0; |
for (i=0; i<30; i=i+1) |
if ((2**i > num) && (out == 0)) |
out = i-1; |
log2 = out; |
end |
endfunction |
/amber23/a23_decode.v
39,7 → 39,7
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
`include "global_defines.v" |
`include "global_defines.vh" |
|
module a23_decode |
( |
130,8 → 130,8
|
); |
|
`include "a23_localparams.v" |
`include "a23_functions.v" |
`include "a23_localparams.vh" |
`include "a23_functions.vh" |
|
localparam [4:0] RST_WAIT1 = 5'd0, |
RST_WAIT2 = 5'd1, |
666,7 → 666,12
|
if ( !immediate_shifter_operand && !instruction[4] ) |
barrel_shift_amount_sel_nxt = 2'd2; // Shift immediate amount |
|
|
// regops that do not change the overflow flag |
if ( opcode == AND || opcode == EOR || opcode == TST || opcode == TEQ || |
opcode == ORR || opcode == MOV || opcode == BIC || opcode == MVN ) |
status_bits_sel_nxt = 3'd5; |
|
if ( opcode == ADD || opcode == CMN ) // CMN is just like an ADD |
begin |
alu_out_sel_nxt = 4'd1; // Add |
852,12 → 857,12
write_data_wen_nxt = 1'd1; |
|
// LDM: load into user mode registers, when in priviledged mode |
// DOnt use mtrans_r15 here because its not loaded yet |
if ( {instruction[22:20],instruction[15]} == 4'b1010 ) |
// Don't use mtrans_r15 here because its not loaded yet |
if ( {instruction[22],instruction[20],instruction[15]} == 3'b110 ) |
user_mode_regs_load_nxt = 1'd1; |
|
// SDM: store the user mode registers, when in priviledged mode |
if ( {instruction[22:20]} == 3'b100 ) |
if ( {instruction[22],instruction[20]} == 3'b10 ) |
o_user_mode_regs_store_nxt = 1'd1; |
|
// update the base register ? |
1054,11 → 1059,11
write_data_wen_nxt = 1'd1; |
|
// LDM: load into user mode registers, when in priviledged mode |
if ( {instruction[22:20],mtrans_r15} == 4'b1010 ) |
if ( {instruction[22],instruction[20],mtrans_r15} == 3'b110 ) |
user_mode_regs_load_nxt = 1'd1; |
|
// SDM: store the user mode registers, when in priviledged mode |
if ( {instruction[22:20]} == 3'b100 ) |
if ( {instruction[22],instruction[20]} == 2'b10 ) |
o_user_mode_regs_store_nxt = 1'd1; |
end |
end |
1085,11 → 1090,11
write_data_wen_nxt = 1'd1; |
|
// LDM: load into user mode registers, when in priviledged mode |
if ( {instruction[22:20],mtrans_r15} == 4'b1010 ) |
if ( {instruction[22],instruction[20],mtrans_r15} == 3'b110 ) |
user_mode_regs_load_nxt = 1'd1; |
|
// SDM: store the user mode registers, when in priviledged mode |
if ( {instruction[22:20]} == 3'b100 ) |
if ( {instruction[22],instruction[20]} == 2'b10 ) |
o_user_mode_regs_store_nxt = 1'd1; |
end |
|
1107,11 → 1112,12
reg_bank_wsel_nxt = mtrans_reg_d2; |
|
// LDM: load into user mode registers, when in priviledged mode |
if ( {instruction[22:20],mtrans_r15} == 4'b1010 ) |
if ( {instruction[22],instruction[20],mtrans_r15} == 3'b110 ) |
user_mode_regs_load_nxt = 1'd1; |
|
// SDM: store the user mode registers, when in priviledged mode |
if ( {instruction[22:20]} == 3'b100 ) |
//if ( {instruction[22:20]} == 3'b100 ) |
if ( {instruction[22],instruction[20]} == 2'b10 ) |
o_user_mode_regs_store_nxt = 1'd1; |
end |
|
1126,11 → 1132,11
pc_wen_nxt = 1'd0; // hold current PC value |
|
// LDM: load into user mode registers, when in priviledged mode |
if ( {instruction[22:20],mtrans_r15} == 4'b1010 ) |
if ( {instruction[22],instruction[20],mtrans_r15} == 3'b110 ) |
user_mode_regs_load_nxt = 1'd1; |
|
// SDM: store the user mode registers, when in priviledged mode |
if ( {instruction[22:20]} == 3'b100 ) |
if ( {instruction[22],instruction[20]} == 2'b10 ) |
o_user_mode_regs_store_nxt = 1'd1; |
end |
|
1180,11 → 1186,11
end |
|
// LDM: load into user mode registers, when in priviledged mode |
if ( {instruction[22:20],mtrans_r15} == 4'b1010 ) |
if ( {instruction[22],instruction[20],mtrans_r15} == 3'b110 ) |
user_mode_regs_load_nxt = 1'd1; |
|
// SDM: store the user mode registers, when in priviledged mode |
if ( {instruction[22:20]} == 3'b100 ) |
if ( {instruction[22],instruction[20]} == 2'b10 ) |
o_user_mode_regs_store_nxt = 1'd1; |
end |
|
1635,7 → 1641,7
// ======================================================== |
//synopsys translate_off |
|
`include "debug_functions.v" |
`include "debug_functions.vh" |
|
a23_decompile u_decompile ( |
.i_clk ( i_clk ), |
/amber23/a23_fetch.v
77,7 → 77,7
|
); |
|
`include "memory_configuration.v" |
`include "memory_configuration.vh" |
|
wire cache_stall; |
wire wb_stall; |
/amber23/a23_barrel_shift_fpga.v
56,7 → 56,7
|
); |
|
`include "a23_localparams.v" |
`include "a23_localparams.vh" |
|
wire [31:0] rot_prod; // Input rotated by the shift amount |
|
/amber23/a23_decompile.v
39,9 → 39,11
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
`include "global_defines.v" |
`include "a23_config_defines.v" |
|
`include "global_timescale.vh" |
`include "global_defines.vh" |
`include "a23_config_defines.vh" |
|
module a23_decompile |
( |
input i_clk, |
58,7 → 60,7
|
); |
|
`include "a23_localparams.v" |
`include "a23_localparams.vh" |
|
`ifdef A23_DECOMPILE |
|
/amber23/a23_execute.v
41,7 → 41,7
// // |
////////////////////////////////////////////////////////////////// |
|
`include "a23_config_defines.v" |
`include "a23_config_defines.vh" |
|
module a23_execute ( |
|
106,7 → 106,6
input i_user_mode_regs_load, |
input i_user_mode_regs_store_nxt, |
input i_firq_not_user_mode, |
input i_firq_not_user_mode_nxt, |
|
input i_write_data_wen, |
input i_base_address_wen, // save LDM base address register, |
122,8 → 121,8
|
); |
|
`include "a23_localparams.v" |
`include "a23_functions.v" |
`include "a23_localparams.vh" |
`include "a23_functions.vh" |
|
// ======================================================== |
// Internal signals |
192,6 → 191,7
wire status_bits_mode_update; |
wire status_bits_irq_mask_update; |
wire status_bits_firq_mask_update; |
wire [1:0] status_bits_out; |
|
wire [31:0] alu_out_pc_filtered; |
wire adex_nxt; |
199,8 → 199,7
// ======================================================== |
// Status Bits in PC register |
// ======================================================== |
wire [1:0] status_bits_out; |
assign status_bits_out = (i_status_bits_mode_wen && i_status_bits_sel == 3'd1) ? |
assign status_bits_out = (i_status_bits_mode_wen && i_status_bits_sel == 3'd1 && execute) ? |
alu_out[1:0] : status_bits_mode ; |
|
|
216,10 → 215,14
assign status_bits_flags_nxt = i_status_bits_sel == 3'd0 ? alu_flags : |
i_status_bits_sel == 3'd1 ? alu_out [31:28] : |
i_status_bits_sel == 3'd3 ? i_copro_read_data[31:28] : |
// 4 = update flags after a multiply operation |
{ multiply_flags, status_bits_flags[1:0] } ; |
// update flags after a multiply operation |
i_status_bits_sel == 3'd4 ? { multiply_flags, status_bits_flags[1:0] } : |
// regops that do not change the overflow flag |
i_status_bits_sel == 3'd5 ? { alu_flags[3:1], status_bits_flags[0] } : |
4'b1111 ; |
|
assign status_bits_mode_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_mode : |
i_status_bits_sel == 3'd5 ? i_status_bits_mode : |
i_status_bits_sel == 3'd1 ? alu_out [1:0] : |
i_copro_read_data [1:0] ; |
|
240,10 → 243,12
|
|
assign status_bits_irq_mask_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_irq_mask : |
i_status_bits_sel == 3'd5 ? i_status_bits_irq_mask : |
i_status_bits_sel == 3'd1 ? alu_out [27] : |
i_copro_read_data [27] ; |
|
assign status_bits_firq_mask_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_firq_mask : |
i_status_bits_sel == 3'd5 ? i_status_bits_firq_mask : |
i_status_bits_sel == 3'd1 ? alu_out [26] : |
i_copro_read_data [26] ; |
|
263,7 → 268,7
// ======================================================== |
// An immediate shift value of 0 is translated into 32 |
assign shift_amount = i_barrel_shift_amount_sel == 2'd0 ? 8'd0 : |
i_barrel_shift_amount_sel == 2'd1 ? rs[7:0] : |
i_barrel_shift_amount_sel == 2'd1 ? rs[7:0] : |
i_barrel_shift_amount_sel == 2'd2 ? {3'd0, i_imm_shift_amount } : |
{3'd0, i_read_data_alignment } ; |
|
/amber23/a23_cache.v
42,8 → 42,8
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
`include "global_defines.v" |
`include "a23_config_defines.v" |
`include "global_defines.vh" |
`include "a23_config_defines.vh" |
|
module a23_cache |
#( |
105,8 → 105,8
input i_wb_stall // wb_stb && !wb_ack |
); |
|
`include "a23_localparams.v" |
`include "a23_functions.v" |
`include "a23_localparams.vh" |
`include "a23_functions.vh" |
|
// One-hot encoded |
localparam C_INIT = 0, |
/amber23/a23_barrel_shift.v
52,7 → 52,7
|
); |
|
`include "a23_localparams.v" |
`include "a23_localparams.vh" |
|
// MSB is carry out |
wire [32:0] lsl_out; |
/amber25/a25_config_defines.v
File deleted
/amber25/a25_localparams.v
File deleted
/amber25/a25_functions.v
File deleted
/amber25/a25_shifter.v
54,7 → 54,7
|
); |
|
`include "a25_localparams.v" |
`include "a25_localparams.vh" |
|
// MSB is carry out |
wire [32:0] lsl_out; |
/amber25/a25_localparams.vh
0,0 → 1,117
////////////////////////////////////////////////////////////////// |
// // |
// Parameters file for Amber 25 Core // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Holds general parameters that are used is several core // |
// modules // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2011 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
|
|
// Instruction Types |
localparam [3:0] REGOP = 4'h0, // Data processing |
MULT = 4'h1, // Multiply |
SWAP = 4'h2, // Single Data Swap |
TRANS = 4'h3, // Single data transfer |
MTRANS = 4'h4, // Multi-word data transfer |
BRANCH = 4'h5, // Branch |
CODTRANS = 4'h6, // Co-processor data transfer |
COREGOP = 4'h7, // Co-processor data operation |
CORTRANS = 4'h8, // Co-processor register transfer |
SWI = 4'h9; // software interrupt |
|
|
// Opcodes |
localparam [3:0] AND = 4'h0, // Logical AND |
EOR = 4'h1, // Logical Exclusive OR |
SUB = 4'h2, // Subtract |
RSB = 4'h3, // Reverse Subtract |
ADD = 4'h4, // Add |
ADC = 4'h5, // Add with Carry |
SBC = 4'h6, // Subtract with Carry |
RSC = 4'h7, // Reverse Subtract with Carry |
TST = 4'h8, // Test (using AND operator) |
TEQ = 4'h9, // Test Equivalence (using EOR operator) |
CMP = 4'ha, // Compare (using Subtract operator) |
CMN = 4'hb, // Compare Negated |
ORR = 4'hc, // Logical OR |
MOV = 4'hd, // Move |
BIC = 4'he, // Bit Clear (using AND & NOT operators) |
MVN = 4'hf; // Move NOT |
|
// Condition Encoding |
localparam [3:0] EQ = 4'h0, // Equal / Z set |
NE = 4'h1, // Not equal / Z clear |
CS = 4'h2, // Carry set / C set |
CC = 4'h3, // Carry clear / C clear |
MI = 4'h4, // Minus / N set |
PL = 4'h5, // Plus / N clear |
VS = 4'h6, // Overflow / V set |
VC = 4'h7, // No overflow / V clear |
HI = 4'h8, // Unsigned higher / C set and Z clear |
LS = 4'h9, // Unsigned lower |
// or same / C clear or Z set |
GE = 4'ha, // Signed greater |
// than or equal / N == V |
LT = 4'hb, // Signed less than / N != V |
GT = 4'hc, // Signed greater |
// than / Z == 0, N == V |
LE = 4'hd, // Signed less than |
// or equal / Z == 1, N != V |
AL = 4'he, // Always |
NV = 4'hf; // Never |
|
// Any instruction with a condition field of 0b1111 is UNPREDICTABLE. |
|
// Shift Types |
localparam [1:0] LSL = 2'h0, |
LSR = 2'h1, |
ASR = 2'h2, |
RRX = 2'h3, |
ROR = 2'h3; |
|
// Modes |
localparam [1:0] SVC = 2'b11, // Supervisor |
IRQ = 2'b10, // Interrupt |
FIRQ = 2'b01, // Fast Interrupt |
USR = 2'b00; // User |
|
// One-Hot Mode encodings |
localparam [5:0] OH_USR = 0, |
OH_IRQ = 1, |
OH_FIRQ = 2, |
OH_SVC = 3; |
|
|
/amber25/a25_dcache.v
42,8 → 42,8
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
`include "global_defines.v" |
`include "a25_config_defines.v" |
`include "global_defines.vh" |
`include "a25_config_defines.vh" |
|
module a25_dcache |
#( |
105,8 → 105,8
input i_wb_cached_ready // wb_stb && !wb_ack |
); |
|
`include "a25_localparams.v" |
`include "a25_functions.v" |
`include "a25_localparams.vh" |
`include "a25_functions.vh" |
|
// One-hot encoded |
localparam C_INIT = 0, |
/amber25/makefile.inc
0,0 → 1,21
INCDIR += +$(IPVLOG)/amber25 |
SRC += $(IPVLOG)/amber25/a25_alu.v |
SRC += $(IPVLOG)/amber25/a25_barrel_shift.v |
SRC += $(IPVLOG)/amber25/a25_coprocessor.v |
SRC += $(IPVLOG)/amber25/a25_core.v |
SRC += $(IPVLOG)/amber25/a25_dcache.v |
SRC += $(IPVLOG)/amber25/a25_decode.v |
SRC += $(IPVLOG)/amber25/a25_decompile.v |
SRC += $(IPVLOG)/amber25/a25_execute.v |
SRC += $(IPVLOG)/amber25/a25_fetch.v |
SRC += $(IPVLOG)/amber25/a25_icache.v |
SRC += $(IPVLOG)/amber25/a25_mem.v |
SRC += $(IPVLOG)/amber25/a25_multiply.v |
SRC += $(IPVLOG)/amber25/a25_register_bank.v |
SRC += $(IPVLOG)/amber25/a25_shifter.v |
SRC += $(IPVLOG)/amber25/a25_wishbone_buf.v |
SRC += $(IPVLOG)/amber25/a25_wishbone.v |
SRC += $(IPVLOG)/amber25/a25_write_back.v |
DEP += $(IPVLOG)/amber25/a25_config_defines.vh |
DEP += $(IPVLOG)/amber25/a25_functions.vh |
DEP += $(IPVLOG)/amber25/a25_localparams.vh |
/amber25/a25_config_defines.vh
0,0 → 1,84
////////////////////////////////////////////////////////////////// |
// // |
// Amber Configuration and Debug for the Amber 25 Core // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Contains a set of defines used to configure and debug // |
// the Amber core // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2011 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
|
`ifndef _A25_CONFIG_DEFINES |
`define _A25_CONFIG_DEFINES |
|
// Cache Ways |
// Changing this parameter is the recommended |
// way to change the Amber cache size; 2, 3, 4 and 8 ways are supported. |
// |
// 2 ways -> 8KB cache |
// 3 ways -> 12KB cache |
// 4 ways -> 16KB cache |
// 8 ways -> 32KB cache |
// |
// e.g. if both caches have 8 ways, the total is 32KB icache + 32KB dcache = 64KB |
|
`define A25_ICACHE_WAYS 4 |
`define A25_DCACHE_WAYS 4 |
|
|
// -------------------------------------------------------------------- |
// Debug switches |
// -------------------------------------------------------------------- |
|
// Enable the decompiler. The default output file is amber.dis |
`define A25_DECOMPILE |
|
// Co-processor 15 debug. Registers in here control the cache |
//`define A25_COPRO15_DEBUG |
|
// Cache debug |
//`define A25_CACHE_DEBUG |
|
// -------------------------------------------------------------------- |
|
|
// -------------------------------------------------------------------- |
// File Names |
// -------------------------------------------------------------------- |
`ifndef A25_DECOMPILE_FILE |
`define A25_DECOMPILE_FILE "amber.dis" |
`endif |
|
`endif |
|
/amber25/a25_icache.v
40,8 → 40,8
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
`include "global_defines.v" |
`include "a25_config_defines.v" |
`include "global_defines.vh" |
`include "a25_config_defines.vh" |
|
module a25_icache |
#( |
98,8 → 98,8
input i_wb_ready |
); |
|
`include "a25_localparams.v" |
`include "a25_functions.v" |
`include "a25_localparams.vh" |
`include "a25_functions.vh" |
|
// One-hot encoded |
localparam C_INIT = 0, |
/amber25/a25_mem.v
78,7 → 78,7
input i_wb_uncached_ready // wishbone access complete and read data valid |
); |
|
`include "memory_configuration.v" |
`include "memory_configuration.vh" |
|
wire [31:0] cache_read_data; |
wire address_cachable; |
/amber25/a25_register_bank.v
81,8 → 81,8
|
); |
|
`include "a25_localparams.v" |
`include "a25_functions.v" |
`include "a25_localparams.vh" |
`include "a25_functions.vh" |
|
|
// User Mode Registers |
/amber25/a25_functions.vh
0,0 → 1,208
////////////////////////////////////////////////////////////////// |
// // |
// Functions for Amber 25 Core // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Functions used in more than one module // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2011 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
|
|
// ======================================================== |
// Instruction type decode |
// ======================================================== |
function [3:0] instruction_type; |
input [31:0] instruction; |
begin |
// Instruction Decode - Order is important! |
casez ({instruction[27:20], instruction[7:4]}) |
12'b00010?001001 : instruction_type = SWAP; |
12'b000000??1001 : instruction_type = MULT; |
12'b00?????????? : instruction_type = REGOP; |
12'b01?????????? : instruction_type = TRANS; |
12'b100????????? : instruction_type = MTRANS; |
12'b101????????? : instruction_type = BRANCH; |
12'b110????????? : instruction_type = CODTRANS; |
12'b1110???????0 : instruction_type = COREGOP; |
12'b1110???????1 : instruction_type = CORTRANS; |
default: instruction_type = SWI; |
endcase |
end |
endfunction |
|
|
// ======================================================== |
// Select 32 bits from a 128 bit bus based on a 2-bit address |
// ======================================================== |
function [31:0] sel32_128; |
input [1:0] select; |
input [127:0] bus; |
begin |
sel32_128 = select==2'd0 ? bus[31:0] : select==2'd1 ? bus[63:32] : select==2'd2 ? bus[95:64] : bus[127:96]; |
end |
endfunction |
|
|
// ======================================================== |
// PC Filter - Remove the status bits |
// ======================================================== |
function [31:0] pcf; |
input [31:0] pc_reg; |
begin |
pcf = {6'd0, pc_reg[25:2], 2'd0}; |
end |
endfunction |
|
|
// ======================================================== |
// 4-bit to 16-bit 1-hot decode |
// ======================================================== |
function [14:0] decode; |
input [3:0] reg_sel; |
begin |
case ( reg_sel ) |
4'h0: decode = 15'h0001; |
4'h1: decode = 15'h0002; |
4'h2: decode = 15'h0004; |
4'h3: decode = 15'h0008; |
4'h4: decode = 15'h0010; |
4'h5: decode = 15'h0020; |
4'h6: decode = 15'h0040; |
4'h7: decode = 15'h0080; |
4'h8: decode = 15'h0100; |
4'h9: decode = 15'h0200; |
4'ha: decode = 15'h0400; |
4'hb: decode = 15'h0800; |
4'hc: decode = 15'h1000; |
4'hd: decode = 15'h2000; |
4'he: decode = 15'h4000; |
default: decode = 15'h0000; |
endcase |
end |
endfunction |
|
|
// ======================================================== |
// Convert Stats Bits Mode to one-hot encoded version |
// ======================================================== |
function [3:0] oh_status_bits_mode; |
input [1:0] fn_status_bits_mode; |
begin |
oh_status_bits_mode = |
fn_status_bits_mode == SVC ? 1'd1 << OH_SVC : |
fn_status_bits_mode == IRQ ? 1'd1 << OH_IRQ : |
fn_status_bits_mode == FIRQ ? 1'd1 << OH_FIRQ : |
1'd1 << OH_USR ; |
end |
endfunction |
|
// ======================================================== |
// Convert mode into ascii name |
// ======================================================== |
function [(14*8)-1:0] mode_name; |
input [4:0] mode; |
begin |
|
mode_name = mode == USR ? "User " : |
mode == SVC ? "Supervisor " : |
mode == IRQ ? "Interrupt " : |
mode == FIRQ ? "Fast Interrupt" : |
"UNKNOWN " ; |
end |
endfunction |
|
|
// ======================================================== |
// Conditional Execution Function |
// ======================================================== |
// EQ Z set |
// NE Z clear |
// CS C set |
// CC C clear |
// MI N set |
// PL N clear |
// VS V set |
// VC V clear |
// HI C set and Z clear |
// LS C clear or Z set |
// GE N == V |
// LT N != V |
// GT Z == 0,N == V |
// LE Z == 1 or N != V |
// AL Always (unconditional) |
// NV Never |
|
function conditional_execute; |
input [3:0] condition; |
input [3:0] flags; |
begin |
conditional_execute |
= ( condition == AL ) || |
( condition == EQ && flags[2] ) || |
( condition == NE && !flags[2] ) || |
( condition == CS && flags[1] ) || |
( condition == CC && !flags[1] ) || |
( condition == MI && flags[3] ) || |
( condition == PL && !flags[3] ) || |
( condition == VS && flags[0] ) || |
( condition == VC && !flags[0] ) || |
|
( condition == HI && flags[1] && !flags[2] ) || |
( condition == LS && (!flags[1] || flags[2]) ) || |
|
( condition == GE && flags[3] == flags[0] ) || |
( condition == LT && flags[3] != flags[0] ) || |
|
( condition == GT && !flags[2] && flags[3] == flags[0] ) || |
( condition == LE && (flags[2] || flags[3] != flags[0])) ; |
|
end |
endfunction |
|
|
// ======================================================== |
// Log 2 |
// ======================================================== |
|
function [31:0] log2; |
input [31:0] num; |
integer i; |
|
begin |
log2 = 32'd0; |
for (i=0; i<30; i=i+1) |
if ((2**i > num) && (log2 == 0)) |
log2 = i-1; |
end |
endfunction |
/amber25/a25_decode.v
39,7 → 39,7
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
`include "global_defines.v" |
`include "global_defines.vh" |
|
module a25_decode |
( |
131,8 → 131,8
|
); |
|
`include "a25_localparams.v" |
`include "a25_functions.v" |
`include "a25_localparams.vh" |
`include "a25_functions.vh" |
|
localparam [4:0] RST_WAIT1 = 5'd0, |
RST_WAIT2 = 5'd1, |
439,7 → 439,7
instruction[15:12] ; |
|
// Load from memory into registers |
assign ldm_user_mode = type == MTRANS && {instruction[22:20],instruction[15]} == 4'b1010; |
assign ldm_user_mode = type == MTRANS && {instruction[22],instruction[20],instruction[15]} == 3'b110; |
assign ldm_flags = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22]; |
assign ldm_status_bits = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22] && i_execute_status_bits[1:0] != USR; |
assign load_rd_byte = (type == TRANS || type == SWAP) && instruction[22]; |
803,6 → 803,11
|
if ( !immediate_shift_op && !instruction[4] ) |
barrel_shift_amount_sel_nxt = 2'd2; // Shift immediate amount |
|
// regops that do not change the overflow flag |
if ( opcode == AND || opcode == EOR || opcode == TST || opcode == TEQ || |
opcode == ORR || opcode == MOV || opcode == BIC || opcode == MVN ) |
status_bits_sel_nxt = 3'd5; |
|
if ( opcode == ADD || opcode == CMN ) // CMN is just like an ADD |
begin |
1000,7 → 1005,7
write_data_wen_nxt = 1'd1; |
|
// stm: store the user mode registers, when in priviledged mode |
if ( {instruction[22:20]} == 3'b100 ) |
if ( {instruction[22],instruction[20]} == 2'b10 ) |
o_user_mode_regs_store_nxt = 1'd1; |
|
// update the base register ? |
1205,7 → 1210,7
write_data_wen_nxt = 1'd1; |
|
// stm: store the user mode registers, when in priviledged mode |
if ( {instruction[22:20]} == 3'b100 ) |
if ( {instruction[22],instruction[20]} == 2'b10 ) |
o_user_mode_regs_store_nxt = 1'd1; |
|
// write to the pc ? |
1241,7 → 1246,7
write_data_wen_nxt = 1'd1; |
|
// stm: store the user mode registers, when in priviledged mode |
if ( {instruction[22:20]} == 3'b100 ) |
if ( {instruction[22],instruction[20]} == 2'b10 ) |
o_user_mode_regs_store_nxt = 1'd1; |
|
// write to the pc ? |
1414,7 → 1419,6
|
// Speed up the long path from u_decode/fetch_instruction_r to u_register_bank/r8_firq |
// This pre-encodes the firq_s3 signal thats used in u_register_bank |
// assign firq_not_user_mode_nxt = !user_mode_regs_load_nxt && status_bits_mode_nxt == FIRQ; |
assign firq_not_user_mode_nxt = status_bits_mode_nxt == FIRQ; |
|
|
1708,7 → 1712,7
// ======================================================== |
//synopsys translate_off |
|
`include "debug_functions.v" |
`include "debug_functions.vh" |
|
a25_decompile u_decompile ( |
.i_clk ( i_clk ), |
/amber25/a25_fetch.v
68,7 → 68,7
|
); |
|
`include "memory_configuration.v" |
`include "memory_configuration.vh" |
|
wire core_stall; |
wire cache_stall; |
/amber25/a25_decompile.v
39,8 → 39,9
// from http://www.opencores.org/lgpl.shtml // |
// // |
////////////////////////////////////////////////////////////////// |
`include "global_defines.v" |
`include "a25_config_defines.v" |
`include "global_timescale.vh" |
`include "global_defines.vh" |
`include "a25_config_defines.vh" |
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module a25_decompile |
( |
58,7 → 59,7
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); |
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`include "a25_localparams.v" |
`include "a25_localparams.vh" |
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`ifdef A25_DECOMPILE |
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/amber25/a25_execute.v
127,8 → 127,8
input i_rd_use_read |
); |
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`include "a25_localparams.v" |
`include "a25_functions.v" |
`include "a25_localparams.vh" |
`include "a25_functions.vh" |
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// ======================================================== |
// Internal signals |
240,10 → 240,14
i_status_bits_sel == 3'd1 ? alu_out [31:28] : |
i_status_bits_sel == 3'd3 ? i_copro_read_data[31:28] : |
// 4 = update flags after a multiply operation |
{ multiply_flags, status_bits_flags[1:0] } ; |
i_status_bits_sel == 3'd4 ? { multiply_flags, status_bits_flags[1:0] } : |
// regops that do not change the overflow flag |
i_status_bits_sel == 3'd5 ? { alu_flags[3:1], status_bits_flags[0] } : |
4'b1111 ; |
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assign status_bits_mode_nxt = ldm_status_bits ? read_data_filtered [1:0] : |
i_status_bits_sel == 3'd0 ? i_status_bits_mode : |
i_status_bits_sel == 3'd5 ? i_status_bits_mode : |
i_status_bits_sel == 3'd1 ? alu_out [1:0] : |
i_copro_read_data [1:0] ; |
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262,11 → 266,13
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assign status_bits_irq_mask_nxt = ldm_status_bits ? read_data_filtered [27] : |
i_status_bits_sel == 3'd0 ? i_status_bits_irq_mask : |
i_status_bits_sel == 3'd5 ? i_status_bits_irq_mask : |
i_status_bits_sel == 3'd1 ? alu_out [27] : |
i_copro_read_data [27] ; |
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assign status_bits_firq_mask_nxt = ldm_status_bits ? read_data_filtered [26] : |
i_status_bits_sel == 3'd0 ? i_status_bits_firq_mask : |
i_status_bits_sel == 3'd5 ? i_status_bits_firq_mask : |
i_status_bits_sel == 3'd1 ? alu_out [26] : |
i_copro_read_data [26] ; |
|