OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

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  • This comparison shows the changes necessary to convert path 
    /amber/trunk
    from Rev 35 to Rev 36
    ↔ Reverse comparison
  •

Rev 35 → Rev 36

/doc/ReleaseChecklist.txt
1,4 → 1,4
1. Run all tests using both A23 and A25 using all cache size configurations.
1. Run all hw tests using both A23 and A25 using all cache size configurations for Spartan6, Virtex6 and generic libs.
2. Synthesise both a23 and a25 cores.
Both cores must pass timing; Spartan6 at 40MHz, Virtex6 at 80Mhz, with max caches
Check all synthesis warnings, clean up as many as possible.
/sw/tools/amber-memparams.sh File deleted
/sw/tools/amber-memparams32.sh
0,0 → 1,190
#!/bin/bash
 
#--------------------------------------------------------------#
# #
# amber-memparams128.sh #
# #
# This file is part of the Amber project #
# http://www.opencores.org/project,amber #
# #
# Description #
# Create a memparams file. Used to seed the boot_mem SRAM #
# #
# Author(s): #
# - Conor Santifort, csantifort.amber@gmail.com #
# #
#//////////////////////////////////////////////////////////////#
# #
# Copyright (C) 2010 Authors and OPENCORES.ORG #
# #
# This source file may be used and distributed without #
# restriction provided that this copyright statement is not #
# removed from the file and that any derivative work contains #
# the original copyright notice and the associated disclaimer. #
# #
# This source file is free software; you can redistribute it #
# and/or modify it under the terms of the GNU Lesser General #
# Public License as published by the Free Software Foundation; #
# either version 2.1 of the License, or (at your option) any #
# later version. #
# #
# This source is distributed in the hope that it will be #
# useful, but WITHOUT ANY WARRANTY; without even the implied #
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR #
# PURPOSE. See the GNU Lesser General Public License for more #
# details. #
# #
# You should have received a copy of the GNU Lesser General #
# Public License along with this source; if not, download it #
# from http://www.opencores.org/lgpl.shtml #
# #
#--------------------------------------------------------------#
 
grep '@' $1 | awk '{print $2}' | awk -F '' '{print $1 $2}' |\
paste -d" " - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | \
awk '{printf " .SRAM0_INIT_" NR-1 " ( 256%ch", 39 } \
$31=="" {printf "00"} \
$30=="" {printf "00"} \
$29=="" {printf "00"} \
$28=="" {printf "00"} \
$27=="" {printf "00"} \
$26=="" {printf "00"} \
$25=="" {printf "00"} \
$24=="" {printf "00"} \
$23=="" {printf "00"} \
$22=="" {printf "00"} \
$21=="" {printf "00"} \
$20=="" {printf "00"} \
$19=="" {printf "00"} \
$18=="" {printf "00"} \
$17=="" {printf "00"} \
$16=="" {printf "00"} \
$15=="" {printf "00"} \
$14=="" {printf "00"} \
$13=="" {printf "00"} \
$12=="" {printf "00"} \
$11=="" {printf "00"} \
$10=="" {printf "00"} \
$9=="" {printf "00"} \
$8=="" {printf "00"} \
$7=="" {printf "00"} \
$6=="" {printf "00"} \
$5=="" {printf "00"} \
$4=="" {printf "00"} \
$3=="" {printf "00"} \
$2=="" {printf "00"} \
{print $32 $31 $30 $29 $28 $27 $26 $25 $24 $23 $22 $21 $20 $19 $18 $17 $16 $15 $14 $13 $12 $11 $10 $9 $8 $7 $6 $5 $4 $3 $2 $1 " )," } ' \
> $2
 
 
grep '@' $1 | awk '{print $2}' | awk -F '' '{print $3 $4}' |\
paste -d" " - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | \
awk '{printf " .SRAM1_INIT_" NR-1 " ( 256%ch", 39 } \
$31=="" {printf "00"} \
$30=="" {printf "00"} \
$29=="" {printf "00"} \
$28=="" {printf "00"} \
$27=="" {printf "00"} \
$26=="" {printf "00"} \
$25=="" {printf "00"} \
$24=="" {printf "00"} \
$23=="" {printf "00"} \
$22=="" {printf "00"} \
$21=="" {printf "00"} \
$20=="" {printf "00"} \
$19=="" {printf "00"} \
$18=="" {printf "00"} \
$17=="" {printf "00"} \
$16=="" {printf "00"} \
$15=="" {printf "00"} \
$14=="" {printf "00"} \
$13=="" {printf "00"} \
$12=="" {printf "00"} \
$11=="" {printf "00"} \
$10=="" {printf "00"} \
$9=="" {printf "00"} \
$8=="" {printf "00"} \
$7=="" {printf "00"} \
$6=="" {printf "00"} \
$5=="" {printf "00"} \
$4=="" {printf "00"} \
$3=="" {printf "00"} \
$2=="" {printf "00"} \
{print $32 $31 $30 $29 $28 $27 $26 $25 $24 $23 $22 $21 $20 $19 $18 $17 $16 $15 $14 $13 $12 $11 $10 $9 $8 $7 $6 $5 $4 $3 $2 $1 " )," } ' \
>> $2
grep '@' $1 | awk '{print $2}' | awk -F '' '{print $5 $6}' |\
paste -d" " - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | \
awk '{printf " .SRAM2_INIT_" NR-1 " ( 256%ch", 39 } \
$31=="" {printf "00"} \
$30=="" {printf "00"} \
$29=="" {printf "00"} \
$28=="" {printf "00"} \
$27=="" {printf "00"} \
$26=="" {printf "00"} \
$25=="" {printf "00"} \
$24=="" {printf "00"} \
$23=="" {printf "00"} \
$22=="" {printf "00"} \
$21=="" {printf "00"} \
$20=="" {printf "00"} \
$19=="" {printf "00"} \
$18=="" {printf "00"} \
$17=="" {printf "00"} \
$16=="" {printf "00"} \
$15=="" {printf "00"} \
$14=="" {printf "00"} \
$13=="" {printf "00"} \
$12=="" {printf "00"} \
$11=="" {printf "00"} \
$10=="" {printf "00"} \
$9=="" {printf "00"} \
$8=="" {printf "00"} \
$7=="" {printf "00"} \
$6=="" {printf "00"} \
$5=="" {printf "00"} \
$4=="" {printf "00"} \
$3=="" {printf "00"} \
$2=="" {printf "00"} \
{print $32 $31 $30 $29 $28 $27 $26 $25 $24 $23 $22 $21 $20 $19 $18 $17 $16 $15 $14 $13 $12 $11 $10 $9 $8 $7 $6 $5 $4 $3 $2 $1 " )," } ' \
>> $2
 
grep '@' $1 | awk '{print $2}' | awk -F '' '{print $7 $8}' |\
paste -d" " - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | \
awk '{printf " .SRAM3_INIT_" NR-1 " ( 256%ch", 39 } \
$31=="" {printf "00"} \
$30=="" {printf "00"} \
$29=="" {printf "00"} \
$28=="" {printf "00"} \
$27=="" {printf "00"} \
$26=="" {printf "00"} \
$25=="" {printf "00"} \
$24=="" {printf "00"} \
$23=="" {printf "00"} \
$22=="" {printf "00"} \
$21=="" {printf "00"} \
$20=="" {printf "00"} \
$19=="" {printf "00"} \
$18=="" {printf "00"} \
$17=="" {printf "00"} \
$16=="" {printf "00"} \
$15=="" {printf "00"} \
$14=="" {printf "00"} \
$13=="" {printf "00"} \
$12=="" {printf "00"} \
$11=="" {printf "00"} \
$10=="" {printf "00"} \
$9=="" {printf "00"} \
$8=="" {printf "00"} \
$7=="" {printf "00"} \
$6=="" {printf "00"} \
$5=="" {printf "00"} \
$4=="" {printf "00"} \
$3=="" {printf "00"} \
$2=="" {printf "00"} \
{print $32 $31 $30 $29 $28 $27 $26 $25 $24 $23 $22 $21 $20 $19 $18 $17 $16 $15 $14 $13 $12 $11 $10 $9 $8 $7 $6 $5 $4 $3 $2 $1 " )," } ' \
>> $2
 
echo " .UNUSED ( 1'd0 ) " >> $2
/sw/tools/amber-memparams128.sh
0,0 → 1,96
#!/bin/bash
 
#--------------------------------------------------------------#
# #
# amber-memparams128.sh #
# #
# This file is part of the Amber project #
# http://www.opencores.org/project,amber #
# #
# Description #
# Create a memparams file. Used to seed the boot_mem SRAM #
# #
# Author(s): #
# - Conor Santifort, csantifort.amber@gmail.com #
# #
#//////////////////////////////////////////////////////////////#
# #
# Copyright (C) 2010 Authors and OPENCORES.ORG #
# #
# This source file may be used and distributed without #
# restriction provided that this copyright statement is not #
# removed from the file and that any derivative work contains #
# the original copyright notice and the associated disclaimer. #
# #
# This source file is free software; you can redistribute it #
# and/or modify it under the terms of the GNU Lesser General #
# Public License as published by the Free Software Foundation; #
# either version 2.1 of the License, or (at your option) any #
# later version. #
# #
# This source is distributed in the hope that it will be #
# useful, but WITHOUT ANY WARRANTY; without even the implied #
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR #
# PURPOSE. See the GNU Lesser General Public License for more #
# details. #
# #
# You should have received a copy of the GNU Lesser General #
# Public License along with this source; if not, download it #
# from http://www.opencores.org/lgpl.shtml #
# #
#--------------------------------------------------------------#
 
grep '@' $1 | awk '{print $2}' | awk 'NR%4==1' |\
paste -d" " - - - - - - - - | \
awk '{printf " .SRAM0_INIT_" NR-1 " ( 256%ch", 39 } \
$8=="" {printf "00000000"} \
$7=="" {printf "00000000"} \
$6=="" {printf "00000000"} \
$5=="" {printf "00000000"} \
$4=="" {printf "00000000"} \
$3=="" {printf "00000000"} \
$2=="" {printf "00000000"} \
{print $8 $7 $6 $5 $4 $3 $2 $1 " )," } ' \
> $2
 
grep '@' $1 | awk '{print $2}' | awk 'NR%4==2' |\
paste -d" " - - - - - - - - | \
awk '{printf " .SRAM1_INIT_" NR-1 " ( 256%ch", 39 } \
$8=="" {printf "00000000"} \
$7=="" {printf "00000000"} \
$6=="" {printf "00000000"} \
$5=="" {printf "00000000"} \
$4=="" {printf "00000000"} \
$3=="" {printf "00000000"} \
$2=="" {printf "00000000"} \
{print $8 $7 $6 $5 $4 $3 $2 $1 " )," } ' \
>> $2
 
grep '@' $1 | awk '{print $2}' | awk 'NR%4==3' |\
paste -d" " - - - - - - - - | \
awk '{printf " .SRAM2_INIT_" NR-1 " ( 256%ch", 39 } \
$8=="" {printf "00000000"} \
$7=="" {printf "00000000"} \
$6=="" {printf "00000000"} \
$5=="" {printf "00000000"} \
$4=="" {printf "00000000"} \
$3=="" {printf "00000000"} \
$2=="" {printf "00000000"} \
{print $8 $7 $6 $5 $4 $3 $2 $1 " )," } ' \
>> $2
 
 
grep '@' $1 | awk '{print $2}' | awk 'NR%4==0' |\
paste -d" " - - - - - - - - | \
awk '{printf " .SRAM3_INIT_" NR-1 " ( 256%ch", 39 } \
$8=="" {printf "00000000"} \
$7=="" {printf "00000000"} \
$6=="" {printf "00000000"} \
$5=="" {printf "00000000"} \
$4=="" {printf "00000000"} \
$3=="" {printf "00000000"} \
$2=="" {printf "00000000"} \
{print $8 $7 $6 $5 $4 $3 $2 $1 " )," } ' \
>> $2
 
echo " .UNUSED ( 1'd0 ) " >> $2
/sw/include/common.mk
43,19 → 43,21
TOOLSPATH = ../tools
AMBER_CROSSTOOL ?= amber-crosstool-not-defined
 
AS = $(AMBER_CROSSTOOL)-as
CC = $(AMBER_CROSSTOOL)-gcc
CXX = $(AMBER_CROSSTOOL)-g++
AR = $(AMBER_CROSSTOOL)-ar
LD = $(AMBER_CROSSTOOL)-ld
DS = $(AMBER_CROSSTOOL)-objdump
OC = $(AMBER_CROSSTOOL)-objcopy
ELF = $(TOOLSPATH)/amber-elfsplitter
BMF = $(TOOLSPATH)/amber-memparams.sh
AS = $(AMBER_CROSSTOOL)-as
CC = $(AMBER_CROSSTOOL)-gcc
CXX = $(AMBER_CROSSTOOL)-g++
AR = $(AMBER_CROSSTOOL)-ar
LD = $(AMBER_CROSSTOOL)-ld
DS = $(AMBER_CROSSTOOL)-objdump
OC = $(AMBER_CROSSTOOL)-objcopy
ELF = $(TOOLSPATH)/amber-elfsplitter
BMF32 = ../tools/amber-memparams32.sh
BMF128 = ../tools/amber-memparams128.sh
 
MMP = $(addsuffix _memparams.v, $(basename $(TGT)))
MEM = $(addsuffix .mem, $(basename $(TGT)))
DIS = $(addsuffix .dis, $(basename $(TGT)))
MMP32 = $(addsuffix _memparams32.v, $(basename $(TGT)))
MMP128 = $(addsuffix _memparams128.v, $(basename $(TGT)))
MEM = $(addsuffix .mem, $(basename $(TGT)))
DIS = $(addsuffix .dis, $(basename $(TGT)))
ifdef USE_MINI_LIBC
OBJ = $(addsuffix .o, $(basename $(SRC))) $(LIBC_OBJ)
91,14 → 93,17
 
 
ifdef USE_MINI_LIBC
debug: mini-libc $(ELF) $(MMP) $(DIS)
debug: mini-libc $(ELF) $(MMP32) $(MMP128) $(DIS)
else
debug: $(ELF) $(MMP) $(DIS)
endif
 
$(MMP): $(MEM)
$(BMF) $(MEM) $(MMP)
$(MMP32): $(MEM)
$(BMF32) $(MEM) $(MMP32)
 
$(MMP128): $(MEM)
$(BMF128) $(MEM) $(MMP128)
 
$(MEM): $(TGT)
$(ELF) $(TGT) > $(MEM)
 
118,5 → 123,5
$(DS) $(DSFLAGS) $^ > $@
 
clean:
@rm -rfv *.o *.elf *.dis *.map *.mem *.v $(MMP)
@rm -rfv *.o *.elf *.dis *.map *.mem *.v $(MMP32) $(MMP128)
 
/sw/dhry/Makefile
17,9 → 17,11
DS = $(AMBER_CROSSTOOL)-objdump
OC = $(AMBER_CROSSTOOL)-objcopy
ELF = $(TOOLSPATH)/amber-elfsplitter
BMF = $(TOOLSPATH)/amber-memparams.sh
BMF32 = ../tools/amber-memparams32.sh
BMF128 = ../tools/amber-memparams128.sh
 
MMP = $(addsuffix _memparams.v, $(basename $(TGT)))
MMP32 = $(addsuffix _memparams32.v, $(basename $(TGT)))
MMP128 = $(addsuffix _memparams128.v, $(basename $(TGT)))
MEM = $(addsuffix .mem, $(basename $(TGT)))
DIS = $(addsuffix .dis, $(basename $(TGT)))
63,7 → 65,7
endif
 
$(MMP): $(MEM)
$(BMF) $(MEM) $(MMP)
$(BMF32) $(MEM) $(MMP32)
 
$(MEM): $(TGT)
$(ELF) $(TGT) > $(MEM)
/sw/boot-loader
sw/boot-loader Property changes : Modified: svn:ignore ## -2,4 +2,4 ## *.mem *.dis *.elf -*_memparams.v +*_memparams*.v Index: sw/ethmac-test =================================================================== --- sw/ethmac-test (revision 35) +++ sw/ethmac-test (revision 36)
sw/ethmac-test Property changes : Modified: svn:ignore ## -2,4 +2,4 ## *.mem *.dis *.elf -*_memparams.v +*_memparams*.v Index: hw/tools/all.sh =================================================================== --- hw/tools/all.sh (revision 35) +++ hw/tools/all.sh (revision 36) @@ -66,10 +66,10 @@ mlas_bug inflate_bug swp_lock_bug \ cache_swap_bug \ " -LOF_FILE=$1 +LOG_FILE=$1 -echo "----------------------------------" >> ${LOF_FILE} -date >> ${LOF_FILE} +echo "----------------------------------" >> ${LOG_FILE} +date >> ${LOG_FILE} for i in $TEST_LIST; do echo "Run test $i" @@ -76,5 +76,5 @@ ../tools/run.sh ${i} $2 $3 done -echo "----------------------------------" >> ${LOF_FILE} +echo "----------------------------------" >> ${LOG_FILE}
/hw/tools/run.sh
71,7 → 71,7
echo " -l : Create wlf dump of complete design"
echo " -nc: Do not re-compile the Verilog. Starts the simulation more quickly"
echo " -s : Use Xilinx Spatran6 Libraries (slower sim)"
echo " -to: Ignore timeout limit for this test"
echo " -to <timeout value>: Use this timeout value instead of the value in the timeouts.txt file"
echo " -v : Use Xilinx Virtex6 Libraries (slower sim)"
echo " -5 : Use Amber25 core instead of Amber23 core"
echo ""
255,8 → 255,13
popd > /dev/null
BOOT_MEM_FILE="../tests/${AMBER_TEST_NAME}.mem"
BOOT_MEM_PARAMS_FILE="../tests/${AMBER_TEST_NAME}_memparams.v"
if [ $SET_5 == 1 ]; then
BOOT_MEM_PARAMS_FILE="../tests/${AMBER_TEST_NAME}_memparams128.v"
else
BOOT_MEM_PARAMS_FILE="../tests/${AMBER_TEST_NAME}_memparams32.v"
fi
elif [ $TEST_TYPE == 2 ]; then
# sw Stand-alone C test
pushd ../../sw/${AMBER_TEST_NAME} > /dev/null
264,7 → 269,11
MAKE_STATUS=$?
popd > /dev/null
BOOT_MEM_FILE="../../sw/${AMBER_TEST_NAME}/${AMBER_TEST_NAME}.mem"
BOOT_MEM_PARAMS_FILE="../../sw/${AMBER_TEST_NAME}/${AMBER_TEST_NAME}_memparams.v"
if [ $SET_5 == 1 ]; then
BOOT_MEM_PARAMS_FILE="../../sw/${AMBER_TEST_NAME}/${AMBER_TEST_NAME}_memparams128.v"
else
BOOT_MEM_PARAMS_FILE="../../sw/${AMBER_TEST_NAME}/${AMBER_TEST_NAME}_memparams32.v"
fi
 
elif [ $TEST_TYPE == 3 ] || [ $TEST_TYPE == 4 ]; then
# sw test using boot loader
285,7 → 294,11
popd > /dev/null
BOOT_MEM_FILE="../../sw/boot-loader/boot-loader.mem"
BOOT_MEM_PARAMS_FILE="../../sw/boot-loader/boot-loader_memparams.v"
if [ $SET_5 == 1 ]; then
BOOT_MEM_PARAMS_FILE="../../sw/boot-loader/boot-loader_memparams128.v"
else
BOOT_MEM_PARAMS_FILE="../../sw/boot-loader/boot-loader_memparams32.v"
fi
MAIN_MEM_FILE="../../sw/${AMBER_TEST_NAME}/${AMBER_TEST_NAME}.mem"
AMBER_LOAD_MAIN_MEM="+define+AMBER_LOAD_MAIN_MEM"
 
303,8 → 316,6
if [ $SET_TO == 0 ]; then
AMBER_TIMEOUT=`../tools/get_timeout.sh ${AMBER_TEST_NAME}`
fi
printf '@00001fec %08x\n' $AMBER_TIMEOUT >> ${BOOT_MEM_FILE}
echo ${AMBER_TEST_NAME} | ../../sw/tools/amber-ascii-mem 1ff0 >> ${BOOT_MEM_FILE}
 
 
#--------------------------------------------------------
/hw/tests/stm_stream.S
40,6 → 40,7
*****************************************************************/
 
#include "amber_registers.h"
#include "amber_macros.h"
 
.section .text
.globl main
108,9 → 109,7
1: mov r9, r14
2: add r9, r9, #1
ldr r12, [r0], #4
cmp r12, r9
addne r10, r9, r13
bne testfail
compare r12, r9, __LINE__
add r10, r14, #8
cmp r9, r10
bne 2b
/hw/tests/timeouts.txt
1,60 → 1,60
flow4 3936
tmp 2756
add 1716
adc 1440
sub 1536
sbc 2676
barrel_shift 1536
barrel_shift_rs 1380
change_sbits 2232
change_mode 1680
bl 1572
bcc 1200
ldr 4276
ldr_str_pc 1576
strb 2300
ldm1 2556
ldm2 2016
ldm3 1832
ldm4 1808
stm1 7012
stm2 2332
ldm_stm_onetwo 5284
stm_stream 52924
mul 180768
mla 383544
swp 2040
irq 101116
firq 29568
swi 1620
undefined_ins 2676
addr_ex 1772
irq_stm 12332
cache1 16408
cache2 1484
cache3 122460
cache_swap 85704
cacheable_area 6348
cache_flush 19460
flow1 3072
flow2 5748
flow3 3396
conflict_rd 2832
hiboot_mem 1436
ddr31 99868
ddr32 205836
ddr33 24684
ethmac_reg 4740
ethmac_mem 79896
ethmac_tx 20364
uart_reg 2028
uart_tx 134116
uart_rx 132420
uart_rxint 127120
bic_bug 1524
movs_bug 1616
flow_bug 1452
mlas_bug 1972
inflate_bug 1408
swp_lock_bug 1356
cache_swap_bug 32656
add 3576
adc 3228
sub 3356
sbc 4256
barrel_shift 5924
barrel_shift_rs 3260
change_sbits 4004
change_mode 3524
bl 3420
bcc 3068
ldr 5712
ldr_str_pc 3428
strb 3948
ldm1 4372
ldm2 3880
ldm3 3684
ldm4 3676
stm1 8708
stm2 4120
ldm_stm_onetwo 5868
stm_stream 69180
mul 175432
mla 362840
swp 3848
irq 96492
firq 29972
swi 3468
undefined_ins 4444
addr_ex 3640
irq_stm 11504
cache1 14884
cache2 3156
cache3 102596
cache_swap 69936
cacheable_area 8428
cache_flush 21828
flow1 4500
flow2 5992
flow3 4716
conflict_rd 4088
hiboot_mem 3240
ddr31 106792
ddr32 216400
ddr33 24656
ethmac_reg 6476
ethmac_mem 73360
ethmac_tx 23744
uart_reg 3632
uart_tx 133872
uart_rx 133924
uart_rxint 126924
bic_bug 3392
movs_bug 3396
flow_bug 3292
mlas_bug 3812
inflate_bug 3220
swp_lock_bug 3220
cache_swap_bug 25448
/hw/tests/Makefile
46,24 → 46,26
AMBER_CROSSTOOL ?= amber-crosstool-not-defined
TOOLSPATH = ../../sw/tools
 
TGT = $(addsuffix .elf, $(basename $(TEST)))
MMP = $(addsuffix _memparams.v, $(basename $(TGT)))
SRC = $(addsuffix .S, $(basename $(TEST)))
MEM = $(addsuffix .mem, $(basename $(TGT)))
DIS = $(addsuffix .dis, $(basename $(TGT)))
OBJ = $(addsuffix .o, $(basename $(SRC)))
MAP = $(addsuffix .map, $(basename $(TGT)))
LDS = sections.lds
TGT = $(addsuffix .elf, $(basename $(TEST)))
MMP32 = $(addsuffix _memparams32.v, $(basename $(TGT)))
MMP128 = $(addsuffix _memparams128.v, $(basename $(TGT)))
SRC = $(addsuffix .S, $(basename $(TEST)))
MEM = $(addsuffix .mem, $(basename $(TGT)))
DIS = $(addsuffix .dis, $(basename $(TGT)))
OBJ = $(addsuffix .o, $(basename $(SRC)))
MAP = $(addsuffix .map, $(basename $(TGT)))
LDS = sections.lds
 
AS = $(AMBER_CROSSTOOL)-as
CC = $(AMBER_CROSSTOOL)-gcc
CXX = $(AMBER_CROSSTOOL)-g++
AR = $(AMBER_CROSSTOOL)-ar
LD = $(AMBER_CROSSTOOL)-ld
DS = $(AMBER_CROSSTOOL)-objdump
OC = $(AMBER_CROSSTOOL)-objcopy
ELF = ../../sw/tools/amber-elfsplitter
BMF = ../../sw/tools/amber-memparams.sh
AS = $(AMBER_CROSSTOOL)-as
CC = $(AMBER_CROSSTOOL)-gcc
CXX = $(AMBER_CROSSTOOL)-g++
AR = $(AMBER_CROSSTOOL)-ar
LD = $(AMBER_CROSSTOOL)-ld
DS = $(AMBER_CROSSTOOL)-objdump
OC = $(AMBER_CROSSTOOL)-objcopy
ELF = ../../sw/tools/amber-elfsplitter
BMF32 = ../../sw/tools/amber-memparams32.sh
BMF128 = ../../sw/tools/amber-memparams128.sh
ASFLAGS = -I../../sw/include
CFLAGS = -c -march=armv2a -mno-thumb-interwork -I../../sw/include
71,11 → 73,14
LDFLAGS = -Bstatic -Map $(MAP) --fix-v4bx
 
all: $(ELF) $(MMP) $(DIS)
all: $(ELF) $(MMP32) $(MMP128) $(DIS)
 
$(MMP): $(MEM)
$(BMF) $(MEM) $(MMP)
$(MMP32): $(MEM)
$(BMF32) $(MEM) $(MMP32)
 
$(MMP128): $(MEM)
$(BMF128) $(MEM) $(MMP128)
 
$(MEM): $(TGT)
$(ELF) $(TGT) > $(MEM)
 
92,5 → 97,5
$(MAKE) -C $(TOOLSPATH)
 
clean:
@rm -rfv *.o *.elf *.dis *.map *.mem *_memparams.v
@rm -rfv *.o *.elf *.dis *.map *.mem *_memparams*.v
 
/hw/tests/barrel_shift.S
39,53 → 39,114
*****************************************************************/
 
#include "amber_registers.h"
#include "amber_macros.h"
 
.section .text
.globl main
main:
 
@ Run through the test 4 times
@ 1 - cache off
@ 2 - cache on but empty
@ 3 - cache on and loaded
@ 4 - same as 3
mov r10, #4
 
 
/* lsl 0 */
mov r1, #1
1: mov r1, #1
mov r2, r1, lsl #0
mov r3, #0x1
cmp r2, r3
bne testfail
expect r2, 1, __LINE__
 
/* lsl 1 */
mov r4, #1
mov r5, r4, lsl #1
mov r6, #2
cmp r5, r6
bne testfail
expect r5, 2, __LINE__
/* lsl 31 */
mov r7, #1
mov r8, r1, lsl #31
mov r9, #0x80000000
cmp r8, r9
bne testfail
expect r8, 0x80000000, __LINE__
/* lsr 1 */
mov r1, #2
mov r2, r1, lsr #1
mov r3, #0x1
cmp r2, r3
bne testfail
expect r2, 1, __LINE__
/* lsr 8 */
mov r4, #0xff00
mov r5, r4, lsr #8
cmp r5, #0xff
bne testfail
expect r5, 0xff, __LINE__
/* ror 8 */
ldr r6, Data1
mov r7, r6, ror #8
ldr r8, Data2
cmp r7, r8
bne testfail
compare r7, r8, __LINE__
 
 
@ ---------------------
@ Sequences of shift operations
@ ---------------------
 
@ lsl
mov r0, #0
mov r1, #1
mov r2, #2
mov r3, #3
mov r4, #4
mov r5, #5
mov r6, r3, lsl #31
mov r7, r0, lsl #2
mov r8, r1, lsl #11
mov r9, r2, lsl #17
expect r6, 0x80000000, __LINE__
expect r7, 0x00000000, __LINE__
expect r8, 0x00000800, __LINE__
expect r9, 0x00040000, __LINE__
 
mov r6, r3, lsl #30
mov r7, r1, lsl #2
mov r8, r2, lsl #4
mov r9, r3, lsl #5
expect r6, 0xc0000000, __LINE__
expect r7, 0x00000004, __LINE__
expect r8, 0x00000020, __LINE__
expect r9, 0x00000060, __LINE__
 
@ lsr
mov r0, #0x80000000
mov r1, #0x7f000000
mov r2, #0x80000001
mov r3, #0x7fffffff
mov r4, #0x7ffffffe
mov r5, #0x55000000
orr r5, r5, #0x55
 
mov r6, r0, lsr #1
mov r7, r0, lsr #2
mov r8, r1, lsr #24
mov r9, r2, lsr #1
expect r6, 0x40000000, __LINE__
expect r7, 0x20000000, __LINE__
expect r8, 0x0000007f, __LINE__
expect r9, 0x40000000, __LINE__
 
@ ---------------------
@ Enable the cache
@ ---------------------
mvn r0, #0
mcr 15, 0, r0, cr3, cr0, 0 @ cacheable area
mov r0, #1
mcr 15, 0, r0, cr2, cr0, 0 @ cache enable
 
subs r10, r10, #1
bne 1b
b testpass
 
/hw/tests
hw/tests Property changes : Modified: svn:ignore ## -1,5 +1,5 ## *.elf -*_memparams.v +*_memparams*.v *.map *.mem *.dis Index: hw/vlog/system/boot_mem.v =================================================================== --- hw/vlog/system/boot_mem.v (revision 35) +++ hw/vlog/system/boot_mem.v (nonexistent) @@ -1,209 +0,0 @@ -////////////////////////////////////////////////////////////////// -// // -// 8KBytes SRAM configured with boot software // -// // -// This file is part of the Amber project // -// http://www.opencores.org/project,amber // -// // -// Description // -// Holds just enough software to get the system going. // -// The boot loader fits into this 8KB embedded SRAM on the // -// FPGA and enables it to load large applications via the // -// serial port (UART) into the DDR3 memory // -// // -// Author(s): // -// - Conor Santifort, csantifort.amber@gmail.com // -// // -////////////////////////////////////////////////////////////////// -// // -// Copyright (C) 2010 Authors and OPENCORES.ORG // -// // -// This source file may be used and distributed without // -// restriction provided that this copyright statement is not // -// removed from the file and that any derivative work contains // -// the original copyright notice and the associated disclaimer. // -// // -// This source file is free software; you can redistribute it // -// and/or modify it under the terms of the GNU Lesser General // -// Public License as published by the Free Software Foundation; // -// either version 2.1 of the License, or (at your option) any // -// later version. // -// // -// This source is distributed in the hope that it will be // -// useful, but WITHOUT ANY WARRANTY; without even the implied // -// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // -// PURPOSE. See the GNU Lesser General Public License for more // -// details. // -// // -// You should have received a copy of the GNU Lesser General // -// Public License along with this source; if not, download it // -// from http://www.opencores.org/lgpl.shtml // -// // -////////////////////////////////////////////////////////////////// - - -module boot_mem #( -parameter WB_DWIDTH = 32, -parameter WB_SWIDTH = 4 -)( -input i_wb_clk, // WISHBONE clock - -input [31:0] i_wb_adr, -input [WB_SWIDTH-1:0] i_wb_sel, -input i_wb_we, -output [WB_DWIDTH-1:0] o_wb_dat, -input [WB_DWIDTH-1:0] i_wb_dat, -input i_wb_cyc, -input i_wb_stb, -output o_wb_ack, -output o_wb_err - -); - -wire start_write, start_read; -reg start_read_d1 = 'd0; -wire [31:0] read_data; -wire [31:0] write_data; -wire [3:0] byte_enable; -wire [10:0] address; - - -// Can't start a write while a read is completing. The ack for the read cycle -// needs to be sent first -assign start_write = i_wb_stb && i_wb_we && !start_read_d1; -assign start_read = i_wb_stb && !i_wb_we && !start_read_d1; - - -always @( posedge i_wb_clk ) - start_read_d1 <= start_read; - -assign o_wb_err = 1'd0; - - -generate -if (WB_DWIDTH == 128) - begin : wb128 - reg [31:0] read_data_r1 = 'd0; - reg [31:0] read_data_r2 = 'd0; - reg [31:0] read_data_r3 = 'd0; - reg [2:0] access_r = 'd0; - reg idle_r = 1'd1; - - assign write_data = i_wb_adr[3:2] == 2'd3 ? i_wb_dat[127:96] : - i_wb_adr[3:2] == 2'd2 ? i_wb_dat[ 95:64] : - i_wb_adr[3:2] == 2'd1 ? i_wb_dat[ 63:32] : - i_wb_dat[ 31: 0] ; - - assign byte_enable = i_wb_adr[3:2] == 2'd3 ? i_wb_sel[15:12] : - i_wb_adr[3:2] == 2'd2 ? i_wb_sel[11: 8] : - i_wb_adr[3:2] == 2'd1 ? i_wb_sel[ 7: 4] : - i_wb_sel[ 3: 0] ; - - assign o_wb_dat = {read_data, read_data_r1, read_data_r2, read_data_r3}; - - // 4-Word burst accesses - always @(posedge i_wb_clk) - begin - read_data_r1 <= read_data; - read_data_r2 <= read_data_r1; - read_data_r3 <= read_data_r2; - - if (idle_r) - begin - // start read of 4 - if (i_wb_stb && !i_wb_we) - begin - idle_r <= 1'd0; - access_r <= access_r + 1'd1; - end - end - else if (access_r == 3'd4) - begin - access_r <= 3'd0; - idle_r <= 1'd1; - end - else - access_r <= access_r + 1'd1; - end - - assign address = start_write ? i_wb_adr[12:2] : {i_wb_adr[12:4],2'd0} + access_r; - assign o_wb_ack = access_r == 3'd4 || start_write; - end -else - begin : wb32 - assign write_data = i_wb_dat; - assign byte_enable = i_wb_sel; - assign o_wb_dat = read_data; - assign address = i_wb_adr[12:2]; - assign o_wb_ack = i_wb_stb && ( start_write || start_read_d1 ); - end -endgenerate - - - -// ------------------------------------------------------ -// Instantiate SRAMs -// ------------------------------------------------------ -// -`ifdef XILINX_FPGA - - `ifdef XILINX_SPARTAN6_FPGA - xs6_sram_2048x32_byte_en - `endif - `ifdef XILINX_VIRTEX6_FPGA - xv6_sram_2048x32_byte_en - `endif - -#( -// This file holds a software image used for FPGA simulations -// This pre-processor syntax works with both the simulator -// and ISE, which I couldn't get to work with giving it the -// file name as a define. - -`ifdef BOOT_MEM_PARAMS_FILE - `include `BOOT_MEM_PARAMS_FILE -`else - // default file - `include "boot-loader_memparams.v" -`endif - -) -`endif - -`ifndef XILINX_FPGA -generic_sram_byte_en -#( - .DATA_WIDTH ( 32 ) , - .ADDRESS_WIDTH ( 11 ) -) -`endif -u_mem ( - .i_clk ( i_wb_clk ), - .i_write_enable ( start_write ), - .i_byte_enable ( byte_enable ), - .i_address ( address ), // 2048 words, 32 bits - .o_read_data ( read_data ), - .i_write_data ( write_data ) -); - - -// ======================================================================================= -// ======================================================================================= -// ======================================================================================= -// Non-synthesizable debug code -// ======================================================================================= - - -//synopsys translate_off -`ifdef XILINX_SPARTAN6_FPGA - `ifdef BOOT_MEM_PARAMS_FILE - initial - $display("Boot mem file is %s", `BOOT_MEM_PARAMS_FILE ); - `endif -`endif -//synopsys translate_on - -endmodule - - - Index: hw/vlog/system/system.v =================================================================== --- hw/vlog/system/system.v (revision 35) +++ hw/vlog/system/system.v (revision 36) @@ -339,23 +339,37 @@ // ------------------------------------------------------------- // Instantiate Boot Memory - 8KBytes of Embedded SRAM // ------------------------------------------------------------- -boot_mem #( - .WB_DWIDTH ( WB_DWIDTH ), - .WB_SWIDTH ( WB_SWIDTH ) - ) -u_boot_mem ( - .i_wb_clk ( sys_clk ), - .i_wb_adr ( s_wb_adr [1] ), - .i_wb_sel ( s_wb_sel [1] ), - .i_wb_we ( s_wb_we [1] ), - .o_wb_dat ( s_wb_dat_r[1] ), - .i_wb_dat ( s_wb_dat_w[1] ), - .i_wb_cyc ( s_wb_cyc [1] ), - .i_wb_stb ( s_wb_stb [1] ), - .o_wb_ack ( s_wb_ack [1] ), - .o_wb_err ( s_wb_err [1] ) -); +generate +if (WB_DWIDTH == 32) begin : boot_mem32 + boot_mem32 u_boot_mem ( + .i_wb_clk ( sys_clk ), + .i_wb_adr ( s_wb_adr [1] ), + .i_wb_sel ( s_wb_sel [1] ), + .i_wb_we ( s_wb_we [1] ), + .o_wb_dat ( s_wb_dat_r[1] ), + .i_wb_dat ( s_wb_dat_w[1] ), + .i_wb_cyc ( s_wb_cyc [1] ), + .i_wb_stb ( s_wb_stb [1] ), + .o_wb_ack ( s_wb_ack [1] ), + .o_wb_err ( s_wb_err [1] ) + ); +end +else begin : boot_mem128 + boot_mem128 u_boot_mem ( + .i_wb_clk ( sys_clk ), + .i_wb_adr ( s_wb_adr [1] ), + .i_wb_sel ( s_wb_sel [1] ), + .i_wb_we ( s_wb_we [1] ), + .o_wb_dat ( s_wb_dat_r[1] ), + .i_wb_dat ( s_wb_dat_w[1] ), + .i_wb_cyc ( s_wb_cyc [1] ), + .i_wb_stb ( s_wb_stb [1] ), + .o_wb_ack ( s_wb_ack [1] ), + .o_wb_err ( s_wb_err [1] ) + ); +end +endgenerate // ------------------------------------------------------------- @@ -540,7 +554,11 @@ // Instantiate Wishbone to Xilinx Spartan-6 DDR3 Bridge // ------------------------------------------------------------- // The clock crossing fifo for spartan-6 is build into the mcb - wb_xs6_ddr3_bridge u_wb_xs6_ddr3_bridge ( + wb_xs6_ddr3_bridge #( + .WB_DWIDTH ( WB_DWIDTH ), + .WB_SWIDTH ( WB_SWIDTH ) + ) + u_wb_xs6_ddr3_bridge( .i_clk ( sys_clk ), .o_cmd_en ( c3_p0_cmd_en ),
/hw/vlog/system/boot_mem128.v
0,0 → 1,157
//////////////////////////////////////////////////////////////////
// //
// 8KBytes SRAM configured with boot software //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Holds just enough software to get the system going. //
// The boot loader fits into this 8KB embedded SRAM on the //
// FPGA and enables it to load large applications via the //
// serial port (UART) into the DDR3 memory //
// //
// Author(s): //
// - Conor Santifort, csantifort.amber@gmail.com //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
 
 
module boot_mem128 #(
parameter WB_DWIDTH = 128,
parameter WB_SWIDTH = 16,
parameter MADDR_WIDTH = 9
)(
input i_wb_clk, // WISHBONE clock
 
input [31:0] i_wb_adr,
input [WB_SWIDTH-1:0] i_wb_sel,
input i_wb_we,
output [WB_DWIDTH-1:0] o_wb_dat,
input [WB_DWIDTH-1:0] i_wb_dat,
input i_wb_cyc,
input i_wb_stb,
output o_wb_ack,
output o_wb_err
 
);
 
 
wire start_write;
wire start_read;
reg start_read_r = 'd0;
wire [WB_DWIDTH-1:0] read_data;
wire [WB_DWIDTH-1:0] write_data;
wire [WB_SWIDTH-1:0] byte_enable;
wire [MADDR_WIDTH-1:0] address;
 
 
// Can't start a write while a read is completing. The ack for the read cycle
// needs to be sent first
assign start_write = i_wb_stb && i_wb_we && !start_read_r;
assign start_read = i_wb_stb && !i_wb_we && !start_read_r;
 
 
always @( posedge i_wb_clk )
start_read_r <= start_read;
 
assign o_wb_err = 1'd0;
 
assign write_data = i_wb_dat;
assign byte_enable = i_wb_sel;
assign o_wb_dat = read_data;
assign address = i_wb_adr[MADDR_WIDTH+3:4];
assign o_wb_ack = i_wb_stb && ( start_write || start_read_r );
 
 
// ------------------------------------------------------
// Instantiate SRAMs
// ------------------------------------------------------
//
`ifdef XILINX_FPGA
 
`ifdef XILINX_SPARTAN6_FPGA
xs6_sram_512x128_byte_en
`endif
`ifdef XILINX_VIRTEX6_FPGA
xv6_sram_512x128_byte_en
`endif
 
#(
// This file holds a software image used for FPGA simulations
// This pre-processor syntax works with both the simulator
// and ISE, which I couldn't get to work with giving it the
// file name as a define.
 
`ifdef BOOT_MEM_PARAMS_FILE
`include `BOOT_MEM_PARAMS_FILE
`else
// default file
`include "boot-loader_memparams128.v"
`endif
 
)
`endif
 
`ifndef XILINX_FPGA
generic_sram_byte_en
#(
.DATA_WIDTH ( WB_DWIDTH ),
.ADDRESS_WIDTH ( MADDR_WIDTH )
)
`endif
u_mem (
.i_clk ( i_wb_clk ),
.i_write_enable ( start_write ),
.i_byte_enable ( byte_enable ),
.i_address ( address ), // 2048 words, 32 bits
.o_read_data ( read_data ),
.i_write_data ( write_data )
);
 
 
// =======================================================================================
// =======================================================================================
// =======================================================================================
// Non-synthesizable debug code
// =======================================================================================
 
 
//synopsys translate_off
`ifdef XILINX_SPARTAN6_FPGA
`ifdef BOOT_MEM_PARAMS_FILE
initial
$display("Boot mem file is %s", `BOOT_MEM_PARAMS_FILE );
`endif
`endif
//synopsys translate_on
endmodule
 
 
 
/hw/vlog/system/wb_xs6_ddr3_bridge.v
43,8 → 43,10
//////////////////////////////////////////////////////////////////
 
 
module wb_xs6_ddr3_bridge
(
module wb_xs6_ddr3_bridge #(
parameter WB_DWIDTH = 32,
parameter WB_SWIDTH = 4
)(
input i_clk,
 
input i_mem_ctrl, // 0=128MB, 1=32MB
51,10 → 53,10
 
// Wishbone Bus
input [31:0] i_wb_adr,
input [3:0] i_wb_sel,
input [WB_SWIDTH-1:0] i_wb_sel,
input i_wb_we,
output reg [31:0] o_wb_dat = 'd0,
input [31:0] i_wb_dat,
output reg [WB_DWIDTH-1:0] o_wb_dat = 'd0,
input [WB_DWIDTH-1:0] i_wb_dat,
input i_wb_cyc,
input i_wb_stb,
output o_wb_ack,
74,93 → 76,161
 
);
wire start_write;
wire start_read;
reg start_write_d1;
reg start_read_d1;
reg start_read_hold = 'd0;
reg [29:0] wb_adr_d1;
wire ddr3_busy;
reg read_ack = 'd0;
wire write_request;
wire read_request;
reg write_request_r;
reg read_request_r;
reg read_active_r = 'd0;
reg [29:0] wb_adr_r;
reg cmd_full_r = 1'd0;
reg read_ack_r = 'd0;
reg read_ready = 1'd1;
reg cmd_en_r = 'd0;
reg wr_en_r = 'd0;
wire write_ack;
 
assign start_write = i_wb_stb && i_wb_we && !start_read_d1;
assign start_read = i_wb_stb && !i_wb_we && read_ready;
assign ddr3_busy = i_cmd_full;// || i_wr_full;
// Buffer 1 write request
reg write_buf_r = 1'd0;
reg [WB_SWIDTH-1:0] wb_sel_buf_r = 'd0;
reg [WB_DWIDTH-1:0] wb_dat_buf_r = 'd0;
reg [31:0] wb_adr_buf_r = 'd0;
wire [WB_SWIDTH-1:0] wb_sel;
wire [WB_DWIDTH-1:0] wb_dat;
wire [31:0] wb_adr;
 
assign o_wb_err = 'd0;
 
assign write_request = i_wb_stb && i_wb_we && !read_request_r;
assign read_request = i_wb_stb && !i_wb_we && read_ready;
 
assign o_wb_err = 'd0;
 
// ------------------------------------------------------
// Outputs
// ------------------------------------------------------
always @( posedge i_clk )
cmd_full_r <= i_cmd_full;
 
// Command FIFO
always @( posedge i_clk )
if ( !ddr3_busy )
if ( !i_cmd_full )
begin
o_cmd_byte_addr <= {wb_adr_d1[29:4], 4'd0};
cmd_en_r <= ( start_write_d1 || start_read_d1 );
o_cmd_instr <= start_write_d1 ? 3'd0 : 3'd1;
o_cmd_byte_addr <= {wb_adr_r[29:4], 4'd0};
cmd_en_r <= ( write_request_r || read_request_r );
o_cmd_instr <= write_request_r ? 3'd0 : 3'd1;
end
 
assign o_cmd_en = cmd_en_r && !i_cmd_full;
 
 
// ------------------------------------------------------
// Write
// Write Buffer
// ------------------------------------------------------
always @( posedge i_clk )
if ( !ddr3_busy )
if ( i_cmd_full && write_request )
begin
wr_en_r <= start_write;
o_wr_mask <= i_wb_adr[3:2] == 2'd0 ? { 12'hfff, ~i_wb_sel } :
i_wb_adr[3:2] == 2'd1 ? { 8'hff, ~i_wb_sel, 4'hf } :
i_wb_adr[3:2] == 2'd2 ? { 4'hf, ~i_wb_sel, 8'hff } :
{ ~i_wb_sel, 12'hfff } ;
o_wr_data <= {4{i_wb_dat}};
write_buf_r <= 1'd1;
wb_sel_buf_r <= i_wb_sel;
wb_dat_buf_r <= i_wb_dat;
wb_adr_buf_r <= i_wb_adr;
end
else if ( !i_cmd_full )
write_buf_r <= 1'd0;
 
// ------------------------------------------------------
// Write
// ------------------------------------------------------
 
// Select between incoming reqiests and the write request buffer
assign wb_sel = write_buf_r ? wb_sel_buf_r : i_wb_sel;
assign wb_dat = write_buf_r ? wb_dat_buf_r : i_wb_dat;
assign wb_adr = write_buf_r ? wb_adr_buf_r : i_wb_adr;
 
 
generate
if (WB_DWIDTH == 32) begin :wb32w
 
always @( posedge i_clk )
if ( !i_cmd_full )
begin
wr_en_r <= write_request || write_buf_r;
o_wr_mask <= wb_adr[3:2] == 2'd0 ? { 12'hfff, ~wb_sel } :
wb_adr[3:2] == 2'd1 ? { 8'hff, ~wb_sel, 4'hf } :
wb_adr[3:2] == 2'd2 ? { 4'hf, ~wb_sel, 8'hff } :
{ ~wb_sel, 12'hfff } ;
o_wr_data <= {4{wb_dat}};
end
 
end
else begin : wb128w
 
always @( posedge i_clk )
if ( !i_cmd_full )
begin
wr_en_r <= write_request;
o_wr_mask <= ~wb_sel;
o_wr_data <= wb_dat;
end
 
end
endgenerate
 
assign o_wr_en = wr_en_r && !i_cmd_full;
 
 
// ------------------------------------------------------
// Read
// ------------------------------------------------------
always @( posedge i_clk )
begin
if ( read_ack )
if ( read_ack_r )
read_ready <= 1'd1;
else if ( start_read )
else if ( read_request )
read_ready <= 1'd0;
if ( !ddr3_busy )
if ( !i_cmd_full )
begin
start_write_d1 <= start_write;
start_read_d1 <= start_read;
wb_adr_d1 <= i_mem_ctrl ? {5'd0, i_wb_adr[24:0]} : i_wb_adr[29:0];
write_request_r <= write_request;
read_request_r <= read_request;
wb_adr_r <= i_mem_ctrl ? {5'd0, i_wb_adr[24:0]} : i_wb_adr[29:0];
end
if ( start_read )
start_read_hold <= 1'd1;
else if ( read_ack )
start_read_hold <= 1'd0;
if ( read_request )
read_active_r <= 1'd1;
else if ( read_ack_r )
read_active_r <= 1'd0;
if ( i_rd_empty == 1'd0 && start_read_hold )
begin
o_wb_dat <= i_wb_adr[3:2] == 2'd0 ? i_rd_data[ 31: 0] :
i_wb_adr[3:2] == 2'd1 ? i_rd_data[ 63:32] :
i_wb_adr[3:2] == 2'd2 ? i_rd_data[ 95:64] :
i_rd_data[127:96] ;
read_ack <= 1'd1;
end
if ( i_rd_empty == 1'd0 && read_active_r )
read_ack_r <= 1'd1;
else
read_ack <= 1'd0;
read_ack_r <= 1'd0;
end
assign o_wb_ack = i_wb_stb && ( start_write || read_ack ) && !i_cmd_full;
 
 
generate
if (WB_DWIDTH == 32) begin :wb32r
 
always @( posedge i_clk )
if ( !i_rd_empty && read_active_r )
o_wb_dat <= i_wb_adr[3:2] == 2'd0 ? i_rd_data[ 31: 0] :
i_wb_adr[3:2] == 2'd1 ? i_rd_data[ 63:32] :
i_wb_adr[3:2] == 2'd2 ? i_rd_data[ 95:64] :
i_rd_data[127:96] ;
 
end
else begin : wb128r
 
always @( posedge i_clk )
if ( !i_rd_empty && read_active_r )
o_wb_dat <= i_rd_data;
 
end
endgenerate
 
assign write_ack = write_request && !write_buf_r;
assign o_wb_ack = ( i_wb_stb && read_ack_r ) || write_ack;
 
endmodule
 
/hw/vlog/system/boot_mem32.v
0,0 → 1,154
//////////////////////////////////////////////////////////////////
// //
// 8KBytes SRAM configured with boot software //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Holds just enough software to get the system going. //
// The boot loader fits into this 8KB embedded SRAM on the //
// FPGA and enables it to load large applications via the //
// serial port (UART) into the DDR3 memory //
// //
// Author(s): //
// - Conor Santifort, csantifort.amber@gmail.com //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
 
 
module boot_mem32 #(
parameter WB_DWIDTH = 32,
parameter WB_SWIDTH = 4,
parameter MADDR_WIDTH = 11
)(
input i_wb_clk, // WISHBONE clock
 
input [31:0] i_wb_adr,
input [WB_SWIDTH-1:0] i_wb_sel,
input i_wb_we,
output [WB_DWIDTH-1:0] o_wb_dat,
input [WB_DWIDTH-1:0] i_wb_dat,
input i_wb_cyc,
input i_wb_stb,
output o_wb_ack,
output o_wb_err
 
);
 
wire start_write;
wire start_read;
reg start_read_r = 'd0;
wire [WB_DWIDTH-1:0] read_data;
wire [WB_DWIDTH-1:0] write_data;
wire [WB_SWIDTH-1:0] byte_enable;
wire [MADDR_WIDTH-1:0] address;
 
 
// Can't start a write while a read is completing. The ack for the read cycle
// needs to be sent first
assign start_write = i_wb_stb && i_wb_we && !start_read_r;
assign start_read = i_wb_stb && !i_wb_we && !start_read_r;
 
 
always @( posedge i_wb_clk )
start_read_r <= start_read;
 
assign o_wb_err = 1'd0;
 
assign write_data = i_wb_dat;
assign byte_enable = i_wb_sel;
assign o_wb_dat = read_data;
assign address = i_wb_adr[MADDR_WIDTH+1:2];
assign o_wb_ack = i_wb_stb && ( start_write || start_read_r );
 
// ------------------------------------------------------
// Instantiate SRAMs
// ------------------------------------------------------
//
`ifdef XILINX_FPGA
 
`ifdef XILINX_SPARTAN6_FPGA
xs6_sram_2048x32_byte_en
`endif
`ifdef XILINX_VIRTEX6_FPGA
xv6_sram_2048x32_byte_en
`endif
 
#(
// This file holds a software image used for FPGA simulations
// This pre-processor syntax works with both the simulator
// and ISE, which I couldn't get to work with giving it the
// file name as a define.
 
`ifdef BOOT_MEM_PARAMS_FILE
`include `BOOT_MEM_PARAMS_FILE
`else
// default file
`include "boot-loader_memparams32.v"
`endif
 
)
`endif
 
`ifndef XILINX_FPGA
generic_sram_byte_en
#(
.DATA_WIDTH ( WB_DWIDTH ),
.ADDRESS_WIDTH ( MADDR_WIDTH )
)
`endif
u_mem (
.i_clk ( i_wb_clk ),
.i_write_enable ( start_write ),
.i_byte_enable ( byte_enable ),
.i_address ( address ), // 2048 words, 32 bits
.o_read_data ( read_data ),
.i_write_data ( write_data )
);
 
 
// =======================================================================================
// =======================================================================================
// =======================================================================================
// Non-synthesizable debug code
// =======================================================================================
 
 
//synopsys translate_off
`ifdef XILINX_SPARTAN6_FPGA
`ifdef BOOT_MEM_PARAMS_FILE
initial
$display("Boot mem file is %s", `BOOT_MEM_PARAMS_FILE );
`endif
`endif
//synopsys translate_on
endmodule
 
 
/hw/vlog/tb/global_defines.v
70,8 → 70,10
`define U_MEM `U_AMBER.u_mem
`define U_DCACHE `U_MEM.u_dcache
`define U_WISHBONE `U_AMBER.u_wishbone
`define U_BOOT_MEM `U_SYSTEM.boot_mem128.u_boot_mem
`else
`define U_WISHBONE `U_FETCH.u_wishbone
`define U_BOOT_MEM `U_SYSTEM.boot_mem32.u_boot_mem
`endif
// ---------------------------------------------------------------
 
/hw/vlog/tb/tb.v
71,11 → 71,11
integer boot_mem_file;
reg [31:0] boot_mem_file_address;
reg [31:0] boot_mem_file_data;
reg [127:0] boot_mem_file_data_128;
integer boot_mem_line_count;
integer fgets_return;
reg [120*8-1:0] line;
reg [120*8-1:0] aligned_line;
reg [8*16-1:0] test_name;
integer timeout = 0;
 
wire [12:0] ddr3_addr;
273,9 → 273,9
// ======================================
// Initialize Boot Memory
// ======================================
`ifndef XILINX_FPGA
initial
begin
`ifndef XILINX_FPGA
$display("Load boot memory from %s", `BOOT_MEM_FILE);
boot_mem_line_count = 0;
boot_mem_file = $fopen(`BOOT_MEM_FILE, "r");
310,8 → 310,16
boot_mem_file_address = hex_chars_to_32bits (aligned_line[119*8-1:111*8]);
boot_mem_file_data = hex_chars_to_32bits (aligned_line[110*8-1:102*8]);
tb.u_system.u_boot_mem.u_mem.mem [boot_mem_file_address[12:2]] = boot_mem_file_data;
 
`ifdef AMBER_A25_CORE
boot_mem_file_data_128 = `U_BOOT_MEM.u_mem.mem[boot_mem_file_address[12:4]];
`U_BOOT_MEM.u_mem.mem[boot_mem_file_address[12:4]] =
insert_32_into_128 ( boot_mem_file_address[3:2],
boot_mem_file_data_128,
boot_mem_file_data );
`else
`U_BOOT_MEM.u_mem.mem[boot_mem_file_address[12:2]] = boot_mem_file_data;
`endif
`ifdef AMBER_LOAD_MEM_DEBUG
$display ("Load Boot Mem: PAddr: 0x%08x, Data 0x%08x",
boot_mem_file_address, boot_mem_file_data);
322,18 → 330,14
$display("Read in %1d lines", boot_mem_line_count);
end
`endif
// Grab the test name from memory
timeout = tb.u_system.u_boot_mem.u_mem.mem [11'h7fb];
test_name = { endian_x32(tb.u_system.u_boot_mem.u_mem.mem [11'h7fc]),
endian_x32(tb.u_system.u_boot_mem.u_mem.mem [11'h7fd]),
endian_x32(tb.u_system.u_boot_mem.u_mem.mem [11'h7fe]),
endian_x32(tb.u_system.u_boot_mem.u_mem.mem [11'h7ff])};
$display("log file %s, timeout %0d, test name %0s ", `AMBER_LOG_FILE, timeout, test_name);
timeout = `AMBER_TIMEOUT ;
$display("log file %s, timeout %0d, test name %0s ", `AMBER_LOG_FILE, timeout, `AMBER_TEST_NAME );
log_file = $fopen(`AMBER_LOG_FILE, "a");
end
`endif
 
 
// ======================================
463,9 → 467,9
begin
display_registers;
$display("++++++++++++++++++++");
$write("Passed %s %0d ticks\n", test_name, `U_TB.clk_count);
$write("Passed %s %0d ticks\n", `AMBER_TEST_NAME, `U_TB.clk_count);
$display("++++++++++++++++++++");
$fwrite(`U_TB.log_file,"Passed %s %0d ticks\n", test_name, `U_TB.clk_count);
$fwrite(`U_TB.log_file,"Passed %s %0d ticks\n", `AMBER_TEST_NAME, `U_TB.clk_count);
$finish;
end
else
474,9 → 478,9
if ( testfail )
begin
$display("++++++++++++++++++++");
$write("Failed %s\n", test_name);
$write("Failed %s\n", `AMBER_TEST_NAME);
$display("++++++++++++++++++++");
$fwrite(`U_TB.log_file,"Failed %s\n", test_name);
$fwrite(`U_TB.log_file,"Failed %s\n", `AMBER_TEST_NAME);
$finish;
end
else
483,14 → 487,14
begin
$display("++++++++++++++++++++");
if (test_status_reg >= 32'h8000)
$write("Failed %s - with error 0x%08x\n", test_name, test_status_reg);
$write("Failed %s - with error 0x%08x\n", `AMBER_TEST_NAME, test_status_reg);
else
$write("Failed %s - with error on line %1d\n", test_name, test_status_reg);
$write("Failed %s - with error on line %1d\n", `AMBER_TEST_NAME, test_status_reg);
$display("++++++++++++++++++++");
if (test_status_reg >= 32'h8000)
$fwrite(`U_TB.log_file,"Failed %s - with error 0x%08h\n", test_name, test_status_reg);
$fwrite(`U_TB.log_file,"Failed %s - with error 0x%08h\n", `AMBER_TEST_NAME, test_status_reg);
else
$fwrite(`U_TB.log_file,"Failed %s - with error on line %1d\n", test_name, test_status_reg);
$fwrite(`U_TB.log_file,"Failed %s - with error on line %1d\n", `AMBER_TEST_NAME, test_status_reg);
$finish;
end
end
/hw/vlog/lib/xs6_sram_512x128_byte_en.v
0,0 → 1,798
//////////////////////////////////////////////////////////////////
// //
// Wrapper for Xilinx Spartan-6 RAM Block //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// 512 words x 128 bits with a per byte write enable //
// //
// Author(s): //
// - Conor Santifort, csantifort.amber@gmail.com //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
 
 
module xs6_sram_512x128_byte_en
#(
parameter SRAM0_INIT_0 = 256'h0,
parameter SRAM0_INIT_1 = 256'h0,
parameter SRAM0_INIT_2 = 256'h0,
parameter SRAM0_INIT_3 = 256'h0,
parameter SRAM0_INIT_4 = 256'h0,
parameter SRAM0_INIT_5 = 256'h0,
parameter SRAM0_INIT_6 = 256'h0,
parameter SRAM0_INIT_7 = 256'h0,
parameter SRAM0_INIT_8 = 256'h0,
parameter SRAM0_INIT_9 = 256'h0,
parameter SRAM0_INIT_10 = 256'h0,
parameter SRAM0_INIT_11 = 256'h0,
parameter SRAM0_INIT_12 = 256'h0,
parameter SRAM0_INIT_13 = 256'h0,
parameter SRAM0_INIT_14 = 256'h0,
parameter SRAM0_INIT_15 = 256'h0,
parameter SRAM0_INIT_16 = 256'h0,
parameter SRAM0_INIT_17 = 256'h0,
parameter SRAM0_INIT_18 = 256'h0,
parameter SRAM0_INIT_19 = 256'h0,
parameter SRAM0_INIT_20 = 256'h0,
parameter SRAM0_INIT_21 = 256'h0,
parameter SRAM0_INIT_22 = 256'h0,
parameter SRAM0_INIT_23 = 256'h0,
parameter SRAM0_INIT_24 = 256'h0,
parameter SRAM0_INIT_25 = 256'h0,
parameter SRAM0_INIT_26 = 256'h0,
parameter SRAM0_INIT_27 = 256'h0,
parameter SRAM0_INIT_28 = 256'h0,
parameter SRAM0_INIT_29 = 256'h0,
parameter SRAM0_INIT_30 = 256'h0,
parameter SRAM0_INIT_31 = 256'h0,
parameter SRAM0_INIT_32 = 256'h0,
parameter SRAM0_INIT_33 = 256'h0,
parameter SRAM0_INIT_34 = 256'h0,
parameter SRAM0_INIT_35 = 256'h0,
parameter SRAM0_INIT_36 = 256'h0,
parameter SRAM0_INIT_37 = 256'h0,
parameter SRAM0_INIT_38 = 256'h0,
parameter SRAM0_INIT_39 = 256'h0,
parameter SRAM0_INIT_40 = 256'h0,
parameter SRAM0_INIT_41 = 256'h0,
parameter SRAM0_INIT_42 = 256'h0,
parameter SRAM0_INIT_43 = 256'h0,
parameter SRAM0_INIT_44 = 256'h0,
parameter SRAM0_INIT_45 = 256'h0,
parameter SRAM0_INIT_46 = 256'h0,
parameter SRAM0_INIT_47 = 256'h0,
parameter SRAM0_INIT_48 = 256'h0,
parameter SRAM0_INIT_49 = 256'h0,
parameter SRAM0_INIT_50 = 256'h0,
parameter SRAM0_INIT_51 = 256'h0,
parameter SRAM0_INIT_52 = 256'h0,
parameter SRAM0_INIT_53 = 256'h0,
parameter SRAM0_INIT_54 = 256'h0,
parameter SRAM0_INIT_55 = 256'h0,
parameter SRAM0_INIT_56 = 256'h0,
parameter SRAM0_INIT_57 = 256'h0,
parameter SRAM0_INIT_58 = 256'h0,
parameter SRAM0_INIT_59 = 256'h0,
parameter SRAM0_INIT_60 = 256'h0,
parameter SRAM0_INIT_61 = 256'h0,
parameter SRAM0_INIT_62 = 256'h0,
parameter SRAM0_INIT_63 = 256'h0,
 
 
parameter SRAM1_INIT_0 = 256'h0,
parameter SRAM1_INIT_1 = 256'h0,
parameter SRAM1_INIT_2 = 256'h0,
parameter SRAM1_INIT_3 = 256'h0,
parameter SRAM1_INIT_4 = 256'h0,
parameter SRAM1_INIT_5 = 256'h0,
parameter SRAM1_INIT_6 = 256'h0,
parameter SRAM1_INIT_7 = 256'h0,
parameter SRAM1_INIT_8 = 256'h0,
parameter SRAM1_INIT_9 = 256'h0,
parameter SRAM1_INIT_10 = 256'h0,
parameter SRAM1_INIT_11 = 256'h0,
parameter SRAM1_INIT_12 = 256'h0,
parameter SRAM1_INIT_13 = 256'h0,
parameter SRAM1_INIT_14 = 256'h0,
parameter SRAM1_INIT_15 = 256'h0,
parameter SRAM1_INIT_16 = 256'h0,
parameter SRAM1_INIT_17 = 256'h0,
parameter SRAM1_INIT_18 = 256'h0,
parameter SRAM1_INIT_19 = 256'h0,
parameter SRAM1_INIT_20 = 256'h0,
parameter SRAM1_INIT_21 = 256'h0,
parameter SRAM1_INIT_22 = 256'h0,
parameter SRAM1_INIT_23 = 256'h0,
parameter SRAM1_INIT_24 = 256'h0,
parameter SRAM1_INIT_25 = 256'h0,
parameter SRAM1_INIT_26 = 256'h0,
parameter SRAM1_INIT_27 = 256'h0,
parameter SRAM1_INIT_28 = 256'h0,
parameter SRAM1_INIT_29 = 256'h0,
parameter SRAM1_INIT_30 = 256'h0,
parameter SRAM1_INIT_31 = 256'h0,
parameter SRAM1_INIT_32 = 256'h0,
parameter SRAM1_INIT_33 = 256'h0,
parameter SRAM1_INIT_34 = 256'h0,
parameter SRAM1_INIT_35 = 256'h0,
parameter SRAM1_INIT_36 = 256'h0,
parameter SRAM1_INIT_37 = 256'h0,
parameter SRAM1_INIT_38 = 256'h0,
parameter SRAM1_INIT_39 = 256'h0,
parameter SRAM1_INIT_40 = 256'h0,
parameter SRAM1_INIT_41 = 256'h0,
parameter SRAM1_INIT_42 = 256'h0,
parameter SRAM1_INIT_43 = 256'h0,
parameter SRAM1_INIT_44 = 256'h0,
parameter SRAM1_INIT_45 = 256'h0,
parameter SRAM1_INIT_46 = 256'h0,
parameter SRAM1_INIT_47 = 256'h0,
parameter SRAM1_INIT_48 = 256'h0,
parameter SRAM1_INIT_49 = 256'h0,
parameter SRAM1_INIT_50 = 256'h0,
parameter SRAM1_INIT_51 = 256'h0,
parameter SRAM1_INIT_52 = 256'h0,
parameter SRAM1_INIT_53 = 256'h0,
parameter SRAM1_INIT_54 = 256'h0,
parameter SRAM1_INIT_55 = 256'h0,
parameter SRAM1_INIT_56 = 256'h0,
parameter SRAM1_INIT_57 = 256'h0,
parameter SRAM1_INIT_58 = 256'h0,
parameter SRAM1_INIT_59 = 256'h0,
parameter SRAM1_INIT_60 = 256'h0,
parameter SRAM1_INIT_61 = 256'h0,
parameter SRAM1_INIT_62 = 256'h0,
parameter SRAM1_INIT_63 = 256'h0,
 
 
 
parameter SRAM2_INIT_0 = 256'h0,
parameter SRAM2_INIT_1 = 256'h0,
parameter SRAM2_INIT_2 = 256'h0,
parameter SRAM2_INIT_3 = 256'h0,
parameter SRAM2_INIT_4 = 256'h0,
parameter SRAM2_INIT_5 = 256'h0,
parameter SRAM2_INIT_6 = 256'h0,
parameter SRAM2_INIT_7 = 256'h0,
parameter SRAM2_INIT_8 = 256'h0,
parameter SRAM2_INIT_9 = 256'h0,
parameter SRAM2_INIT_10 = 256'h0,
parameter SRAM2_INIT_11 = 256'h0,
parameter SRAM2_INIT_12 = 256'h0,
parameter SRAM2_INIT_13 = 256'h0,
parameter SRAM2_INIT_14 = 256'h0,
parameter SRAM2_INIT_15 = 256'h0,
parameter SRAM2_INIT_16 = 256'h0,
parameter SRAM2_INIT_17 = 256'h0,
parameter SRAM2_INIT_18 = 256'h0,
parameter SRAM2_INIT_19 = 256'h0,
parameter SRAM2_INIT_20 = 256'h0,
parameter SRAM2_INIT_21 = 256'h0,
parameter SRAM2_INIT_22 = 256'h0,
parameter SRAM2_INIT_23 = 256'h0,
parameter SRAM2_INIT_24 = 256'h0,
parameter SRAM2_INIT_25 = 256'h0,
parameter SRAM2_INIT_26 = 256'h0,
parameter SRAM2_INIT_27 = 256'h0,
parameter SRAM2_INIT_28 = 256'h0,
parameter SRAM2_INIT_29 = 256'h0,
parameter SRAM2_INIT_30 = 256'h0,
parameter SRAM2_INIT_31 = 256'h0,
parameter SRAM2_INIT_32 = 256'h0,
parameter SRAM2_INIT_33 = 256'h0,
parameter SRAM2_INIT_34 = 256'h0,
parameter SRAM2_INIT_35 = 256'h0,
parameter SRAM2_INIT_36 = 256'h0,
parameter SRAM2_INIT_37 = 256'h0,
parameter SRAM2_INIT_38 = 256'h0,
parameter SRAM2_INIT_39 = 256'h0,
parameter SRAM2_INIT_40 = 256'h0,
parameter SRAM2_INIT_41 = 256'h0,
parameter SRAM2_INIT_42 = 256'h0,
parameter SRAM2_INIT_43 = 256'h0,
parameter SRAM2_INIT_44 = 256'h0,
parameter SRAM2_INIT_45 = 256'h0,
parameter SRAM2_INIT_46 = 256'h0,
parameter SRAM2_INIT_47 = 256'h0,
parameter SRAM2_INIT_48 = 256'h0,
parameter SRAM2_INIT_49 = 256'h0,
parameter SRAM2_INIT_50 = 256'h0,
parameter SRAM2_INIT_51 = 256'h0,
parameter SRAM2_INIT_52 = 256'h0,
parameter SRAM2_INIT_53 = 256'h0,
parameter SRAM2_INIT_54 = 256'h0,
parameter SRAM2_INIT_55 = 256'h0,
parameter SRAM2_INIT_56 = 256'h0,
parameter SRAM2_INIT_57 = 256'h0,
parameter SRAM2_INIT_58 = 256'h0,
parameter SRAM2_INIT_59 = 256'h0,
parameter SRAM2_INIT_60 = 256'h0,
parameter SRAM2_INIT_61 = 256'h0,
parameter SRAM2_INIT_62 = 256'h0,
parameter SRAM2_INIT_63 = 256'h0,
 
parameter SRAM3_INIT_0 = 256'h0,
parameter SRAM3_INIT_1 = 256'h0,
parameter SRAM3_INIT_2 = 256'h0,
parameter SRAM3_INIT_3 = 256'h0,
parameter SRAM3_INIT_4 = 256'h0,
parameter SRAM3_INIT_5 = 256'h0,
parameter SRAM3_INIT_6 = 256'h0,
parameter SRAM3_INIT_7 = 256'h0,
parameter SRAM3_INIT_8 = 256'h0,
parameter SRAM3_INIT_9 = 256'h0,
parameter SRAM3_INIT_10 = 256'h0,
parameter SRAM3_INIT_11 = 256'h0,
parameter SRAM3_INIT_12 = 256'h0,
parameter SRAM3_INIT_13 = 256'h0,
parameter SRAM3_INIT_14 = 256'h0,
parameter SRAM3_INIT_15 = 256'h0,
parameter SRAM3_INIT_16 = 256'h0,
parameter SRAM3_INIT_17 = 256'h0,
parameter SRAM3_INIT_18 = 256'h0,
parameter SRAM3_INIT_19 = 256'h0,
parameter SRAM3_INIT_20 = 256'h0,
parameter SRAM3_INIT_21 = 256'h0,
parameter SRAM3_INIT_22 = 256'h0,
parameter SRAM3_INIT_23 = 256'h0,
parameter SRAM3_INIT_24 = 256'h0,
parameter SRAM3_INIT_25 = 256'h0,
parameter SRAM3_INIT_26 = 256'h0,
parameter SRAM3_INIT_27 = 256'h0,
parameter SRAM3_INIT_28 = 256'h0,
parameter SRAM3_INIT_29 = 256'h0,
parameter SRAM3_INIT_30 = 256'h0,
parameter SRAM3_INIT_31 = 256'h0,
parameter SRAM3_INIT_32 = 256'h0,
parameter SRAM3_INIT_33 = 256'h0,
parameter SRAM3_INIT_34 = 256'h0,
parameter SRAM3_INIT_35 = 256'h0,
parameter SRAM3_INIT_36 = 256'h0,
parameter SRAM3_INIT_37 = 256'h0,
parameter SRAM3_INIT_38 = 256'h0,
parameter SRAM3_INIT_39 = 256'h0,
parameter SRAM3_INIT_40 = 256'h0,
parameter SRAM3_INIT_41 = 256'h0,
parameter SRAM3_INIT_42 = 256'h0,
parameter SRAM3_INIT_43 = 256'h0,
parameter SRAM3_INIT_44 = 256'h0,
parameter SRAM3_INIT_45 = 256'h0,
parameter SRAM3_INIT_46 = 256'h0,
parameter SRAM3_INIT_47 = 256'h0,
parameter SRAM3_INIT_48 = 256'h0,
parameter SRAM3_INIT_49 = 256'h0,
parameter SRAM3_INIT_50 = 256'h0,
parameter SRAM3_INIT_51 = 256'h0,
parameter SRAM3_INIT_52 = 256'h0,
parameter SRAM3_INIT_53 = 256'h0,
parameter SRAM3_INIT_54 = 256'h0,
parameter SRAM3_INIT_55 = 256'h0,
parameter SRAM3_INIT_56 = 256'h0,
parameter SRAM3_INIT_57 = 256'h0,
parameter SRAM3_INIT_58 = 256'h0,
parameter SRAM3_INIT_59 = 256'h0,
parameter SRAM3_INIT_60 = 256'h0,
parameter SRAM3_INIT_61 = 256'h0,
parameter SRAM3_INIT_62 = 256'h0,
parameter SRAM3_INIT_63 = 256'h0,
 
parameter UNUSED = 1'd1
 
)
 
(
input i_clk,
input [127:0] i_write_data,
input i_write_enable,
input [8:0] i_address,
input [15:0] i_byte_enable,
output [127:0] o_read_data
 
);
 
wire [23:0] nc24_00, nc24_01, nc24_02, nc24_03;
wire [15:0] wea;
 
assign wea = {16{i_write_enable}} & i_byte_enable;
 
 
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
 
.INIT_00 ( SRAM0_INIT_0 ),
.INIT_01 ( SRAM0_INIT_1 ),
.INIT_02 ( SRAM0_INIT_2 ),
.INIT_03 ( SRAM0_INIT_3 ),
.INIT_04 ( SRAM0_INIT_4 ),
.INIT_05 ( SRAM0_INIT_5 ),
.INIT_06 ( SRAM0_INIT_6 ),
.INIT_07 ( SRAM0_INIT_7 ),
.INIT_08 ( SRAM0_INIT_8 ),
.INIT_09 ( SRAM0_INIT_9 ),
.INIT_0A ( SRAM0_INIT_10 ),
.INIT_0B ( SRAM0_INIT_11 ),
.INIT_0C ( SRAM0_INIT_12 ),
.INIT_0D ( SRAM0_INIT_13 ),
.INIT_0E ( SRAM0_INIT_14 ),
.INIT_0F ( SRAM0_INIT_15 ),
.INIT_10 ( SRAM0_INIT_16 ),
.INIT_11 ( SRAM0_INIT_17 ),
.INIT_12 ( SRAM0_INIT_18 ),
.INIT_13 ( SRAM0_INIT_19 ),
.INIT_14 ( SRAM0_INIT_20 ),
.INIT_15 ( SRAM0_INIT_21 ),
.INIT_16 ( SRAM0_INIT_22 ),
.INIT_17 ( SRAM0_INIT_23 ),
.INIT_18 ( SRAM0_INIT_24 ),
.INIT_19 ( SRAM0_INIT_25 ),
.INIT_1A ( SRAM0_INIT_26 ),
.INIT_1B ( SRAM0_INIT_27 ),
.INIT_1C ( SRAM0_INIT_28 ),
.INIT_1D ( SRAM0_INIT_29 ),
.INIT_1E ( SRAM0_INIT_30 ),
.INIT_1F ( SRAM0_INIT_31 ),
.INIT_20 ( SRAM0_INIT_32 ),
.INIT_21 ( SRAM0_INIT_33 ),
.INIT_22 ( SRAM0_INIT_34 ),
.INIT_23 ( SRAM0_INIT_35 ),
.INIT_24 ( SRAM0_INIT_36 ),
.INIT_25 ( SRAM0_INIT_37 ),
.INIT_26 ( SRAM0_INIT_38 ),
.INIT_27 ( SRAM0_INIT_39 ),
.INIT_28 ( SRAM0_INIT_40 ),
.INIT_29 ( SRAM0_INIT_41 ),
.INIT_2A ( SRAM0_INIT_42 ),
.INIT_2B ( SRAM0_INIT_43 ),
.INIT_2C ( SRAM0_INIT_44 ),
.INIT_2D ( SRAM0_INIT_45 ),
.INIT_2E ( SRAM0_INIT_46 ),
.INIT_2F ( SRAM0_INIT_47 ),
.INIT_30 ( SRAM0_INIT_48 ),
.INIT_31 ( SRAM0_INIT_49 ),
.INIT_32 ( SRAM0_INIT_50 ),
.INIT_33 ( SRAM0_INIT_51 ),
.INIT_34 ( SRAM0_INIT_52 ),
.INIT_35 ( SRAM0_INIT_53 ),
.INIT_36 ( SRAM0_INIT_54 ),
.INIT_37 ( SRAM0_INIT_55 ),
.INIT_38 ( SRAM0_INIT_56 ),
.INIT_39 ( SRAM0_INIT_57 ),
.INIT_3A ( SRAM0_INIT_58 ),
.INIT_3B ( SRAM0_INIT_59 ),
.INIT_3C ( SRAM0_INIT_60 ),
.INIT_3D ( SRAM0_INIT_61 ),
.INIT_3E ( SRAM0_INIT_62 ),
.INIT_3F ( SRAM0_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram0 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea[3:0] ),
.DOA ( o_read_data[31:0] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[31:0] )
);
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
 
.INIT_00 ( SRAM1_INIT_0 ),
.INIT_01 ( SRAM1_INIT_1 ),
.INIT_02 ( SRAM1_INIT_2 ),
.INIT_03 ( SRAM1_INIT_3 ),
.INIT_04 ( SRAM1_INIT_4 ),
.INIT_05 ( SRAM1_INIT_5 ),
.INIT_06 ( SRAM1_INIT_6 ),
.INIT_07 ( SRAM1_INIT_7 ),
.INIT_08 ( SRAM1_INIT_8 ),
.INIT_09 ( SRAM1_INIT_9 ),
.INIT_0A ( SRAM1_INIT_10 ),
.INIT_0B ( SRAM1_INIT_11 ),
.INIT_0C ( SRAM1_INIT_12 ),
.INIT_0D ( SRAM1_INIT_13 ),
.INIT_0E ( SRAM1_INIT_14 ),
.INIT_0F ( SRAM1_INIT_15 ),
.INIT_10 ( SRAM1_INIT_16 ),
.INIT_11 ( SRAM1_INIT_17 ),
.INIT_12 ( SRAM1_INIT_18 ),
.INIT_13 ( SRAM1_INIT_19 ),
.INIT_14 ( SRAM1_INIT_20 ),
.INIT_15 ( SRAM1_INIT_21 ),
.INIT_16 ( SRAM1_INIT_22 ),
.INIT_17 ( SRAM1_INIT_23 ),
.INIT_18 ( SRAM1_INIT_24 ),
.INIT_19 ( SRAM1_INIT_25 ),
.INIT_1A ( SRAM1_INIT_26 ),
.INIT_1B ( SRAM1_INIT_27 ),
.INIT_1C ( SRAM1_INIT_28 ),
.INIT_1D ( SRAM1_INIT_29 ),
.INIT_1E ( SRAM1_INIT_30 ),
.INIT_1F ( SRAM1_INIT_31 ),
.INIT_20 ( SRAM1_INIT_32 ),
.INIT_21 ( SRAM1_INIT_33 ),
.INIT_22 ( SRAM1_INIT_34 ),
.INIT_23 ( SRAM1_INIT_35 ),
.INIT_24 ( SRAM1_INIT_36 ),
.INIT_25 ( SRAM1_INIT_37 ),
.INIT_26 ( SRAM1_INIT_38 ),
.INIT_27 ( SRAM1_INIT_39 ),
.INIT_28 ( SRAM1_INIT_40 ),
.INIT_29 ( SRAM1_INIT_41 ),
.INIT_2A ( SRAM1_INIT_42 ),
.INIT_2B ( SRAM1_INIT_43 ),
.INIT_2C ( SRAM1_INIT_44 ),
.INIT_2D ( SRAM1_INIT_45 ),
.INIT_2E ( SRAM1_INIT_46 ),
.INIT_2F ( SRAM1_INIT_47 ),
.INIT_30 ( SRAM1_INIT_48 ),
.INIT_31 ( SRAM1_INIT_49 ),
.INIT_32 ( SRAM1_INIT_50 ),
.INIT_33 ( SRAM1_INIT_51 ),
.INIT_34 ( SRAM1_INIT_52 ),
.INIT_35 ( SRAM1_INIT_53 ),
.INIT_36 ( SRAM1_INIT_54 ),
.INIT_37 ( SRAM1_INIT_55 ),
.INIT_38 ( SRAM1_INIT_56 ),
.INIT_39 ( SRAM1_INIT_57 ),
.INIT_3A ( SRAM1_INIT_58 ),
.INIT_3B ( SRAM1_INIT_59 ),
.INIT_3C ( SRAM1_INIT_60 ),
.INIT_3D ( SRAM1_INIT_61 ),
.INIT_3E ( SRAM1_INIT_62 ),
.INIT_3F ( SRAM1_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram1 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea[7:4] ),
.DOA ( o_read_data[63:32] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[63:32] )
);
 
 
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
 
.INIT_00 ( SRAM2_INIT_0 ),
.INIT_01 ( SRAM2_INIT_1 ),
.INIT_02 ( SRAM2_INIT_2 ),
.INIT_03 ( SRAM2_INIT_3 ),
.INIT_04 ( SRAM2_INIT_4 ),
.INIT_05 ( SRAM2_INIT_5 ),
.INIT_06 ( SRAM2_INIT_6 ),
.INIT_07 ( SRAM2_INIT_7 ),
.INIT_08 ( SRAM2_INIT_8 ),
.INIT_09 ( SRAM2_INIT_9 ),
.INIT_0A ( SRAM2_INIT_10 ),
.INIT_0B ( SRAM2_INIT_11 ),
.INIT_0C ( SRAM2_INIT_12 ),
.INIT_0D ( SRAM2_INIT_13 ),
.INIT_0E ( SRAM2_INIT_14 ),
.INIT_0F ( SRAM2_INIT_15 ),
.INIT_10 ( SRAM2_INIT_16 ),
.INIT_11 ( SRAM2_INIT_17 ),
.INIT_12 ( SRAM2_INIT_18 ),
.INIT_13 ( SRAM2_INIT_19 ),
.INIT_14 ( SRAM2_INIT_20 ),
.INIT_15 ( SRAM2_INIT_21 ),
.INIT_16 ( SRAM2_INIT_22 ),
.INIT_17 ( SRAM2_INIT_23 ),
.INIT_18 ( SRAM2_INIT_24 ),
.INIT_19 ( SRAM2_INIT_25 ),
.INIT_1A ( SRAM2_INIT_26 ),
.INIT_1B ( SRAM2_INIT_27 ),
.INIT_1C ( SRAM2_INIT_28 ),
.INIT_1D ( SRAM2_INIT_29 ),
.INIT_1E ( SRAM2_INIT_30 ),
.INIT_1F ( SRAM2_INIT_31 ),
.INIT_20 ( SRAM2_INIT_32 ),
.INIT_21 ( SRAM2_INIT_33 ),
.INIT_22 ( SRAM2_INIT_34 ),
.INIT_23 ( SRAM2_INIT_35 ),
.INIT_24 ( SRAM2_INIT_36 ),
.INIT_25 ( SRAM2_INIT_37 ),
.INIT_26 ( SRAM2_INIT_38 ),
.INIT_27 ( SRAM2_INIT_39 ),
.INIT_28 ( SRAM2_INIT_40 ),
.INIT_29 ( SRAM2_INIT_41 ),
.INIT_2A ( SRAM2_INIT_42 ),
.INIT_2B ( SRAM2_INIT_43 ),
.INIT_2C ( SRAM2_INIT_44 ),
.INIT_2D ( SRAM2_INIT_45 ),
.INIT_2E ( SRAM2_INIT_46 ),
.INIT_2F ( SRAM2_INIT_47 ),
.INIT_30 ( SRAM2_INIT_48 ),
.INIT_31 ( SRAM2_INIT_49 ),
.INIT_32 ( SRAM2_INIT_50 ),
.INIT_33 ( SRAM2_INIT_51 ),
.INIT_34 ( SRAM2_INIT_52 ),
.INIT_35 ( SRAM2_INIT_53 ),
.INIT_36 ( SRAM2_INIT_54 ),
.INIT_37 ( SRAM2_INIT_55 ),
.INIT_38 ( SRAM2_INIT_56 ),
.INIT_39 ( SRAM2_INIT_57 ),
.INIT_3A ( SRAM2_INIT_58 ),
.INIT_3B ( SRAM2_INIT_59 ),
.INIT_3C ( SRAM2_INIT_60 ),
.INIT_3D ( SRAM2_INIT_61 ),
.INIT_3E ( SRAM2_INIT_62 ),
.INIT_3F ( SRAM2_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram2 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea[11:8] ),
.DOA ( o_read_data[95:64] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[95:64] )
);
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
 
.INIT_00 ( SRAM3_INIT_0 ),
.INIT_01 ( SRAM3_INIT_1 ),
.INIT_02 ( SRAM3_INIT_2 ),
.INIT_03 ( SRAM3_INIT_3 ),
.INIT_04 ( SRAM3_INIT_4 ),
.INIT_05 ( SRAM3_INIT_5 ),
.INIT_06 ( SRAM3_INIT_6 ),
.INIT_07 ( SRAM3_INIT_7 ),
.INIT_08 ( SRAM3_INIT_8 ),
.INIT_09 ( SRAM3_INIT_9 ),
.INIT_0A ( SRAM3_INIT_10 ),
.INIT_0B ( SRAM3_INIT_11 ),
.INIT_0C ( SRAM3_INIT_12 ),
.INIT_0D ( SRAM3_INIT_13 ),
.INIT_0E ( SRAM3_INIT_14 ),
.INIT_0F ( SRAM3_INIT_15 ),
.INIT_10 ( SRAM3_INIT_16 ),
.INIT_11 ( SRAM3_INIT_17 ),
.INIT_12 ( SRAM3_INIT_18 ),
.INIT_13 ( SRAM3_INIT_19 ),
.INIT_14 ( SRAM3_INIT_20 ),
.INIT_15 ( SRAM3_INIT_21 ),
.INIT_16 ( SRAM3_INIT_22 ),
.INIT_17 ( SRAM3_INIT_23 ),
.INIT_18 ( SRAM3_INIT_24 ),
.INIT_19 ( SRAM3_INIT_25 ),
.INIT_1A ( SRAM3_INIT_26 ),
.INIT_1B ( SRAM3_INIT_27 ),
.INIT_1C ( SRAM3_INIT_28 ),
.INIT_1D ( SRAM3_INIT_29 ),
.INIT_1E ( SRAM3_INIT_30 ),
.INIT_1F ( SRAM3_INIT_31 ),
.INIT_20 ( SRAM3_INIT_32 ),
.INIT_21 ( SRAM3_INIT_33 ),
.INIT_22 ( SRAM3_INIT_34 ),
.INIT_23 ( SRAM3_INIT_35 ),
.INIT_24 ( SRAM3_INIT_36 ),
.INIT_25 ( SRAM3_INIT_37 ),
.INIT_26 ( SRAM3_INIT_38 ),
.INIT_27 ( SRAM3_INIT_39 ),
.INIT_28 ( SRAM3_INIT_40 ),
.INIT_29 ( SRAM3_INIT_41 ),
.INIT_2A ( SRAM3_INIT_42 ),
.INIT_2B ( SRAM3_INIT_43 ),
.INIT_2C ( SRAM3_INIT_44 ),
.INIT_2D ( SRAM3_INIT_45 ),
.INIT_2E ( SRAM3_INIT_46 ),
.INIT_2F ( SRAM3_INIT_47 ),
.INIT_30 ( SRAM3_INIT_48 ),
.INIT_31 ( SRAM3_INIT_49 ),
.INIT_32 ( SRAM3_INIT_50 ),
.INIT_33 ( SRAM3_INIT_51 ),
.INIT_34 ( SRAM3_INIT_52 ),
.INIT_35 ( SRAM3_INIT_53 ),
.INIT_36 ( SRAM3_INIT_54 ),
.INIT_37 ( SRAM3_INIT_55 ),
.INIT_38 ( SRAM3_INIT_56 ),
.INIT_39 ( SRAM3_INIT_57 ),
.INIT_3A ( SRAM3_INIT_58 ),
.INIT_3B ( SRAM3_INIT_59 ),
.INIT_3C ( SRAM3_INIT_60 ),
.INIT_3D ( SRAM3_INIT_61 ),
.INIT_3E ( SRAM3_INIT_62 ),
.INIT_3F ( SRAM3_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram3 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea[15:12] ),
.DOA ( o_read_data[127:96] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[127:96] )
);
 
 
endmodule
/hw/vlog/amber25/a25_wishbone_buf.v
89,7 → 89,7
// Access Buffer
// ----------------------------------------------------
always @(posedge i_clk)
if (!wbuf_used_r && i_req)
if (i_req && !wbuf_used_r)
begin
wbuf_used_r <= !i_accepted;
wbuf_wdata_r <= i_wdata;
97,6 → 97,14
wbuf_be_r <= i_write ? i_be : 16'hffff;
wbuf_write_r <= i_write;
end
else if ( i_req && wbuf_used_r && o_valid && i_accepted)
begin
wbuf_used_r <= 1'd1;
wbuf_wdata_r <= i_wdata;
wbuf_addr_r <= i_addr;
wbuf_be_r <= i_write ? i_be : 16'hffff;
wbuf_write_r <= i_write;
end
else if (o_valid && i_accepted && wbuf_write_r)
wbuf_used_r <= 1'd0;
else if (i_rdata_valid && !wbuf_write_r)
/hw/vlog/amber25/a25_config_defines.v
53,8 → 53,8
//
// e.g. if both caches have 8 ways, the total is 32KB icache + 32KB dcache = 64KB
 
`define A25_ICACHE_WAYS 2
`define A25_DCACHE_WAYS 2
`define A25_ICACHE_WAYS 4
`define A25_DCACHE_WAYS 4
 
 
// --------------------------------------------------------------------
/hw/sim
hw/sim Property changes : Modified: svn:ignore ## -16,3 +16,5 ## *.vtakwave work rt +vish_stacktrace.vstf +vsim_stacktrace.vstf Index: hw/fpga/bin/xv6_source_files.prj =================================================================== --- hw/fpga/bin/xv6_source_files.prj (revision 35) +++ hw/fpga/bin/xv6_source_files.prj (revision 36) @@ -38,7 +38,8 @@ # ---------------------------------------------------------------- # System -verilog work ../../vlog/system/boot_mem.v +verilog work ../../vlog/system/boot_mem32.v +verilog work ../../vlog/system/boot_mem128.v verilog work ../../vlog/system/clocks_resets.v verilog work ../../vlog/system/interrupt_controller.v verilog work ../../vlog/system/system.v @@ -115,6 +116,7 @@ verilog work ../../vlog/lib/xv6_sram_256x128_byte_en.v verilog work ../../vlog/lib/xv6_sram_256x21_line_en.v verilog work ../../vlog/lib/xv6_sram_256x32_byte_en.v +verilog work ../../vlog/lib/xv6_sram_512x128_byte_en.v # Xilinx Virtex-6 DDR3 I/F verilog work ../../vlog/xv6_ddr3/ui_cmd.v
/hw/fpga/bin/xs6_source_files.prj
38,7 → 38,8
# ----------------------------------------------------------------
 
# System
verilog work ../../vlog/system/boot_mem.v
verilog work ../../vlog/system/boot_mem32.v
verilog work ../../vlog/system/boot_mem128.v
verilog work ../../vlog/system/clocks_resets.v
verilog work ../../vlog/system/interrupt_controller.v
verilog work ../../vlog/system/system.v
115,6 → 116,7
verilog work ../../vlog/lib/xs6_sram_256x128_byte_en.v
verilog work ../../vlog/lib/xs6_sram_256x21_line_en.v
verilog work ../../vlog/lib/xs6_sram_256x32_byte_en.v
verilog work ../../vlog/lib/xs6_sram_512x128_byte_en.v
 
# Xilinx Spartan-6 DDR3 I/F
verilog work ../../vlog/xs6_ddr3/mcb_ddr3.v

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