URL
https://opencores.org/ocsvn/amber/amber/trunk
Subversion Repositories amber
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- from Rev 40 to Rev 41
- ↔ Reverse comparison
Rev 40 → Rev 41
/trunk/hw/vlog/xs6_ddr3/datasheet.txt
0,0 → 1,76
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CORE Generator Options: |
Target Device : xc6slx45t-fgg484 |
Speed Grade : -3 |
HDL : verilog |
Synthesis Tool : XST |
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MIG Output Options: |
Component Name : ddr3 |
No of Controllers : 1 |
Hardware Test Bench : disabled |
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/*******************************************************/ |
/* Controller 3 */ |
/*******************************************************/ |
Controller Options : |
Memory : DDR3_SDRAM |
Design Clock Frequency : 2500 ps (400.00 MHz) |
Memory Type : Components |
Memory Part : MT41J64M16XX-187E |
Equivalent Part(s) : MT41J64M16LA-187E |
Row Address : 13 |
Column Address : 10 |
Bank Address : 3 |
Data Mask : enabled |
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Memory Options : |
Burst Length : 8(00) |
CAS Latency : 6 |
TDQS enable : Disabled |
DLL Enable : Enable |
Write Leveling Enable : Disabled |
Output Drive Strength : RZQ/6 |
Additive Latency (AL) : 0 |
RTT (nominal) - ODT : RZQ/4 |
Auto Self Refresh : Enabled |
CAS write latency : 5 |
Partial-Array Self Refresh : Full Array |
RTT_WR : Dynamic ODT off |
High Temparature Self Refresh Rate : Normal |
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User Interface Parameters : |
Configuration Type : One 128-bit bi-directional port |
Ports Selected : Port0 |
Memory Address Mapping : ROW_BANK_COLUMN |
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Arbitration Algorithm : Round Robin |
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Arbitration : |
Time Slot0 : 0 |
Time Slot1 : 0 |
Time Slot2 : 0 |
Time Slot3 : 0 |
Time Slot4 : 0 |
Time Slot5 : 0 |
Time Slot6 : 0 |
Time Slot7 : 0 |
Time Slot8 : 0 |
Time Slot9 : 0 |
Time Slot10: 0 |
Time Slot11: 0 |
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FPGA Options : |
Class for Address and Control : II |
Class for Data : II |
Memory Interface Pin Termination : UNCALIB_TERM |
DQ/DQS : 50 Ohms |
Calibration Row Address : 0000 |
Calibration Column Address : 000 |
Calibration Bank Address : 0 |
Bypass Calibration : enabled |
Debug Signals for Memory Controller : Enable |
Input Clock Type : Differential |
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/trunk/hw/vlog/xs6_ddr3/README.txt
0,0 → 1,38
*** Steps to create the Spartan-6 DDR3 memory interface for the SP605 development board. |
These instructions are based on using Xilinx ISE 11.5 |
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Use Coregen/MIG 3.3 to create the controller. |
- Component Name: ddr3 |
- Bank 3 Memory Type DDR3 SDRAM |
- Frequency: 400MHz |
- Memory Part: MT41J64M16XX-187E |
- Configuration Selection: One 128-bit bi-directional port |
- Memory Address Mapping Selection: Row, Bank, Column |
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Once the controller is generated copy all the Verilog files from the user_design/rtl directory to $AMBER_BASE/hw/vlog/xs6_ddr3. |
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Then make the following modifications |
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1. ddr3.v |
Rename this module to mcb_ddr3.v. |
Replace the inputs c3_sys_clk_p, c3_sys_clk_n with sys_clk_ibufg. |
Delete the outputs c3_clk0 and c3_rst0. |
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2. memc3_infrastructure.v |
Replace the inputs c3_sys_clk_p, c3_sys_clk_n with sys_clk_ibufg. |
Delete the outputs c3_clk0 and c3_rst0. |
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Change the localparam from |
localparam CLK_PERIOD_NS = C_MEMCLK_PERIOD / 1000.0; |
to |
localparam CLK_PERIOD_NS = C_MEMCLK_PERIOD / 500.0; |
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Delete the generate statement from lines 124 to 154 |
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On the PLL_ADV instantiation, |
Change the parameter CLKFBOUT_MULT from 2 to 4. |
Disconnect the CLKOUT2 output |
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Delete the U_BUFG_CLK0 instantiation. |
Delete the rst0_sync_r logic. |