OpenCores

/DE0_nano/DE0_nano.qsf File deleted

/DE0_nano/program_device.sh File deleted

/DE0_nano/jtag_intfc.sh File deleted

/DE0_nano/DE0_nano.v File deleted

/DE1_SoC/program_device.sh File deleted

/DE1_SoC/jtag_intfc.sh File deleted

/DE1_SoC/DE1_SoC.v File deleted

/DE1_SoC/DE1_SoC.qsf File deleted

/DE2_115/De2_115.qsf File deleted

/DE2_115/program_device.sh File deleted

/DE2_115/jtag_intfc.sh File deleted

/DE2_115/DE2_115.v File deleted

/DE10_Nano_VB2/program_device.sh File deleted

/DE10_Nano_VB2/jtag_intfc.sh File deleted \ No newline at end of file

/DE10_Nano_VB2/DE10_Nano_VB2.v File deleted

/DE10_Nano_VB2/DE10_Nano_VB2.qsf File deleted

/DE5/program_device.sh File deleted

DE5/program_device.sh Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: DE5/DE5.v =================================================================== --- DE5/DE5.v (revision 45) +++ DE5/DE5.v (nonexistent) @@ -1,148 +0,0 @@ - -//======================================================= -// This code is generated by Terasic System Builder -//======================================================= - -module Top( - - //////////// CLOCK ////////// - OSC_50_B3B, - OSC_50_B3D, - OSC_50_B4A, - OSC_50_B4D, - OSC_50_B7A, - OSC_50_B7D, - OSC_50_B8A, - OSC_50_B8D, - - //////////// LED x 10 ////////// - LED, - LED_BRACKET, - LED_RJ45_L, - LED_RJ45_R, - - //////////// BUTTON x 4 and CPU_RESET_n ////////// - BUTTON, - CPU_RESET_n, - - //////////// SWITCH x 4 ////////// - SW, - - //////////// 7-Segement ////////// - HEX0_D, - HEX0_DP, - HEX1_D, - HEX1_DP, - - //////////// Temperature ////////// - TEMP_CLK, - TEMP_DATA, - TEMP_INT_n, - TEMP_OVERT_n, - - //////////// Fan ////////// - FAN_CTRL, - - //////////// RS232 ////////// - RS422_DE, - RS422_DIN, - RS422_DOUT, - RS422_RE_n, - RS422_TE, - - //////////// Flash/MAX Address/Data Share Bus ////////// - FSM_A, - FSM_D, - - //////////// Flash Control ////////// - FLASH_ADV_n, - FLASH_CE_n, - FLASH_CLK, - FLASH_OE_n, - FLASH_RDY_BSY_n, - FLASH_RESET_n, - FLASH_WE_n -); - -//======================================================= -// PARAMETER declarations -//======================================================= - - -//======================================================= -// PORT declarations -//======================================================= - -//////////// CLOCK ////////// -input OSC_50_B3B; -input OSC_50_B3D; -input OSC_50_B4A; -input OSC_50_B4D; -input OSC_50_B7A; -input OSC_50_B7D; -input OSC_50_B8A; -input OSC_50_B8D; - -//////////// LED x 10 ////////// -output [3:0] LED; -output [3:0] LED_BRACKET; -output LED_RJ45_L; -output LED_RJ45_R; - -//////////// BUTTON x 4 and CPU_RESET_n ////////// -input [3:0] BUTTON; -input CPU_RESET_n; - -//////////// SWITCH x 4 ////////// -input [3:0] SW; - -//////////// 7-Segement ////////// -output [6:0] HEX0_D; -output HEX0_DP; -output [6:0] HEX1_D; -output HEX1_DP; - -//////////// Temperature ////////// -output TEMP_CLK; -inout TEMP_DATA; -input TEMP_INT_n; -input TEMP_OVERT_n; - -//////////// Fan ////////// -inout FAN_CTRL; - -//////////// RS232 ////////// -output RS422_DE; -input RS422_DIN; -output RS422_DOUT; -output RS422_RE_n; -output RS422_TE; - -//////////// Flash/MAX Address/Data Share Bus ////////// -output [26:0] FSM_A; -inout [31:0] FSM_D; - -//////////// Flash Control ////////// -output FLASH_ADV_n; -output [1:0] FLASH_CE_n; -output FLASH_CLK; -output FLASH_OE_n; -input [1:0] FLASH_RDY_BSY_n; -output FLASH_RESET_n; -output FLASH_WE_n; - - -//======================================================= -// REG/WIRE declarations -//======================================================= - - - - -//======================================================= -// Structural coding -//======================================================= - - - -endmodule

DE5/DE5.v Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: DE5/jtag_intfc.sh =================================================================== --- DE5/jtag_intfc.sh (revision 45) +++ DE5/jtag_intfc.sh (nonexistent) @@ -1,11 +0,0 @@ -#!/bin/bash - -PRODUCT_ID="0x6010" -HARDWARE_NAME="DE5 Standard *" -DEVICE_NAME="@1*" - -JTAG_INTFC="$PRONOC_WORK/toolchain/bin/jtag_quartus_stp -a $HARDWARE_NAME -b $DEVICE_NAME" - - - -

DE5/jtag_intfc.sh Property changes : Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Index: DE5/DE5.qsf =================================================================== --- DE5/DE5.qsf (revision 45) +++ DE5/DE5.qsf (nonexistent) @@ -1,302 +0,0 @@ -#============================================================ -# Build by Terasic System Builder -#============================================================ - -set_global_assignment -name FAMILY "Stratix V" -set_global_assignment -name DEVICE 5SGXEA7N2F45C2 -set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.0" -set_global_assignment -name LAST_QUARTUS_VERSION "12.0" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:38:23 JULY 08,2019" -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1932 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 2_H2 -set_global_assignment -name SDC_FILE Top.SDC - -#============================================================ -# CLOCK -#============================================================ -set_location_assignment PIN_AW35 -to OSC_50_B3B -set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_B3B -set_location_assignment PIN_BC28 -to OSC_50_B3D -set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_50_B3D -set_location_assignment PIN_AP10 -to OSC_50_B4A -set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_50_B4A -set_location_assignment PIN_AY18 -to OSC_50_B4D -set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_50_B4D -set_location_assignment PIN_M8 -to OSC_50_B7A -set_instance_assignment -name IO_STANDARD "1.5 V" -to OSC_50_B7A -set_location_assignment PIN_J18 -to OSC_50_B7D -set_instance_assignment -name IO_STANDARD "1.5 V" -to OSC_50_B7D -set_location_assignment PIN_R36 -to OSC_50_B8A -set_instance_assignment -name IO_STANDARD "1.5 V" -to OSC_50_B8A -set_location_assignment PIN_R25 -to OSC_50_B8D -set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_50_B8D - -#============================================================ -# LED x 10 -#============================================================ -set_location_assignment PIN_AW37 -to LED[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[0] -set_location_assignment PIN_AV37 -to LED[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[1] -set_location_assignment PIN_BB36 -to LED[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[2] -set_location_assignment PIN_BB39 -to LED[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[3] -set_location_assignment PIN_AH15 -to LED_BRACKET[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_BRACKET[0] -set_location_assignment PIN_AH13 -to LED_BRACKET[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_BRACKET[1] -set_location_assignment PIN_AJ13 -to LED_BRACKET[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_BRACKET[2] -set_location_assignment PIN_AJ14 -to LED_BRACKET[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_BRACKET[3] -set_location_assignment PIN_AG15 -to LED_RJ45_L -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_RJ45_L -set_location_assignment PIN_AG16 -to LED_RJ45_R -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_RJ45_R - -#============================================================ -# BUTTON x 4 and CPU_RESET_n -#============================================================ -set_location_assignment PIN_AK15 -to BUTTON[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to BUTTON[0] -set_location_assignment PIN_AK14 -to BUTTON[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to BUTTON[1] -set_location_assignment PIN_AL14 -to BUTTON[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to BUTTON[2] -set_location_assignment PIN_AL15 -to BUTTON[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to BUTTON[3] -set_location_assignment PIN_BC37 -to CPU_RESET_n -set_instance_assignment -name IO_STANDARD "2.5 V" -to CPU_RESET_n - -#============================================================ -# SWITCH x 4 -#============================================================ -set_location_assignment PIN_B25 -to SW[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to SW[0] -set_location_assignment PIN_A25 -to SW[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to SW[1] -set_location_assignment PIN_B23 -to SW[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to SW[2] -set_location_assignment PIN_A23 -to SW[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to SW[3] - -#============================================================ -# 7-Segement -#============================================================ -set_location_assignment PIN_G8 -to HEX0_D[0] -set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX0_D[0] -set_location_assignment PIN_H8 -to HEX0_D[1] -set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX0_D[1] -set_location_assignment PIN_J9 -to HEX0_D[2] -set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX0_D[2] -set_location_assignment PIN_K10 -to HEX0_D[3] -set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX0_D[3] -set_location_assignment PIN_K8 -to HEX0_D[4] -set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX0_D[4] -set_location_assignment PIN_K9 -to HEX0_D[5] -set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX0_D[5] -set_location_assignment PIN_N8 -to HEX0_D[6] -set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX0_D[6] -set_location_assignment PIN_P8 -to HEX0_DP -set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX0_DP -set_location_assignment PIN_H18 -to HEX1_D[0] -set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX1_D[0] -set_location_assignment PIN_G16 -to HEX1_D[1] -set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX1_D[1] -set_location_assignment PIN_F16 -to HEX1_D[2] -set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX1_D[2] -set_location_assignment PIN_A7 -to HEX1_D[3] -set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX1_D[3] -set_location_assignment PIN_B7 -to HEX1_D[4] -set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX1_D[4] -set_location_assignment PIN_C9 -to HEX1_D[5] -set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX1_D[5] -set_location_assignment PIN_D10 -to HEX1_D[6] -set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX1_D[6] -set_location_assignment PIN_E9 -to HEX1_DP -set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX1_DP - -#============================================================ -# Temperature -#============================================================ -set_location_assignment PIN_D21 -to TEMP_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to TEMP_CLK -set_location_assignment PIN_D20 -to TEMP_DATA -set_instance_assignment -name IO_STANDARD "2.5 V" -to TEMP_DATA -set_location_assignment PIN_C21 -to TEMP_INT_n -set_instance_assignment -name IO_STANDARD "2.5 V" -to TEMP_INT_n -set_location_assignment PIN_C22 -to TEMP_OVERT_n -set_instance_assignment -name IO_STANDARD "2.5 V" -to TEMP_OVERT_n - -#============================================================ -# Fan -#============================================================ -set_location_assignment PIN_AR32 -to FAN_CTRL -set_instance_assignment -name IO_STANDARD "2.5 V" -to FAN_CTRL - -#============================================================ -# RS232 -#============================================================ -set_location_assignment PIN_AG14 -to RS422_DE -set_instance_assignment -name IO_STANDARD "2.5 V" -to RS422_DE -set_location_assignment PIN_AE18 -to RS422_DIN -set_instance_assignment -name IO_STANDARD "2.5 V" -to RS422_DIN -set_location_assignment PIN_AE17 -to RS422_DOUT -set_instance_assignment -name IO_STANDARD "2.5 V" -to RS422_DOUT -set_location_assignment PIN_AF17 -to RS422_RE_n -set_instance_assignment -name IO_STANDARD "2.5 V" -to RS422_RE_n -set_location_assignment PIN_AF16 -to RS422_TE -set_instance_assignment -name IO_STANDARD "2.5 V" -to RS422_TE - -#============================================================ -# Flash/MAX Address/Data Share Bus -#============================================================ -set_location_assignment PIN_AG26 -to FSM_D[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[0] -set_location_assignment PIN_AD33 -to FSM_D[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[1] -set_location_assignment PIN_AE34 -to FSM_D[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[2] -set_location_assignment PIN_AF31 -to FSM_D[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[3] -set_location_assignment PIN_AG28 -to FSM_D[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[4] -set_location_assignment PIN_AG30 -to FSM_D[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[5] -set_location_assignment PIN_AF29 -to FSM_D[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[6] -set_location_assignment PIN_AE29 -to FSM_D[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[7] -set_location_assignment PIN_AG25 -to FSM_D[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[8] -set_location_assignment PIN_AF34 -to FSM_D[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[9] -set_location_assignment PIN_AE33 -to FSM_D[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[10] -set_location_assignment PIN_AE31 -to FSM_D[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[11] -set_location_assignment PIN_AF28 -to FSM_D[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[12] -set_location_assignment PIN_AE30 -to FSM_D[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[13] -set_location_assignment PIN_AG29 -to FSM_D[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[14] -set_location_assignment PIN_AG27 -to FSM_D[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[15] -set_location_assignment PIN_AP28 -to FSM_D[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[16] -set_location_assignment PIN_AN28 -to FSM_D[17] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[17] -set_location_assignment PIN_AU31 -to FSM_D[18] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[18] -set_location_assignment PIN_AW32 -to FSM_D[19] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[19] -set_location_assignment PIN_BD32 -to FSM_D[20] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[20] -set_location_assignment PIN_AY31 -to FSM_D[21] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[21] -set_location_assignment PIN_BA30 -to FSM_D[22] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[22] -set_location_assignment PIN_BB30 -to FSM_D[23] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[23] -set_location_assignment PIN_AM29 -to FSM_D[24] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[24] -set_location_assignment PIN_AR29 -to FSM_D[25] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[25] -set_location_assignment PIN_AV31 -to FSM_D[26] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[26] -set_location_assignment PIN_AV32 -to FSM_D[27] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[27] -set_location_assignment PIN_BC31 -to FSM_D[28] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[28] -set_location_assignment PIN_AW30 -to FSM_D[29] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[29] -set_location_assignment PIN_BC32 -to FSM_D[30] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[30] -set_location_assignment PIN_BD31 -to FSM_D[31] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[31] -set_location_assignment PIN_AU32 -to FSM_A[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[0] -set_location_assignment PIN_AH30 -to FSM_A[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[1] -set_location_assignment PIN_AJ30 -to FSM_A[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[2] -set_location_assignment PIN_AH31 -to FSM_A[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[3] -set_location_assignment PIN_AK30 -to FSM_A[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[4] -set_location_assignment PIN_AJ32 -to FSM_A[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[5] -set_location_assignment PIN_AG33 -to FSM_A[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[6] -set_location_assignment PIN_AL30 -to FSM_A[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[7] -set_location_assignment PIN_AK33 -to FSM_A[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[8] -set_location_assignment PIN_AJ33 -to FSM_A[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[9] -set_location_assignment PIN_AN30 -to FSM_A[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[10] -set_location_assignment PIN_AH33 -to FSM_A[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[11] -set_location_assignment PIN_AK32 -to FSM_A[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[12] -set_location_assignment PIN_AM32 -to FSM_A[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[13] -set_location_assignment PIN_AM31 -to FSM_A[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[14] -set_location_assignment PIN_AL31 -to FSM_A[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[15] -set_location_assignment PIN_AN33 -to FSM_A[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[16] -set_location_assignment PIN_AP33 -to FSM_A[17] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[17] -set_location_assignment PIN_AT32 -to FSM_A[18] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[18] -set_location_assignment PIN_AT29 -to FSM_A[19] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[19] -set_location_assignment PIN_AP31 -to FSM_A[20] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[20] -set_location_assignment PIN_AR30 -to FSM_A[21] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[21] -set_location_assignment PIN_AU30 -to FSM_A[22] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[22] -set_location_assignment PIN_AJ31 -to FSM_A[23] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[23] -set_location_assignment PIN_AP30 -to FSM_A[24] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[24] -set_location_assignment PIN_AN31 -to FSM_A[25] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[25] -set_location_assignment PIN_AT30 -to FSM_A[26] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[26] - -#============================================================ -# Flash Control -#============================================================ -set_location_assignment PIN_AK29 -to FLASH_ADV_n -set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_ADV_n -set_location_assignment PIN_AE27 -to FLASH_CE_n[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_CE_n[0] -set_location_assignment PIN_BA31 -to FLASH_CE_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_CE_n[1] -set_location_assignment PIN_AL29 -to FLASH_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_CLK -set_location_assignment PIN_AY30 -to FLASH_OE_n -set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_OE_n -set_location_assignment PIN_BA29 -to FLASH_RDY_BSY_n[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_RDY_BSY_n[0] -set_location_assignment PIN_BB32 -to FLASH_RDY_BSY_n[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_RDY_BSY_n[1] -set_location_assignment PIN_AE28 -to FLASH_RESET_n -set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_RESET_n -set_location_assignment PIN_AR31 -to FLASH_WE_n -set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_WE_n - -#============================================================ -# End of pin assignments by Terasic System Builder -#============================================================ - - -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files Index: Altera/DE0_nano/DE0_nano.qsf =================================================================== --- Altera/DE0_nano/DE0_nano.qsf (nonexistent) +++ Altera/DE0_nano/DE0_nano.qsf (revision 48) @@ -0,0 +1,383 @@ +# Copyright (C) 1991-2011 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE22F17C6 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Pin & Location Assignments +# ========================== +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_R8 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 + +#============================================================ +# LED +#============================================================ +set_location_assignment PIN_A15 -to LED[0] +set_location_assignment PIN_A13 -to LED[1] +set_location_assignment PIN_B13 -to LED[2] +set_location_assignment PIN_A11 -to LED[3] +set_location_assignment PIN_D1 -to LED[4] +set_location_assignment PIN_F3 -to LED[5] +set_location_assignment PIN_B1 -to LED[6] +set_location_assignment PIN_L3 -to LED[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] + +#============================================================ +# KEY +#============================================================ +set_location_assignment PIN_J15 -to KEY[0] +set_location_assignment PIN_E1 -to KEY[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] + +#============================================================ +# SW +#============================================================ +set_location_assignment PIN_M1 -to SW[0] +set_location_assignment PIN_T8 -to SW[1] +set_location_assignment PIN_B9 -to SW[2] +set_location_assignment PIN_M15 -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] + +#============================================================ +# SDRAM +#============================================================ +set_location_assignment PIN_P2 -to DRAM_ADDR[0] +set_location_assignment PIN_N5 -to DRAM_ADDR[1] +set_location_assignment PIN_N6 -to DRAM_ADDR[2] +set_location_assignment PIN_M8 -to DRAM_ADDR[3] +set_location_assignment PIN_P8 -to DRAM_ADDR[4] +set_location_assignment PIN_T7 -to DRAM_ADDR[5] +set_location_assignment PIN_N8 -to DRAM_ADDR[6] +set_location_assignment PIN_T6 -to DRAM_ADDR[7] +set_location_assignment PIN_R1 -to DRAM_ADDR[8] +set_location_assignment PIN_P1 -to DRAM_ADDR[9] +set_location_assignment PIN_N2 -to DRAM_ADDR[10] +set_location_assignment PIN_N1 -to DRAM_ADDR[11] +set_location_assignment PIN_L4 -to DRAM_ADDR[12] +set_location_assignment PIN_M7 -to DRAM_BA[0] +set_location_assignment PIN_M6 -to DRAM_BA[1] +set_location_assignment PIN_L7 -to DRAM_CKE +set_location_assignment PIN_R4 -to DRAM_CLK +set_location_assignment PIN_P6 -to DRAM_CS_N +set_location_assignment PIN_G2 -to DRAM_DQ[0] +set_location_assignment PIN_G1 -to DRAM_DQ[1] +set_location_assignment PIN_L8 -to DRAM_DQ[2] +set_location_assignment PIN_K5 -to DRAM_DQ[3] +set_location_assignment PIN_K2 -to DRAM_DQ[4] +set_location_assignment PIN_J2 -to DRAM_DQ[5] +set_location_assignment PIN_J1 -to DRAM_DQ[6] +set_location_assignment PIN_R7 -to DRAM_DQ[7] +set_location_assignment PIN_T4 -to DRAM_DQ[8] +set_location_assignment PIN_T2 -to DRAM_DQ[9] +set_location_assignment PIN_T3 -to DRAM_DQ[10] +set_location_assignment PIN_R3 -to DRAM_DQ[11] +set_location_assignment PIN_R5 -to DRAM_DQ[12] +set_location_assignment PIN_P3 -to DRAM_DQ[13] +set_location_assignment PIN_N3 -to DRAM_DQ[14] +set_location_assignment PIN_K1 -to DRAM_DQ[15] +set_location_assignment PIN_R6 -to DRAM_DQM[0] +set_location_assignment PIN_T5 -to DRAM_DQM[1] +set_location_assignment PIN_L1 -to DRAM_CAS_N +set_location_assignment PIN_L2 -to DRAM_RAS_N +set_location_assignment PIN_C2 -to DRAM_WE_N + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N + +#============================================================ +# Accelerometer and EEPROM +#============================================================ +set_location_assignment PIN_F2 -to I2C_SCLK +set_location_assignment PIN_F1 -to I2C_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT + +set_location_assignment PIN_G5 -to G_SENSOR_CS_N +set_location_assignment PIN_M2 -to G_SENSOR_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_INT + +#============================================================ +# ADC +#============================================================ +set_location_assignment PIN_A10 -to ADC_CS_N +set_location_assignment PIN_B10 -to ADC_SADDR +set_location_assignment PIN_B14 -to ADC_SCLK +set_location_assignment PIN_A9 -to ADC_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SADDR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDAT + +#============================================================ +# 2x13 GPIO Header +#============================================================ +set_location_assignment PIN_A14 -to GPIO_2[0] +set_location_assignment PIN_B16 -to GPIO_2[1] +set_location_assignment PIN_C14 -to GPIO_2[2] +set_location_assignment PIN_C16 -to GPIO_2[3] +set_location_assignment PIN_C15 -to GPIO_2[4] +set_location_assignment PIN_D16 -to GPIO_2[5] +set_location_assignment PIN_D15 -to GPIO_2[6] +set_location_assignment PIN_D14 -to GPIO_2[7] +set_location_assignment PIN_F15 -to GPIO_2[8] +set_location_assignment PIN_F16 -to GPIO_2[9] +set_location_assignment PIN_F14 -to GPIO_2[10] +set_location_assignment PIN_G16 -to GPIO_2[11] +set_location_assignment PIN_G15 -to GPIO_2[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[12] + +set_location_assignment PIN_E15 -to GPIO_2_IN[0] +set_location_assignment PIN_E16 -to GPIO_2_IN[1] +set_location_assignment PIN_M16 -to GPIO_2_IN[2] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[2] + +#============================================================ +# GPIO_0, GPIO_0 connect to GPIO Default +#============================================================ +set_location_assignment PIN_A8 -to GPIO_0_IN[0] +set_location_assignment PIN_D3 -to GPIO_0[0] +set_location_assignment PIN_B8 -to GPIO_0_IN[1] +set_location_assignment PIN_C3 -to GPIO_0[1] +set_location_assignment PIN_A2 -to GPIO_0[2] +set_location_assignment PIN_A3 -to GPIO_0[3] +set_location_assignment PIN_B3 -to GPIO_0[4] +set_location_assignment PIN_B4 -to GPIO_0[5] +set_location_assignment PIN_A4 -to GPIO_0[6] +set_location_assignment PIN_B5 -to GPIO_0[7] +set_location_assignment PIN_A5 -to GPIO_0[8] +set_location_assignment PIN_D5 -to GPIO_0[9] +set_location_assignment PIN_B6 -to GPIO_0[10] +set_location_assignment PIN_A6 -to GPIO_0[11] +set_location_assignment PIN_B7 -to GPIO_0[12] +set_location_assignment PIN_D6 -to GPIO_0[13] +set_location_assignment PIN_A7 -to GPIO_0[14] +set_location_assignment PIN_C6 -to GPIO_0[15] +set_location_assignment PIN_C8 -to GPIO_0[16] +set_location_assignment PIN_E6 -to GPIO_0[17] +set_location_assignment PIN_E7 -to GPIO_0[18] +set_location_assignment PIN_D8 -to GPIO_0[19] +set_location_assignment PIN_E8 -to GPIO_0[20] +set_location_assignment PIN_F8 -to GPIO_0[21] +set_location_assignment PIN_F9 -to GPIO_0[22] +set_location_assignment PIN_E9 -to GPIO_0[23] +set_location_assignment PIN_C9 -to GPIO_0[24] +set_location_assignment PIN_D9 -to GPIO_0[25] +set_location_assignment PIN_E11 -to GPIO_0[26] +set_location_assignment PIN_E10 -to GPIO_0[27] +set_location_assignment PIN_C11 -to GPIO_0[28] +set_location_assignment PIN_B11 -to GPIO_0[29] +set_location_assignment PIN_A12 -to GPIO_0[30] +set_location_assignment PIN_D11 -to GPIO_0[31] +set_location_assignment PIN_D12 -to GPIO_0[32] +set_location_assignment PIN_B12 -to GPIO_0[33] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] + +#============================================================ +# GPIO_0, GPIO_1 connect to GPIO Default +#============================================================ +set_location_assignment PIN_T9 -to GPIO_1_IN[0] +set_location_assignment PIN_F13 -to GPIO_1[0] +set_location_assignment PIN_R9 -to GPIO_1_IN[1] +set_location_assignment PIN_T15 -to GPIO_1[1] +set_location_assignment PIN_T14 -to GPIO_1[2] +set_location_assignment PIN_T13 -to GPIO_1[3] +set_location_assignment PIN_R13 -to GPIO_1[4] +set_location_assignment PIN_T12 -to GPIO_1[5] +set_location_assignment PIN_R12 -to GPIO_1[6] +set_location_assignment PIN_T11 -to GPIO_1[7] +set_location_assignment PIN_T10 -to GPIO_1[8] +set_location_assignment PIN_R11 -to GPIO_1[9] +set_location_assignment PIN_P11 -to GPIO_1[10] +set_location_assignment PIN_R10 -to GPIO_1[11] +set_location_assignment PIN_N12 -to GPIO_1[12] +set_location_assignment PIN_P9 -to GPIO_1[13] +set_location_assignment PIN_N9 -to GPIO_1[14] +set_location_assignment PIN_N11 -to GPIO_1[15] +set_location_assignment PIN_L16 -to GPIO_1[16] +set_location_assignment PIN_K16 -to GPIO_1[17] +set_location_assignment PIN_R16 -to GPIO_1[18] +set_location_assignment PIN_L15 -to GPIO_1[19] +set_location_assignment PIN_P15 -to GPIO_1[20] +set_location_assignment PIN_P16 -to GPIO_1[21] +set_location_assignment PIN_R14 -to GPIO_1[22] +set_location_assignment PIN_N16 -to GPIO_1[23] +set_location_assignment PIN_N15 -to GPIO_1[24] +set_location_assignment PIN_P14 -to GPIO_1[25] +set_location_assignment PIN_L14 -to GPIO_1[26] +set_location_assignment PIN_N14 -to GPIO_1[27] +set_location_assignment PIN_M10 -to GPIO_1[28] +set_location_assignment PIN_L13 -to GPIO_1[29] +set_location_assignment PIN_J16 -to GPIO_1[30] +set_location_assignment PIN_K15 -to GPIO_1[31] +set_location_assignment PIN_J13 -to GPIO_1[32] +set_location_assignment PIN_J14 -to GPIO_1[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] + +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" + +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" + +set_instance_assignment -name FAST_INPUT_REGISTER ON -to * +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to * +set_instance_assignment -name TSU_REQUIREMENT "10 ns" -from * -to * +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to * + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top Index: Altera/DE0_nano/DE0_nano.v =================================================================== --- Altera/DE0_nano/DE0_nano.v (nonexistent) +++ Altera/DE0_nano/DE0_nano.v (revision 48) @@ -0,0 +1,139 @@ +//======================================================= +// This code is generated by Terasic System Builder +//======================================================= + +module DE0_Nano( + + //////////// CLOCK ////////// + CLOCK_50, + + //////////// LED ////////// + LED, + + //////////// KEY ////////// + KEY, + + //////////// SW ////////// + SW, + + //////////// SDRAM ////////// + DRAM_ADDR, + DRAM_BA, + DRAM_CAS_N, + DRAM_CKE, + DRAM_CLK, + DRAM_CS_N, + DRAM_DQ, + DRAM_DQM, + DRAM_RAS_N, + DRAM_WE_N, + + //////////// EPCS ////////// + EPCS_ASDO, + EPCS_DATA0, + EPCS_DCLK, + EPCS_NCSO, + + //////////// Accelerometer and EEPROM ////////// + G_SENSOR_CS_N, + G_SENSOR_INT, + I2C_SCLK, + I2C_SDAT, + + //////////// ADC ////////// + ADC_CS_N, + ADC_SADDR, + ADC_SCLK, + ADC_SDAT, + + //////////// 2x13 GPIO Header ////////// + GPIO_2, + GPIO_2_IN, + + //////////// GPIO_0, GPIO_0 connect to GPIO Default ////////// + GPIO_0, + GPIO_0_IN, + + //////////// GPIO_1, GPIO_1 connect to GPIO Default ////////// + GPIO_1, + GPIO_1_IN +); + +//======================================================= +// PARAMETER declarations +//======================================================= + + +//======================================================= +// PORT declarations +//======================================================= + +//////////// CLOCK ////////// +input CLOCK_50; + +//////////// LED ////////// +output [7:0] LED; + +//////////// KEY ////////// +input [1:0] KEY; + +//////////// SW ////////// +input [3:0] SW; + +//////////// SDRAM ////////// +output [12:0] DRAM_ADDR; +output [1:0] DRAM_BA; +output DRAM_CAS_N; +output DRAM_CKE; +output DRAM_CLK; +output DRAM_CS_N; +inout [15:0] DRAM_DQ; +output [1:0] DRAM_DQM; +output DRAM_RAS_N; +output DRAM_WE_N; + +//////////// EPCS ////////// +output EPCS_ASDO; +input EPCS_DATA0; +output EPCS_DCLK; +output EPCS_NCSO; + +//////////// Accelerometer and EEPROM ////////// +output G_SENSOR_CS_N; +input G_SENSOR_INT; +output I2C_SCLK; +inout I2C_SDAT; + +//////////// ADC ////////// +output ADC_CS_N; +output ADC_SADDR; +output ADC_SCLK; +input ADC_SDAT; + +//////////// 2x13 GPIO Header ////////// +inout [12:0] GPIO_2; +input [2:0] GPIO_2_IN; + +//////////// GPIO_0, GPIO_0 connect to GPIO Default ////////// +inout [33:0] GPIO_0; +input [1:0] GPIO_0_IN; + +//////////// GPIO_1, GPIO_1 connect to GPIO Default ////////// +inout [33:0] GPIO_1; +input [1:0] GPIO_1_IN; + + +//======================================================= +// REG/WIRE declarations +//======================================================= + + + + +//======================================================= +// Structural coding +//======================================================= + + + +endmodule Index: Altera/DE0_nano/jtag_intfc.sh =================================================================== --- Altera/DE0_nano/jtag_intfc.sh (nonexistent) +++ Altera/DE0_nano/jtag_intfc.sh (revision 48) @@ -0,0 +1,6 @@ +#!/bin/bash + +PRODUCT_ID="0x6001" +JTAG_INTFC="$PRONOC_WORK/toolchain/bin/jtag_libusb -a $PRODUCT_ID" + + Index: Altera/DE0_nano/program_device.sh =================================================================== --- Altera/DE0_nano/program_device.sh (nonexistent) +++ Altera/DE0_nano/program_device.sh (revision 48) @@ -0,0 +1,24 @@ +#!/bin/bash + +#usage: +# sh program_device.sh programming_file.sof + +#programming file +#given as an argument: $1 + +#Programming mode +PROG_MODE=jtag + +#cable name. Connect the board to ur PC and then run jtagconfig in terminal to find the cable name +NAME="USB-Blaster" + + +#programming command +if [ -n "${QUARTUS_BIN+set}" ]; then + $QUARTUS_BIN/quartus_pgm -m $PROG_MODE -c "$NAME" -o "p;${1}" +else + quartus_pgm -m $PROG_MODE -c "$NAME" -o "p;${1}" +fi + + + Index: Altera/DE10_Nano_VB2/DE10_Nano_VB2.qsf =================================================================== --- Altera/DE10_Nano_VB2/DE10_Nano_VB2.qsf (nonexistent) +++ Altera/DE10_Nano_VB2/DE10_Nano_VB2.qsf (revision 48) @@ -0,0 +1,481 @@ +#============================================================ +# Build by Terasic V1.0.0 +#============================================================ + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEBA6U23I7 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2 +set_global_assignment -name LAST_QUARTUS_VERSION 16.0.2 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:08:14 OCTOBER 14, 2016" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA + + + +#============================================================ +# ADC +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO + +#============================================================ +# ARDUINO +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N + +#============================================================ +# FPGA +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 + +#============================================================ +# GPIO +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35] + +#============================================================ +# HDMI +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS + +#============================================================ +# HPS +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + + + +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_location_assignment PIN_U9 -to ADC_CONVST +set_location_assignment PIN_V10 -to ADC_SCK +set_location_assignment PIN_AC4 -to ADC_SDI +set_location_assignment PIN_AD4 -to ADC_SDO +set_location_assignment PIN_AG13 -to ARDUINO_IO[0] +set_location_assignment PIN_AF13 -to ARDUINO_IO[1] +set_location_assignment PIN_AG10 -to ARDUINO_IO[2] +set_location_assignment PIN_AG9 -to ARDUINO_IO[3] +set_location_assignment PIN_U14 -to ARDUINO_IO[4] +set_location_assignment PIN_U13 -to ARDUINO_IO[5] +set_location_assignment PIN_AG8 -to ARDUINO_IO[6] +set_location_assignment PIN_AH8 -to ARDUINO_IO[7] +set_location_assignment PIN_AF17 -to ARDUINO_IO[8] +set_location_assignment PIN_AE15 -to ARDUINO_IO[9] +set_location_assignment PIN_AF15 -to ARDUINO_IO[10] +set_location_assignment PIN_AG16 -to ARDUINO_IO[11] +set_location_assignment PIN_AH11 -to ARDUINO_IO[12] +set_location_assignment PIN_AH12 -to ARDUINO_IO[13] +set_location_assignment PIN_AH9 -to ARDUINO_IO[14] +set_location_assignment PIN_AG11 -to ARDUINO_IO[15] +set_location_assignment PIN_AH7 -to ARDUINO_RESET_N +set_location_assignment PIN_V11 -to FPGA_CLK1_50 +set_location_assignment PIN_Y13 -to FPGA_CLK2_50 +set_location_assignment PIN_E11 -to FPGA_CLK3_50 +set_location_assignment PIN_V12 -to GPIO_0[0] +set_location_assignment PIN_E8 -to GPIO_0[1] +set_location_assignment PIN_W12 -to GPIO_0[2] +set_location_assignment PIN_D11 -to GPIO_0[3] +set_location_assignment PIN_D8 -to GPIO_0[4] +set_location_assignment PIN_AH13 -to GPIO_0[5] +set_location_assignment PIN_AF7 -to GPIO_0[6] +set_location_assignment PIN_AH14 -to GPIO_0[7] +set_location_assignment PIN_AF4 -to GPIO_0[8] +set_location_assignment PIN_AH3 -to GPIO_0[9] +set_location_assignment PIN_AD5 -to GPIO_0[10] +set_location_assignment PIN_AG14 -to GPIO_0[11] +set_location_assignment PIN_AE23 -to GPIO_0[12] +set_location_assignment PIN_AE6 -to GPIO_0[13] +set_location_assignment PIN_AD23 -to GPIO_0[14] +set_location_assignment PIN_AE24 -to GPIO_0[15] +set_location_assignment PIN_D12 -to GPIO_0[16] +set_location_assignment PIN_AD20 -to GPIO_0[17] +set_location_assignment PIN_C12 -to GPIO_0[18] +set_location_assignment PIN_AD17 -to GPIO_0[19] +set_location_assignment PIN_AC23 -to GPIO_0[20] +set_location_assignment PIN_AC22 -to GPIO_0[21] +set_location_assignment PIN_Y19 -to GPIO_0[22] +set_location_assignment PIN_AB23 -to GPIO_0[23] +set_location_assignment PIN_AA19 -to GPIO_0[24] +set_location_assignment PIN_W11 -to GPIO_0[25] +set_location_assignment PIN_AA18 -to GPIO_0[26] +set_location_assignment PIN_W14 -to GPIO_0[27] +set_location_assignment PIN_Y18 -to GPIO_0[28] +set_location_assignment PIN_Y17 -to GPIO_0[29] +set_location_assignment PIN_AB25 -to GPIO_0[30] +set_location_assignment PIN_AB26 -to GPIO_0[31] +set_location_assignment PIN_Y11 -to GPIO_0[32] +set_location_assignment PIN_AA26 -to GPIO_0[33] +set_location_assignment PIN_AA13 -to GPIO_0[34] +set_location_assignment PIN_AA11 -to GPIO_0[35] +set_location_assignment PIN_Y15 -to GPIO_1[0] +set_location_assignment PIN_AC24 -to GPIO_1[1] +set_location_assignment PIN_AA15 -to GPIO_1[2] +set_location_assignment PIN_AD26 -to GPIO_1[3] +set_location_assignment PIN_AG28 -to GPIO_1[4] +set_location_assignment PIN_AF28 -to GPIO_1[5] +set_location_assignment PIN_AE25 -to GPIO_1[6] +set_location_assignment PIN_AF27 -to GPIO_1[7] +set_location_assignment PIN_AG26 -to GPIO_1[8] +set_location_assignment PIN_AH27 -to GPIO_1[9] +set_location_assignment PIN_AG25 -to GPIO_1[10] +set_location_assignment PIN_AH26 -to GPIO_1[11] +set_location_assignment PIN_AH24 -to GPIO_1[12] +set_location_assignment PIN_AF25 -to GPIO_1[13] +set_location_assignment PIN_AG23 -to GPIO_1[14] +set_location_assignment PIN_AF23 -to GPIO_1[15] +set_location_assignment PIN_AG24 -to GPIO_1[16] +set_location_assignment PIN_AH22 -to GPIO_1[17] +set_location_assignment PIN_AH21 -to GPIO_1[18] +set_location_assignment PIN_AG21 -to GPIO_1[19] +set_location_assignment PIN_AH23 -to GPIO_1[20] +set_location_assignment PIN_AA20 -to GPIO_1[21] +set_location_assignment PIN_AF22 -to GPIO_1[22] +set_location_assignment PIN_AE22 -to GPIO_1[23] +set_location_assignment PIN_AG20 -to GPIO_1[24] +set_location_assignment PIN_AF21 -to GPIO_1[25] +set_location_assignment PIN_AG19 -to GPIO_1[26] +set_location_assignment PIN_AH19 -to GPIO_1[27] +set_location_assignment PIN_AG18 -to GPIO_1[28] +set_location_assignment PIN_AH18 -to GPIO_1[29] +set_location_assignment PIN_AF18 -to GPIO_1[30] +set_location_assignment PIN_AF20 -to GPIO_1[31] +set_location_assignment PIN_AG15 -to GPIO_1[32] +set_location_assignment PIN_AE20 -to GPIO_1[33] +set_location_assignment PIN_AE19 -to GPIO_1[34] +set_location_assignment PIN_AE17 -to GPIO_1[35] +set_location_assignment PIN_U10 -to HDMI_I2C_SCL +set_location_assignment PIN_AA4 -to HDMI_I2C_SDA +set_location_assignment PIN_T13 -to HDMI_I2S +set_location_assignment PIN_T11 -to HDMI_LRCLK +set_location_assignment PIN_U11 -to HDMI_MCLK +set_location_assignment PIN_T12 -to HDMI_SCLK +set_location_assignment PIN_AG5 -to HDMI_TX_CLK +set_location_assignment PIN_AD12 -to HDMI_TX_D[0] +set_location_assignment PIN_AE12 -to HDMI_TX_D[1] +set_location_assignment PIN_W8 -to HDMI_TX_D[2] +set_location_assignment PIN_Y8 -to HDMI_TX_D[3] +set_location_assignment PIN_AD11 -to HDMI_TX_D[4] +set_location_assignment PIN_AD10 -to HDMI_TX_D[5] +set_location_assignment PIN_AE11 -to HDMI_TX_D[6] +set_location_assignment PIN_Y5 -to HDMI_TX_D[7] +set_location_assignment PIN_AF10 -to HDMI_TX_D[8] +set_location_assignment PIN_Y4 -to HDMI_TX_D[9] +set_location_assignment PIN_AE9 -to HDMI_TX_D[10] +set_location_assignment PIN_AB4 -to HDMI_TX_D[11] +set_location_assignment PIN_AE7 -to HDMI_TX_D[12] +set_location_assignment PIN_AF6 -to HDMI_TX_D[13] +set_location_assignment PIN_AF8 -to HDMI_TX_D[14] +set_location_assignment PIN_AF5 -to HDMI_TX_D[15] +set_location_assignment PIN_AE4 -to HDMI_TX_D[16] +set_location_assignment PIN_AH2 -to HDMI_TX_D[17] +set_location_assignment PIN_AH4 -to HDMI_TX_D[18] +set_location_assignment PIN_AH5 -to HDMI_TX_D[19] +set_location_assignment PIN_AH6 -to HDMI_TX_D[20] +set_location_assignment PIN_AG6 -to HDMI_TX_D[21] +set_location_assignment PIN_AF9 -to HDMI_TX_D[22] +set_location_assignment PIN_AE8 -to HDMI_TX_D[23] +set_location_assignment PIN_AD19 -to HDMI_TX_DE +set_location_assignment PIN_T8 -to HDMI_TX_HS +set_location_assignment PIN_AF11 -to HDMI_TX_INT +set_location_assignment PIN_V13 -to HDMI_TX_VS + +set_location_assignment PIN_AH17 -to KEY[0] +set_location_assignment PIN_AH16 -to KEY[1] +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_AA23 -to LED[7] +set_location_assignment PIN_Y24 -to SW[0] +set_location_assignment PIN_W24 -to SW[1] +set_location_assignment PIN_W21 -to SW[2] +set_location_assignment PIN_W20 -to SW[3] + + + +set_global_assignment -name SDC_FILE DE10_Nano_golden_top.sdc +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files Index: Altera/DE10_Nano_VB2/DE10_Nano_VB2.v =================================================================== --- Altera/DE10_Nano_VB2/DE10_Nano_VB2.v (nonexistent) +++ Altera/DE10_Nano_VB2/DE10_Nano_VB2.v (revision 48) @@ -0,0 +1,150 @@ +// ============================================================================ +// Copyright (c) 2015 by Terasic Technologies Inc. +// ============================================================================ +// +// Permission: +// +// Terasic grants permission to use and modify this code for use +// in synthesis for all Terasic Development Boards and Altera Development +// Kits made by Terasic. Other use of this code, including the selling +// ,duplication, or modification of any portion is strictly prohibited. +// +// Disclaimer: +// +// This VHDL/Verilog or C/C++ source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Terasic provides no warranty regarding the use +// or functionality of this code. +// +// ============================================================================ +// +// Terasic Technologies Inc +// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan +// +// +// web: http://www.terasic.com/ +// email: support@terasic.com +// +// ============================================================================ +//Date: Tue Mar 3 15:11:40 2015 +// ============================================================================ + +//`define ENABLE_HPS + +module DE10_Nano_golden_top( + + ///////// ADC ///////// + output ADC_CONVST, + output ADC_SCK, + output ADC_SDI, + input ADC_SDO, + + ///////// ARDUINO ///////// + inout [15:0] ARDUINO_IO, + inout ARDUINO_RESET_N, + + ///////// FPGA ///////// + input FPGA_CLK1_50, + input FPGA_CLK2_50, + input FPGA_CLK3_50, + + ///////// GPIO ///////// + inout [35:0] GPIO_0, + inout [35:0] GPIO_1, + + ///////// HDMI ///////// + inout HDMI_I2C_SCL, + inout HDMI_I2C_SDA, + inout HDMI_I2S, + inout HDMI_LRCLK, + inout HDMI_MCLK, + inout HDMI_SCLK, + output HDMI_TX_CLK, + output [23:0] HDMI_TX_D, + output HDMI_TX_DE, + output HDMI_TX_HS, + input HDMI_TX_INT, + output HDMI_TX_VS, + +`ifdef ENABLE_HPS + ///////// HPS ///////// + inout HPS_CONV_USB_N, + output [14:0] HPS_DDR3_ADDR, + output [2:0] HPS_DDR3_BA, + output HPS_DDR3_CAS_N, + output HPS_DDR3_CKE, + output HPS_DDR3_CK_N, + output HPS_DDR3_CK_P, + output HPS_DDR3_CS_N, + output [3:0] HPS_DDR3_DM, + inout [31:0] HPS_DDR3_DQ, + inout [3:0] HPS_DDR3_DQS_N, + inout [3:0] HPS_DDR3_DQS_P, + output HPS_DDR3_ODT, + output HPS_DDR3_RAS_N, + output HPS_DDR3_RESET_N, + input HPS_DDR3_RZQ, + output HPS_DDR3_WE_N, + output HPS_ENET_GTX_CLK, + inout HPS_ENET_INT_N, + output HPS_ENET_MDC, + inout HPS_ENET_MDIO, + input HPS_ENET_RX_CLK, + input [3:0] HPS_ENET_RX_DATA, + input HPS_ENET_RX_DV, + output [3:0] HPS_ENET_TX_DATA, + output HPS_ENET_TX_EN, + inout HPS_GSENSOR_INT, + inout HPS_I2C0_SCLK, + inout HPS_I2C0_SDAT, + inout HPS_I2C1_SCLK, + inout HPS_I2C1_SDAT, + inout HPS_KEY, + inout HPS_LED, + inout HPS_LTC_GPIO, + output HPS_SD_CLK, + inout HPS_SD_CMD, + inout [3:0] HPS_SD_DATA, + output HPS_SPIM_CLK, + input HPS_SPIM_MISO, + output HPS_SPIM_MOSI, + inout HPS_SPIM_SS, + input HPS_UART_RX, + output HPS_UART_TX, + input HPS_USB_CLKOUT, + inout [7:0] HPS_USB_DATA, + input HPS_USB_DIR, + input HPS_USB_NXT, + output HPS_USB_STP, +`endif /*ENABLE_HPS*/ + + ///////// KEY ///////// + input [1:0] KEY, + + ///////// LED ///////// + output [7:0] LED, + + ///////// SW ///////// + input [3:0] SW +); + + +//======================================================= +// REG/WIRE declarations +//======================================================= + + + + + +//======================================================= +// Structural coding +//======================================================= + + + + + +endmodule Index: Altera/DE10_Nano_VB2/jtag_intfc.sh =================================================================== --- Altera/DE10_Nano_VB2/jtag_intfc.sh (nonexistent) +++ Altera/DE10_Nano_VB2/jtag_intfc.sh (revision 48) @@ -0,0 +1,9 @@ +#!/bin/bash + +PRODUCT_ID="0x6010" +HARDWARE_NAME='DE-SoC *' +DEVICE_NAME="@2*" + +JTAG_INTFC="$PRONOC_WORK/toolchain/bin/jtag_quartus_stp -a $HARDWARE_NAME -b $DEVICE_NAME" + + \ No newline at end of file Index: Altera/DE10_Nano_VB2/program_device.sh =================================================================== --- Altera/DE10_Nano_VB2/program_device.sh (nonexistent) +++ Altera/DE10_Nano_VB2/program_device.sh (revision 48) @@ -0,0 +1,24 @@ +#!/bin/bash + +#usage: +# sh program_device.sh programming_file.sof + +#programming file +#given as an argument: $1 + +#Programming mode +PROG_MODE=jtag + +#cable name. Connect the board to ur PC and then run jtagconfig in terminal to find the cable name +NAME="DE-SoC" + +#device name +DEVICE=@2 + + +#programming command +if [ -n "${QUARTUS_BIN+set}" ]; then + $QUARTUS_BIN/quartus_pgm -m $PROG_MODE -c "$NAME" -o "p;${1}${DEVICE}" +else + quartus_pgm -m $PROG_MODE -c "$NAME" -o "p;${1}${DEVICE}" +fi Index: Altera/DE1_SoC/DE1_SoC.qsf =================================================================== --- Altera/DE1_SoC/DE1_SoC.qsf (nonexistent) +++ Altera/DE1_SoC/DE1_SoC.qsf (revision 48) @@ -0,0 +1,967 @@ +#============================================================ +# Altera DE1-SoC board settings +#============================================================ + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEMA5F31C6 +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" + + +#============================================================ +# ADC +#============================================================ +set_location_assignment PIN_AJ4 -to ADC_CS_N +set_location_assignment PIN_AK4 -to ADC_DIN +set_location_assignment PIN_AK3 -to ADC_DOUT +set_location_assignment PIN_AK2 -to ADC_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_DIN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_DOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK + +#============================================================ +# AUD +#============================================================ +set_location_assignment PIN_K7 -to AUD_ADCDAT +set_location_assignment PIN_K8 -to AUD_ADCLRCK +set_location_assignment PIN_H7 -to AUD_BCLK +set_location_assignment PIN_J7 -to AUD_DACDAT +set_location_assignment PIN_H8 -to AUD_DACLRCK +set_location_assignment PIN_G7 -to AUD_XCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_AF14 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 + +#============================================================ +# CLOCK2 +#============================================================ +set_location_assignment PIN_AA16 -to CLOCK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50 + +#============================================================ +# CLOCK3 +#============================================================ +set_location_assignment PIN_Y26 -to CLOCK3_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50 + +#============================================================ +# CLOCK4 +#============================================================ +set_location_assignment PIN_K14 -to CLOCK4_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK4_50 + +#============================================================ +# DRAM +#============================================================ +set_location_assignment PIN_AK14 -to DRAM_ADDR[0] +set_location_assignment PIN_AH14 -to DRAM_ADDR[1] +set_location_assignment PIN_AG15 -to DRAM_ADDR[2] +set_location_assignment PIN_AE14 -to DRAM_ADDR[3] +set_location_assignment PIN_AB15 -to DRAM_ADDR[4] +set_location_assignment PIN_AC14 -to DRAM_ADDR[5] +set_location_assignment PIN_AD14 -to DRAM_ADDR[6] +set_location_assignment PIN_AF15 -to DRAM_ADDR[7] +set_location_assignment PIN_AH15 -to DRAM_ADDR[8] +set_location_assignment PIN_AG13 -to DRAM_ADDR[9] +set_location_assignment PIN_AG12 -to DRAM_ADDR[10] +set_location_assignment PIN_AH13 -to DRAM_ADDR[11] +set_location_assignment PIN_AJ14 -to DRAM_ADDR[12] +set_location_assignment PIN_AF13 -to DRAM_BA[0] +set_location_assignment PIN_AJ12 -to DRAM_BA[1] +set_location_assignment PIN_AF11 -to DRAM_CAS_N +set_location_assignment PIN_AK13 -to DRAM_CKE +set_location_assignment PIN_AH12 -to DRAM_CLK +set_location_assignment PIN_AG11 -to DRAM_CS_N +set_location_assignment PIN_AK6 -to DRAM_DQ[0] +set_location_assignment PIN_AJ7 -to DRAM_DQ[1] +set_location_assignment PIN_AK7 -to DRAM_DQ[2] +set_location_assignment PIN_AK8 -to DRAM_DQ[3] +set_location_assignment PIN_AK9 -to DRAM_DQ[4] +set_location_assignment PIN_AG10 -to DRAM_DQ[5] +set_location_assignment PIN_AK11 -to DRAM_DQ[6] +set_location_assignment PIN_AJ11 -to DRAM_DQ[7] +set_location_assignment PIN_AH10 -to DRAM_DQ[8] +set_location_assignment PIN_AJ10 -to DRAM_DQ[9] +set_location_assignment PIN_AJ9 -to DRAM_DQ[10] +set_location_assignment PIN_AH9 -to DRAM_DQ[11] +set_location_assignment PIN_AH8 -to DRAM_DQ[12] +set_location_assignment PIN_AH7 -to DRAM_DQ[13] +set_location_assignment PIN_AJ6 -to DRAM_DQ[14] +set_location_assignment PIN_AJ5 -to DRAM_DQ[15] +set_location_assignment PIN_AB13 -to DRAM_LDQM +set_location_assignment PIN_AE13 -to DRAM_RAS_N +set_location_assignment PIN_AK12 -to DRAM_UDQM +set_location_assignment PIN_AA13 -to DRAM_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N + +#============================================================ +# FAN +#============================================================ +set_location_assignment PIN_AA12 -to FAN_CTRL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FAN_CTRL + +#============================================================ +# FPGA +#============================================================ +set_location_assignment PIN_J12 -to FPGA_I2C_SCLK +set_location_assignment PIN_K12 -to FPGA_I2C_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_I2C_SDAT + +#============================================================ +# GPIO +#============================================================ +set_location_assignment PIN_AC18 -to GPIO_0[0] +set_location_assignment PIN_AH18 -to GPIO_0[10] +set_location_assignment PIN_AH17 -to GPIO_0[11] +set_location_assignment PIN_AG16 -to GPIO_0[12] +set_location_assignment PIN_AE16 -to GPIO_0[13] +set_location_assignment PIN_AF16 -to GPIO_0[14] +set_location_assignment PIN_AG17 -to GPIO_0[15] +set_location_assignment PIN_AA18 -to GPIO_0[16] +set_location_assignment PIN_AA19 -to GPIO_0[17] +set_location_assignment PIN_AE17 -to GPIO_0[18] +set_location_assignment PIN_AC20 -to GPIO_0[19] +set_location_assignment PIN_Y17 -to GPIO_0[1] +set_location_assignment PIN_AH19 -to GPIO_0[20] +set_location_assignment PIN_AJ20 -to GPIO_0[21] +set_location_assignment PIN_AH20 -to GPIO_0[22] +set_location_assignment PIN_AK21 -to GPIO_0[23] +set_location_assignment PIN_AD19 -to GPIO_0[24] +set_location_assignment PIN_AD20 -to GPIO_0[25] +set_location_assignment PIN_AE18 -to GPIO_0[26] +set_location_assignment PIN_AE19 -to GPIO_0[27] +set_location_assignment PIN_AF20 -to GPIO_0[28] +set_location_assignment PIN_AF21 -to GPIO_0[29] +set_location_assignment PIN_AD17 -to GPIO_0[2] +set_location_assignment PIN_AF19 -to GPIO_0[30] +set_location_assignment PIN_AG21 -to GPIO_0[31] +set_location_assignment PIN_AF18 -to GPIO_0[32] +set_location_assignment PIN_AG20 -to GPIO_0[33] +set_location_assignment PIN_AG18 -to GPIO_0[34] +set_location_assignment PIN_AJ21 -to GPIO_0[35] +set_location_assignment PIN_Y18 -to GPIO_0[3] +set_location_assignment PIN_AK16 -to GPIO_0[4] +set_location_assignment PIN_AK18 -to GPIO_0[5] +set_location_assignment PIN_AK19 -to GPIO_0[6] +set_location_assignment PIN_AJ19 -to GPIO_0[7] +set_location_assignment PIN_AJ17 -to GPIO_0[8] +set_location_assignment PIN_AJ16 -to GPIO_0[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] + +set_location_assignment PIN_AB17 -to GPIO_1[0] +set_location_assignment PIN_AG26 -to GPIO_1[10] +set_location_assignment PIN_AH24 -to GPIO_1[11] +set_location_assignment PIN_AH27 -to GPIO_1[12] +set_location_assignment PIN_AJ27 -to GPIO_1[13] +set_location_assignment PIN_AK29 -to GPIO_1[14] +set_location_assignment PIN_AK28 -to GPIO_1[15] +set_location_assignment PIN_AK27 -to GPIO_1[16] +set_location_assignment PIN_AJ26 -to GPIO_1[17] +set_location_assignment PIN_AK26 -to GPIO_1[18] +set_location_assignment PIN_AH25 -to GPIO_1[19] +set_location_assignment PIN_AA21 -to GPIO_1[1] +set_location_assignment PIN_AJ25 -to GPIO_1[20] +set_location_assignment PIN_AJ24 -to GPIO_1[21] +set_location_assignment PIN_AK24 -to GPIO_1[22] +set_location_assignment PIN_AG23 -to GPIO_1[23] +set_location_assignment PIN_AK23 -to GPIO_1[24] +set_location_assignment PIN_AH23 -to GPIO_1[25] +set_location_assignment PIN_AK22 -to GPIO_1[26] +set_location_assignment PIN_AJ22 -to GPIO_1[27] +set_location_assignment PIN_AH22 -to GPIO_1[28] +set_location_assignment PIN_AG22 -to GPIO_1[29] +set_location_assignment PIN_AB21 -to GPIO_1[2] +set_location_assignment PIN_AF24 -to GPIO_1[30] +set_location_assignment PIN_AF23 -to GPIO_1[31] +set_location_assignment PIN_AE22 -to GPIO_1[32] +set_location_assignment PIN_AD21 -to GPIO_1[33] +set_location_assignment PIN_AA20 -to GPIO_1[34] +set_location_assignment PIN_AC22 -to GPIO_1[35] +set_location_assignment PIN_AC23 -to GPIO_1[3] +set_location_assignment PIN_AD24 -to GPIO_1[4] +set_location_assignment PIN_AE23 -to GPIO_1[5] +set_location_assignment PIN_AE24 -to GPIO_1[6] +set_location_assignment PIN_AF25 -to GPIO_1[7] +set_location_assignment PIN_AF26 -to GPIO_1[8] +set_location_assignment PIN_AG25 -to GPIO_1[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9] + +#============================================================ +# HEX0 +#============================================================ +set_location_assignment PIN_AE26 -to HEX0[0] +set_location_assignment PIN_AE27 -to HEX0[1] +set_location_assignment PIN_AE28 -to HEX0[2] +set_location_assignment PIN_AG27 -to HEX0[3] +set_location_assignment PIN_AF28 -to HEX0[4] +set_location_assignment PIN_AG28 -to HEX0[5] +set_location_assignment PIN_AH28 -to HEX0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] + +#============================================================ +# HEX1 +#============================================================ +set_location_assignment PIN_AJ29 -to HEX1[0] +set_location_assignment PIN_AH29 -to HEX1[1] +set_location_assignment PIN_AH30 -to HEX1[2] +set_location_assignment PIN_AG30 -to HEX1[3] +set_location_assignment PIN_AF29 -to HEX1[4] +set_location_assignment PIN_AF30 -to HEX1[5] +set_location_assignment PIN_AD27 -to HEX1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] + +#============================================================ +# HEX2 +#============================================================ +set_location_assignment PIN_AB23 -to HEX2[0] +set_location_assignment PIN_AE29 -to HEX2[1] +set_location_assignment PIN_AD29 -to HEX2[2] +set_location_assignment PIN_AC28 -to HEX2[3] +set_location_assignment PIN_AD30 -to HEX2[4] +set_location_assignment PIN_AC29 -to HEX2[5] +set_location_assignment PIN_AC30 -to HEX2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] + +#============================================================ +# HEX3 +#============================================================ +set_location_assignment PIN_AD26 -to HEX3[0] +set_location_assignment PIN_AC27 -to HEX3[1] +set_location_assignment PIN_AD25 -to HEX3[2] +set_location_assignment PIN_AC25 -to HEX3[3] +set_location_assignment PIN_AB28 -to HEX3[4] +set_location_assignment PIN_AB25 -to HEX3[5] +set_location_assignment PIN_AB22 -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] + +#============================================================ +# HEX4 +#============================================================ +set_location_assignment PIN_AA24 -to HEX4[0] +set_location_assignment PIN_Y23 -to HEX4[1] +set_location_assignment PIN_Y24 -to HEX4[2] +set_location_assignment PIN_W22 -to HEX4[3] +set_location_assignment PIN_W24 -to HEX4[4] +set_location_assignment PIN_V23 -to HEX4[5] +set_location_assignment PIN_W25 -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] + +#============================================================ +# HEX5 +#============================================================ +set_location_assignment PIN_V25 -to HEX5[0] +set_location_assignment PIN_AA28 -to HEX5[1] +set_location_assignment PIN_Y27 -to HEX5[2] +set_location_assignment PIN_AB27 -to HEX5[3] +set_location_assignment PIN_AB26 -to HEX5[4] +set_location_assignment PIN_AA26 -to HEX5[5] +set_location_assignment PIN_AA25 -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] + +#============================================================ +# IRDA +#============================================================ +set_location_assignment PIN_AA30 -to IRDA_RXD +set_location_assignment PIN_AB30 -to IRDA_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_TXD + +#============================================================ +# KEY +#============================================================ +set_location_assignment PIN_AA14 -to KEY[0] +set_location_assignment PIN_AA15 -to KEY[1] +set_location_assignment PIN_W15 -to KEY[2] +set_location_assignment PIN_Y16 -to KEY[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3] + +#============================================================ +# LEDR +#============================================================ +set_location_assignment PIN_V16 -to LEDR[0] +set_location_assignment PIN_W16 -to LEDR[1] +set_location_assignment PIN_V17 -to LEDR[2] +set_location_assignment PIN_V18 -to LEDR[3] +set_location_assignment PIN_W17 -to LEDR[4] +set_location_assignment PIN_W19 -to LEDR[5] +set_location_assignment PIN_Y19 -to LEDR[6] +set_location_assignment PIN_W20 -to LEDR[7] +set_location_assignment PIN_W21 -to LEDR[8] +set_location_assignment PIN_Y21 -to LEDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] + +#============================================================ +# PS2 +#============================================================ +set_location_assignment PIN_AD7 -to PS2_CLK +set_location_assignment PIN_AE7 -to PS2_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT + +set_location_assignment PIN_AD9 -to PS2_CLK2 +set_location_assignment PIN_AE9 -to PS2_DAT2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2 + +#============================================================ +# SW +#============================================================ +set_location_assignment PIN_AB12 -to SW[0] +set_location_assignment PIN_AC12 -to SW[1] +set_location_assignment PIN_AF9 -to SW[2] +set_location_assignment PIN_AF10 -to SW[3] +set_location_assignment PIN_AD11 -to SW[4] +set_location_assignment PIN_AD12 -to SW[5] +set_location_assignment PIN_AE11 -to SW[6] +set_location_assignment PIN_AC9 -to SW[7] +set_location_assignment PIN_AD10 -to SW[8] +set_location_assignment PIN_AE12 -to SW[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] + +#============================================================ +# TD +#============================================================ +set_location_assignment PIN_H15 -to TD_CLK27 +set_location_assignment PIN_D2 -to TD_DATA[0] +set_location_assignment PIN_B1 -to TD_DATA[1] +set_location_assignment PIN_E2 -to TD_DATA[2] +set_location_assignment PIN_B2 -to TD_DATA[3] +set_location_assignment PIN_D1 -to TD_DATA[4] +set_location_assignment PIN_E1 -to TD_DATA[5] +set_location_assignment PIN_C2 -to TD_DATA[6] +set_location_assignment PIN_B3 -to TD_DATA[7] +set_location_assignment PIN_A5 -to TD_HS +set_location_assignment PIN_F6 -to TD_RESET_N +set_location_assignment PIN_A3 -to TD_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS + +#============================================================ +# USB +#============================================================ +set_location_assignment PIN_AF4 -to USB_B2_CLK +set_location_assignment PIN_AH4 -to USB_B2_DATA[0] +set_location_assignment PIN_AH3 -to USB_B2_DATA[1] +set_location_assignment PIN_AJ2 -to USB_B2_DATA[2] +set_location_assignment PIN_AJ1 -to USB_B2_DATA[3] +set_location_assignment PIN_AH2 -to USB_B2_DATA[4] +set_location_assignment PIN_AG3 -to USB_B2_DATA[5] +set_location_assignment PIN_AG2 -to USB_B2_DATA[6] +set_location_assignment PIN_AG1 -to USB_B2_DATA[7] +set_location_assignment PIN_AF5 -to USB_EMPTY +set_location_assignment PIN_AG5 -to USB_FULL +set_location_assignment PIN_AF6 -to USB_OE_N +set_location_assignment PIN_AG6 -to USB_RD_N +set_location_assignment PIN_AG7 -to USB_RESET_N +set_location_assignment PIN_AG8 -to USB_SCL +set_location_assignment PIN_AF8 -to USB_SDA +set_location_assignment PIN_AH5 -to USB_WR_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_EMPTY +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FULL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_OE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_RD_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_WR_N + +#============================================================ +# VGA +#============================================================ +set_location_assignment PIN_B13 -to VGA_B[0] +set_location_assignment PIN_G13 -to VGA_B[1] +set_location_assignment PIN_H13 -to VGA_B[2] +set_location_assignment PIN_F14 -to VGA_B[3] +set_location_assignment PIN_H14 -to VGA_B[4] +set_location_assignment PIN_F15 -to VGA_B[5] +set_location_assignment PIN_G15 -to VGA_B[6] +set_location_assignment PIN_J14 -to VGA_B[7] +set_location_assignment PIN_F10 -to VGA_BLANK_N +set_location_assignment PIN_A11 -to VGA_CLK +set_location_assignment PIN_J9 -to VGA_G[0] +set_location_assignment PIN_J10 -to VGA_G[1] +set_location_assignment PIN_H12 -to VGA_G[2] +set_location_assignment PIN_G10 -to VGA_G[3] +set_location_assignment PIN_G11 -to VGA_G[4] +set_location_assignment PIN_G12 -to VGA_G[5] +set_location_assignment PIN_F11 -to VGA_G[6] +set_location_assignment PIN_E11 -to VGA_G[7] +set_location_assignment PIN_B11 -to VGA_HS +set_location_assignment PIN_A13 -to VGA_R[0] +set_location_assignment PIN_C13 -to VGA_R[1] +set_location_assignment PIN_E13 -to VGA_R[2] +set_location_assignment PIN_B12 -to VGA_R[3] +set_location_assignment PIN_C12 -to VGA_R[4] +set_location_assignment PIN_D12 -to VGA_R[5] +set_location_assignment PIN_E12 -to VGA_R[6] +set_location_assignment PIN_F13 -to VGA_R[7] +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_location_assignment PIN_D11 -to VGA_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS + +#============================================================ +# HPS +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_BA[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_BA[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_BA[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_CAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_CKE +set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_CK_N +set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_CK_P +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_CS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DM[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DM[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DM[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DM[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[15] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[16] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[17] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[18] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[19] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[20] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[21] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[22] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[23] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[24] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[25] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[26] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[27] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[28] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[29] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[30] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[31] +set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ODT +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_RAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_RESET_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_NCSO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C2_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C2_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C_CONTROL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP +set_instance_assignment -name io_standard "3.3-V LVTTL" -to HPS_GPIO[0] +set_instance_assignment -name io_standard "3.3-V LVTTL" -to HPS_GPIO[1] + +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CAS_N +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CS_N +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ODT +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_RAS_N +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_WE_N +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_RESET_N + +set_instance_assignment -name D5_DELAY 2 -to HPS_DDR3_CK_P +set_instance_assignment -name D5_DELAY 2 -to HPS_DDR3_CK_N + +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[3] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[4] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[5] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[6] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[7] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[8] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[9] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[10] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[11] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[12] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[13] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[14] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[15] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[16] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[17] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[18] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[19] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[20] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[21] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[22] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[23] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[24] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[25] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[26] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[27] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[28] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[29] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[30] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[31] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[3] + +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[8] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[9] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[10] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[11] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[12] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[13] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[14] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[15] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[16] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[17] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[18] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[19] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[20] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[21] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[22] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[23] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[24] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[25] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[26] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[27] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[28] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[29] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[30] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[31] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to HPS_DDR3_CK_P +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to HPS_DDR3_CK_N +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[3] + +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[4] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[5] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[6] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[7] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[8] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[9] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[10] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[11] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[12] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[13] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[14] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[15] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[16] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[17] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[18] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[19] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[20] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[21] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[22] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[23] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[24] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[25] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[26] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[27] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[28] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[29] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[30] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[31] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[10] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[11] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[12] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[13] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[14] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[4] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[5] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[6] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[7] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[8] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[9] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CAS_N +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CKE +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CS_N +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ODT +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_RAS_N +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_WE_N +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_RESET_N +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CK_P +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CK_N + +#============================================================ +# End of pin and io_standard assignments +#============================================================ + + +set_global_assignment -name LAST_QUARTUS_VERSION 14.0 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation +set_global_assignment -name SDC_FILE DE1_SoC.sdc +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name STATE_MACHINE_PROCESSING "USER-ENCODED" Index: Altera/DE1_SoC/DE1_SoC.v =================================================================== --- Altera/DE1_SoC/DE1_SoC.v (nonexistent) +++ Altera/DE1_SoC/DE1_SoC.v (revision 48) @@ -0,0 +1,198 @@ +============================================================================ +// Copyright (c) 2013 by Terasic Technologies Inc. +// ============================================================================ +// +// Permission: +// +// Terasic grants permission to use and modify this code for use +// in synthesis for all Terasic Development Boards and Altera Development +// Kits made by Terasic. Other use of this code, including the selling +// ,duplication, or modification of any portion is strictly prohibited. +// +// Disclaimer: +// +// This VHDL/Verilog or C/C++ source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Terasic provides no warranty regarding the use +// or functionality of this code. +// +// ============================================================================ +// +// Terasic Technologies Inc +// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan +// +// +// web: http://www.terasic.com/ +// email: support@terasic.com +// +// ============================================================================ +//Date: Thu Jul 11 11:26:45 2013 +// ============================================================================ + +`define ENABLE_ADC +`define ENABLE_AUD +`define ENABLE_CLOCK2 +`define ENABLE_CLOCK3 +`define ENABLE_CLOCK4 +`define ENABLE_CLOCK +`define ENABLE_DRAM +`define ENABLE_FAN +`define ENABLE_FPGA +`define ENABLE_GPIO +`define ENABLE_HEX +//`define ENABLE_HPS +`define ENABLE_IRDA +`define ENABLE_KEY +`define ENABLE_LEDR +`define ENABLE_PS2 +`define ENABLE_SW +`define ENABLE_TD +`define ENABLE_VGA + +module DE1_SOC_golden_top( + + /* Enables ADC - 3.3V */ + `ifdef ENABLE_ADC + + output ADC_CONVST, + output ADC_DIN, + input ADC_DOUT, + output ADC_SCLK, + + `endif + + /* Enables AUD - 3.3V */ + `ifdef ENABLE_AUD + + input AUD_ADCDAT, + inout AUD_ADCLRCK, + inout AUD_BCLK, + output AUD_DACDAT, + inout AUD_DACLRCK, + output AUD_XCK, + + `endif + + /* Enables CLOCK2 */ + `ifdef ENABLE_CLOCK2 + input CLOCK2_50, + `endif + + /* Enables CLOCK3 */ + `ifdef ENABLE_CLOCK3 + input CLOCK3_50, + `endif + + /* Enables CLOCK4 */ + `ifdef ENABLE_CLOCK4 + input CLOCK4_50, + `endif + + /* Enables CLOCK */ + `ifdef ENABLE_CLOCK + input CLOCK_50, + `endif + + /* Enables DRAM - 3.3V */ + `ifdef ENABLE_DRAM + output [12:0] DRAM_ADDR, + output [1:0] DRAM_BA, + output DRAM_CAS_N, + output DRAM_CKE, + output DRAM_CLK, + output DRAM_CS_N, + inout [15:0] DRAM_DQ, + output DRAM_LDQM, + output DRAM_RAS_N, + output DRAM_UDQM, + output DRAM_WE_N, + `endif + + /* Enables FAN - 3.3V */ + `ifdef ENABLE_FAN + output FAN_CTRL, + `endif + + /* Enables FPGA - 3.3V */ + `ifdef ENABLE_FPGA + output FPGA_I2C_SCLK, + inout FPGA_I2C_SDAT, + `endif + + /* Enables GPIO - 3.3V */ + `ifdef ENABLE_GPIO + inout [35:0] GPIO_0, + inout [35:0] GPIO_1, + `endif + + + /* Enables HEX - 3.3V */ + `ifdef ENABLE_HEX + output [6:0] HEX0, + output [6:0] HEX1, + output [6:0] HEX2, + output [6:0] HEX3, + output [6:0] HEX4, + output [6:0] HEX5, + `endif + + /* Enables HPS */ + `ifdef ENABLE_HPS + inout HPS_CONV_USB_N, + output [14:0] HPS_DDR3_ADDR, + output [2:0] HPS_DDR3_BA, + output HPS_DDR3_CAS_N, + output HPS_DDR3_CKE, + output HPS_DDR3_CK_N, //1.5V + output HPS_DDR3_CK_P, //1.5V + output HPS_DDR3_CS_N, + output [3:0] HPS_DDR3_DM, + inout [31:0] HPS_DDR3_DQ, + inout [3:0] HPS_DDR3_DQS_N, + inout [3:0] HPS_DDR3_DQS_P, + output HPS_DDR3_ODT, + output HPS_DDR3_RAS_N, + output HPS_DDR3_RESET_N, + input HPS_DDR3_RZQ, + output HPS_DDR3_WE_N, + output HPS_ENET_GTX_CLK, + inout HPS_ENET_INT_N, + output HPS_ENET_MDC, + inout HPS_ENET_MDIO, + input HPS_ENET_RX_CLK, + input [3:0] HPS_ENET_RX_DATA, + input HPS_ENET_RX_DV, + output [3:0] HPS_ENET_TX_DATA, + output HPS_ENET_TX_EN, + inout [3:0] HPS_FLASH_DATA, + output HPS_FLASH_DCLK, + output HPS_FLASH_NCSO, + inout HPS_GSENSOR_INT, + inout HPS_I2C1_SCLK, + inout HPS_I2C1_SDAT, + inout HPS_I2C2_SCLK, + inout HPS_I2C2_SDAT, + inout HPS_I2C_CONTROL, + inout HPS_KEY, + inout HPS_LED, + inout HPS_LTC_GPIO, + output HPS_SD_CLK, + inout HPS_SD_CMD, + inout [3:0] HPS_SD_DATA, + output HPS_SPIM_CLK, + input HPS_SPIM_MISO, + output HPS_SPIM_MOSI, + inout HPS_SPIM_SS, + input HPS_UART_RX, + output HPS_UART_TX, + input HPS_USB_CLKOUT, + inout [7:0] HPS_USB_DATA, + input HPS_USB_DIR, + input HPS_USB_NXT, + output HPS_USB_STP, +`endif + +endmodule + Index: Altera/DE1_SoC/jtag_intfc.sh =================================================================== --- Altera/DE1_SoC/jtag_intfc.sh (nonexistent) +++ Altera/DE1_SoC/jtag_intfc.sh (revision 48) @@ -0,0 +1,6 @@ +#!/bin/bash + +PRODUCT_ID="0x6001" +JTAG_INTFC="$PRONOC_WORK/toolchain/bin/jtag_libusb -a $PRODUCT_ID" + + Index: Altera/DE1_SoC/program_device.sh =================================================================== --- Altera/DE1_SoC/program_device.sh (nonexistent) +++ Altera/DE1_SoC/program_device.sh (revision 48) @@ -0,0 +1,28 @@ +#!/bin/bash + +#usage: +# sh program_device.sh programming_file.sof + +#programming file +#given as an argument: $1 + +#Programming mode +PROG_MODE=jtag + +#cable name. Connect the board to ur PC and then run jtagconfig in terminal to find the cable name +NAME="DE-SoC" + +#device name +DEVICE=@2 + + +#programming command +if [ -n "${QUARTUS_BIN+set}" ]; then + $QUARTUS_BIN/quartus_pgm -m $PROG_MODE -c "$NAME" -o "p;${1}${DEVICE}" +else + quartus_pgm -m $PROG_MODE -c "$NAME" -o "p;${1}${DEVICE}" +fi + + + + Index: Altera/DE2_115/DE2_115.v =================================================================== --- Altera/DE2_115/DE2_115.v (nonexistent) +++ Altera/DE2_115/DE2_115.v (revision 48) @@ -0,0 +1,447 @@ +// -------------------------------------------------------------------- +// Copyright (c) 2010 by Terasic Technologies Inc. +// -------------------------------------------------------------------- +// +// Permission: +// +// Terasic grants permission to use and modify this code for use +// in synthesis for all Terasic Development Boards and Altera Development +// Kits made by Terasic. Other use of this code, including the selling +// ,duplication, or modification of any portion is strictly prohibited. +// +// Disclaimer: +// +// This VHDL/Verilog or C/C++ source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Terasic provides no warranty regarding the use +// or functionality of this code. +// +// -------------------------------------------------------------------- +// +// Terasic Technologies Inc +// 356 Fu-Shin E. Rd Sec. 1. JhuBei City, +// HsinChu County, Taiwan +// 302 +// +// web: http://www.terasic.com/ +// email: support@terasic.com +// +// -------------------------------------------------------------------- +// +// Major Functions: DE2_115 Top Entity Reference Design +// +// -------------------------------------------------------------------- +// +// Revision History : +// -------------------------------------------------------------------- +// Ver :| Author :| Mod. Date :| Changes Made: +// V1.0 :| Richard :| 07/09/10 :| Initial Revision +// -------------------------------------------------------------------- +module DE2_115_GOLDEN_TOP( + + //////// CLOCK ////////// + CLOCK_50, + CLOCK2_50, + CLOCK3_50, + ENETCLK_25, + + //////// Sma ////////// + SMA_CLKIN, + SMA_CLKOUT, + + //////// LED ////////// + LEDG, + LEDR, + + //////// KEY ////////// + KEY, + + //////// SW ////////// + SW, + + //////// SEG7 ////////// + HEX0, + HEX1, + HEX2, + HEX3, + HEX4, + HEX5, + HEX6, + HEX7, + + //////// LCD ////////// + LCD_BLON, + LCD_DATA, + LCD_EN, + LCD_ON, + LCD_RS, + LCD_RW, + + //////// RS232 ////////// + UART_CTS, + UART_RTS, + UART_RXD, + UART_TXD, + + //////// PS2 ////////// + PS2_CLK, + PS2_DAT, + PS2_CLK2, + PS2_DAT2, + + //////// SDCARD ////////// + SD_CLK, + SD_CMD, + SD_DAT, + SD_WP_N, + + //////// VGA ////////// + VGA_B, + VGA_BLANK_N, + VGA_CLK, + VGA_G, + VGA_HS, + VGA_R, + VGA_SYNC_N, + VGA_VS, + + //////// Audio ////////// + AUD_ADCDAT, + AUD_ADCLRCK, + AUD_BCLK, + AUD_DACDAT, + AUD_DACLRCK, + AUD_XCK, + + //////// I2C for EEPROM ////////// + EEP_I2C_SCLK, + EEP_I2C_SDAT, + + //////// I2C for Audio and Tv-Decode ////////// + I2C_SCLK, + I2C_SDAT, + + //////// Ethernet 0 ////////// + ENET0_GTX_CLK, + ENET0_INT_N, + ENET0_MDC, + ENET0_MDIO, + ENET0_RST_N, + ENET0_RX_CLK, + ENET0_RX_COL, + ENET0_RX_CRS, + ENET0_RX_DATA, + ENET0_RX_DV, + ENET0_RX_ER, + ENET0_TX_CLK, + ENET0_TX_DATA, + ENET0_TX_EN, + ENET0_TX_ER, + ENET0_LINK100, + + //////// Ethernet 1 ////////// + ENET1_GTX_CLK, + ENET1_INT_N, + ENET1_MDC, + ENET1_MDIO, + ENET1_RST_N, + ENET1_RX_CLK, + ENET1_RX_COL, + ENET1_RX_CRS, + ENET1_RX_DATA, + ENET1_RX_DV, + ENET1_RX_ER, + ENET1_TX_CLK, + ENET1_TX_DATA, + ENET1_TX_EN, + ENET1_TX_ER, + ENET1_LINK100, + + //////// TV Decoder ////////// + TD_CLK27, + TD_DATA, + TD_HS, + TD_RESET_N, + TD_VS, + + /////// USB OTG controller + OTG_DATA, + OTG_ADDR, + OTG_CS_N, + OTG_WR_N, + OTG_RD_N, + OTG_INT, + OTG_RST_N, + OTG_DREQ, + OTG_DACK_N, + OTG_FSPEED, + OTG_LSPEED, + + //////// IR Receiver ////////// + IRDA_RXD, + + //////// SDRAM ////////// + DRAM_ADDR, + DRAM_BA, + DRAM_CAS_N, + DRAM_CKE, + DRAM_CLK, + DRAM_CS_N, + DRAM_DQ, + DRAM_DQM, + DRAM_RAS_N, + DRAM_WE_N, + + //////// SRAM ////////// + SRAM_ADDR, + SRAM_CE_N, + SRAM_DQ, + SRAM_LB_N, + SRAM_OE_N, + SRAM_UB_N, + SRAM_WE_N, + + //////// Flash ////////// + FL_ADDR, + FL_CE_N, + FL_DQ, + FL_OE_N, + FL_RST_N, + FL_RY, + FL_WE_N, + FL_WP_N, + + //////// GPIO ////////// + GPIO, + + //////// HSMC (LVDS) ////////// +// HSMC_CLKIN_N1, +// HSMC_CLKIN_N2, + HSMC_CLKIN_P1, + HSMC_CLKIN_P2, + HSMC_CLKIN0, +// HSMC_CLKOUT_N1, +// HSMC_CLKOUT_N2, + HSMC_CLKOUT_P1, + HSMC_CLKOUT_P2, + HSMC_CLKOUT0, + HSMC_D, +// HSMC_RX_D_N, + HSMC_RX_D_P, +// HSMC_TX_D_N, + HSMC_TX_D_P, + + //////// EXTEND IO ////////// + EX_IO +); + +//======================================================= +// PARAMETER declarations +//======================================================= + + +//======================================================= +// PORT declarations +//======================================================= + +//////////// CLOCK ////////// +input CLOCK_50; +input CLOCK2_50; +input CLOCK3_50; +input ENETCLK_25; + +//////////// Sma ////////// +input SMA_CLKIN; +output SMA_CLKOUT; + +//////////// LED ////////// +output [8:0] LEDG; +output [17:0] LEDR; + +//////////// KEY ////////// +input [3:0] KEY; + +//////////// SW ////////// +input [17:0] SW; + +//////////// SEG7 ////////// +output [6:0] HEX0; +output [6:0] HEX1; +output [6:0] HEX2; +output [6:0] HEX3; +output [6:0] HEX4; +output [6:0] HEX5; +output [6:0] HEX6; +output [6:0] HEX7; + +//////////// LCD ////////// +output LCD_BLON; +inout [7:0] LCD_DATA; +output LCD_EN; +output LCD_ON; +output LCD_RS; +output LCD_RW; + +//////////// RS232 ////////// +output UART_CTS; +input UART_RTS; +input UART_RXD; +output UART_TXD; + +//////////// PS2 ////////// +inout PS2_CLK; +inout PS2_DAT; +inout PS2_CLK2; +inout PS2_DAT2; + +//////////// SDCARD ////////// +output SD_CLK; +inout SD_CMD; +inout [3:0] SD_DAT; +input SD_WP_N; + +//////////// VGA ////////// +output [7:0] VGA_B; +output VGA_BLANK_N; +output VGA_CLK; +output [7:0] VGA_G; +output VGA_HS; +output [7:0] VGA_R; +output VGA_SYNC_N; +output VGA_VS; + +//////////// Audio ////////// +input AUD_ADCDAT; +inout AUD_ADCLRCK; +inout AUD_BCLK; +output AUD_DACDAT; +inout AUD_DACLRCK; +output AUD_XCK; + +//////////// I2C for EEPROM ////////// +output EEP_I2C_SCLK; +inout EEP_I2C_SDAT; + +//////////// I2C for Audio and Tv-Decode ////////// +output I2C_SCLK; +inout I2C_SDAT; + +//////////// Ethernet 0 ////////// +output ENET0_GTX_CLK; +input ENET0_INT_N; +output ENET0_MDC; +inout ENET0_MDIO; +output ENET0_RST_N; +input ENET0_RX_CLK; +input ENET0_RX_COL; +input ENET0_RX_CRS; +input [3:0] ENET0_RX_DATA; +input ENET0_RX_DV; +input ENET0_RX_ER; +input ENET0_TX_CLK; +output [3:0] ENET0_TX_DATA; +output ENET0_TX_EN; +output ENET0_TX_ER; +input ENET0_LINK100; + +//////////// Ethernet 1 ////////// +output ENET1_GTX_CLK; +input ENET1_INT_N; +output ENET1_MDC; +inout ENET1_MDIO; +output ENET1_RST_N; +input ENET1_RX_CLK; +input ENET1_RX_COL; +input ENET1_RX_CRS; +input [3:0] ENET1_RX_DATA; +input ENET1_RX_DV; +input ENET1_RX_ER; +input ENET1_TX_CLK; +output [3:0] ENET1_TX_DATA; +output ENET1_TX_EN; +output ENET1_TX_ER; +input ENET1_LINK100; + +//////////// TV Decoder 1 ////////// +input TD_CLK27; +input [7:0] TD_DATA; +input TD_HS; +output TD_RESET_N; +input TD_VS; + + +//////////// USB OTG controller ////////// +inout [15:0] OTG_DATA; +output [1:0] OTG_ADDR; +output OTG_CS_N; +output OTG_WR_N; +output OTG_RD_N; +input [1:0] OTG_INT; +output OTG_RST_N; +input [1:0] OTG_DREQ; +output [1:0] OTG_DACK_N; +inout OTG_FSPEED; +inout OTG_LSPEED; + +//////////// IR Receiver ////////// +input IRDA_RXD; + +//////////// SDRAM ////////// +output [12:0] DRAM_ADDR; +output [1:0] DRAM_BA; +output DRAM_CAS_N; +output DRAM_CKE; +output DRAM_CLK; +output DRAM_CS_N; +inout [31:0] DRAM_DQ; +output [3:0] DRAM_DQM; +output DRAM_RAS_N; +output DRAM_WE_N; + +//////////// SRAM ////////// +output [19:0] SRAM_ADDR; +output SRAM_CE_N; +inout [15:0] SRAM_DQ; +output SRAM_LB_N; +output SRAM_OE_N; +output SRAM_UB_N; +output SRAM_WE_N; + +//////////// Flash ////////// +output [22:0] FL_ADDR; +output FL_CE_N; +inout [7:0] FL_DQ; +output FL_OE_N; +output FL_RST_N; +input FL_RY; +output FL_WE_N; +output FL_WP_N; + +//////////// GPIO ////////// +inout [35:0] GPIO; + +//////////// HSMC (LVDS) ////////// + +//input HSMC_CLKIN_N1; +//input HSMC_CLKIN_N2; +input HSMC_CLKIN_P1; +input HSMC_CLKIN_P2; +input HSMC_CLKIN0; +//output HSMC_CLKOUT_N1; +//output HSMC_CLKOUT_N2; +output HSMC_CLKOUT_P1; +output HSMC_CLKOUT_P2; +output HSMC_CLKOUT0; +inout [3:0] HSMC_D; +//input [16:0] HSMC_RX_D_N; +input [16:0] HSMC_RX_D_P; +//output [16:0] HSMC_TX_D_N; +output [16:0] HSMC_TX_D_P; + +//////// EXTEND IO ////////// +inout [6:0] EX_IO; + +endmodule + Index: Altera/DE2_115/De2_115.qsf =================================================================== --- Altera/DE2_115/De2_115.qsf (nonexistent) +++ Altera/DE2_115/De2_115.qsf (revision 48) @@ -0,0 +1,546 @@ + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE115F29C7 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 780 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + +set_location_assignment PIN_Y2 -to CLOCK_50 +set_location_assignment PIN_AG14 -to CLOCK2_50 +set_location_assignment PIN_AG15 -to CLOCK3_50 +set_location_assignment PIN_AH14 -to SMA_CLKIN +set_location_assignment PIN_AE23 -to SMA_CLKOUT +set_location_assignment PIN_E21 -to LEDG[0] +set_location_assignment PIN_E22 -to LEDG[1] +set_location_assignment PIN_E25 -to LEDG[2] +set_location_assignment PIN_E24 -to LEDG[3] +set_location_assignment PIN_H21 -to LEDG[4] +set_location_assignment PIN_G20 -to LEDG[5] +set_location_assignment PIN_G22 -to LEDG[6] +set_location_assignment PIN_G21 -to LEDG[7] +set_location_assignment PIN_F17 -to LEDG[8] +set_location_assignment PIN_G19 -to LEDR[0] +set_location_assignment PIN_E19 -to LEDR[2] +set_location_assignment PIN_F19 -to LEDR[1] +set_location_assignment PIN_F21 -to LEDR[3] +set_location_assignment PIN_F18 -to LEDR[4] +set_location_assignment PIN_E18 -to LEDR[5] +set_location_assignment PIN_J19 -to LEDR[6] +set_location_assignment PIN_H19 -to LEDR[7] +set_location_assignment PIN_J17 -to LEDR[8] +set_location_assignment PIN_G17 -to LEDR[9] +set_location_assignment PIN_J15 -to LEDR[10] +set_location_assignment PIN_H16 -to LEDR[11] +set_location_assignment PIN_J16 -to LEDR[12] +set_location_assignment PIN_H17 -to LEDR[13] +set_location_assignment PIN_F15 -to LEDR[14] +set_location_assignment PIN_G15 -to LEDR[15] +set_location_assignment PIN_G16 -to LEDR[16] +set_location_assignment PIN_H15 -to LEDR[17] +set_location_assignment PIN_M23 -to KEY[0] +set_location_assignment PIN_M21 -to KEY[1] +set_location_assignment PIN_N21 -to KEY[2] +set_location_assignment PIN_R24 -to KEY[3] +set_location_assignment PIN_AB28 -to SW[0] +set_location_assignment PIN_AC28 -to SW[1] +set_location_assignment PIN_AC27 -to SW[2] +set_location_assignment PIN_AD27 -to SW[3] +set_location_assignment PIN_AB27 -to SW[4] +set_location_assignment PIN_AC26 -to SW[5] +set_location_assignment PIN_AD26 -to SW[6] +set_location_assignment PIN_AB26 -to SW[7] +set_location_assignment PIN_AC25 -to SW[8] +set_location_assignment PIN_AB25 -to SW[9] +set_location_assignment PIN_AC24 -to SW[10] +set_location_assignment PIN_AB24 -to SW[11] +set_location_assignment PIN_AB23 -to SW[12] +set_location_assignment PIN_AA24 -to SW[13] +set_location_assignment PIN_AA23 -to SW[14] +set_location_assignment PIN_AA22 -to SW[15] +set_location_assignment PIN_Y24 -to SW[16] +set_location_assignment PIN_Y23 -to SW[17] +set_location_assignment PIN_G18 -to HEX0[0] +set_location_assignment PIN_F22 -to HEX0[1] +set_location_assignment PIN_E17 -to HEX0[2] +set_location_assignment PIN_L26 -to HEX0[3] +set_location_assignment PIN_L25 -to HEX0[4] +set_location_assignment PIN_J22 -to HEX0[5] +set_location_assignment PIN_H22 -to HEX0[6] +set_location_assignment PIN_M24 -to HEX1[0] +set_location_assignment PIN_Y22 -to HEX1[1] +set_location_assignment PIN_W21 -to HEX1[2] +set_location_assignment PIN_W22 -to HEX1[3] +set_location_assignment PIN_W25 -to HEX1[4] +set_location_assignment PIN_U23 -to HEX1[5] +set_location_assignment PIN_U24 -to HEX1[6] +set_location_assignment PIN_AA25 -to HEX2[0] +set_location_assignment PIN_AA26 -to HEX2[1] +set_location_assignment PIN_Y25 -to HEX2[2] +set_location_assignment PIN_W26 -to HEX2[3] +set_location_assignment PIN_Y26 -to HEX2[4] +set_location_assignment PIN_W27 -to HEX2[5] +set_location_assignment PIN_W28 -to HEX2[6] +set_location_assignment PIN_V21 -to HEX3[0] +set_location_assignment PIN_U21 -to HEX3[1] +set_location_assignment PIN_AB20 -to HEX3[2] +set_location_assignment PIN_AA21 -to HEX3[3] +set_location_assignment PIN_AD24 -to HEX3[4] +set_location_assignment PIN_AF23 -to HEX3[5] +set_location_assignment PIN_Y19 -to HEX3[6] +set_location_assignment PIN_AB19 -to HEX4[0] +set_location_assignment PIN_AA19 -to HEX4[1] +set_location_assignment PIN_AG21 -to HEX4[2] +set_location_assignment PIN_AH21 -to HEX4[3] +set_location_assignment PIN_AE19 -to HEX4[4] +set_location_assignment PIN_AF19 -to HEX4[5] +set_location_assignment PIN_AE18 -to HEX4[6] +set_location_assignment PIN_AD18 -to HEX5[0] +set_location_assignment PIN_AC18 -to HEX5[1] +set_location_assignment PIN_AB18 -to HEX5[2] +set_location_assignment PIN_AH19 -to HEX5[3] +set_location_assignment PIN_AG19 -to HEX5[4] +set_location_assignment PIN_AF18 -to HEX5[5] +set_location_assignment PIN_AH18 -to HEX5[6] +set_location_assignment PIN_AA17 -to HEX6[0] +set_location_assignment PIN_AB16 -to HEX6[1] +set_location_assignment PIN_AA16 -to HEX6[2] +set_location_assignment PIN_AB17 -to HEX6[3] +set_location_assignment PIN_AB15 -to HEX6[4] +set_location_assignment PIN_AA15 -to HEX6[5] +set_location_assignment PIN_AC17 -to HEX6[6] +set_location_assignment PIN_AD17 -to HEX7[0] +set_location_assignment PIN_AE17 -to HEX7[1] +set_location_assignment PIN_AG17 -to HEX7[2] +set_location_assignment PIN_AH17 -to HEX7[3] +set_location_assignment PIN_AF17 -to HEX7[4] +set_location_assignment PIN_AG18 -to HEX7[5] +set_location_assignment PIN_AA14 -to HEX7[6] +set_location_assignment PIN_L6 -to LCD_BLON +set_location_assignment PIN_M5 -to LCD_DATA[7] +set_location_assignment PIN_M3 -to LCD_DATA[6] +set_location_assignment PIN_K2 -to LCD_DATA[5] +set_location_assignment PIN_K1 -to LCD_DATA[4] +set_location_assignment PIN_K7 -to LCD_DATA[3] +set_location_assignment PIN_L2 -to LCD_DATA[2] +set_location_assignment PIN_L1 -to LCD_DATA[1] +set_location_assignment PIN_L3 -to LCD_DATA[0] +set_location_assignment PIN_L4 -to LCD_EN +set_location_assignment PIN_M1 -to LCD_RW +set_location_assignment PIN_M2 -to LCD_RS +set_location_assignment PIN_L5 -to LCD_ON +set_location_assignment PIN_G9 -to UART_TXD +set_location_assignment PIN_G12 -to UART_RXD +set_location_assignment PIN_G14 -to UART_CTS +set_location_assignment PIN_J13 -to UART_RTS +set_location_assignment PIN_G6 -to PS2_KBCLK +set_location_assignment PIN_H5 -to PS2_KBDAT +set_location_assignment PIN_G5 -to PS2_MSCLK +set_location_assignment PIN_F5 -to PS2_MSDAT +set_location_assignment PIN_AE14 -to SD_DAT[0] +set_location_assignment PIN_AF13 -to SD_DAT[1] +set_location_assignment PIN_AB14 -to SD_DAT[2] +set_location_assignment PIN_AC14 -to SD_DAT[3] +set_location_assignment PIN_AE13 -to SD_CLK +set_location_assignment PIN_AD14 -to SD_CMD +set_location_assignment PIN_AF14 -to SD_WP_N +set_location_assignment PIN_D12 -to VGA_B[7] +set_location_assignment PIN_D11 -to VGA_B[6] +set_location_assignment PIN_C12 -to VGA_B[5] +set_location_assignment PIN_A11 -to VGA_B[4] +set_location_assignment PIN_B11 -to VGA_B[3] +set_location_assignment PIN_C11 -to VGA_B[2] +set_location_assignment PIN_A10 -to VGA_B[1] +set_location_assignment PIN_B10 -to VGA_B[0] +set_location_assignment PIN_C9 -to VGA_G[7] +set_location_assignment PIN_F10 -to VGA_G[6] +set_location_assignment PIN_B8 -to VGA_G[5] +set_location_assignment PIN_C8 -to VGA_G[4] +set_location_assignment PIN_H12 -to VGA_G[3] +set_location_assignment PIN_F8 -to VGA_G[2] +set_location_assignment PIN_G11 -to VGA_G[1] +set_location_assignment PIN_G8 -to VGA_G[0] +set_location_assignment PIN_H10 -to VGA_R[7] +set_location_assignment PIN_H8 -to VGA_R[6] +set_location_assignment PIN_J12 -to VGA_R[5] +set_location_assignment PIN_G10 -to VGA_R[4] +set_location_assignment PIN_F12 -to VGA_R[3] +set_location_assignment PIN_D10 -to VGA_R[2] +set_location_assignment PIN_E11 -to VGA_R[1] +set_location_assignment PIN_E12 -to VGA_R[0] +set_location_assignment PIN_A12 -to VGA_CLK +set_location_assignment PIN_F11 -to VGA_BLANK_N +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_location_assignment PIN_G13 -to VGA_HS +set_location_assignment PIN_C13 -to VGA_VS +set_location_assignment PIN_D1 -to AUD_DACDAT +set_location_assignment PIN_E3 -to AUD_DACLRCK +set_location_assignment PIN_D2 -to AUD_ADCDAT +set_location_assignment PIN_C2 -to AUD_ADCLRCK +set_location_assignment PIN_E1 -to AUD_XCK +set_location_assignment PIN_F2 -to AUD_BCLK +set_location_assignment PIN_D14 -to EEP_I2C_SCLK +set_location_assignment PIN_E14 -to EEP_I2C_SDAT +set_location_assignment PIN_B7 -to I2C_SCLK +set_location_assignment PIN_A8 -to I2C_SDAT +set_location_assignment PIN_A17 -to ENET0_GTX_CLK +set_location_assignment PIN_A21 -to ENET0_INT_N +set_location_assignment PIN_C20 -to ENET0_MDC +set_location_assignment PIN_B21 -to ENET0_MDIO +set_location_assignment PIN_C19 -to ENET0_RESET_N +set_location_assignment PIN_A15 -to ENET0_RX_CLK +set_location_assignment PIN_E15 -to ENET0_RX_COL +set_location_assignment PIN_D15 -to ENET0_RX_CRS +set_location_assignment PIN_C16 -to ENET0_RX_DATA[0] +set_location_assignment PIN_D16 -to ENET0_RX_DATA[1] +set_location_assignment PIN_D17 -to ENET0_RX_DATA[2] +set_location_assignment PIN_C15 -to ENET0_RX_DATA[3] +set_location_assignment PIN_C17 -to ENET0_RX_DV +set_location_assignment PIN_D18 -to ENET0_RX_ER +set_location_assignment PIN_B17 -to ENET0_TX_CLK +set_location_assignment PIN_C18 -to ENET0_TX_DATA[0] +set_location_assignment PIN_D19 -to ENET0_TX_DATA[1] +set_location_assignment PIN_A19 -to ENET0_TX_DATA[2] +set_location_assignment PIN_B19 -to ENET0_TX_DATA[3] +set_location_assignment PIN_A18 -to ENET0_TX_EN +set_location_assignment PIN_B18 -to ENET0_TX_ER +set_location_assignment PIN_C23 -to ENET1_GTX_CLK +set_location_assignment PIN_D24 -to ENET1_INT_N +set_location_assignment PIN_D23 -to ENET1_MDC +set_location_assignment PIN_D25 -to ENET1_MDIO +set_location_assignment PIN_D22 -to ENET1_RESET_N +set_location_assignment PIN_B15 -to ENET1_RX_CLK +set_location_assignment PIN_B22 -to ENET1_RX_COL +set_location_assignment PIN_D20 -to ENET1_RX_CRS +set_location_assignment PIN_B23 -to ENET1_RX_DATA[0] +set_location_assignment PIN_C21 -to ENET1_RX_DATA[1] +set_location_assignment PIN_A23 -to ENET1_RX_DATA[2] +set_location_assignment PIN_D21 -to ENET1_RX_DATA[3] +set_location_assignment PIN_A22 -to ENET1_RX_DV +set_location_assignment PIN_C24 -to ENET1_RX_ER +set_location_assignment PIN_C22 -to ENET1_TX_CLK +set_location_assignment PIN_C25 -to ENET1_TX_DATA[0] +set_location_assignment PIN_A26 -to ENET1_TX_DATA[1] +set_location_assignment PIN_B26 -to ENET1_TX_DATA[2] +set_location_assignment PIN_C26 -to ENET1_TX_DATA[3] +set_location_assignment PIN_B25 -to ENET1_TX_EN +set_location_assignment PIN_A25 -to ENET1_TX_ER +set_location_assignment PIN_C14 -to ENET0_LINK100 +set_location_assignment PIN_D13 -to ENET1_LINK100 +set_location_assignment PIN_A14 -to ENETCLK_25 +set_location_assignment PIN_F7 -to TD_DATA[7] +set_location_assignment PIN_E7 -to TD_DATA[6] +set_location_assignment PIN_D6 -to TD_DATA[5] +set_location_assignment PIN_D7 -to TD_DATA[4] +set_location_assignment PIN_C7 -to TD_DATA[3] +set_location_assignment PIN_D8 -to TD_DATA[2] +set_location_assignment PIN_A7 -to TD_DATA[1] +set_location_assignment PIN_E8 -to TD_DATA[0] +set_location_assignment PIN_B14 -to TD_CLK27 +set_location_assignment PIN_G7 -to TD_RESET_N +set_location_assignment PIN_E4 -to TD_VS +set_location_assignment PIN_E5 -to TD_HS +set_location_assignment PIN_D4 -to OTG_DACK_N[1] +set_location_assignment PIN_C4 -to OTG_DACK_N[0] +set_location_assignment PIN_A3 -to OTG_CS_N +set_location_assignment PIN_B3 -to OTG_OE_N +set_location_assignment PIN_B4 -to OTG_DREQ[1] +set_location_assignment PIN_J1 -to OTG_DREQ[0] +set_location_assignment PIN_A4 -to OTG_WE_N +set_location_assignment PIN_H7 -to OTG_ADDR[0] +set_location_assignment PIN_C3 -to OTG_ADDR[1] +set_location_assignment PIN_C6 -to OTG_FSPEED +set_location_assignment PIN_B6 -to OTG_LSPEED +set_location_assignment PIN_D5 -to OTG_INT[1] +set_location_assignment PIN_A6 -to OTG_INT[0] +set_location_assignment PIN_C5 -to OTG_RST_N +set_location_assignment PIN_J6 -to OTG_DATA[0] +set_location_assignment PIN_K4 -to OTG_DATA[1] +set_location_assignment PIN_J5 -to OTG_DATA[2] +set_location_assignment PIN_K3 -to OTG_DATA[3] +set_location_assignment PIN_J4 -to OTG_DATA[4] +set_location_assignment PIN_J3 -to OTG_DATA[5] +set_location_assignment PIN_J7 -to OTG_DATA[6] +set_location_assignment PIN_H6 -to OTG_DATA[7] +set_location_assignment PIN_H3 -to OTG_DATA[8] +set_location_assignment PIN_H4 -to OTG_DATA[9] +set_location_assignment PIN_G1 -to OTG_DATA[10] +set_location_assignment PIN_G2 -to OTG_DATA[11] +set_location_assignment PIN_G3 -to OTG_DATA[12] +set_location_assignment PIN_F1 -to OTG_DATA[13] +set_location_assignment PIN_F3 -to OTG_DATA[14] +set_location_assignment PIN_G4 -to OTG_DATA[15] +set_location_assignment PIN_Y15 -to IRDA_RXD +set_location_assignment PIN_AE5 -to DRAM_CLK +set_location_assignment PIN_U1 -to DRAM_DQ[31] +set_location_assignment PIN_U4 -to DRAM_DQ[30] +set_location_assignment PIN_T3 -to DRAM_DQ[29] +set_location_assignment PIN_R3 -to DRAM_DQ[28] +set_location_assignment PIN_R2 -to DRAM_DQ[27] +set_location_assignment PIN_R1 -to DRAM_DQ[26] +set_location_assignment PIN_R7 -to DRAM_DQ[25] +set_location_assignment PIN_U5 -to DRAM_DQ[24] +set_location_assignment PIN_M8 -to DRAM_DQ[16] +set_location_assignment PIN_L8 -to DRAM_DQ[17] +set_location_assignment PIN_P2 -to DRAM_DQ[18] +set_location_assignment PIN_N3 -to DRAM_DQ[19] +set_location_assignment PIN_N4 -to DRAM_DQ[20] +set_location_assignment PIN_M4 -to DRAM_DQ[21] +set_location_assignment PIN_M7 -to DRAM_DQ[22] +set_location_assignment PIN_L7 -to DRAM_DQ[23] +set_location_assignment PIN_Y3 -to DRAM_DQ[8] +set_location_assignment PIN_Y4 -to DRAM_DQ[9] +set_location_assignment PIN_AB1 -to DRAM_DQ[10] +set_location_assignment PIN_AA3 -to DRAM_DQ[11] +set_location_assignment PIN_AB2 -to DRAM_DQ[12] +set_location_assignment PIN_AC1 -to DRAM_DQ[13] +set_location_assignment PIN_AB3 -to DRAM_DQ[14] +set_location_assignment PIN_AC2 -to DRAM_DQ[15] +set_location_assignment PIN_W3 -to DRAM_DQ[0] +set_location_assignment PIN_W2 -to DRAM_DQ[1] +set_location_assignment PIN_V4 -to DRAM_DQ[2] +set_location_assignment PIN_W1 -to DRAM_DQ[3] +set_location_assignment PIN_V3 -to DRAM_DQ[4] +set_location_assignment PIN_V2 -to DRAM_DQ[5] +set_location_assignment PIN_V1 -to DRAM_DQ[6] +set_location_assignment PIN_U3 -to DRAM_DQ[7] +set_location_assignment PIN_W4 -to DRAM_DQM[1] +set_location_assignment PIN_K8 -to DRAM_DQM[2] +set_location_assignment PIN_U2 -to DRAM_DQM[0] +set_location_assignment PIN_N8 -to DRAM_DQM[3] +set_location_assignment PIN_U6 -to DRAM_RAS_N +set_location_assignment PIN_V7 -to DRAM_CAS_N +set_location_assignment PIN_AA6 -to DRAM_CKE +set_location_assignment PIN_V6 -to DRAM_WE_N +set_location_assignment PIN_T4 -to DRAM_CS_N +set_location_assignment PIN_U7 -to DRAM_BA[0] +set_location_assignment PIN_R4 -to DRAM_BA[1] +set_location_assignment PIN_Y7 -to DRAM_ADDR[12] +set_location_assignment PIN_AA5 -to DRAM_ADDR[11] +set_location_assignment PIN_R5 -to DRAM_ADDR[10] +set_location_assignment PIN_Y6 -to DRAM_ADDR[9] +set_location_assignment PIN_Y5 -to DRAM_ADDR[8] +set_location_assignment PIN_AA7 -to DRAM_ADDR[7] +set_location_assignment PIN_W7 -to DRAM_ADDR[6] +set_location_assignment PIN_W8 -to DRAM_ADDR[5] +set_location_assignment PIN_V5 -to DRAM_ADDR[4] +set_location_assignment PIN_P1 -to DRAM_ADDR[3] +set_location_assignment PIN_U8 -to DRAM_ADDR[2] +set_location_assignment PIN_V8 -to DRAM_ADDR[1] +set_location_assignment PIN_R6 -to DRAM_ADDR[0] +set_location_assignment PIN_AG3 -to SRAM_DQ[15] +set_location_assignment PIN_AF3 -to SRAM_DQ[14] +set_location_assignment PIN_AE4 -to SRAM_DQ[13] +set_location_assignment PIN_AE3 -to SRAM_DQ[12] +set_location_assignment PIN_AE1 -to SRAM_DQ[11] +set_location_assignment PIN_AE2 -to SRAM_DQ[10] +set_location_assignment PIN_AD2 -to SRAM_DQ[9] +set_location_assignment PIN_AD1 -to SRAM_DQ[8] +set_location_assignment PIN_AF7 -to SRAM_DQ[7] +set_location_assignment PIN_AH6 -to SRAM_DQ[6] +set_location_assignment PIN_AG6 -to SRAM_DQ[5] +set_location_assignment PIN_AF6 -to SRAM_DQ[4] +set_location_assignment PIN_AH4 -to SRAM_DQ[3] +set_location_assignment PIN_AG4 -to SRAM_DQ[2] +set_location_assignment PIN_AF4 -to SRAM_DQ[1] +set_location_assignment PIN_AH3 -to SRAM_DQ[0] +set_location_assignment PIN_AC4 -to SRAM_UB_N +set_location_assignment PIN_AD4 -to SRAM_LB_N +set_location_assignment PIN_AF8 -to SRAM_CE_N +set_location_assignment PIN_AD5 -to SRAM_OE_N +set_location_assignment PIN_AE8 -to SRAM_WE_N +set_location_assignment PIN_AE6 -to SRAM_ADDR[5] +set_location_assignment PIN_AB5 -to SRAM_ADDR[6] +set_location_assignment PIN_AC5 -to SRAM_ADDR[7] +set_location_assignment PIN_AF5 -to SRAM_ADDR[8] +set_location_assignment PIN_T7 -to SRAM_ADDR[9] +set_location_assignment PIN_AF2 -to SRAM_ADDR[10] +set_location_assignment PIN_AD3 -to SRAM_ADDR[11] +set_location_assignment PIN_AB4 -to SRAM_ADDR[12] +set_location_assignment PIN_AC3 -to SRAM_ADDR[13] +set_location_assignment PIN_AA4 -to SRAM_ADDR[14] +set_location_assignment PIN_AB7 -to SRAM_ADDR[0] +set_location_assignment PIN_AD7 -to SRAM_ADDR[1] +set_location_assignment PIN_AE7 -to SRAM_ADDR[2] +set_location_assignment PIN_AC7 -to SRAM_ADDR[3] +set_location_assignment PIN_AB6 -to SRAM_ADDR[4] +set_location_assignment PIN_T8 -to SRAM_ADDR[19] +set_location_assignment PIN_AB8 -to SRAM_ADDR[18] +set_location_assignment PIN_AB9 -to SRAM_ADDR[17] +set_location_assignment PIN_AC11 -to SRAM_ADDR[16] +set_location_assignment PIN_AB11 -to SRAM_ADDR[15] +set_location_assignment PIN_AF12 -to FL_DQ[7] +set_location_assignment PIN_AH11 -to FL_DQ[6] +set_location_assignment PIN_AG11 -to FL_DQ[5] +set_location_assignment PIN_AF11 -to FL_DQ[4] +set_location_assignment PIN_AH10 -to FL_DQ[3] +set_location_assignment PIN_AG10 -to FL_DQ[2] +set_location_assignment PIN_AF10 -to FL_DQ[1] +set_location_assignment PIN_AH8 -to FL_DQ[0] +set_location_assignment PIN_AG12 -to FL_ADDR[0] +set_location_assignment PIN_AD11 -to FL_ADDR[22] +set_location_assignment PIN_AD10 -to FL_ADDR[21] +set_location_assignment PIN_AE10 -to FL_ADDR[20] +set_location_assignment PIN_AD12 -to FL_ADDR[19] +set_location_assignment PIN_AC12 -to FL_ADDR[18] +set_location_assignment PIN_AH12 -to FL_ADDR[17] +set_location_assignment PIN_AA8 -to FL_ADDR[16] +set_location_assignment PIN_Y10 -to FL_ADDR[15] +set_location_assignment PIN_AC8 -to FL_ADDR[14] +set_location_assignment PIN_AD8 -to FL_ADDR[13] +set_location_assignment PIN_AA10 -to FL_ADDR[12] +set_location_assignment PIN_AF9 -to FL_ADDR[11] +set_location_assignment PIN_AE9 -to FL_ADDR[10] +set_location_assignment PIN_AB10 -to FL_ADDR[9] +set_location_assignment PIN_AB12 -to FL_ADDR[8] +set_location_assignment PIN_AB13 -to FL_ADDR[7] +set_location_assignment PIN_AA12 -to FL_ADDR[6] +set_location_assignment PIN_AA13 -to FL_ADDR[5] +set_location_assignment PIN_Y12 -to FL_ADDR[4] +set_location_assignment PIN_Y14 -to FL_ADDR[3] +set_location_assignment PIN_Y13 -to FL_ADDR[2] +set_location_assignment PIN_AH7 -to FL_ADDR[1] +set_location_assignment PIN_AG7 -to FL_CE_N +set_location_assignment PIN_AG8 -to FL_OE_N +set_location_assignment PIN_AC10 -to FL_WE_N +set_location_assignment PIN_AE11 -to FL_RESET_N +set_location_assignment PIN_AE12 -to FL_WP_N +set_location_assignment PIN_Y1 -to FL_RY +set_location_assignment PIN_AB22 -to GPIO[0] +set_location_assignment PIN_AC15 -to GPIO[1] +set_location_assignment PIN_AB21 -to GPIO[2] +set_location_assignment PIN_Y17 -to GPIO[3] +set_location_assignment PIN_AC21 -to GPIO[4] +set_location_assignment PIN_Y16 -to GPIO[5] +set_location_assignment PIN_AD21 -to GPIO[6] +set_location_assignment PIN_AE16 -to GPIO[7] +set_location_assignment PIN_AD15 -to GPIO[8] +set_location_assignment PIN_AE15 -to GPIO[9] +set_location_assignment PIN_AC19 -to GPIO[10] +set_location_assignment PIN_AF16 -to GPIO[11] +set_location_assignment PIN_AD19 -to GPIO[12] +set_location_assignment PIN_AF15 -to GPIO[13] +set_location_assignment PIN_AF24 -to GPIO[14] +set_location_assignment PIN_AE21 -to GPIO[15] +set_location_assignment PIN_AF25 -to GPIO[16] +set_location_assignment PIN_AC22 -to GPIO[17] +set_location_assignment PIN_AE22 -to GPIO[18] +set_location_assignment PIN_AF21 -to GPIO[19] +set_location_assignment PIN_AF22 -to GPIO[20] +set_location_assignment PIN_AD22 -to GPIO[21] +set_location_assignment PIN_AG25 -to GPIO[22] +set_location_assignment PIN_AD25 -to GPIO[23] +set_location_assignment PIN_AH25 -to GPIO[24] +set_location_assignment PIN_AE25 -to GPIO[25] +set_location_assignment PIN_AG22 -to GPIO[26] +set_location_assignment PIN_AE24 -to GPIO[27] +set_location_assignment PIN_AH22 -to GPIO[28] +set_location_assignment PIN_AF26 -to GPIO[29] +set_location_assignment PIN_AE20 -to GPIO[30] +set_location_assignment PIN_AG23 -to GPIO[31] +set_location_assignment PIN_AF20 -to GPIO[32] +set_location_assignment PIN_AH26 -to GPIO[33] +set_location_assignment PIN_AH23 -to GPIO[34] +set_location_assignment PIN_AG26 -to GPIO[35] +set_location_assignment PIN_J27 -to HSMC_CLKIN_P1 +set_location_assignment PIN_J28 -to HSMC_CLKIN_N1 +set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2 +set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2 +set_location_assignment PIN_D27 -to HSMC_TX_D_P[0] +set_location_assignment PIN_D28 -to HSMC_TX_D_N[0] +set_location_assignment PIN_F24 -to HSMC_RX_D_P[0] +set_location_assignment PIN_F25 -to HSMC_RX_D_N[0] +set_location_assignment PIN_E27 -to HSMC_TX_D_P[1] +set_location_assignment PIN_C27 -to HSMC_RX_D_N[1] +set_location_assignment PIN_E28 -to HSMC_TX_D_N[1] +set_location_assignment PIN_D26 -to HSMC_RX_D_P[1] +set_location_assignment PIN_F27 -to HSMC_TX_D_P[2] +set_location_assignment PIN_F28 -to HSMC_TX_D_N[2] +set_location_assignment PIN_F26 -to HSMC_RX_D_P[2] +set_location_assignment PIN_E26 -to HSMC_RX_D_N[2] +set_location_assignment PIN_G27 -to HSMC_TX_D_P[3] +set_location_assignment PIN_G28 -to HSMC_TX_D_N[3] +set_location_assignment PIN_G25 -to HSMC_RX_D_P[3] +set_location_assignment PIN_G26 -to HSMC_RX_D_N[3] +set_location_assignment PIN_K27 -to HSMC_TX_D_P[4] +set_location_assignment PIN_K28 -to HSMC_TX_D_N[4] +set_location_assignment PIN_H25 -to HSMC_RX_D_P[4] +set_location_assignment PIN_H26 -to HSMC_RX_D_N[4] +set_location_assignment PIN_M27 -to HSMC_TX_D_P[5] +set_location_assignment PIN_M28 -to HSMC_TX_D_N[5] +set_location_assignment PIN_K25 -to HSMC_RX_D_P[5] +set_location_assignment PIN_K26 -to HSMC_RX_D_N[5] +set_location_assignment PIN_K21 -to HSMC_TX_D_P[6] +set_location_assignment PIN_K22 -to HSMC_TX_D_N[6] +set_location_assignment PIN_L23 -to HSMC_RX_D_P[6] +set_location_assignment PIN_L24 -to HSMC_RX_D_N[6] +set_location_assignment PIN_H23 -to HSMC_TX_D_P[7] +set_location_assignment PIN_H24 -to HSMC_TX_D_N[7] +set_location_assignment PIN_M25 -to HSMC_RX_D_P[7] +set_location_assignment PIN_M26 -to HSMC_RX_D_N[7] +set_location_assignment PIN_J23 -to HSMC_TX_D_P[8] +set_location_assignment PIN_J24 -to HSMC_TX_D_N[8] +set_location_assignment PIN_R25 -to HSMC_RX_D_P[8] +set_location_assignment PIN_R26 -to HSMC_RX_D_N[8] +set_location_assignment PIN_P27 -to HSMC_TX_D_P[9] +set_location_assignment PIN_P28 -to HSMC_TX_D_N[9] +set_location_assignment PIN_T25 -to HSMC_RX_D_P[9] +set_location_assignment PIN_T26 -to HSMC_RX_D_N[9] +set_location_assignment PIN_J25 -to HSMC_TX_D_P[10] +set_location_assignment PIN_J26 -to HSMC_TX_D_N[10] +set_location_assignment PIN_U25 -to HSMC_RX_D_P[10] +set_location_assignment PIN_U26 -to HSMC_RX_D_N[10] +set_location_assignment PIN_L27 -to HSMC_TX_D_P[11] +set_location_assignment PIN_L28 -to HSMC_TX_D_N[11] +set_location_assignment PIN_L21 -to HSMC_RX_D_P[11] +set_location_assignment PIN_L22 -to HSMC_RX_D_N[11] +set_location_assignment PIN_V25 -to HSMC_TX_D_P[12] +set_location_assignment PIN_V26 -to HSMC_TX_D_N[12] +set_location_assignment PIN_N25 -to HSMC_RX_D_P[12] +set_location_assignment PIN_N26 -to HSMC_RX_D_N[12] +set_location_assignment PIN_R27 -to HSMC_TX_D_P[13] +set_location_assignment PIN_R28 -to HSMC_TX_D_N[13] +set_location_assignment PIN_P25 -to HSMC_RX_D_P[13] +set_location_assignment PIN_P26 -to HSMC_RX_D_N[13] +set_location_assignment PIN_U27 -to HSMC_TX_D_P[14] +set_location_assignment PIN_U28 -to HSMC_TX_D_N[14] +set_location_assignment PIN_P21 -to HSMC_RX_D_P[14] +set_location_assignment PIN_R21 -to HSMC_RX_D_N[14] +set_location_assignment PIN_V27 -to HSMC_TX_D_P[15] +set_location_assignment PIN_V28 -to HSMC_TX_D_N[15] +set_location_assignment PIN_R22 -to HSMC_RX_D_P[15] +set_location_assignment PIN_R23 -to HSMC_RX_D_N[15] +set_location_assignment PIN_U22 -to HSMC_TX_D_P[16] +set_location_assignment PIN_V22 -to HSMC_TX_D_N[16] +set_location_assignment PIN_T21 -to HSMC_RX_D_P[16] +set_location_assignment PIN_T22 -to HSMC_RX_D_N[16] +set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2 +set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2 +set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1 +set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1 +set_location_assignment PIN_AD28 -to HSMC_CLKOUT0 +set_location_assignment PIN_AE26 -to HSMC_D[0] +set_location_assignment PIN_AE28 -to HSMC_D[1] +set_location_assignment PIN_AE27 -to HSMC_D[2] +set_location_assignment PIN_AF27 -to HSMC_D[3] +set_location_assignment PIN_AH15 -to HSMC_CLKIN0 +set_location_assignment PIN_J10 -to EXT_IO[0] +set_location_assignment PIN_J14 -to EXT_IO[1] +set_location_assignment PIN_H13 -to EXT_IO[2] +set_location_assignment PIN_H14 -to EXT_IO[3] +set_location_assignment PIN_F14 -to EXT_IO[4] +set_location_assignment PIN_E10 -to EXT_IO[5] +set_location_assignment PIN_D9 -to EXT_IO[6] + + Index: Altera/DE2_115/jtag_intfc.sh =================================================================== --- Altera/DE2_115/jtag_intfc.sh (nonexistent) +++ Altera/DE2_115/jtag_intfc.sh (revision 48) @@ -0,0 +1,6 @@ +#!/bin/bash + +PRODUCT_ID="0x6001" +JTAG_INTFC="$PRONOC_WORK/toolchain/bin/jtag_libusb -a $PRODUCT_ID" + + Index: Altera/DE2_115/program_device.sh =================================================================== --- Altera/DE2_115/program_device.sh (nonexistent) +++ Altera/DE2_115/program_device.sh (revision 48) @@ -0,0 +1,26 @@ +#!/bin/bash + +#usage: +# sh program_device.sh programming_file.sof + +#programming file +#given as an argument: $1 + +#Programming mode +PROG_MODE=jtag + +#cable name. Connect the board to ur PC and then run jtagconfig in terminal to find the cable name +NAME="USB-Blaster" + + +#programming command +if [ -n "${QUARTUS_BIN+set}" ]; then + $QUARTUS_BIN/quartus_pgm -m $PROG_MODE -c "$NAME" -o "p;${1}" +else + quartus_pgm -m $PROG_MODE -c "$NAME" -o "p;${1}" +fi + + + + + Index: Altera/DE5/DE5.qsf =================================================================== --- Altera/DE5/DE5.qsf (nonexistent) +++ Altera/DE5/DE5.qsf (revision 48) @@ -0,0 +1,302 @@ +#============================================================ +# Build by Terasic System Builder +#============================================================ + +set_global_assignment -name FAMILY "Stratix V" +set_global_assignment -name DEVICE 5SGXEA7N2F45C2 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.0" +set_global_assignment -name LAST_QUARTUS_VERSION "12.0" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:38:23 JULY 08,2019" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1932 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 2_H2 +set_global_assignment -name SDC_FILE Top.SDC + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_AW35 -to OSC_50_B3B +set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_B3B +set_location_assignment PIN_BC28 -to OSC_50_B3D +set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_50_B3D +set_location_assignment PIN_AP10 -to OSC_50_B4A +set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_50_B4A +set_location_assignment PIN_AY18 -to OSC_50_B4D +set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_50_B4D +set_location_assignment PIN_M8 -to OSC_50_B7A +set_instance_assignment -name IO_STANDARD "1.5 V" -to OSC_50_B7A +set_location_assignment PIN_J18 -to OSC_50_B7D +set_instance_assignment -name IO_STANDARD "1.5 V" -to OSC_50_B7D +set_location_assignment PIN_R36 -to OSC_50_B8A +set_instance_assignment -name IO_STANDARD "1.5 V" -to OSC_50_B8A +set_location_assignment PIN_R25 -to OSC_50_B8D +set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_50_B8D + +#============================================================ +# LED x 10 +#============================================================ +set_location_assignment PIN_AW37 -to LED[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[0] +set_location_assignment PIN_AV37 -to LED[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[1] +set_location_assignment PIN_BB36 -to LED[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[2] +set_location_assignment PIN_BB39 -to LED[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[3] +set_location_assignment PIN_AH15 -to LED_BRACKET[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_BRACKET[0] +set_location_assignment PIN_AH13 -to LED_BRACKET[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_BRACKET[1] +set_location_assignment PIN_AJ13 -to LED_BRACKET[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_BRACKET[2] +set_location_assignment PIN_AJ14 -to LED_BRACKET[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_BRACKET[3] +set_location_assignment PIN_AG15 -to LED_RJ45_L +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_RJ45_L +set_location_assignment PIN_AG16 -to LED_RJ45_R +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_RJ45_R + +#============================================================ +# BUTTON x 4 and CPU_RESET_n +#============================================================ +set_location_assignment PIN_AK15 -to BUTTON[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to BUTTON[0] +set_location_assignment PIN_AK14 -to BUTTON[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to BUTTON[1] +set_location_assignment PIN_AL14 -to BUTTON[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to BUTTON[2] +set_location_assignment PIN_AL15 -to BUTTON[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to BUTTON[3] +set_location_assignment PIN_BC37 -to CPU_RESET_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to CPU_RESET_n + +#============================================================ +# SWITCH x 4 +#============================================================ +set_location_assignment PIN_B25 -to SW[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to SW[0] +set_location_assignment PIN_A25 -to SW[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to SW[1] +set_location_assignment PIN_B23 -to SW[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to SW[2] +set_location_assignment PIN_A23 -to SW[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to SW[3] + +#============================================================ +# 7-Segement +#============================================================ +set_location_assignment PIN_G8 -to HEX0_D[0] +set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX0_D[0] +set_location_assignment PIN_H8 -to HEX0_D[1] +set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX0_D[1] +set_location_assignment PIN_J9 -to HEX0_D[2] +set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX0_D[2] +set_location_assignment PIN_K10 -to HEX0_D[3] +set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX0_D[3] +set_location_assignment PIN_K8 -to HEX0_D[4] +set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX0_D[4] +set_location_assignment PIN_K9 -to HEX0_D[5] +set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX0_D[5] +set_location_assignment PIN_N8 -to HEX0_D[6] +set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX0_D[6] +set_location_assignment PIN_P8 -to HEX0_DP +set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX0_DP +set_location_assignment PIN_H18 -to HEX1_D[0] +set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX1_D[0] +set_location_assignment PIN_G16 -to HEX1_D[1] +set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX1_D[1] +set_location_assignment PIN_F16 -to HEX1_D[2] +set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX1_D[2] +set_location_assignment PIN_A7 -to HEX1_D[3] +set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX1_D[3] +set_location_assignment PIN_B7 -to HEX1_D[4] +set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX1_D[4] +set_location_assignment PIN_C9 -to HEX1_D[5] +set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX1_D[5] +set_location_assignment PIN_D10 -to HEX1_D[6] +set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX1_D[6] +set_location_assignment PIN_E9 -to HEX1_DP +set_instance_assignment -name IO_STANDARD "1.5 V" -to HEX1_DP + +#============================================================ +# Temperature +#============================================================ +set_location_assignment PIN_D21 -to TEMP_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to TEMP_CLK +set_location_assignment PIN_D20 -to TEMP_DATA +set_instance_assignment -name IO_STANDARD "2.5 V" -to TEMP_DATA +set_location_assignment PIN_C21 -to TEMP_INT_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to TEMP_INT_n +set_location_assignment PIN_C22 -to TEMP_OVERT_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to TEMP_OVERT_n + +#============================================================ +# Fan +#============================================================ +set_location_assignment PIN_AR32 -to FAN_CTRL +set_instance_assignment -name IO_STANDARD "2.5 V" -to FAN_CTRL + +#============================================================ +# RS232 +#============================================================ +set_location_assignment PIN_AG14 -to RS422_DE +set_instance_assignment -name IO_STANDARD "2.5 V" -to RS422_DE +set_location_assignment PIN_AE18 -to RS422_DIN +set_instance_assignment -name IO_STANDARD "2.5 V" -to RS422_DIN +set_location_assignment PIN_AE17 -to RS422_DOUT +set_instance_assignment -name IO_STANDARD "2.5 V" -to RS422_DOUT +set_location_assignment PIN_AF17 -to RS422_RE_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to RS422_RE_n +set_location_assignment PIN_AF16 -to RS422_TE +set_instance_assignment -name IO_STANDARD "2.5 V" -to RS422_TE + +#============================================================ +# Flash/MAX Address/Data Share Bus +#============================================================ +set_location_assignment PIN_AG26 -to FSM_D[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[0] +set_location_assignment PIN_AD33 -to FSM_D[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[1] +set_location_assignment PIN_AE34 -to FSM_D[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[2] +set_location_assignment PIN_AF31 -to FSM_D[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[3] +set_location_assignment PIN_AG28 -to FSM_D[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[4] +set_location_assignment PIN_AG30 -to FSM_D[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[5] +set_location_assignment PIN_AF29 -to FSM_D[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[6] +set_location_assignment PIN_AE29 -to FSM_D[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[7] +set_location_assignment PIN_AG25 -to FSM_D[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[8] +set_location_assignment PIN_AF34 -to FSM_D[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[9] +set_location_assignment PIN_AE33 -to FSM_D[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[10] +set_location_assignment PIN_AE31 -to FSM_D[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[11] +set_location_assignment PIN_AF28 -to FSM_D[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[12] +set_location_assignment PIN_AE30 -to FSM_D[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[13] +set_location_assignment PIN_AG29 -to FSM_D[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[14] +set_location_assignment PIN_AG27 -to FSM_D[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[15] +set_location_assignment PIN_AP28 -to FSM_D[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[16] +set_location_assignment PIN_AN28 -to FSM_D[17] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[17] +set_location_assignment PIN_AU31 -to FSM_D[18] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[18] +set_location_assignment PIN_AW32 -to FSM_D[19] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[19] +set_location_assignment PIN_BD32 -to FSM_D[20] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[20] +set_location_assignment PIN_AY31 -to FSM_D[21] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[21] +set_location_assignment PIN_BA30 -to FSM_D[22] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[22] +set_location_assignment PIN_BB30 -to FSM_D[23] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[23] +set_location_assignment PIN_AM29 -to FSM_D[24] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[24] +set_location_assignment PIN_AR29 -to FSM_D[25] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[25] +set_location_assignment PIN_AV31 -to FSM_D[26] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[26] +set_location_assignment PIN_AV32 -to FSM_D[27] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[27] +set_location_assignment PIN_BC31 -to FSM_D[28] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[28] +set_location_assignment PIN_AW30 -to FSM_D[29] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[29] +set_location_assignment PIN_BC32 -to FSM_D[30] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[30] +set_location_assignment PIN_BD31 -to FSM_D[31] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_D[31] +set_location_assignment PIN_AU32 -to FSM_A[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[0] +set_location_assignment PIN_AH30 -to FSM_A[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[1] +set_location_assignment PIN_AJ30 -to FSM_A[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[2] +set_location_assignment PIN_AH31 -to FSM_A[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[3] +set_location_assignment PIN_AK30 -to FSM_A[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[4] +set_location_assignment PIN_AJ32 -to FSM_A[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[5] +set_location_assignment PIN_AG33 -to FSM_A[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[6] +set_location_assignment PIN_AL30 -to FSM_A[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[7] +set_location_assignment PIN_AK33 -to FSM_A[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[8] +set_location_assignment PIN_AJ33 -to FSM_A[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[9] +set_location_assignment PIN_AN30 -to FSM_A[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[10] +set_location_assignment PIN_AH33 -to FSM_A[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[11] +set_location_assignment PIN_AK32 -to FSM_A[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[12] +set_location_assignment PIN_AM32 -to FSM_A[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[13] +set_location_assignment PIN_AM31 -to FSM_A[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[14] +set_location_assignment PIN_AL31 -to FSM_A[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[15] +set_location_assignment PIN_AN33 -to FSM_A[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[16] +set_location_assignment PIN_AP33 -to FSM_A[17] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[17] +set_location_assignment PIN_AT32 -to FSM_A[18] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[18] +set_location_assignment PIN_AT29 -to FSM_A[19] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[19] +set_location_assignment PIN_AP31 -to FSM_A[20] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[20] +set_location_assignment PIN_AR30 -to FSM_A[21] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[21] +set_location_assignment PIN_AU30 -to FSM_A[22] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[22] +set_location_assignment PIN_AJ31 -to FSM_A[23] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[23] +set_location_assignment PIN_AP30 -to FSM_A[24] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[24] +set_location_assignment PIN_AN31 -to FSM_A[25] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[25] +set_location_assignment PIN_AT30 -to FSM_A[26] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FSM_A[26] + +#============================================================ +# Flash Control +#============================================================ +set_location_assignment PIN_AK29 -to FLASH_ADV_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_ADV_n +set_location_assignment PIN_AE27 -to FLASH_CE_n[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_CE_n[0] +set_location_assignment PIN_BA31 -to FLASH_CE_n[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_CE_n[1] +set_location_assignment PIN_AL29 -to FLASH_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_CLK +set_location_assignment PIN_AY30 -to FLASH_OE_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_OE_n +set_location_assignment PIN_BA29 -to FLASH_RDY_BSY_n[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_RDY_BSY_n[0] +set_location_assignment PIN_BB32 -to FLASH_RDY_BSY_n[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_RDY_BSY_n[1] +set_location_assignment PIN_AE28 -to FLASH_RESET_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_RESET_n +set_location_assignment PIN_AR31 -to FLASH_WE_n +set_instance_assignment -name IO_STANDARD "2.5 V" -to FLASH_WE_n + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + + +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files Index: Altera/DE5/DE5.v =================================================================== --- Altera/DE5/DE5.v (nonexistent) +++ Altera/DE5/DE5.v (revision 48) @@ -0,0 +1,148 @@ + +//======================================================= +// This code is generated by Terasic System Builder +//======================================================= + +module Top( + + //////////// CLOCK ////////// + OSC_50_B3B, + OSC_50_B3D, + OSC_50_B4A, + OSC_50_B4D, + OSC_50_B7A, + OSC_50_B7D, + OSC_50_B8A, + OSC_50_B8D, + + //////////// LED x 10 ////////// + LED, + LED_BRACKET, + LED_RJ45_L, + LED_RJ45_R, + + //////////// BUTTON x 4 and CPU_RESET_n ////////// + BUTTON, + CPU_RESET_n, + + //////////// SWITCH x 4 ////////// + SW, + + //////////// 7-Segement ////////// + HEX0_D, + HEX0_DP, + HEX1_D, + HEX1_DP, + + //////////// Temperature ////////// + TEMP_CLK, + TEMP_DATA, + TEMP_INT_n, + TEMP_OVERT_n, + + //////////// Fan ////////// + FAN_CTRL, + + //////////// RS232 ////////// + RS422_DE, + RS422_DIN, + RS422_DOUT, + RS422_RE_n, + RS422_TE, + + //////////// Flash/MAX Address/Data Share Bus ////////// + FSM_A, + FSM_D, + + //////////// Flash Control ////////// + FLASH_ADV_n, + FLASH_CE_n, + FLASH_CLK, + FLASH_OE_n, + FLASH_RDY_BSY_n, + FLASH_RESET_n, + FLASH_WE_n +); + +//======================================================= +// PARAMETER declarations +//======================================================= + + +//======================================================= +// PORT declarations +//======================================================= + +//////////// CLOCK ////////// +input OSC_50_B3B; +input OSC_50_B3D; +input OSC_50_B4A; +input OSC_50_B4D; +input OSC_50_B7A; +input OSC_50_B7D; +input OSC_50_B8A; +input OSC_50_B8D; + +//////////// LED x 10 ////////// +output [3:0] LED; +output [3:0] LED_BRACKET; +output LED_RJ45_L; +output LED_RJ45_R; + +//////////// BUTTON x 4 and CPU_RESET_n ////////// +input [3:0] BUTTON; +input CPU_RESET_n; + +//////////// SWITCH x 4 ////////// +input [3:0] SW; + +//////////// 7-Segement ////////// +output [6:0] HEX0_D; +output HEX0_DP; +output [6:0] HEX1_D; +output HEX1_DP; + +//////////// Temperature ////////// +output TEMP_CLK; +inout TEMP_DATA; +input TEMP_INT_n; +input TEMP_OVERT_n; + +//////////// Fan ////////// +inout FAN_CTRL; + +//////////// RS232 ////////// +output RS422_DE; +input RS422_DIN; +output RS422_DOUT; +output RS422_RE_n; +output RS422_TE; + +//////////// Flash/MAX Address/Data Share Bus ////////// +output [26:0] FSM_A; +inout [31:0] FSM_D; + +//////////// Flash Control ////////// +output FLASH_ADV_n; +output [1:0] FLASH_CE_n; +output FLASH_CLK; +output FLASH_OE_n; +input [1:0] FLASH_RDY_BSY_n; +output FLASH_RESET_n; +output FLASH_WE_n; + + +//======================================================= +// REG/WIRE declarations +//======================================================= + + + + +//======================================================= +// Structural coding +//======================================================= + + + +endmodule Index: Altera/DE5/jtag_intfc.sh =================================================================== --- Altera/DE5/jtag_intfc.sh (nonexistent) +++ Altera/DE5/jtag_intfc.sh (revision 48) @@ -0,0 +1,11 @@ +#!/bin/bash + +PRODUCT_ID="0x6010" +HARDWARE_NAME="DE5 Standard *" +DEVICE_NAME="@1*" + +JTAG_INTFC="$PRONOC_WORK/toolchain/bin/jtag_quartus_stp -a $HARDWARE_NAME -b $DEVICE_NAME" + + + + Index: Altera/DE5/program_device.sh =================================================================== --- Altera/DE5/program_device.sh (nonexistent) +++ Altera/DE5/program_device.sh (revision 48) @@ -0,0 +1,24 @@ +#!/bin/bash + +#usage: +# sh program_device.sh programming_file.sof + +#programming file +#given as an argument: $1 + +#Programming mode +PROG_MODE=jtag + +#cable name. Connect the board to ur PC and then run jtagconfig in terminal to find the cable name +NAME="DE5 Standard" + +#device name +#DEVICE=@2 + + +#programming command +if [ -n "${QUARTUS_BIN+set}" ]; then + $QUARTUS_BIN/quartus_pgm -m $PROG_MODE -c "$NAME" -o "p;${1}" +else + quartus_pgm -m $PROG_MODE -c "$NAME" -o "p;${1}" +fi Index: Xilinx/Arty_z7_20/Arty_z7_20.v =================================================================== --- Xilinx/Arty_z7_20/Arty_z7_20.v (nonexistent) +++ Xilinx/Arty_z7_20/Arty_z7_20.v (revision 48) @@ -0,0 +1,187 @@ +module Arty_z7 ( + + //Clock Signal + clk, + + //Switches + sw, + + //RGB LEDs + led4_b, + led4_g, + led4_r, + led5_b, + led5_g, + led5_r, + + //LEDs + led, + + //Buttons + btn, + + //Audio Out + aud_pwm, + aud_sd, + + //HDMI RX Signals + hdmi_rx_clk_n, + hdmi_rx_clk_p, + hdmi_rx_d_n, + hdmi_rx_d_p, + hdmi_rx_cec, + hdmi_rx_hpd, + hdmi_rx_scl, + hdmi_rx_sda, + + //HDMI TX Signals + hdmi_tx_cec, + hdmi_tx_clk_n, + hdmi_tx_clk_p, + hdmi_tx_d_n, + hdmi_tx_d_p, + hdmi_tx_hpdn, + hdmi_tx_scl, + hdmi_tx_sda, + + //ChipKit SPI + ck_miso, + ck_mosi, + ck_sck, + ck_ss, + + //ChipKit I2C + ck_scl, + ck_sda, + + //ChipKit Outer Digital Header + ck_io0 , + ck_io1 , + ck_io2 , + ck_io3 , + ck_io4 , + ck_io5 , + ck_io6 , + ck_io7 , + ck_io8 , + ck_io9 , + ck_io10, + ck_io11, + ck_io12, + ck_io13, + + + ck_io26, + ck_io27, + ck_io28, + ck_io29, + ck_io30, + ck_io31, + ck_io32, + ck_io33, + ck_io34, + ck_io35, + ck_io36, + ck_io37, + ck_io38, + ck_io39, + ck_io40, + ck_io41 + + + + + +); + + //Clock Signal + input clk; + + //Switches + input [1:0] sw; + + //RGB LEDs + output led4_b; + output led4_g; + output led4_r; + output led5_b; + output led5_g; + output led5_r; + + //LEDs + output [3: 0] led; + + //Buttons + input [3: 0] btn; + + //Audio Out + output aud_pwm; + output aud_sd; + + //HDMI RX Signals + input hdmi_rx_clk_n; + input hdmi_rx_clk_p; + input [2:0] hdmi_rx_d_n; + input [2:0] hdmi_rx_d_p; + inout hdmi_rx_cec; + output hdmi_rx_hpd; + input hdmi_rx_scl; + inout hdmi_rx_sda; + + //HDMI TX Signals + inout hdmi_tx_cec; + output hdmi_tx_clk_n; + output hdmi_tx_clk_p; + output [2:0] hdmi_tx_d_n; + output [2:0] hdmi_tx_d_p; + input hdmi_tx_hpdn; + inout hdmi_tx_scl; + inout hdmi_tx_sda; + + //ChipKit SPI + inout ck_miso; + inout ck_mosi; + inout ck_sck; + inout ck_ss; + + //ChipKit I2C + inout ck_scl; + inout ck_sda; + + //ChipKit Outer Digital Header + inout ck_io0 ; + inout ck_io1 ; + inout ck_io2 ; + inout ck_io3 ; + inout ck_io4 ; + inout ck_io5 ; + inout ck_io6 ; + inout ck_io7 ; + inout ck_io8 ; + inout ck_io9 ; + inout ck_io10; + inout ck_io11; + inout ck_io12; + inout ck_io13; + + + inout ck_io26; + inout ck_io27; + inout ck_io28; + inout ck_io29; + inout ck_io30; + inout ck_io31; + inout ck_io32; + inout ck_io33; + inout ck_io34; + inout ck_io35; + inout ck_io36; + inout ck_io37; + inout ck_io38; + inout ck_io39; + inout ck_io40; + inout ck_io41; + + + +endmodule Index: Xilinx/Arty_z7_20/Arty_z7_20.xdc =================================================================== --- Xilinx/Arty_z7_20/Arty_z7_20.xdc (nonexistent) +++ Xilinx/Arty_z7_20/Arty_z7_20.xdc (revision 48) @@ -0,0 +1,188 @@ +## This file is a general .xdc for the ARTY Z7-20 Rev.B +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock Signal +set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=SYSCLK +create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];#set + +## Switches +#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L7N_T1_AD2N_35 Sch=SW0 +#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L7P_T1_AD2P_35 Sch=SW1 + +## RGB LEDs +#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { led4_b }]; #IO_L22N_T3_AD7P_35 Sch=LED4_B +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { led4_g }]; #IO_L16P_T2_35 Sch=LED4_G +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led4_r }]; #IO_L21P_T3_DQS_AD14P_35 Sch=LED4_R +#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_0_35 Sch=LED5_B +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L22P_T3_AD7P_35 Sch=LED5_G +#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L23N_T3_35 Sch=LED5_R + +## LEDs +#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L6N_T0_VREF_34 Sch=LED0 +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L6P_T0_34 Sch=LED1 +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=LED2 +#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L23P_T3_35 Sch=LED3 + +## Buttons +#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L4P_T0_35 Sch=BTN0 +#set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4N_T0_35 Sch=BTN1 +#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=BTN2 +#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=BTN3 + +## Pmod Header JA +#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L17P_T2_34 Sch=JA1_P +#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L17N_T2_34 Sch=JA1_N +#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L7P_T1_34 Sch=JA2_P +#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L7N_T1_34 Sch=JA2_N +#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L12P_T1_MRCC_34 Sch=JA3_P +#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L12N_T1_MRCC_34 Sch=JA3_N +#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[4] }]; #IO_L22P_T3_34 Sch=JA4_P +#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[4] }]; #IO_L22N_T3_34 Sch=JA4_N + +## Pmod Header JB +#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L8N_T1_34 Sch=JB1_N +#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L8P_T1_34 Sch=JB1_P +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L1N_T0_34 Sch=JB2_N +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L1P_T0_34 Sch=JB2_P +#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L18N_T2_34 Sch=JB3_N +#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L18P_T2_34 Sch=JB3_P +#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { jb_n[4] }]; #IO_L4N_T0_34 Sch=JB4_N +#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jb_p[4] }]; #IO_L4P_T0_34 Sch=JB4_P + +## Audio Out +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L20N_T3_34 Sch=AUD_PWM +#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L20P_T3_34 Sch=AUD_SD + +## Crypto SDA +#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_25_35 Sch=CRYPTO_SDA + +## HDMI RX Signals +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L13N_T2_MRCC_35 Sch=HDMI_RX_CEC +#set_property -dict { PACKAGE_PIN P19 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L13N_T2_MRCC_34 Sch=HDMI_RX_CLK_N +#set_property -dict { PACKAGE_PIN N18 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L13P_T2_MRCC_34 Sch=HDMI_RX_CLK_P +#set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[0] }]; #IO_L16N_T2_34 Sch=HDMI_RX_D0_N +#set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[0] }]; #IO_L16P_T2_34 Sch=HDMI_RX_D0_P +#set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[1] }]; #IO_L15N_T2_DQS_34 Sch=HDMI_RX_D1_N +#set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[1] }]; #IO_L15P_T2_DQS_34 Sch=HDMI_RX_D1_P +#set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=HDMI_RX_D2_N +#set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=HDMI_RX_D2_P +#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_25_34 Sch=HDMI_RX_HPD +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=HDMI_RX_SCL +#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L11N_T1_SRCC_34 Sch=HDMI_RX_SDA + +## HDMI TX Signals +#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L19N_T3_VREF_35 Sch=HDMI_TX_CEC +#set_property -dict { PACKAGE_PIN L17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L11N_T1_SRCC_35 Sch=HDMI_TX_CLK_N +#set_property -dict { PACKAGE_PIN L16 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L11P_T1_SRCC_35 Sch=HDMI_TX_CLK_P +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[0] }]; #IO_L12N_T1_MRCC_35 Sch=HDMI_TX_D0_N +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[0] }]; #IO_L12P_T1_MRCC_35 Sch=HDMI_TX_D0_P +#set_property -dict { PACKAGE_PIN J19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[1] }]; #IO_L10N_T1_AD11N_35 Sch=HDMI_TX_D1_N +#set_property -dict { PACKAGE_PIN K19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[1] }]; #IO_L10P_T1_AD11P_35 Sch=HDMI_TX_D1_P +#set_property -dict { PACKAGE_PIN H18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[2] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=HDMI_TX_D2_N +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[2] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=HDMI_TX_D2_P +#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpdn }]; #IO_0_34 Sch=HDMI_TX_HDPN +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L8P_T1_AD10P_35 Sch=HDMI_TX_SCL +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L8N_T1_AD10N_35 Sch=HDMI_TX_SDA + +## ChipKit Outer Digital Header +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L5P_T0_34 Sch=CK_IO0 +#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L2N_T0_34 Sch=CK_IO1 +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=CK_IO2 +#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L3N_T0_DQS_34 Sch=CK_IO3 +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L10P_T1_34 Sch=CK_IO4 +#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L5N_T0_34 Sch=CK_IO5 +#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L19P_T3_34 Sch=CK_IO6 +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L9N_T1_DQS_34 Sch=CK_IO7 +#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L21P_T3_DQS_34 Sch=CK_IO8 +#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L21N_T3_DQS_34 Sch=CK_IO9 +#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L9P_T1_DQS_34 Sch=CK_IO10 +#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L19N_T3_VREF_34 Sch=CK_IO11 +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L23N_T3_34 Sch=CK_IO12 +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L23P_T3_34 Sch=CK_IO13 + +## ChipKit Inner Digital Header +#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19N_T3_VREF_13 Sch=CK_IO26 +#set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L6N_T0_VREF_13 Sch=CK_IO27 +#set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L22P_T3_13 Sch=CK_IO28 +#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_L11P_T1_SRCC_13 Sch=CK_IO29 +#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L11N_T1_SRCC_13 Sch=CK_IO30 +#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L17N_T2_13 Sch=CK_IO31 +#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L15P_T2_DQS_13 Sch=CK_IO32 +#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L21N_T3_DQS_13 Sch=CK_IO33 +#set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L16P_T2_13 Sch=CK_IO34 +#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L22N_T3_13 Sch=CK_IO35 +#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L13N_T2_MRCC_13 Sch=CK_IO36 +#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L13P_T2_MRCC_13 Sch=cCK_IO37 +#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L15N_T2_DQS_13 Sch=CK_IO38 +#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L14N_T2_SRCC_13 Sch=CK_IO39 +#set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L16N_T2_13 Sch=CK_IO40 +#set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L14P_T2_SRCC_13 Sch=CK_IO41 + +## ChipKit Outer Analog Header - as Single-Ended Analog Inputs +## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O. +## WARNING: Do not use both sets of constraints at the same time! +## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs. +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_35 Sch=CK_AN0_N ChipKit pin=A0 +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_35 Sch=CK_AN0_P ChipKit pin=A0 +#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { vaux9_n }]; #IO_L5N_T0_AD9N_35 Sch=CK_AN1_N ChipKit pin=A1 +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { vaux9_p }]; #IO_L5P_T0_AD9P_35 Sch=CK_AN1_P ChipKit pin=A1 +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L20N_T3_AD6N_35 Sch=CK_AN2_N ChipKit pin=A2 +#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L20P_T3_AD6P_35 Sch=CK_AN2_P ChipKit pin=A2 +#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L24N_T3_AD15N_35 Sch=CK_AN3_N ChipKit pin=A3 +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L24P_T3_AD15P_35 Sch=CK_AN3_P ChipKit pin=A3 +#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L17N_T2_AD5N_35 Sch=CK_AN4_N ChipKit pin=A4 +#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L17P_T2_AD5P_35 Sch=CK_AN4_P ChipKit pin=A4 +#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L18N_T2_AD13N_35 Sch=CK_AN5_N ChipKit pin=A5 +#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L18P_T2_AD13P_35 Sch=CK_AN5_P ChipKit pin=A5 +## ChipKit Outer Analog Header - as Digital I/O +## NOTE: The following constraints should be used when using these ports as digital I/O. +#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_L18N_T2_13 Sch=CK_A0 +#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L20P_T3_13 Sch=CK_A1 +#set_property -dict { PACKAGE_PIN W11 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L18P_T2_13 Sch=CK_A2 +#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L21P_T3_DQS_13 Sch=CK_A3 +#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L19P_T3_13 Sch=CK_A4 +#set_property -dict { PACKAGE_PIN U10 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L12N_T1_MRCC_13 Sch=CK_A5 + +## ChipKit Inner Analog Header - as Differential Analog Inputs +## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O. +## WARNING: Do not use both sets of constraints at the same time! +## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs. +#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L15P_T2_DQS_AD12P_35 Sch=AD12_P ChipKit pin=A6 +#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L15N_T2_DQS_AD12N_35 Sch=AD12_N ChipKit pin=A7 +#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_35 Sch=AD0_P ChipKit pin=A8 +#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_35 Sch=AD0_N ChipKit pin=A9 +#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_35 Sch=AD8_P ChipKit pin=A10 +#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_35 Sch=AD8_N ChipKit pin=A11 +## ChipKit Inner Analog Header - as Digital I/O +## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O. +#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L15P_T2_DQS_AD12P_35 Sch=AD12_P +#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L15N_T2_DQS_AD12N_35 Sch=AD12_N +#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L1P_T0_AD0P_35 Sch=AD0_P +#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L1N_T0_AD0N_35 Sch=AD0_N +#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L2P_T0_AD8P_35 Sch=AD8_P +#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L2N_T0_AD8N_35 Sch=AD8_N + +## ChipKit SPI +## NOTE: The ChipKit SPI header ports can also be used as digital I/O +#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L10N_T1_34 Sch=CK_MISO +#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L2P_T0_34 Sch=CK_MISO +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L19P_T3_35 Sch=CK_SCK +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L6P_T0_35 Sch=CK_SS + +## ChipKit I2C +#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_34 Sch=CK_SCL +#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_34 Sch=CK_SDA + +## Misc. ChipKit Ports +#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L20N_T3_13 Sch=CK_IOA + +## Not Connected Pins +#set_property PACKAGE_PIN F17 [get_ports {netic20_f17}]; #IO_L6N_T0_VREF_35 +#set_property PACKAGE_PIN G18 [get_ports {netic20_g18}]; #IO_L16N_T2_35 +#set_property PACKAGE_PIN T9 [get_ports {netic20_t9}]; #IO_L12P_T1_MRCC_13 +#set_property PACKAGE_PIN U9 [get_ports {netic20_u9}]; #IO_L17P_T2_13 + + + Index: Xilinx/Arty_z7_20/board_property.tcl =================================================================== --- Xilinx/Arty_z7_20/board_property.tcl (nonexistent) +++ Xilinx/Arty_z7_20/board_property.tcl (revision 48) @@ -0,0 +1,16 @@ +proc set_project_properties { } { + set_property "board_part_repo_paths" [list "$::env(PRONOC_WORK)/toolchain/board_files"] [current_project] + set_property "part" "xc7z020clg400-1" [current_project] + set_property "board_part" "digilentinc.com:arty-z7-20:part0:1.0" [current_project] + set_property "default_lib" "xil_defaultlib" [current_project] +} + + +proc program_board {bit_file} { + open_hw + connect_hw_server + open_hw_target + set_property PROGRAM.FILE $bit_file [get_hw_devices xc7z020_1] + program_hw_devices [get_hw_devices xc7z020_1] + refresh_hw_device [get_hw_devices xc7z020_1] +} Index: Xilinx/Arty_z7_20/jtag_intfc.sh =================================================================== --- Xilinx/Arty_z7_20/jtag_intfc.sh (nonexistent) +++ Xilinx/Arty_z7_20/jtag_intfc.sh (revision 48) @@ -0,0 +1,3 @@ +#!/bin/bash +JTAG_INTFC="$PRONOC_WORK/toolchain/bin/jtag_xilinx_xsct -a 3 -b 36" +#it works only for 32-bit jtag data width for 64 pass -b 68 Index: Xilinx/kc705/board_property.tcl =================================================================== --- Xilinx/kc705/board_property.tcl (nonexistent) +++ Xilinx/kc705/board_property.tcl (revision 48) @@ -0,0 +1,16 @@ +proc set_project_properties { } { + set_property "board_part_repo_paths" [list "$::env(PRONOC_WORK)/toolchain/board_files"] [current_project] + set_property "part" "xc7k325tffg900-2" [current_project] + set_property "board_part" "xilinx.com:kc705:part0:1.1" [current_project] + set_property "default_lib" "xil_defaultlib" [current_project] +} + + +proc program_board {bit_file} { + open_hw + connect_hw_server + open_hw_target + set_property PROGRAM.FILE $bit_file [get_hw_devices xc7k325t_0] + program_hw_devices [get_hw_devices xc7k325t_0] + refresh_hw_device [get_hw_devices xc7k325t_0] +} Index: Xilinx/kc705/jtag_intfc.sh =================================================================== --- Xilinx/kc705/jtag_intfc.sh (nonexistent) +++ Xilinx/kc705/jtag_intfc.sh (revision 48) @@ -0,0 +1,3 @@ +#!/bin/bash +JTAG_INTFC="$PRONOC_WORK/toolchain/bin/jtag_xilinx_xsct -a 2 -b 36" +#it works only for 32-bit jtag data width for 64 pass -b 68 Index: Xilinx/kc705/kc705.v =================================================================== --- Xilinx/kc705/kc705.v (nonexistent) +++ Xilinx/kc705/kc705.v (revision 48) @@ -0,0 +1,119 @@ +module kc705_wrapper( + // FMC conector + // clk and rst inputs + // output FMC_HPC_LA00_CC_N,//reset + output FMC_HPC_LA00_CC_P,//clk + // 32 input data + input FMC_HPC_LA01_CC_N, + input FMC_HPC_LA01_CC_P, + input FMC_HPC_LA02_N, + input FMC_HPC_LA02_P, + input FMC_HPC_LA03_N, + input FMC_HPC_LA03_P, + input FMC_HPC_LA04_N, + input FMC_HPC_LA04_P, + input FMC_HPC_LA05_N, + input FMC_HPC_LA05_P, + input FMC_HPC_LA06_N, + input FMC_HPC_LA06_P, + input FMC_HPC_LA07_N, + input FMC_HPC_LA07_P, + input FMC_HPC_LA08_N, + input FMC_HPC_LA08_P, + input FMC_HPC_LA09_N, + input FMC_HPC_LA09_P, + input FMC_HPC_LA10_N, + input FMC_HPC_LA10_P, + input FMC_HPC_LA11_N, + input FMC_HPC_LA11_P, + input FMC_HPC_LA12_N, + input FMC_HPC_LA12_P, + input FMC_HPC_LA13_N, + input FMC_HPC_LA13_P, + input FMC_HPC_LA14_N, + input FMC_HPC_LA14_P, + input FMC_HPC_LA15_N, + input FMC_HPC_LA15_P, + input FMC_HPC_LA16_N, + input FMC_HPC_LA16_P, + // ready input output + output FMC_HPC_LA17_CC_N, + // valid outut input + input FMC_HPC_LA17_CC_P, + // 32 bit output data + output FMC_HPC_LA18_CC_N, + output FMC_HPC_LA18_CC_P, + output FMC_HPC_LA19_N, + output FMC_HPC_LA19_P, + output FMC_HPC_LA20_N, + output FMC_HPC_LA20_P, + output FMC_HPC_LA21_N, + output FMC_HPC_LA21_P, + output FMC_HPC_LA22_N, + output FMC_HPC_LA22_P, + output FMC_HPC_LA23_N, + output FMC_HPC_LA23_P, + output FMC_HPC_LA24_N, + output FMC_HPC_LA24_P, + output FMC_HPC_LA25_N, + output FMC_HPC_LA25_P, + output FMC_HPC_LA26_N, + output FMC_HPC_LA26_P, + output FMC_HPC_LA27_N, + output FMC_HPC_LA27_P, + output FMC_HPC_LA28_N, + output FMC_HPC_LA28_P, + output FMC_HPC_LA29_N, + output FMC_HPC_LA29_P, + output FMC_HPC_LA30_N, + output FMC_HPC_LA30_P, + output FMC_HPC_LA31_N, + output FMC_HPC_LA31_P, + output FMC_HPC_LA32_N, + output FMC_HPC_LA32_P, + output FMC_HPC_LA33_N, + output FMC_HPC_LA33_P, + //ready output input + input FMC_HPC_HA00_CC_N, + // valid output intput + output FMC_HPC_HA00_CC_P, + // SPI and uart irq inputs + // input FMC_HPC_HA01_CC_N, + // input FMC_HPC_HA01_CC_P, + //asincronous rstn input + input FMC_HPC_HA02_N, + ///clk status leds + output FMC_HPC_HA02_P, + output FMC_HPC_HA03_N, + //diferential clk_input + input clk_p, + input clk_n, + //UART + input rxd, + output txd, + //JTAG + input tdi, + output tdo, + input tms, + input tck, + //SPI for SD-card + output spi_cs, + output spi_sclk, + output spi_mosi, + input spi_miso, + //leds + output [7: 0] led, + //buttons + input button_n, + input button_s, + input button_w, + input button_e, + input button_c, + //Dip sw + input [3: 0] dipsw + + +); + + +endmodule Index: Xilinx/kc705/kc705.xdc =================================================================== --- Xilinx/kc705/kc705.xdc (nonexistent) +++ Xilinx/kc705/kc705.xdc (revision 48) @@ -0,0 +1,279 @@ +##------------------------------------- +## LED Status Pinout (bottom to top) +##------------------------------------- + +#set_property PACKAGE_PIN AB8 [get_ports {led[0]}] +#set_property PACKAGE_PIN AA8 [get_ports {led[1]}] +#set_property PACKAGE_PIN AC9 [get_ports {led[2]}] +#set_property PACKAGE_PIN AB9 [get_ports {led[3]}] +#set_property PACKAGE_PIN AE26 [get_ports {led[4]}] +#set_property PACKAGE_PIN G19 [get_ports {led[5]}] +#set_property PACKAGE_PIN E18 [get_ports {led[6]}] +#set_property PACKAGE_PIN F16 [get_ports {led[7]}] + +#set_property IOSTANDARD LVCMOS15 [get_ports {led[0]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {led[1]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {led[2]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {led[3]}] +#set_property IOSTANDARD LVCMOS25 [get_ports {led[4]}] +#set_property IOSTANDARD LVCMOS25 [get_ports {led[5]}] +#set_property IOSTANDARD LVCMOS25 [get_ports {led[6]}] +#set_property IOSTANDARD LVCMOS25 [get_ports {led[7]}] + +#set_property SLEW SLOW [get_ports {led[7]}] +#set_property SLEW SLOW [get_ports {led[6]}] +#set_property SLEW SLOW [get_ports {led[5]}] +#set_property SLEW SLOW [get_ports {led[4]}] +#set_property SLEW SLOW [get_ports {led[3]}] +#set_property SLEW SLOW [get_ports {led[2]}] +#set_property SLEW SLOW [get_ports {led[1]}] +#set_property SLEW SLOW [get_ports {led[0]}] + +#set_property DRIVE 4 [get_ports {led[7]}] +#set_property DRIVE 4 [get_ports {led[6]}] +#set_property DRIVE 4 [get_ports {led[5]}] +#set_property DRIVE 4 [get_ports {led[4]}] +#set_property DRIVE 4 [get_ports {led[3]}] +#set_property DRIVE 4 [get_ports {led[2]}] +#set_property DRIVE 4 [get_ports {led[1]}] +#set_property DRIVE 4 [get_ports {led[0]}] + +#------------- +# BUTTON +#------------ + +#set_property PACKAGE_PIN AA12 [get_ports {button_n}] +#set_property PACKAGE_PIN AB12 [get_ports {button_s}] +#set_property PACKAGE_PIN AC6 [get_ports {button_w}] +#set_property PACKAGE_PIN AG5 [get_ports {button_e}] +#set_property PACKAGE_PIN G12 [get_ports {button_c}] + +#set_property IOSTANDARD LVCMOS15 [get_ports {button_n}] +#set_property IOSTANDARD LVCMOS15 [get_ports {button_s}] +#set_property IOSTANDARD LVCMOS15 [get_ports {button_w}] +#set_property IOSTANDARD LVCMOS15 [get_ports {button_e}] +#set_property IOSTANDARD LVCMOS25 [get_ports {button_c}] + +#-------------------- +# DIP SW +#------------------- + +#set_property PACKAGE_PIN Y28 [get_ports {dipsw[3]}] +#set_property PACKAGE_PIN AA28 [get_ports {dipsw[2]}] +#set_property PACKAGE_PIN W29 [get_ports {dipsw[1]}] +#set_property PACKAGE_PIN Y29 [get_ports {dipsw[0]}] + +#set_property IOSTANDARD LVCMOS25 [get_ports {dipsw[3]}] +#set_property IOSTANDARD LVCMOS25 [get_ports {dipsw[2]}] +#set_property IOSTANDARD LVCMOS25 [get_ports {dipsw[1]}] +#set_property IOSTANDARD LVCMOS25 [get_ports {dipsw[0]}] + +#----------------------- +# CLK +#----------------------- + +# on board differential clock, 200MHz +#set_property PACKAGE_PIN AD12 [get_ports clk_p] +#set_property IOSTANDARD DIFF_SSTL15 [get_ports clk_n] +#set_property PACKAGE_PIN AD11 [get_ports clk_n] +#set_property IOSTANDARD DIFF_SSTL15 [get_ports clk_n] + + + +# UART Pins +#set_property PACKAGE_PIN M19 [get_ports rxd] +#set_property IOSTANDARD LVCMOS25 [get_ports rxd] +#set_property PACKAGE_PIN K24 [get_ports txd] +#set_property IOSTANDARD LVCMOS25 [get_ports txd] + +# SD/SPI Pins +#set_property PACKAGE_PIN AC21 [get_ports spi_cs] +#set_property IOSTANDARD LVCMOS25 [get_ports spi_cs] +#set_property PACKAGE_PIN AB23 [get_ports spi_sclk] +#set_property IOSTANDARD LVCMOS25 [get_ports spi_sclk] +#set_property PACKAGE_PIN AB22 [get_ports spi_mosi] +#set_property IOSTANDARD LVCMOS25 [get_ports spi_mosi] +#set_property PACKAGE_PIN AC20 [get_ports spi_miso] +#set_property IOSTANDARD LVCMOS25 [get_ports spi_miso] + +# JTAG DEBUGGER /* julian pavon rivera::josh m4j0rt0m */ +#set_property PACKAGE_PIN AB25 [get_ports tms] +#set_property IOSTANDARD LVCMOS25 [get_ports tms] +#set_property PACKAGE_PIN L25 [get_ports tck] +#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_IBUF] +#set_property IOSTANDARD LVCMOS25 [get_ports tck] +#set_property PACKAGE_PIN AB28 [get_ports tdo] +#set_property IOSTANDARD LVCMOS25 [get_ports tdo] +#set_property PACKAGE_PIN AA27 [get_ports tdi] +#set_property IOSTANDARD LVCMOS25 [get_ports tdi] + +#FMC LA +#set_property PACKAGE_PIN B25 [get_ports FMC_HPC_LA00_CC_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA00_CC_N] +#set_property PACKAGE_PIN C25 [get_ports FMC_HPC_LA00_CC_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA00_CC_P] +#set_property PACKAGE_PIN C26 [get_ports FMC_HPC_LA01_CC_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA01_CC_N] +#set_property PACKAGE_PIN D26 [get_ports FMC_HPC_LA01_CC_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA01_CC_P] +#set_property PACKAGE_PIN H25 [get_ports FMC_HPC_LA02_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA02_N] +#set_property PACKAGE_PIN H24 [get_ports FMC_HPC_LA02_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA02_P] +#set_property PACKAGE_PIN H27 [get_ports FMC_HPC_LA03_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA03_N] +#set_property PACKAGE_PIN H26 [get_ports FMC_HPC_LA03_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA03_P] +#set_property PACKAGE_PIN F28 [get_ports FMC_HPC_LA04_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA04_N] +#set_property PACKAGE_PIN G28 [get_ports FMC_HPC_LA04_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA04_P] +#set_property PACKAGE_PIN F30 [get_ports FMC_HPC_LA05_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA05_N] +#set_property PACKAGE_PIN G29 [get_ports FMC_HPC_LA05_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA05_P] +#set_property PACKAGE_PIN G30 [get_ports FMC_HPC_LA06_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA06_N] +#set_property PACKAGE_PIN H30 [get_ports FMC_HPC_LA06_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA06_P] +#set_property PACKAGE_PIN D28 [get_ports FMC_HPC_LA07_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA07_N] +#set_property PACKAGE_PIN E28 [get_ports FMC_HPC_LA07_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA07_P] +#set_property PACKAGE_PIN E30 [get_ports FMC_HPC_LA08_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA08_N] +#set_property PACKAGE_PIN E29 [get_ports FMC_HPC_LA08_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA08_P] +#set_property PACKAGE_PIN A30 [get_ports FMC_HPC_LA09_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA09_N] +#set_property PACKAGE_PIN B30 [get_ports FMC_HPC_LA09_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA09_P] +#set_property PACKAGE_PIN C30 [get_ports FMC_HPC_LA10_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA10_N] +#set_property PACKAGE_PIN D29 [get_ports FMC_HPC_LA10_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA10_P] +#set_property PACKAGE_PIN F27 [get_ports FMC_HPC_LA11_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA11_N] +#set_property PACKAGE_PIN G27 [get_ports FMC_HPC_LA11_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA11_P] +#set_property PACKAGE_PIN B29 [get_ports FMC_HPC_LA12_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA12_N] +#set_property PACKAGE_PIN C29 [get_ports FMC_HPC_LA12_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA12_P] +#set_property PACKAGE_PIN A26 [get_ports FMC_HPC_LA13_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA13_N] +#set_property PACKAGE_PIN A25 [get_ports FMC_HPC_LA13_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA13_P] +#set_property PACKAGE_PIN A28 [get_ports FMC_HPC_LA14_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA14_N] +#set_property PACKAGE_PIN B28 [get_ports FMC_HPC_LA14_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA14_P] +#set_property PACKAGE_PIN B24 [get_ports FMC_HPC_LA15_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA15_N] +#set_property PACKAGE_PIN C24 [get_ports FMC_HPC_LA15_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA15_P] +#set_property PACKAGE_PIN A27 [get_ports FMC_HPC_LA16_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA16_N] +#set_property PACKAGE_PIN B27 [get_ports FMC_HPC_LA16_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA16_P] +#set_property PACKAGE_PIN E20 [get_ports FMC_HPC_LA17_CC_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA17_CC_N] +#set_property PACKAGE_PIN F20 [get_ports FMC_HPC_LA17_CC_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA17_CC_P] +#set_property PACKAGE_PIN E21 [get_ports FMC_HPC_LA18_CC_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA18_CC_N] +#set_property PACKAGE_PIN F21 [get_ports FMC_HPC_LA18_CC_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA18_CC_P] +#set_property PACKAGE_PIN F18 [get_ports FMC_HPC_LA19_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA19_N] +#set_property PACKAGE_PIN G18 [get_ports FMC_HPC_LA19_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA19_P] +#set_property PACKAGE_PIN D19 [get_ports FMC_HPC_LA20_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA20_N] +#set_property PACKAGE_PIN E19 [get_ports FMC_HPC_LA20_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA20_P] +#set_property PACKAGE_PIN A21 [get_ports FMC_HPC_LA21_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA21_N] +#set_property PACKAGE_PIN A20 [get_ports FMC_HPC_LA21_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA21_P] +#set_property PACKAGE_PIN B20 [get_ports FMC_HPC_LA22_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA22_N] +#set_property PACKAGE_PIN C20 [get_ports FMC_HPC_LA22_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA22_P] +#set_property PACKAGE_PIN A22 [get_ports FMC_HPC_LA23_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA23_N] +#set_property PACKAGE_PIN B22 [get_ports FMC_HPC_LA23_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA23_P] +#set_property PACKAGE_PIN A17 [get_ports FMC_HPC_LA24_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA24_N] +#set_property PACKAGE_PIN A16 [get_ports FMC_HPC_LA24_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA24_P] +#set_property PACKAGE_PIN F17 [get_ports FMC_HPC_LA25_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA25_N] +#set_property PACKAGE_PIN G17 [get_ports FMC_HPC_LA25_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA25_P] +#set_property PACKAGE_PIN A18 [get_ports FMC_HPC_LA26_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA26_N] +#set_property PACKAGE_PIN B18 [get_ports FMC_HPC_LA26_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA26_P] +#set_property PACKAGE_PIN B19 [get_ports FMC_HPC_LA27_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA27_N] +#set_property PACKAGE_PIN C19 [get_ports FMC_HPC_LA27_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA27_P] +#set_property PACKAGE_PIN C16 [get_ports FMC_HPC_LA28_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA28_N] +#set_property PACKAGE_PIN D16 [get_ports FMC_HPC_LA28_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA28_P] +#set_property PACKAGE_PIN B17 [get_ports FMC_HPC_LA29_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA29_N] +#set_property PACKAGE_PIN C17 [get_ports FMC_HPC_LA29_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA29_P] +#set_property PACKAGE_PIN C22 [get_ports FMC_HPC_LA30_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA30_N] +#set_property PACKAGE_PIN D22 [get_ports FMC_HPC_LA30_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA30_P] +#set_property PACKAGE_PIN F22 [get_ports FMC_HPC_LA31_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA31_N] +#set_property PACKAGE_PIN G22 [get_ports FMC_HPC_LA31_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA31_P] +#set_property PACKAGE_PIN C21 [get_ports FMC_HPC_LA32_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA32_N] +#set_property PACKAGE_PIN D21 [get_ports FMC_HPC_LA32_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA32_P] +#set_property PACKAGE_PIN H22 [get_ports FMC_HPC_LA33_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA33_N] +#set_property PACKAGE_PIN H21 [get_ports FMC_HPC_LA33_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA33_P] +## FMC HA +#set_property PACKAGE_PIN D13 [get_ports FMC_HPC_HA00_CC_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA00_CC_N] +#set_property PACKAGE_PIN D12 [get_ports FMC_HPC_HA00_CC_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA00_CC_P] +#set_property PACKAGE_PIN G14 [get_ports FMC_HPC_HA01_CC_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA01_CC_N] +#set_property PACKAGE_PIN H14 [get_ports FMC_HPC_HA01_CC_P] +# set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA01_CC_P] +#set_property PACKAGE_PIN C11 [get_ports FMC_HPC_HA02_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA02_N] +#set_property PACKAGE_PIN D11 [get_ports FMC_HPC_HA02_P] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA02_P] +#set_property PACKAGE_PIN B12 [get_ports FMC_HPC_HA03_N] +#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA03_N] + + + +#TIME +#jtag clk +#create_clock -period 100.000 -name jtag_clk -waveform {0.000 50.000} -add [get_ports tck] +#main clk +#create_clock -period 5.000 -name ext_clk -waveform {0.000 2.500} -add [get_ports clk_p] +#create_clock -period 5.000 -name asic_clk -waveform {0.000 2.500} -add [get_nets clk_asic] +#create_clock -period 20.000 -name Sysclk_clk -waveform {0.000 10.000} -add [get_nets clk] +#Diferent clock domains +#set_false_path -from [get_clocks asic_clk] -to [get_clocks Sysclk_clk] +#set_false_path -from [get_clocks Sysclk_clk] -to [get_clocks asic_clk] +#set_clock_groups -asynchronous \ +#-group {jtag_clk} \ +#-group {ext_clk} \ +#-group {asic_clk} \ +#-group {Sysclk_clk}

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