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URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/interface
    from Rev 16 to Rev 17
    ↔ Reverse comparison
  •

Rev 16 → Rev 17

/reset.ITC
12,10 → 12,11
'reset_o' => {
'outport_type' => 'concatenate',
'connect_name' => 'reset_i',
'name' => 'reset_o',
'range' => '',
'connect_type' => 'input',
'range' => '',
'name' => 'reset_o',
'connect_range' => '',
'default_out' => 'Active low',
'type' => 'output'
}
},
/wb_slave.ITC
12,104 → 12,135
'tag_o' => {
'outport_type' => 'concatenate',
'connect_name' => 'tag_i',
'name' => 'tag_o',
'range' => 'TAGw-1:0',
'connect_type' => 'input',
'range' => 'TAGw-1 : 0',
'name' => 'tag_o',
'connect_range' => 'TAGw-1 : 0',
'connect_range' => 'TAGw-1:0',
'default_out' => 'Active low',
'type' => 'output'
},
'stb_o' => {
'cyc_o' => {
'outport_type' => 'concatenate',
'connect_name' => 'stb_i',
'connect_name' => 'cyc_i',
'name' => 'cyc_o',
'range' => '',
'connect_type' => 'input',
'range' => '',
'name' => 'stb_o',
'connect_range' => '',
'default_out' => 'Active low',
'type' => 'output'
},
'cyc_o' => {
'stb_o' => {
'outport_type' => 'concatenate',
'connect_name' => 'cyc_i',
'connect_name' => 'stb_i',
'name' => 'stb_o',
'range' => '',
'connect_type' => 'input',
'range' => '',
'name' => 'cyc_o',
'connect_range' => '',
'default_out' => 'Active low',
'type' => 'output'
},
'dat_i' => {
'outport_type' => 'concatenate',
'connect_name' => 'dat_o',
'name' => 'dat_i',
'range' => 'Dw-1:0',
'connect_type' => 'output',
'range' => 'Dw-1 : 0',
'name' => 'dat_i',
'connect_range' => 'Dw-1 : 0',
'connect_range' => 'Dw-1:0',
'default_out' => 'Active low',
'type' => 'input'
},
'bte_o' => {
'outport_type' => 'concatenate',
'connect_name' => 'bte_i',
'name' => 'bte_o',
'range' => 'BTEw-1:0',
'connect_type' => 'input',
'connect_range' => 'BTEw-1:0',
'default_out' => 'Active low',
'type' => 'output'
},
'dat_o' => {
'outport_type' => 'concatenate',
'connect_name' => 'dat_i',
'name' => 'dat_o',
'range' => 'Dw-1:0',
'connect_type' => 'input',
'connect_range' => 'Dw-1:0',
'default_out' => 'Active low',
'type' => 'output'
},
'err_i' => {
'outport_type' => 'concatenate',
'connect_name' => 'err_o',
'name' => 'err_i',
'range' => '',
'connect_type' => 'output',
'range' => '',
'name' => 'err_i',
'connect_range' => '',
'default_out' => 'Active low',
'type' => 'input'
},
'dat_o' => {
'cti_o' => {
'outport_type' => 'concatenate',
'connect_name' => 'dat_i',
'connect_name' => 'cti_i',
'name' => 'cti_o',
'range' => 'CTIw-1:0',
'connect_type' => 'input',
'range' => 'Dw-1 : 0',
'name' => 'dat_o',
'connect_range' => 'Dw-1 : 0',
'connect_range' => 'CTIw-1:0',
'default_out' => 'Active low',
'type' => 'output'
},
'adr_o' => {
'outport_type' => 'concatenate',
'connect_name' => 'adr_i',
'name' => 'adr_o',
'range' => 'Aw-1:0',
'connect_type' => 'input',
'range' => 'Aw-1 : 0',
'name' => 'adr_o',
'connect_range' => 'Aw-1 : 0',
'connect_range' => 'Aw-1:0',
'default_out' => 'Active low',
'type' => 'output'
},
'rty_i' => {
'outport_type' => 'concatenate',
'connect_name' => 'rty_o',
'name' => 'rty_i',
'range' => '',
'connect_type' => 'output',
'connect_range' => '',
'default_out' => 'Active low',
'type' => 'input'
},
'we_o' => {
'outport_type' => 'concatenate',
'connect_name' => 'we_i',
'name' => 'we_o',
'range' => '',
'connect_type' => 'input',
'range' => '',
'name' => 'we_o',
'connect_range' => '',
'default_out' => 'Active low',
'type' => 'output'
},
'rty_i' => {
'outport_type' => 'concatenate',
'connect_name' => 'rty_o',
'connect_type' => 'output',
'range' => '',
'name' => 'rty_i',
'connect_range' => '',
'type' => 'input'
},
'sel_o' => {
'outport_type' => 'concatenate',
'connect_name' => 'sel_i',
'name' => 'sel_o',
'range' => 'SELw-1:0',
'connect_type' => 'input',
'range' => 'SELw-1 : 0',
'name' => 'sel_o',
'connect_range' => 'SELw-1 : 0',
'connect_range' => 'SELw-1:0',
'default_out' => 'Active low',
'type' => 'output'
},
'ack_i' => {
'outport_type' => 'concatenate',
'connect_name' => 'ack_o',
'name' => 'ack_i',
'range' => '',
'connect_type' => 'output',
'range' => '',
'name' => 'ack_i',
'connect_range' => '',
'default_out' => 'Active low',
'type' => 'input'
}
},
'file_name' => '/home/alireza/Mywork/develop/gui/main/lib/verilog/bus.v',
'file_name' => '/home/alireza/Mywork/mpsoc/perl_gui/lib/verilog/bus.v',
'module_name' => 'wb_slave_socket',
'type' => 'socket',
'category' => 'wishbone'
/interrupt_cpu.ITC
9,10 → 9,11
'int_o' => {
'outport_type' => 'concatenate',
'connect_name' => 'int_i',
'name' => 'int_o',
'range' => '',
'connect_type' => 'input',
'range' => '',
'name' => 'int_o',
'connect_range' => '',
'default_out' => 'Active low',
'type' => 'output'
}
},
/wb_master.ITC
1,7 → 1,7
$HashRef = bless( {
'connection_num' => 'single connection',
'name' => 'wb_master',
'description' => 'wish bone bus master interface',
'description' => 'Wishbone bus master interface',
'modules' => {
'clk_socket' => {},
'wb_master_socket' => {},
16,6 → 16,7
'range' => '',
'name' => 'err_o',
'connect_range' => '',
'default_out' => 'Active low',
'type' => 'output'
},
'stb_i' => {
25,6 → 26,7
'range' => '',
'name' => 'stb_i',
'connect_range' => '',
'default_out' => 'Active low',
'type' => 'input'
},
'cyc_i' => {
34,6 → 36,7
'range' => '',
'name' => 'cyc_i',
'connect_range' => '',
'default_out' => 'Active low',
'type' => 'input'
},
'dat_i' => {
40,9 → 43,10
'outport_type' => 'concatenate',
'connect_name' => 'dat_o',
'connect_type' => 'output',
'range' => 'Dw-1 : 0',
'range' => 'Dw-1:0',
'name' => 'dat_i',
'connect_range' => 'Dw-1 : 0',
'connect_range' => 'Dw-1:0',
'default_out' => 'Active low',
'type' => 'input'
},
'ack_o' => {
52,6 → 56,7
'range' => '',
'name' => 'ack_o',
'connect_range' => '',
'default_out' => 'Active low',
'type' => 'output'
},
'rty_o' => {
61,24 → 66,17
'range' => '',
'name' => 'rty_o',
'connect_range' => '',
'default_out' => 'Active low',
'type' => 'output'
},
'tag_i' => {
'outport_type' => 'concatenate',
'connect_name' => 'tag_o',
'connect_type' => 'output',
'range' => 'TAGw-1 : 0',
'name' => 'tag_i',
'connect_range' => 'TAGw-1 : 0',
'type' => 'input'
},
'adr_i' => {
'outport_type' => 'concatenate',
'connect_name' => 'adr_o',
'connect_type' => 'output',
'range' => 'Aw-1 : 0',
'range' => 'Aw-1:0',
'name' => 'adr_i',
'connect_range' => 'Aw-1 : 0',
'connect_range' => 'Aw-1:0',
'default_out' => 'Active low',
'type' => 'input'
},
'dat_o' => {
85,11 → 83,32
'outport_type' => 'concatenate',
'connect_name' => 'dat_i',
'connect_type' => 'input',
'range' => 'Dw-1 : 0',
'range' => 'Dw-1:0',
'name' => 'dat_o',
'connect_range' => 'Dw-1 : 0',
'connect_range' => 'Dw-1:0',
'default_out' => 'Active low',
'type' => 'output'
},
'tag_i' => {
'outport_type' => 'concatenate',
'connect_name' => 'tag_o',
'connect_type' => 'output',
'range' => 'TAGw-1:0',
'name' => 'tag_i',
'connect_range' => 'TAGw-1:0',
'default_out' => 'Active low',
'type' => 'input'
},
'cti_i' => {
'outport_type' => 'concatenate',
'connect_name' => 'cti_o',
'connect_type' => 'output',
'range' => 'CTIw-1:0',
'name' => 'cti_i',
'connect_range' => 'CTIw-1:0',
'default_out' => 'Active low',
'type' => 'input'
},
'we_i' => {
'outport_type' => 'concatenate',
'connect_name' => 'we_o',
97,6 → 116,7
'range' => '',
'name' => 'we_i',
'connect_range' => '',
'default_out' => 'Active low',
'type' => 'input'
},
'sel_i' => {
103,13 → 123,24
'outport_type' => 'concatenate',
'connect_name' => 'sel_o',
'connect_type' => 'output',
'range' => 'SELw-1 : 0',
'range' => 'SELw-1:0',
'name' => 'sel_i',
'connect_range' => 'SELw-1 : 0',
'connect_range' => 'SELw-1:0',
'default_out' => 'Active low',
'type' => 'input'
},
'bte_i' => {
'outport_type' => 'concatenate',
'connect_name' => 'bte_o',
'connect_type' => 'output',
'range' => 'BTEw-1:0',
'name' => 'bte_i',
'connect_range' => 'BTEw-1:0',
'default_out' => 'Active low',
'type' => 'input'
}
},
'file_name' => '/home/alireza/Mywork/develop/gui/main/lib/verilog/bus.v',
'file_name' => '/home/alireza/Mywork/mpsoc/perl_gui/lib/verilog/bus.v',
'module_name' => 'wb_master_socket',
'type' => 'socket',
'category' => 'wishbone'
/enable.ITC
11,15 → 11,16
'clk_o' => {
'outport_type' => 'concatenate',
'connect_name' => 'enable_o',
'name' => 'enable_i',
'range' => '',
'connect_type' => 'output',
'range' => '',
'name' => 'enable_i',
'connect_range' => '',
'default_out' => 'Active high',
'type' => 'input'
}
},
'file_name' => '/home/alireza/Mywork/mpsoc/perl_gui/lib/verilog/bus.v',
'module_name' => 'clk_socket',
'type' => 'plug',
'category' => 'source'
'category' => 'source',
'type' => 'plug'
}, 'intfc_gen' );
/ni.ITC
12,6 → 12,7
'range' => 'Yw-1:0',
'name' => 'current_y',
'connect_range' => 'Yw-1:0',
'default_out' => 'Active low',
'type' => 'input'
},
'flit_in' => {
21,6 → 22,7
'range' => 'Fw-1:0',
'name' => 'flit_in',
'connect_range' => 'Fw-1:0',
'default_out' => 'Active low',
'type' => 'input'
},
'current_x' => {
30,6 → 32,7
'range' => 'Xw-1:0',
'name' => 'current_x',
'connect_range' => 'Xw-1:0',
'default_out' => 'Active low',
'type' => 'input'
},
'credit_out' => {
39,6 → 42,7
'range' => 'V-1:0',
'name' => 'credit_out',
'connect_range' => 'V-1:0',
'default_out' => 'Active low',
'type' => 'output'
},
'flit_out' => {
48,6 → 52,7
'range' => 'Fw-1:0',
'name' => 'flit_out',
'connect_range' => 'Fw-1:0',
'default_out' => 'Active low',
'type' => 'output'
},
'credit_in' => {
57,6 → 62,7
'range' => 'V-1:0',
'name' => 'credit_in',
'connect_range' => 'V-1:0',
'default_out' => 'Active low',
'type' => 'input'
},
'flit_in_wr' => {
66,6 → 72,7
'range' => '',
'name' => 'flit_in_wr',
'connect_range' => '',
'default_out' => 'Active low',
'type' => 'input'
},
'flit_out_wr' => {
75,6 → 82,7
'range' => '',
'name' => 'flit_out_wr',
'connect_range' => '',
'default_out' => 'Active low',
'type' => 'output'
}
},
/interrupt_peripheral.ITC
12,8 → 12,9
'name' => 'int_i',
'range' => '',
'connect_type' => 'output',
'type' => 'input',
'connect_range' => ''
'connect_range' => '',
'default_out' => 'Active low',
'type' => 'input'
}
},
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/int_ctrl/int_ctrl.v',
/clk.ITC
12,10 → 12,11
'clk_o' => {
'outport_type' => 'concatenate',
'connect_name' => 'clk_i',
'name' => 'clk_o',
'range' => '',
'connect_type' => 'input',
'range' => '',
'name' => 'clk_o',
'connect_range' => '',
'default_out' => 'Active low',
'type' => 'output'
}
},
/noc.ITC
5,31 → 5,34
'ni' => {}
},
'ports' => {
'credit_in' => {
'outport_type' => 'concatenate',
'connect_name' => 'credit_out',
'name' => 'credit_in',
'range' => 'V-1 : 0',
'connect_type' => 'output',
'connect_range' => 'V-1 : 0',
'default_out' => '{V{1\'b0}}',
'type' => 'input'
},
'flit_in' => {
'outport_type' => 'concatenate',
'connect_name' => 'flit_out',
'name' => 'flit_in',
'range' => 'Fw-1 : 0',
'connect_type' => 'output',
'range' => 'Fw-1 : 0',
'name' => 'flit_in',
'connect_range' => 'Fw-1 : 0',
'default_out' => '{Fw{1\'b0}}',
'type' => 'input'
},
'credit_in' => {
'outport_type' => 'concatenate',
'connect_name' => 'credit_out',
'connect_type' => 'output',
'range' => 'V-1 : 0',
'name' => 'credit_in',
'connect_range' => 'V-1 : 0',
'type' => 'input'
},
'flit_in_wr' => {
'outport_type' => 'concatenate',
'connect_name' => 'flit_out_wr',
'name' => 'flit_in_wr',
'range' => '',
'connect_type' => 'output',
'range' => '',
'name' => 'flit_in_wr',
'connect_range' => '',
'default_out' => '1\'b0',
'type' => 'input'
}
},
/wb_addr_map.ITC
14,6 → 14,7
'range' => 'Aw-1 : 0',
'name' => 'grant_addr',
'connect_range' => 'Aw-1 : 0',
'default_out' => 'Active low',
'type' => 'output'
},
's_sel_one_hot' => {
23,6 → 24,7
'range' => 'S-1 : 0',
'name' => 'sel_one_hot',
'connect_range' => 'S-1 : 0',
'default_out' => 'Active low',
'type' => 'input'
}
},

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