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URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/interface
    from Rev 43 to Rev 48
    ↔ Reverse comparison
  •

Rev 43 → Rev 48

/RxD_sim.ITC
19,7 → 19,7
'timeout' => 0
},
'connection_num' => 'single connection',
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/jtag/jtag_uart/jtag_uart_wb.v',
'file_name' => 'mpsoc/rtl/src_peripheral/jtag/jtag_uart/jtag_uart_wb.v',
'module_name' => 'jtag_uart_wb',
'name' => 'RxD_sim',
'ports' => {
/clk.ITC
20,7 → 20,7
'type' => 'output'
}
},
'file_name' => '/home/alireza/Mywork/develop/gui/main/lib/verilog/bus.v',
'file_name' => 'mpsoc/perl_gui/lib/verilog/bus.v',
'module_name' => 'clk_socket',
'type' => 'socket',
'category' => 'source'
/enable.ITC
19,7 → 19,7
'type' => 'input'
}
},
'file_name' => '/home/alireza/Mywork/mpsoc/perl_gui/lib/verilog/bus.v',
'file_name' => 'mpsoc/perl_gui/lib/verilog/bus.v',
'module_name' => 'clk_socket',
'category' => 'source',
'type' => 'plug'
/interrupt_cpu.ITC
10,7 → 10,7
################################################################################
 
$HashRef = bless( {
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/int_ctrl/int_ctrl.v',
'file_name' => 'mpsoc/rtl/src_peripheral/int_ctrl/int_ctrl.v',
'description' => 'interrupt signal between interrupt controller and cpu',
'modules' => {
'int_ctrl' => {}
/interrupt_peripheral.ITC
17,7 → 17,7
'type' => 'input'
}
},
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/int_ctrl/int_ctrl.v',
'file_name' => 'mpsoc/rtl/src_peripheral/int_ctrl/int_ctrl.v',
'module_name' => 'int_ctrl',
'type' => 'socket',
'category' => 'interrupt'
/jtag_to_wb.ITC
0,0 → 1,49
#######################################################################
## File: jtag_to_wb.ITC
##
## Copyright (C) 2014-2019 Alireza Monemi
##
## This file is part of ProNoC 1.9.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$HashRef = bless( {
'module_name' => 'single_port_ram_top',
'category' => 'Communication',
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'name' => 'jtag_to_wb',
'modules' => {
'wb_single_port_ram' => {},
'single_port_ram_top' => {}
},
'ports' => {
'jwb_i' => {
'connect_name' => 'jwb_i',
'default_out' => 'Active low',
'type' => 'input',
'connect_type' => 'output',
'range' => 'JWB_INw-1:0',
'connect_range' => 'JWB_INw-1:0',
'name' => 'jwb_i',
'outport_type' => 'concatenate'
},
'jwb_o' => {
'outport_type' => 'concatenate',
'name' => 'jwb_o',
'connect_type' => 'input',
'type' => 'output',
'default_out' => 'Active low',
'connect_range' => 'JWB_OUTw-1:0',
'range' => 'JWB_OUTw-1:0',
'connect_name' => 'jwb_o'
}
},
'connection_num' => 'single connection',
'file_name' => 'mpsoc/rtl/src_peripheral/ram/wb_single_port_ram.v',
'type' => 'socket'
}, 'intfc_gen' );
/ni.ITC
1,112 → 1,68
#######################################################################
## File: ni.ITC
##
## Copyright (C) 2014-2016 Alireza Monemi
## Copyright (C) 2014-2019 Alireza Monemi
##
## This file is part of ProNoC 1.8.1
## This file is part of ProNoC 1.9.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
## MAY CAUSE UNEXPECTED BEHAVIOR.
################################################################################
 
$HashRef = bless( {
'connection_num' => 'single connection',
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'name' => 'ni',
'modules' => {
'ni' => {}
},
'category' => 'NoC',
'ports' => {
'flit_in_wr' => {
'connect_type' => 'output',
'name' => 'flit_in_wr',
'default_out' => 'Active low',
'range' => '',
'outport_type' => 'concatenate',
'type' => 'input',
'connect_name' => 'flit_out_wr',
'connect_range' => ''
},
'credit_in' => {
'range' => 'V-1:0',
'outport_type' => 'concatenate',
'connect_range' => 'V-1:0',
'connect_name' => 'credit_out',
'type' => 'input',
'name' => 'credit_in',
'chanel_in' => {
'connect_type' => 'output',
'default_out' => 'Active low'
},
'current_e_addr' => {
'default_out' => 'Active low',
'connect_type' => 'output',
'name' => 'current_e_addr',
'type' => 'input',
'connect_range' => 'EAw-1:0',
'connect_name' => 'current_e_addr',
'outport_type' => 'concatenate',
'range' => 'EAw-1:0'
},
'current_r_addr' => {
'connect_range' => 'smartflit_chanel_t',
'name' => 'chan_in',
'default_out' => 'Active low',
'connect_type' => 'output',
'name' => 'current_r_addr',
'type' => 'input',
'connect_range' => 'RAw-1:0',
'connect_name' => 'current_r_addr',
'outport_type' => 'concatenate',
'range' => 'RAw-1:0'
'connect_name' => 'chan_out',
'range' => 'smartflit_chanel_t',
'type' => 'input'
},
 
 
'credit_out' => {
'name' => 'credit_out',
'chanel_out' => {
'range' => 'smartflit_chanel_t',
'type' => 'output',
'outport_type' => 'concatenate',
'connect_range' => 'smartflit_chanel_t',
'connect_type' => 'input',
'default_out' => 'Active low',
'outport_type' => 'concatenate',
'range' => 'V-1:0',
'connect_range' => 'V-1:0',
'connect_name' => 'credit_in',
'type' => 'output'
'connect_name' => 'chan_in',
'name' => 'chan_out',
'default_out' => 'Active low'
},
'flit_in' => {
'connect_range' => 'Fw-1:0',
'connect_name' => 'flit_out',
'type' => 'input',
'range' => 'Fw-1:0',
'outport_type' => 'concatenate',
'default_out' => 'Active low',
'name' => 'flit_in',
'connect_type' => 'output'
},
'flit_out' => {
'connect_range' => 'Fw-1:0',
'connect_name' => 'flit_in',
'type' => 'output',
'outport_type' => 'concatenate',
'range' => 'Fw-1:0',
'default_out' => 'Active low',
'name' => 'flit_out',
'connect_type' => 'input'
},
'flit_out_wr' => {
'type' => 'output',
'connect_range' => '',
'connect_name' => 'flit_in_wr',
'outport_type' => 'concatenate',
'range' => '',
'default_out' => 'Active low',
'connect_type' => 'input',
'name' => 'flit_out_wr'
}
'current_r_addr' => {
'connect_name' => 'current_r_addr',
'default_out' => 'Active low',
'name' => 'current_r_addr',
'connect_range' => 'RAw-1:0',
'outport_type' => 'concatenate',
'connect_type' => 'output',
'type' => 'input',
'range' => 'RAw-1:0'
},
'current_e_addr' => {
'default_out' => 'Active low',
'name' => 'current_e_addr',
'connect_name' => 'current_e_addr',
'connect_type' => 'output',
'outport_type' => 'concatenate',
'connect_range' => 'EAw-1:0',
'type' => 'input',
'range' => 'EAw-1:0'
}
},
'file_name' => 'mpsoc/rtl/src_peripheral/ni/ni.v',
'type' => 'socket',
'module_name' => 'ni',
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ni/ni.v',
'category' => 'NoC',
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'type' => 'socket'
'modules' => {
'ni' => {}
},
'connection_num' => 'single connection'
}, 'intfc_gen' );
/noc.ITC
36,7 → 36,7
'type' => 'input'
}
},
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ni/ni.v',
'file_name' => 'mpsoc/rtl/src_peripheral/ni/ni.v',
'module_name' => 'ni',
'type' => 'plug',
'category' => 'NoC'
/reset.ITC
20,7 → 20,7
'type' => 'output'
}
},
'file_name' => '/home/alireza/Mywork/develop/gui/main/lib/verilog/bus.v',
'file_name' => 'mpsoc/perl_gui/lib/verilog/bus.v',
'module_name' => 'reset_socket',
'type' => 'socket',
'category' => 'source'
/snoop.ITC
12,7 → 12,7
$HashRef = bless( {
'connection_num' => 'multi connection',
'category' => 'wishbone',
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/bus/wishbone_bus.v',
'file_name' => 'mpsoc/rtl/src_peripheral/bus/wishbone_bus.v',
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
/wb_addr_map.ITC
28,7 → 28,7
'type' => 'input'
}
},
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/bus/wishbone_bus.v',
'file_name' => 'mpsoc/rtl/src_peripheral/bus/wishbone_bus.v',
'module_name' => 'wishbone_bus',
'type' => 'socket',
'category' => 'wishbone'
/wb_master.ITC
140,7 → 140,7
'type' => 'input'
}
},
'file_name' => '/home/alireza/Mywork/mpsoc/perl_gui/lib/verilog/bus.v',
'file_name' => 'mpsoc/perl_gui/lib/verilog/bus.v',
'module_name' => 'wb_master_socket',
'type' => 'socket',
'category' => 'wishbone'
/wb_slave.ITC
140,7 → 140,7
'type' => 'input'
}
},
'file_name' => '/home/alireza/Mywork/mpsoc/perl_gui/lib/verilog/bus.v',
'file_name' => 'mpsoc/perl_gui/lib/verilog/bus.v',
'module_name' => 'wb_slave_socket',
'type' => 'socket',
'category' => 'wishbone'

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