Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

/jtag_uart.IP File deleted

jtag_uart.IP Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: jtag_wb.IP =================================================================== --- jtag_wb.IP (revision 38) +++ jtag_wb.IP (nonexistent) @@ -1,220 +0,0 @@ -####################################################################### -## File: jtag_wb.IP -## -## Copyright (C) 2014-2016 Alireza Monemi -## -## This file is part of ProNoC 1.8.0 -## -## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT -## MAY CAUSE UNEXPECTED BEHAIVOR. -################################################################################ - -$ipgen = bless( { - 'hdl_files' => [ - '/mpsoc/src_peripheral/jtag/jtag_wb' - ], - 'modules' => { - 'vjtag_wb' => {}, - 'vjtag_ctrl' => {}, - 'wb_if' => {} - }, - 'unused' => { - 'plug:wb_master[0]' => [ - 'rty_i', - 'tag_o', - 'err_i', - 'bte_o' - ] - }, - 'parameters_order' => [ - 'DW', - 'AW', - 'S_Aw', - 'M_Aw', - 'TAGw', - 'SELw', - 'VJTAG_INDEX' - ], - 'category' => 'Communication', - 'module_name' => 'vjtag_wb', - 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/jtag/jtag_wb/vjtag_wb.v', - 'version' => 1, - 'ports_order' => [ - 'clk', - 'reset', - 'm_sel_o', - 'm_dat_o', - 'm_addr_o', - 'm_cti_o', - 'm_stb_o', - 'm_cyc_o', - 'm_we_o', - 'm_dat_i', - 'm_ack_i', - 'status_i' - ], - 'plugs' => { - 'clk' => { - 'clk' => {}, - 'type' => 'num', - 'value' => 1, - '0' => { - 'name' => 'clk' - } - }, - 'reset' => { - 'type' => 'num', - 'value' => 1, - 'reset' => {}, - '0' => { - 'name' => 'reset' - } - }, - 'wb_master' => { - 'type' => 'num', - 'value' => 1, - 'wb_master' => {}, - '0' => { - 'name' => 'wbm' - } - } - }, - 'ip_name' => 'jtag_wb', - 'parameters' => { - 'DW' => { - 'default' => '32', - 'info' => 'Parameter', - 'content' => '4,1024,8', - 'redefine_param' => 1, - 'global_param' => 'Localparam', - 'type' => 'Spin-button' - }, - 'VJTAG_INDEX' => { - 'global_param' => 'Localparam', - 'redefine_param' => 1, - 'type' => 'Entry', - 'default' => 'CORE_ID', - 'content' => '', - 'info' => 'JTAG control host identifies each instance of this IP core by a unique index number. The default value is the tile ID number. You assign an index value between 0 to 255.' - }, - 'S_Aw' => { - 'global_param' => 'Localparam', - 'redefine_param' => 1, - 'type' => 'Fixed', - 'default' => ' 7', - 'content' => '', - 'info' => 'Parameter' - }, - 'SELw' => { - 'content' => '', - 'info' => 'Parameter', - 'default' => ' 4', - 'type' => 'Fixed', - 'global_param' => 'Localparam', - 'redefine_param' => 1 - }, - 'TAGw' => { - 'default' => ' 3', - 'content' => '', - 'info' => 'Parameter', - 'redefine_param' => 1, - 'global_param' => 'Localparam', - 'type' => 'Fixed' - }, - 'AW' => { - 'type' => 'Fixed', - 'global_param' => 'Localparam', - 'redefine_param' => 1, - 'content' => '', - 'info' => 'Parameter', - 'default' => '32' - }, - 'M_Aw' => { - 'type' => 'Fixed', - 'global_param' => 'Localparam', - 'redefine_param' => 1, - 'info' => 'Parameter', - 'content' => '', - 'default' => ' 32' - } - }, - 'description' => 'A jtag to wishbone bus interface.', - 'ports' => { - 'm_stb_o' => { - 'intfc_port' => 'stb_o', - 'range' => '', - 'type' => 'output', - 'intfc_name' => 'plug:wb_master[0]' - }, - 'm_cyc_o' => { - 'range' => '', - 'type' => 'output', - 'intfc_port' => 'cyc_o', - 'intfc_name' => 'plug:wb_master[0]' - }, - 'm_addr_o' => { - 'intfc_name' => 'plug:wb_master[0]', - 'type' => 'output', - 'range' => 'M_Aw-1 : 0', - 'intfc_port' => 'adr_o' - }, - 'm_dat_o' => { - 'type' => 'output', - 'range' => 'DW-1 : 0', - 'intfc_port' => 'dat_o', - 'intfc_name' => 'plug:wb_master[0]' - }, - 'status_i' => { - 'range' => '', - 'type' => 'input', - 'intfc_port' => 'NC', - 'intfc_name' => 'IO' - }, - 'clk' => { - 'intfc_port' => 'clk_i', - 'range' => '', - 'type' => 'input', - 'intfc_name' => 'plug:clk[0]' - }, - 'm_ack_i' => { - 'intfc_name' => 'plug:wb_master[0]', - 'type' => 'input', - 'range' => '', - 'intfc_port' => 'ack_i' - }, - 'm_dat_i' => { - 'type' => 'input', - 'range' => 'DW-1 : 0', - 'intfc_port' => 'dat_i', - 'intfc_name' => 'plug:wb_master[0]' - }, - 'm_sel_o' => { - 'intfc_name' => 'plug:wb_master[0]', - 'range' => 'SELw-1 : 0', - 'type' => 'output', - 'intfc_port' => 'sel_o' - }, - 'm_cti_o' => { - 'intfc_name' => 'plug:wb_master[0]', - 'range' => 'TAGw-1 : 0', - 'type' => 'output', - 'intfc_port' => 'cti_o' - }, - 'reset' => { - 'intfc_port' => 'reset_i', - 'type' => 'input', - 'range' => '', - 'intfc_name' => 'plug:reset[0]' - }, - 'm_we_o' => { - 'intfc_name' => 'plug:wb_master[0]', - 'type' => 'output', - 'range' => '', - 'intfc_port' => 'we_o' - } - }, - 'gui_status' => { - 'timeout' => 0, - 'status' => 'ideal' - } - }, 'ip_gen' );

jtag_wb.IP Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: Altera_jtag_uart.IP =================================================================== --- Altera_jtag_uart.IP (nonexistent) +++ Altera_jtag_uart.IP (revision 48) @@ -0,0 +1,313 @@ +####################################################################### +## File: altera_jtag_uart.IP +## +## Copyright (C) 2014-2019 Alireza Monemi +## +## This file is part of ProNoC 2.0.0 +## +## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT +## MAY CAUSE UNEXPECTED BEHAIVOR. +################################################################################ + +$ipgen = bless( { + 'parameters_order' => [ + 'SIM_BUFFER_SIZE', + 'SIM_WAIT_COUNT', + 'INCLUDE_SIM_PRINTF' + ], + 'ip_name' => 'altera_jtag_uart', + 'modules' => { + 'altera_jtag_uart' => {} + }, + 'system_h' => ' + +#define ${IP}_DATA_REG (*((volatile unsigned int *) ($BASE))) +#define ${IP}_CONTROL_REG (*((volatile unsigned int *) ($BASE+4))) +#define ${IP}_CONTROL_WSPACE_MSK 0xFFFF0000 +#define ${IP}_DATA_RVALID_MSK 0x00008000 +#define ${IP}_DATA_DATA_MSK 0x000000FF + +//////////////////////////////*basic function for jtag_uart*//////////////////////////////////////// +void jtag_putchar(char ch); +char jtag_getchar(void); +void outbyte(char c); //called in printf(); +char inbyte(void); +void jtag_putchar(char ch); +char jtag_getchar(void); +int jtag_scanstr(char* buf); +int jtag_scanint(int *num); +/////////////////////////////*END: basic function for jtag_uart*//////////////////////////////////// + +#define INCLUDE_${INCLUDE_SIM_PRINTF} + +#ifdef INCLUDE_SIMPLE_PRINTF + #include "simple-printf/printf.h" +#endif + +#ifdef INCLUDE_SIMPLE_PRINTF_LONG + #include "simple-printf/printf.h" +#endif', + 'file_name' => 'mpsoc/rtl/src_peripheral/jtag/jtag_uart/altera_jtag_uart.v', + 'module_name' => 'altera_jtag_uart', + 'ports' => { + 's_cyc_i' => { + 'intfc_name' => 'plug:wb_slave[0]', + 'range' => '', + 'type' => 'input', + 'intfc_port' => 'cyc_i' + }, + 's_cti_i' => { + 'range' => '2 : 0', + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'cti_i', + 'type' => 'input' + }, + 's_dat_i' => { + 'intfc_port' => 'dat_i', + 'type' => 'input', + 'range' => '31 : 0', + 'intfc_name' => 'plug:wb_slave[0]' + }, + 'RxD_wr_sim' => { + 'intfc_port' => 'RxD_wr_sim', + 'type' => 'input', + 'range' => '', + 'intfc_name' => 'socket:RxD_sim[0]' + }, + 's_we_i' => { + 'intfc_port' => 'we_i', + 'type' => 'input', + 'range' => '', + 'intfc_name' => 'plug:wb_slave[0]' + }, + 'RxD_din_sim' => { + 'intfc_port' => 'RxD_din_sim', + 'type' => 'input', + 'range' => '7:0 ', + 'intfc_name' => 'socket:RxD_sim[0]' + }, + 'clk' => { + 'intfc_port' => 'clk_i', + 'type' => 'input', + 'range' => '', + 'intfc_name' => 'plug:clk[0]' + }, + 's_stb_i' => { + 'intfc_port' => 'stb_i', + 'type' => 'input', + 'range' => '', + 'intfc_name' => 'plug:wb_slave[0]' + }, + 'reset' => { + 'intfc_port' => 'reset_i', + 'type' => 'input', + 'range' => '', + 'intfc_name' => 'plug:reset[0]' + }, + 's_addr_i' => { + 'range' => '', + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'adr_i', + 'type' => 'input' + }, + 'irq' => { + 'range' => '', + 'intfc_name' => 'plug:interrupt_peripheral[0]', + 'intfc_port' => 'int_o', + 'type' => 'output' + }, + 's_dat_o' => { + 'range' => '31 : 0', + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'dat_o', + 'type' => 'output' + }, + 'RxD_ready_sim' => { + 'type' => 'output', + 'intfc_port' => 'RxD_ready_sim', + 'intfc_name' => 'socket:RxD_sim[0]', + 'range' => '' + }, + 's_sel_i' => { + 'intfc_port' => 'sel_i', + 'type' => 'input', + 'range' => '3 : 0', + 'intfc_name' => 'plug:wb_slave[0]' + }, + 's_ack_o' => { + 'range' => '', + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'ack_o', + 'type' => 'output' + } + }, + 'sw_files' => [ + '/mpsoc/src_processor/src_lib/simple-printf' + ], + 'gui_status' => { + 'timeout' => 0, + 'status' => 'ideal' + }, + 'system_c' => ' + +void outbyte(char c){jtag_putchar(c);} //called in printf(); + +char inbyte(){return jtag_getchar();} + +void jtag_putchar(char ch){ //print one char from jtag_uart + while((${IP}_CONTROL_REG&${IP}_CONTROL_WSPACE_MSK)==0); + ${IP}_DATA_REG=ch; +} + +char jtag_getchar(void){ //get one char from jtag_uart + unsigned int data; + data=${IP}_DATA_REG; + while(!(data & ${IP}_DATA_RVALID_MSK)) //wait for terminal input + data=${IP}_DATA_REG; + return (data & ${IP}_DATA_DATA_MSK); +} + +int jtag_scanstr(char* buf){ //scan string until to buf, return str length + char ch; unsigned int i=0; + while(1){ + ch=jtag_getchar(); + if(ch==\'\\n\') { buf[i]=0; jtag_putchar(ch); i++; break; } //ENTER + else if(ch==127) { printf("\\b \\b"); if(i>0) i--; } //backspace + else { jtag_putchar(ch); buf[i]=ch; i++; } //valid + } + return i; +} + +int jtag_scanint(int *num){ //return the scanned integer + unsigned int curr_num,strlen,i=0; + char str[11]; + strlen=jtag_scanstr(str); //scan str + if(strlen>11) { printf("overflows 32-bit integer value\\n");return 1; } //check overflow + *num=0; + for(i=0;i9); //not integer: do nothing + else *num=*num*10+curr_num; //is integer + } + return 0; +} + +#ifdef INCLUDE_SIMPLE_PRINTF + #include "simple-printf/printf.c" +#endif + +#ifdef INCLUDE_SIMPLE_PRINTF_LONG + #include "simple-printf/prinf_long.c" +#endif + + +', + 'category' => 'Communication', + 'parameters' => { + 'SIM_WAIT_COUNT' => { + 'global_param' => 'Localparam', + 'info' => 'This parameter is valid only in simulation. +If internal buffer has a data, the internal timer incremented by one in each clock cycle. If the timer reaches the WAIT_COUNT value, it writes the buffer value on the simulator terminal.', + 'content' => '2,100000,1', + 'redefine_param' => 1, + 'default' => '1000', + 'type' => 'Spin-button' + }, + 'SIM_BUFFER_SIZE' => { + 'info' => 'Internal buffer size. +This parameter is valid only in simulation. +If internal buffer overflows, the buffer content are displayed on simulator terminal.', + 'content' => '10,10000,1', + 'global_param' => 'Localparam', + 'type' => 'Spin-button', + 'default' => '100', + 'redefine_param' => 1 + }, + 'INCLUDE_SIM_PRINTF' => { + 'info' => 'Select source code for printf command: + "NONE": Do not include simple_printf source code. Select "NONE" In case printf command is supported in , or it is not needed in the software code. + "SIMPLE_PRINTF" Include a source code of printf command which supports a subset of formatted data: %%d, %%i, %%u, %%x, %%c, and %%s. long and floating formats are not supported. + "SIMPLE_PRINTF_LONG" Include a source code of printf command which supports a subset of formatted data: %%d, %%i, %%u, %%x, %%c, %%l, and %%s. floating format is not supported. + ', + 'content' => 'NONE,SIMPLE_PRINTF,SIMPLE_PRINTF_LONG', + 'global_param' => 'Don\'t include', + 'redefine_param' => 0, + 'default' => 'SIMPLE_PRINTF', + 'type' => 'Combo-box' + }, + + }, + 'ports_order' => [ + 'reset', + 'clk', + 'irq', + 's_dat_i', + 's_sel_i', + 's_addr_i', + 's_cti_i', + 's_stb_i', + 's_cyc_i', + 's_we_i', + 's_dat_o', + 's_ack_o', + 'RxD_din_sim', + 'RxD_wr_sim', + 'RxD_ready_sim' + ], + 'description' => 'The Altera JTAG UART IP core (qsys_jtag_uart) with Wishbone bus interface.', + 'version' => 20, + 'unused' => { + 'plug:wb_slave[0]' => [ + 'tag_i', + 'bte_i', + 'rty_o', + 'err_o' + ] + }, + 'sockets' => { + 'RxD_sim' => { + 'connection_num' => 'single connection', + 'value' => 1, + 'type' => 'num', + '0' => { + 'name' => 'RxD_sim' + } + } + }, + 'plugs' => { + 'interrupt_peripheral' => { + 'value' => 1, + 'type' => 'num', + '0' => { + 'name' => 'interrupt_peripheral' + } + }, + 'reset' => { + 'value' => 1, + 'type' => 'num', + '0' => { + 'name' => 'reset' + } + }, + 'clk' => { + 'value' => 1, + 'type' => 'num', + '0' => { + 'name' => 'clk' + } + }, + 'wb_slave' => { + 'value' => 1, + 'type' => 'num', + '0' => { + 'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller', + 'width' => 5, + 'name' => 'wb_slave' + } + } + }, + 'hdl_files' => [ + '/mpsoc/rtl/src_peripheral/jtag/jtag_uart/altera_jtag_uart.v', + '/mpsoc/rtl/src_peripheral/jtag/jtag_uart/altera_uart_simulator.v' + ] + }, 'ip_gen' ); Index: ProNoC_jtag_uart.IP =================================================================== --- ProNoC_jtag_uart.IP (nonexistent) +++ ProNoC_jtag_uart.IP (revision 48) @@ -0,0 +1,418 @@ +####################################################################### +## File: ProNoC_jtag_uart.IP +## +## Copyright (C) 2014-2019 Alireza Monemi +## +## This file is part of ProNoC 1.9.1 +## +## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT +## MAY CAUSE UNEXPECTED BEHAIVOR. +################################################################################ + +$ipgen = bless( { + 'system_h' => ' +#define ${IP}_DATA_REG (*((volatile unsigned int *) ($BASE))) +#define ${IP}_CONTROL_REG (*((volatile unsigned int *) ($BASE+4))) +#define ${IP}_CONTROL_WSPACE_MSK 0xFFFF0000 +#define ${IP}_DATA_RVALID_MSK 0x00008000 +#define ${IP}_DATA_DATA_MSK 0x000000FF + +//////////////////////////////*basic function for jtag_uart*//////////////////////////////////////// +void jtag_putchar(char ch); +char jtag_getchar(void); +void outbyte(char c); //called in printf(); +char inbyte(void); +void jtag_putchar(char ch); +char jtag_getchar(void); +int jtag_scanstr(char* buf); +int jtag_scanint(int *num); +/////////////////////////////*END: basic function for jtag_uart*//////////////////////////////////// + +#define INCLUDE_${INCLUDE_SIM_PRINTF} + +#ifdef INCLUDE_SIMPLE_PRINTF + #include "simple-printf/printf.h" +#endif + +#ifdef INCLUDE_SIMPLE_PRINTF_LONG + #include "simple-printf/printf.h" +#endif', + 'ports' => { + 'wb_adr_i' => { + 'intfc_name' => 'plug:wb_slave[0]', + 'range' => '', + 'type' => 'input', + 'intfc_port' => 'adr_i' + }, + 'wb_stb_i' => { + 'type' => 'input', + 'intfc_port' => 'stb_i', + 'intfc_name' => 'plug:wb_slave[0]', + 'range' => '' + }, + 'clk' => { + 'intfc_name' => 'plug:clk[0]', + 'range' => '', + 'intfc_port' => 'clk_i', + 'type' => 'input' + }, + 'wb_we_i' => { + 'range' => '', + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'we_i', + 'type' => 'input' + }, + 'wb_dat_o' => { + 'intfc_port' => 'dat_o', + 'type' => 'output', + 'intfc_name' => 'plug:wb_slave[0]', + 'range' => 'Dw-1: 0' + }, + 'wb_to_jtag' => { + 'range' => 'WB2Jw-1 : 0', + 'intfc_name' => 'socket:jtag_to_wb[0]', + 'intfc_port' => 'jwb_o', + 'type' => 'output' + }, + 'reset' => { + 'range' => '', + 'intfc_name' => 'plug:reset[0]', + 'intfc_port' => 'reset_i', + 'type' => 'input' + }, + 'wb_ack_o' => { + 'intfc_port' => 'ack_o', + 'type' => 'output', + 'intfc_name' => 'plug:wb_slave[0]', + 'range' => '' + }, + 'wb_cyc_i' => { + 'intfc_port' => 'cyc_i', + 'type' => 'input', + 'intfc_name' => 'plug:wb_slave[0]', + 'range' => '' + }, + 'jtag_to_wb' => { + 'range' => 'J2WBw-1 : 0', + 'intfc_name' => 'socket:jtag_to_wb[0]', + 'intfc_port' => 'jwb_i', + 'type' => 'input' + }, +'RxD_wr_sim' => { + 'intfc_port' => 'RxD_wr_sim', + 'type' => 'input', + 'range' => '', + 'intfc_name' => 'socket:RxD_sim[0]' + }, + 'RxD_din_sim' => { + 'intfc_port' => 'RxD_din_sim', + 'type' => 'input', + 'range' => '7:0 ', + 'intfc_name' => 'socket:RxD_sim[0]' + }, + 'RxD_ready_sim' => { + 'type' => 'output', + 'intfc_port' => 'RxD_ready_sim', + 'intfc_name' => 'socket:RxD_sim[0]', + 'range' => '' + }, + 'wb_dat_i' => { + 'intfc_port' => 'dat_i', + 'type' => 'input', + 'range' => 'Dw-1: 0', + 'intfc_name' => 'plug:wb_slave[0]' + } + }, + 'unused' => { + 'plug:wb_slave[0]' => [ + 'tag_i', + 'err_o', + 'cti_i', + 'bte_i', + 'rty_o', + 'sel_i' + ] + }, + + 'category' => 'Communication', + 'plugs' => { + 'wb_slave' => { + 'type' => 'num', + '0' => { + 'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller', + 'width' => 4, + 'name' => 'wb_slave' + }, + 'value' => 1 + }, + 'clk' => { + 'type' => 'num', + '0' => { + 'name' => 'clk' + }, + 'value' => 1 + }, + 'reset' => { + '0' => { + 'name' => 'reset' + }, + 'type' => 'num', + 'value' => 1 + } + }, + 'file_name' => 'mpsoc/rtl/src_peripheral/jtag/jtag_uart/pronoc_jtag_uart.v', + 'parameters' => { + 'JDw' => { + 'type' => 'Fixed', + 'global_param' => 'Parameter', + 'default' => '32', + 'info' => 'Parameter', + 'redefine_param' => 1, + 'content' => '' + }, + 'JINDEXw' => { + 'info' => 'Parameter', + 'default' => '8', + 'content' => '', + 'redefine_param' => 1, + 'global_param' => 'Parameter', + 'type' => 'Fixed' + }, + 'J2WBw' => { + 'type' => 'Fixed', + 'global_param' => 'Parameter', + 'redefine_param' => 1, + 'content' => '', + 'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1', + 'info' => undef + }, + 'Dw' => { + 'default' => '32', + 'info' => 'Parameter', + 'redefine_param' => 1, + 'content' => '', + 'type' => 'Fixed', + 'global_param' => 'Localparam' + }, + 'JAw' => { + 'global_param' => 'Parameter', + 'type' => 'Fixed', + 'info' => 'Parameter', + 'default' => '32', + 'content' => '', + 'redefine_param' => 1 + }, + 'JSTATUSw' => { + 'global_param' => 'Parameter', + 'type' => 'Fixed', + 'content' => '', + 'redefine_param' => 1, + 'info' => 'Parameter', + 'default' => '8' + }, + 'INCLUDE_SIM_PRINTF' => { + 'redefine_param' => 0, + 'content' => 'NONE,SIMPLE_PRINTF,SIMPLE_PRINTF_LONG', + 'default' => 'SIMPLE_PRINTF', + 'info' => 'Select source code for printf command: + "NONE": Do not include simple_printf source code. Select "NONE" In case printf command is supported in , or it is not needed in the software code. + "SIMPLE_PRINTF" Include a source code of printf command which supports a subset of formatted data: %%d, %%i, %%u, %%x, %%c, and %%s. long and floating formats are not supported. + "SIMPLE_PRINTF_LONG" Include a source code of printf command which supports a subset of formatted data: %%d, %%i, %%u, %%x, %%c, %%l, and %%s. floating format is not supported.', + 'type' => 'Combo-box', + 'global_param' => 'Don\'t include' + }, + 'Aw' => { + 'type' => 'Fixed', + 'global_param' => 'Localparam', + 'redefine_param' => 1, + 'content' => '', + 'default' => '1', + 'info' => 'Parameter' + }, + 'JTAG_CONNECT' => { + 'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"', + 'redefine_param' => 1, + 'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC. + +For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.', + 'default' => '"XILINX_JTAG_WB"', + 'global_param' => 'Parameter', + 'type' => 'Combo-box' + }, + 'JTAG_INDEX' => { + 'content' => '', + 'redefine_param' => 1, + 'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.', + 'default' => '126-CORE_ID', + 'global_param' => 'Parameter', + 'type' => 'Entry' + }, + 'BUFF_Aw' => { + 'global_param' => 'Localparam', + 'type' => 'Spin-button', + 'content' => '2,16,1', + 'redefine_param' => 1, + 'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.', + 'default' => '6' + }, + 'SELw' => { + 'global_param' => 'Localparam', + 'type' => 'Fixed', + 'info' => 'Parameter', + 'default' => '4', + 'content' => '', + 'redefine_param' => 1 + }, + 'JTAG_CHAIN' => { + 'global_param' => 'Parameter', + 'type' => 'Combo-box', + 'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are: + 4: JTAG runtime memory programmers. + 3: UART + 1,2: reserved', + 'default' => '3', + 'content' => '1,2,3,4', + 'redefine_param' => 0 + }, + 'WB2Jw' => { + 'content' => '', + 'redefine_param' => 1, + 'info' => '', + 'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1', + 'global_param' => 'Parameter', + 'type' => 'Fixed' + }, + 'TAGw' => { + 'type' => 'Fixed', + 'global_param' => 'Localparam', + 'default' => '3', + 'info' => 'Parameter', + 'redefine_param' => 1, + 'content' => '' + } + }, + 'gui_status' => { + 'status' => 'ideal', + 'timeout' => 0 + }, + 'ip_name' => 'ProNoC_jtag_uart', + 'ports_order' => [ + 'clk', + 'reset', + 'wb_dat_o', + 'wb_ack_o', + 'wb_adr_i', + 'wb_stb_i', + 'wb_cyc_i', + 'wb_we_i', + 'wb_dat_i', + 'wb_to_jtag', + 'jtag_to_wb', + 'RxD_din_sim', + 'RxD_wr_sim', + 'RxD_ready_sim' + ], + 'version' => 11, + 'description' => 'A jtag uart module. Controled using Altera Vjtag or Xilinx BSCANE2.', + 'parameters_order' => [ + 'Aw', + 'SELw', + 'TAGw', + 'Dw', + 'BUFF_Aw', + 'JTAG_INDEX', + 'JDw', + 'JAw', + 'JINDEXw', + 'JSTATUSw', + 'JTAG_CHAIN', + 'JTAG_CONNECT', + 'J2WBw', + 'WB2Jw', + 'INCLUDE_SIM_PRINTF' + ], + 'hdl_files' => [ + '/mpsoc/rtl/src_peripheral/jtag/jtag_uart/pronoc_jtag_uart.v', + '/mpsoc/rtl/src_peripheral/jtag/jtag_uart/altera_uart_simulator.v' + ], + 'sw_files' => [ + '/mpsoc/src_processor/src_lib/simple-printf' + ], + 'sockets' => { + 'RxD_sim' => { + 'connection_num' => 'single connection', + 'value' => 1, + 'type' => 'num', + '0' => { + 'name' => 'RxD_sim' + } + }, + +'jtag_to_wb' => { + 'value' => 1, + 'type' => 'num', + '0' => { + 'name' => 'jtag_to_wb' + }, + 'connection_num' => 'single connection' + } + }, + 'modules' => { + 'uart_dual_port_ram' => {}, + 'pronoc_jtag_uart' => {} + }, + 'system_c' => ' +void outbyte(char c){jtag_putchar(c);} //called in printf(); + +char inbyte(){return jtag_getchar();} + +void jtag_putchar(char ch){ //print one char from jtag_uart + while((${IP}_CONTROL_REG&${IP}_CONTROL_WSPACE_MSK)==0); + ${IP}_DATA_REG=ch; +} + +char jtag_getchar(void){ //get one char from jtag_uart + unsigned int data; + data=${IP}_DATA_REG; + while(!(data & ${IP}_DATA_RVALID_MSK)) //wait for terminal input + data=${IP}_DATA_REG; + return (data & ${IP}_DATA_DATA_MSK); +} + +int jtag_scanstr(char* buf){ //scan string until to buf, return str length + char ch; unsigned int i=0; + while(1){ + ch=jtag_getchar(); + if(ch==\'\\n\') { buf[i]=0; jtag_putchar(ch); i++; break; } //ENTER + else if(ch==127) { printf("\\b \\b"); if(i>0) i--; } //backspace + else { jtag_putchar(ch); buf[i]=ch; i++; } //valid + } + return i; +} + +int jtag_scanint(int *num){ //return the scanned integer + unsigned int curr_num,strlen,i=0; + char str[11]; + strlen=jtag_scanstr(str); //scan str + if(strlen>11) { printf("overflows 32-bit integer value\\n");return 1; } //check overflow + *num=0; + for(i=0;i9); //not integer: do nothing + else *num=*num*10+curr_num; //is integer + } + return 0; +} + +#ifdef INCLUDE_SIMPLE_PRINTF + #include "simple-printf/printf.c" +#endif + +#ifdef INCLUDE_SIMPLE_PRINTF_LONG + #include "simple-printf/prinf_long.c" +#endif + + +', + 'module_name' => 'pronoc_jtag_uart' + }, 'ip_gen' ); Index: ProNoC_jtag_wb.IP =================================================================== --- ProNoC_jtag_wb.IP (nonexistent) +++ ProNoC_jtag_wb.IP (revision 48) @@ -0,0 +1,296 @@ +####################################################################### +## File: ProNoC_jtag_wb.IP +## +## Copyright (C) 2014-2019 Alireza Monemi +## +## This file is part of ProNoC 1.9.1 +## +## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT +## MAY CAUSE UNEXPECTED BEHAIVOR. +################################################################################ + +$ipgen = bless( { + 'modules' => { + 'pronoc_jtag_wb' => {} + }, + 'category' => 'Communication', + 'ports_order' => [ + 'clk', + 'reset', + 'status_i', + 'm_sel_o', + 'm_dat_o', + 'm_addr_o', + 'm_cti_o', + 'm_stb_o', + 'm_cyc_o', + 'm_we_o', + 'm_dat_i', + 'm_ack_i', + 'jtag_to_wb', + 'wb_to_jtag' + ], + 'parameters' => { + 'WB2Jw' => { + 'content' => '', + 'type' => 'Fixed', + 'info' => 'Parameter', + 'redefine_param' => 1, + 'global_param' => 'Parameter', + 'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1' + }, + 'Dw' => { + 'type' => 'Fixed', + 'info' => 'Parameter', + 'content' => '', + 'default' => '32', + 'global_param' => 'Localparam', + 'redefine_param' => 1 + }, + 'J2WBw' => { + 'global_param' => 'Parameter', + 'redefine_param' => 1, + 'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1', + 'content' => '', + 'type' => 'Fixed', + 'info' => 'Parameter' + }, + 'JTAG_INDEX' => { + 'redefine_param' => 1, + 'global_param' => 'Parameter', + 'default' => 'CORE_ID', + 'content' => '', + 'info' => 'The index number id used for communicating with this IP. All modules connected to the same jtag tab should have a unique JTAG index number. The default value is CORE_ID. The core ID is the tile number in MPSoC. So if each tile has one JTAG_TO_WB module, its index would be different. In case there are multiple number of JTAG_TO_WB modules in one tile or the CORE_ID index number has been taken by another module such as RAM you need to manualy set a new value for this parameter.', + 'type' => 'Entry' + }, + 'JTAG_CONNECT' => { + 'content' => '"ALTERA_JTAG_WB","XILINX_JTAG_WB"', + 'type' => 'Combo-box', + 'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the Virtual JTAG tap IP core from Altera lib is used to communicate with the Host PC. + +For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the BSCANE2 JTAG tap IP core from XILINX lib is used to communicate with the Host PC.', + 'redefine_param' => 1, + 'global_param' => 'Parameter', + 'default' => '"XILINX_JTAG_WB"' + }, + 'JDw' => { + 'content' => '', + 'info' => 'Parameter', + 'type' => 'Fixed', + 'global_param' => 'Parameter', + 'redefine_param' => 1, + 'default' => '32' + }, + 'JINDEXw' => { + 'content' => '', + 'type' => 'Fixed', + 'info' => 'Parameter', + 'global_param' => 'Parameter', + 'redefine_param' => 1, + 'default' => '8' + }, + 'JTAG_CHAIN' => { + 'content' => '1,2,3,4', + 'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are: + 4: JTAG runtime memory programmers. + 3: UART + 1,2: reserved', + 'type' => 'Combo-box', + 'redefine_param' => 0, + 'global_param' => 'Parameter', + 'default' => '4' + }, + 'JSTATUSw' => { + 'info' => 'Parameter', + 'type' => 'Fixed', + 'content' => '', + 'default' => '8', + 'redefine_param' => 1, + 'global_param' => 'Parameter' + }, + 'JAw' => { + 'content' => '', + 'type' => 'Fixed', + 'info' => 'Parameter', + 'redefine_param' => 1, + 'global_param' => 'Parameter', + 'default' => '32' + }, + 'SELw' => { + 'type' => 'Fixed', + 'info' => 'Parameter', + 'content' => '', + 'default' => '4', + 'redefine_param' => 1, + 'global_param' => 'Localparam' + }, + 'Aw' => { + 'content' => '', + 'type' => 'Fixed', + 'info' => 'Parameter', + 'redefine_param' => 1, + 'global_param' => 'Localparam', + 'default' => '32' + }, + 'TAGw' => { + 'redefine_param' => 1, + 'global_param' => 'Localparam', + 'default' => '3', + 'content' => '', + 'info' => 'Parameter', + 'type' => 'Fixed' + } + }, + 'module_name' => 'pronoc_jtag_wb', + 'ports' => { + 'status_i' => { + 'type' => 'input', + 'range' => 'JSTATUSw-1 : 0', + 'intfc_name' => 'IO', + 'intfc_port' => 'NC' + }, + 'm_cyc_o' => { + 'type' => 'output', + 'range' => '', + 'intfc_name' => 'plug:wb_master[0]', + 'intfc_port' => 'cyc_o' + }, + 'clk' => { + 'intfc_port' => 'clk_i', + 'intfc_name' => 'plug:clk[0]', + 'range' => '', + 'type' => 'input' + }, + 'm_sel_o' => { + 'intfc_port' => 'sel_o', + 'intfc_name' => 'plug:wb_master[0]', + 'range' => 'SELw-1 : 0', + 'type' => 'output' + }, + 'm_cti_o' => { + 'intfc_port' => 'cti_o', + 'intfc_name' => 'plug:wb_master[0]', + 'range' => 'TAGw-1 : 0', + 'type' => 'output' + }, + 'wb_to_jtag' => { + 'range' => 'WB2Jw-1: 0', + 'type' => 'output', + 'intfc_port' => 'jwb_o', + 'intfc_name' => 'socket:jtag_to_wb[0]' + }, + 'm_we_o' => { + 'type' => 'output', + 'range' => '', + 'intfc_port' => 'we_o', + 'intfc_name' => 'plug:wb_master[0]' + }, + 'jtag_to_wb' => { + 'range' => 'J2WBw-1 : 0', + 'type' => 'input', + 'intfc_name' => 'socket:jtag_to_wb[0]', + 'intfc_port' => 'jwb_i' + }, + 'm_dat_i' => { + 'intfc_port' => 'dat_i', + 'intfc_name' => 'plug:wb_master[0]', + 'range' => 'Dw-1 : 0', + 'type' => 'input' + }, + 'm_stb_o' => { + 'type' => 'output', + 'range' => '', + 'intfc_port' => 'stb_o', + 'intfc_name' => 'plug:wb_master[0]' + }, + 'm_ack_i' => { + 'type' => 'input', + 'range' => '', + 'intfc_port' => 'ack_i', + 'intfc_name' => 'plug:wb_master[0]' + }, + 'reset' => { + 'intfc_name' => 'plug:reset[0]', + 'intfc_port' => 'reset_i', + 'type' => 'input', + 'range' => '' + }, + 'm_addr_o' => { + 'intfc_port' => 'adr_o', + 'intfc_name' => 'plug:wb_master[0]', + 'range' => 'Aw-1 : 0', + 'type' => 'output' + }, + 'm_dat_o' => { + 'range' => 'Dw-1 : 0', + 'type' => 'output', + 'intfc_port' => 'dat_o', + 'intfc_name' => 'plug:wb_master[0]' + } + }, + 'parameters_order' => [ + 'JTAG_CONNECT', + 'JTAG_INDEX', + 'JDw', + 'JAw', + 'JINDEXw', + 'JSTATUSw', + 'J2WBw', + 'WB2Jw', + 'Dw', + 'Aw', + 'TAGw', + 'SELw', + 'JTAG_CHAIN' + ], + 'sockets' => { + 'jtag_to_wb' => { + 'connection_num' => 'single connection', + 'value' => 1, + '0' => { + 'name' => 'jtag_to_wb' + }, + 'type' => 'num' + } + }, + 'plugs' => { + 'reset' => { + 'type' => 'num', + '0' => { + 'name' => 'reset' + }, + 'value' => 1 + }, + 'wb_master' => { + 'value' => 1, + '0' => { + 'name' => 'wb_master' + }, + 'type' => 'num' + }, + 'clk' => { + '0' => { + 'name' => 'clk' + }, + 'value' => 1, + 'type' => 'num' + } + }, + 'hdl_files' => [], + 'version' => 8, + 'file_name' => 'mpsoc/rtl/src_peripheral/jtag/jtag_wb/pronoc_jtag_wb.v', + 'gui_status' => { + 'timeout' => 0, + 'status' => 'ideal' + }, + 'description' => 'JTAG to Wishbone bus interface. This module allows reading/writing data to the IP cores connected to the wishbone bus (e.g. memory cores). ', + 'ip_name' => 'ProNoC_jtag_wb', + 'unused' => { + 'plug:wb_master[0]' => [ + 'tag_o', + 'bte_o', + 'err_i', + 'rty_i' + ] + } + }, 'ip_gen' ); Index: altera_jtag_uart.IP =================================================================== --- altera_jtag_uart.IP (nonexistent) +++ altera_jtag_uart.IP (revision 48) @@ -0,0 +1,313 @@ +####################################################################### +## File: altera_jtag_uart.IP +## +## Copyright (C) 2014-2019 Alireza Monemi +## +## This file is part of ProNoC 2.0.0 +## +## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT +## MAY CAUSE UNEXPECTED BEHAIVOR. +################################################################################ + +$ipgen = bless( { + 'parameters_order' => [ + 'SIM_BUFFER_SIZE', + 'SIM_WAIT_COUNT', + 'INCLUDE_SIM_PRINTF' + ], + 'ip_name' => 'altera_jtag_uart', + 'modules' => { + 'altera_jtag_uart' => {} + }, + 'system_h' => ' + +#define ${IP}_DATA_REG (*((volatile unsigned int *) ($BASE))) +#define ${IP}_CONTROL_REG (*((volatile unsigned int *) ($BASE+4))) +#define ${IP}_CONTROL_WSPACE_MSK 0xFFFF0000 +#define ${IP}_DATA_RVALID_MSK 0x00008000 +#define ${IP}_DATA_DATA_MSK 0x000000FF + +//////////////////////////////*basic function for jtag_uart*//////////////////////////////////////// +void jtag_putchar(char ch); +char jtag_getchar(void); +void outbyte(char c); //called in printf(); +char inbyte(void); +void jtag_putchar(char ch); +char jtag_getchar(void); +int jtag_scanstr(char* buf); +int jtag_scanint(int *num); +/////////////////////////////*END: basic function for jtag_uart*//////////////////////////////////// + +#define INCLUDE_${INCLUDE_SIM_PRINTF} + +#ifdef INCLUDE_SIMPLE_PRINTF + #include "simple-printf/printf.h" +#endif + +#ifdef INCLUDE_SIMPLE_PRINTF_LONG + #include "simple-printf/printf.h" +#endif', + 'file_name' => 'mpsoc/rtl/src_peripheral/jtag/jtag_uart/altera_jtag_uart.v', + 'module_name' => 'altera_jtag_uart', + 'ports' => { + 's_cyc_i' => { + 'intfc_name' => 'plug:wb_slave[0]', + 'range' => '', + 'type' => 'input', + 'intfc_port' => 'cyc_i' + }, + 's_cti_i' => { + 'range' => '2 : 0', + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'cti_i', + 'type' => 'input' + }, + 's_dat_i' => { + 'intfc_port' => 'dat_i', + 'type' => 'input', + 'range' => '31 : 0', + 'intfc_name' => 'plug:wb_slave[0]' + }, + 'RxD_wr_sim' => { + 'intfc_port' => 'RxD_wr_sim', + 'type' => 'input', + 'range' => '', + 'intfc_name' => 'socket:RxD_sim[0]' + }, + 's_we_i' => { + 'intfc_port' => 'we_i', + 'type' => 'input', + 'range' => '', + 'intfc_name' => 'plug:wb_slave[0]' + }, + 'RxD_din_sim' => { + 'intfc_port' => 'RxD_din_sim', + 'type' => 'input', + 'range' => '7:0 ', + 'intfc_name' => 'socket:RxD_sim[0]' + }, + 'clk' => { + 'intfc_port' => 'clk_i', + 'type' => 'input', + 'range' => '', + 'intfc_name' => 'plug:clk[0]' + }, + 's_stb_i' => { + 'intfc_port' => 'stb_i', + 'type' => 'input', + 'range' => '', + 'intfc_name' => 'plug:wb_slave[0]' + }, + 'reset' => { + 'intfc_port' => 'reset_i', + 'type' => 'input', + 'range' => '', + 'intfc_name' => 'plug:reset[0]' + }, + 's_addr_i' => { + 'range' => '', + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'adr_i', + 'type' => 'input' + }, + 'irq' => { + 'range' => '', + 'intfc_name' => 'plug:interrupt_peripheral[0]', + 'intfc_port' => 'int_o', + 'type' => 'output' + }, + 's_dat_o' => { + 'range' => '31 : 0', + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'dat_o', + 'type' => 'output' + }, + 'RxD_ready_sim' => { + 'type' => 'output', + 'intfc_port' => 'RxD_ready_sim', + 'intfc_name' => 'socket:RxD_sim[0]', + 'range' => '' + }, + 's_sel_i' => { + 'intfc_port' => 'sel_i', + 'type' => 'input', + 'range' => '3 : 0', + 'intfc_name' => 'plug:wb_slave[0]' + }, + 's_ack_o' => { + 'range' => '', + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'ack_o', + 'type' => 'output' + } + }, + 'sw_files' => [ + '/mpsoc/src_processor/src_lib/simple-printf' + ], + 'gui_status' => { + 'timeout' => 0, + 'status' => 'ideal' + }, + 'system_c' => ' + +void outbyte(char c){jtag_putchar(c);} //called in printf(); + +char inbyte(){return jtag_getchar();} + +void jtag_putchar(char ch){ //print one char from jtag_uart + while((${IP}_CONTROL_REG&${IP}_CONTROL_WSPACE_MSK)==0); + ${IP}_DATA_REG=ch; +} + +char jtag_getchar(void){ //get one char from jtag_uart + unsigned int data; + data=${IP}_DATA_REG; + while(!(data & ${IP}_DATA_RVALID_MSK)) //wait for terminal input + data=${IP}_DATA_REG; + return (data & ${IP}_DATA_DATA_MSK); +} + +int jtag_scanstr(char* buf){ //scan string until to buf, return str length + char ch; unsigned int i=0; + while(1){ + ch=jtag_getchar(); + if(ch==\'\\n\') { buf[i]=0; jtag_putchar(ch); i++; break; } //ENTER + else if(ch==127) { printf("\\b \\b"); if(i>0) i--; } //backspace + else { jtag_putchar(ch); buf[i]=ch; i++; } //valid + } + return i; +} + +int jtag_scanint(int *num){ //return the scanned integer + unsigned int curr_num,strlen,i=0; + char str[11]; + strlen=jtag_scanstr(str); //scan str + if(strlen>11) { printf("overflows 32-bit integer value\\n");return 1; } //check overflow + *num=0; + for(i=0;i9); //not integer: do nothing + else *num=*num*10+curr_num; //is integer + } + return 0; +} + +#ifdef INCLUDE_SIMPLE_PRINTF + #include "simple-printf/printf.c" +#endif + +#ifdef INCLUDE_SIMPLE_PRINTF_LONG + #include "simple-printf/prinf_long.c" +#endif + + +', + 'category' => 'Communication', + 'parameters' => { + 'SIM_WAIT_COUNT' => { + 'global_param' => 'Localparam', + 'info' => 'This parameter is valid only in simulation. +If internal buffer has a data, the internal timer incremented by one in each clock cycle. If the timer reaches the WAIT_COUNT value, it writes the buffer value on the simulator terminal.', + 'content' => '2,100000,1', + 'redefine_param' => 1, + 'default' => '1000', + 'type' => 'Spin-button' + }, + 'SIM_BUFFER_SIZE' => { + 'info' => 'Internal buffer size. +This parameter is valid only in simulation. +If internal buffer overflows, the buffer content are displayed on simulator terminal.', + 'content' => '10,10000,1', + 'global_param' => 'Localparam', + 'type' => 'Spin-button', + 'default' => '100', + 'redefine_param' => 1 + }, + 'INCLUDE_SIM_PRINTF' => { + 'info' => 'Select source code for printf command: + "NONE": Do not include simple_printf source code. Select "NONE" In case printf command is supported in , or it is not needed in the software code. + "SIMPLE_PRINTF" Include a source code of printf command which supports a subset of formatted data: %%d, %%i, %%u, %%x, %%c, and %%s. long and floating formats are not supported. + "SIMPLE_PRINTF_LONG" Include a source code of printf command which supports a subset of formatted data: %%d, %%i, %%u, %%x, %%c, %%l, and %%s. floating format is not supported. + ', + 'content' => 'NONE,SIMPLE_PRINTF,SIMPLE_PRINTF_LONG', + 'global_param' => 'Don\'t include', + 'redefine_param' => 0, + 'default' => 'NONE', + 'type' => 'Combo-box' + }, + + }, + 'ports_order' => [ + 'reset', + 'clk', + 'irq', + 's_dat_i', + 's_sel_i', + 's_addr_i', + 's_cti_i', + 's_stb_i', + 's_cyc_i', + 's_we_i', + 's_dat_o', + 's_ack_o', + 'RxD_din_sim', + 'RxD_wr_sim', + 'RxD_ready_sim' + ], + 'description' => 'The Altera JTAG UART IP core (qsys_jtag_uart) with Wishbone bus interface.', + 'version' => 20, + 'unused' => { + 'plug:wb_slave[0]' => [ + 'tag_i', + 'bte_i', + 'rty_o', + 'err_o' + ] + }, + 'sockets' => { + 'RxD_sim' => { + 'connection_num' => 'single connection', + 'value' => 1, + 'type' => 'num', + '0' => { + 'name' => 'RxD_sim' + } + } + }, + 'plugs' => { + 'interrupt_peripheral' => { + 'value' => 1, + 'type' => 'num', + '0' => { + 'name' => 'interrupt_peripheral' + } + }, + 'reset' => { + 'value' => 1, + 'type' => 'num', + '0' => { + 'name' => 'reset' + } + }, + 'clk' => { + 'value' => 1, + 'type' => 'num', + '0' => { + 'name' => 'clk' + } + }, + 'wb_slave' => { + 'value' => 1, + 'type' => 'num', + '0' => { + 'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller', + 'width' => 5, + 'name' => 'wb_slave' + } + } + }, + 'hdl_files' => [ + '/mpsoc/rtl/src_peripheral/jtag/jtag_uart/altera_jtag_uart.v', + '/mpsoc/rtl/src_peripheral/jtag/jtag_uart/altera_uart_simulator.v' + ] + }, 'ip_gen' ); Index: ethmac_100.IP =================================================================== --- ethmac_100.IP (revision 38) +++ ethmac_100.IP (revision 48) @@ -1,468 +1,527 @@ ####################################################################### ## File: ethmac_100.IP ## -## Copyright (C) 2014-2016 Alireza Monemi +## Copyright (C) 2014-2019 Alireza Monemi ## -## This file is part of ProNoC 1.7.0 +## This file is part of ProNoC 1.9.1 ## ## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ## MAY CAUSE UNEXPECTED BEHAIVOR. ################################################################################ -$ethtop = bless( { - 'version' => 1, - 'module_name' => 'ethtop', - 'unused' => { - 'plug:wb_master[0]' => [ - 'bte_o', - 'rty_i', - 'cti_o', - 'tag_o' - ], - 'plug:wb_slave[0]' => [ - 'cti_i', - 'bte_i', - 'tag_i', - 'rty_o' - ] - }, - 'plugs' => { - 'wb_master' => { - 'wb_master' => {}, - 'value' => 1, - 'type' => 'num', - '0' => { - 'name' => 'wb_master' - } - }, - 'wb_slave' => { +$ipgen = bless( { + 'version' => 2, + 'parameters' => { + 'TX_FIFO_DATA_WIDTH' => { + 'type' => 'Fixed', + 'global_param' => 0, + 'redefine_param' => 1, + 'default' => ' 32', + 'content' => '', + 'info' => undef + }, + 'TX_FIFO_DEPTH' => { + 'default' => ' 16', + 'content' => '', + 'info' => undef, + 'type' => 'Fixed', + 'redefine_param' => 1, + 'global_param' => 0 + }, + 'RX_FIFO_CNT_WIDTH' => { + 'info' => undef, + 'default' => ' 5', + 'content' => '', + 'global_param' => 0, + 'redefine_param' => 1, + 'type' => 'Fixed' + }, + 'RX_FIFO_DATA_WIDTH' => { + 'default' => ' 32', + 'content' => '', + 'info' => undef, + 'type' => 'Fixed', + 'global_param' => 0, + 'redefine_param' => 1 + }, + 'TX_FIFO_CNT_WIDTH' => { + 'content' => '', + 'default' => ' 5', + 'info' => undef, + 'type' => 'Fixed', + 'redefine_param' => 1, + 'global_param' => 0 + }, + 'RX_FIFO_DEPTH' => { + 'default' => ' 16', + 'content' => '', + 'info' => undef, + 'type' => 'Fixed', + 'global_param' => 0, + 'redefine_param' => 1 + } + }, + 'gen_sw_files' => [ + '/mpsoc/rtl/src_peripheral/ethmac/ethfrename_sep_t${IP}.h' + ], + 'system_h' => ' + +void ${IP}_init(); +void ${IP}_interrupt(); +void ${IP}_recv_ack(void); +int ${IP}_send(int length); //return (-1) or length (still processing previous) or asserted + +#define ${IP}_BASE_ADDR $BASE +#define ${IP}_MODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x00 ))) +#define ${IP}_INT_SOURCE (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x04 ))) +#define ${IP}_INT_MASK (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x08 ))) +#define ${IP}_IPGT (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x0C ))) +#define ${IP}_IPGR1 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x10 ))) +#define ${IP}_IPGR2 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x14 ))) +#define ${IP}_PACKETLEN (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x18 ))) +#define ${IP}_COLLCONF (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x1C ))) +#define ${IP}_TX_BD_NUM (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x20 ))) +#define ${IP}_CTRLMODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x24 ))) +#define ${IP}_MIIMODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x28 ))) +#define ${IP}_MIICOMMAND (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x2C ))) +#define ${IP}_MIIADDR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x30 ))) +#define ${IP}_MIITX_DATA (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x34 ))) +#define ${IP}_MIIRX_DATA (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x38 ))) +#define ${IP}_MIISTATUS (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x3C ))) +#define ${IP}_MAC_ADDR0 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x40 ))) +#define ${IP}_MAC_ADDR1 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x44 ))) +#define ${IP}_HASH0_ADR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x48 ))) +#define ${IP}_HASH1_ADR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x4C ))) +#define ${IP}_TXCTRL (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x50 ))) +#define ${IP}_TXBD0H (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x404 ))) +#define ${IP}_TXBD0L (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x400 ))) +#define ${IP}_RXBD0H (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x604 ))) //this depends on TX_BD_NUM but this is the standard value +#define ${IP}_RXBD0L (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x600 ))) //this depends on TX_BD_NUM but this is the standard value + + +#include "${IP}.h"', + 'plugs' => { + 'reset' => { + 'reset' => {}, + 'type' => 'num', + 'value' => 1, + '0' => { + 'name' => 'reset' + } + }, + 'wb_slave' => { + 'value' => 1, + 'type' => 'num', + 'wb_slave' => {}, + '0' => { + 'width' => 11, + 'name' => 'wb_slave', + 'addr' => '0x9200_0000 0x92ff_ffff Ethernet Controller' + } + }, + 'interrupt_peripheral' => { + '0' => { + 'name' => 'interrupt_peripheral' + }, + 'interrupt_peripheral' => {}, + 'type' => 'num', + 'value' => 1 + }, + 'clk' => { + 'clk' => {}, + '0' => { + 'name' => 'clk' + }, + 'type' => 'num', + 'value' => 1 + }, + 'wb_master' => { 'value' => 1, - 'wb_slave' => {}, 'type' => 'num', + 'wb_master' => {}, '0' => { - 'addr' => '0x9200_0000 0x92ff_ffff Ethernet Controller', - 'width' => 11, - 'name' => 'wb_slave' + 'name' => 'wb_master' } - }, - 'clk' => { - 'value' => 1, - 'clk' => {}, - 'type' => 'num', - '0' => { - 'name' => 'clk' - } - }, - 'interrupt_peripheral' => { - 'value' => 1, - 'interrupt_peripheral' => {}, - '0' => { - 'name' => 'interrupt_peripheral' - }, - 'type' => 'num' - }, - 'reset' => { - 'value' => 1, - '0' => { - 'name' => 'reset' - }, - 'type' => 'num', - 'reset' => {} - } - }, - 'custom_file_num' => 1, - 'ports' => { - 'wb_clk_i' => { - 'range' => '', - 'intfc_name' => 'plug:clk[0]', - 'intfc_port' => 'clk_i', - 'type' => 'input' - }, - 'm_wb_adr_o' => { - 'intfc_port' => 'adr_o', - 'type' => 'output', - 'range' => '31:0', - 'intfc_name' => 'plug:wb_master[0]' + } + }, + 'sw_files' => [], + 'custom_file' => { + '0' => {} + }, + 'file_name' => 'mpsoc/rtl/src_peripheral/ethmac/ethtop.v', + 'custom_file_num' => 1, + 'parameters_order' => [ + 'TX_FIFO_DATA_WIDTH', + 'TX_FIFO_DEPTH', + 'TX_FIFO_CNT_WIDTH', + 'RX_FIFO_DATA_WIDTH', + 'RX_FIFO_DEPTH', + 'RX_FIFO_CNT_WIDTH' + ], + 'ip_name' => 'ethmac_100', + 'description' => 'The Ethernet MAC 10/100 Mbps. +For more information please check: https://opencores.org/project,ethmac', + 'ports' => { + 'm_wb_adr_o' => { + 'intfc_port' => 'adr_o', + 'range' => '31:0', + 'type' => 'output', + 'intfc_name' => 'plug:wb_master[0]' + }, + 'wb_err_o' => { + 'intfc_name' => 'plug:wb_slave[0]', + 'range' => '', + 'type' => 'output', + 'intfc_port' => 'err_o' + }, + 'wb_we_i' => { + 'range' => '', + 'type' => 'input', + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'we_i' + }, + 'm_wb_sel_o' => { + 'intfc_name' => 'plug:wb_master[0]', + 'range' => '3:0', + 'type' => 'output', + 'intfc_port' => 'sel_o' + }, + 'mrxdv_pad_i' => { + 'range' => '', + 'type' => 'input', + 'intfc_name' => 'IO', + 'intfc_port' => 'IO' }, - 'mtxd_pad_o' => { - 'intfc_port' => 'IO', - 'type' => 'output', - 'range' => '3:0', - 'intfc_name' => 'IO' - }, - 'int_o' => { - 'intfc_port' => 'int_o', - 'type' => 'output', - 'range' => '', - 'intfc_name' => 'plug:interrupt_peripheral[0]' - }, - 'mdc_pad_o' => { + 'int_o' => { + 'intfc_port' => 'int_o', + 'type' => 'output', + 'range' => '', + 'intfc_name' => 'plug:interrupt_peripheral[0]' + }, + 'm_wb_dat_i' => { + 'intfc_port' => 'dat_i', + 'type' => 'input', + 'range' => '31:0', + 'intfc_name' => 'plug:wb_master[0]' + }, + 'wb_clk_i' => { + 'type' => 'input', + 'range' => '', + 'intfc_name' => 'plug:clk[0]', + 'intfc_port' => 'clk_i' + }, + 'm_wb_ack_i' => { + 'type' => 'input', + 'range' => '', + 'intfc_name' => 'plug:wb_master[0]', + 'intfc_port' => 'ack_i' + }, + 'wb_rst_i' => { + 'intfc_port' => 'reset_i', + 'range' => '', + 'type' => 'input', + 'intfc_name' => 'plug:reset[0]' + }, + 'mrxd_pad_i' => { 'intfc_port' => 'IO', - 'type' => 'output', - 'range' => '', + 'range' => '3:0', + 'type' => 'input', 'intfc_name' => 'IO' }, - 'wb_ack_o' => { - 'intfc_port' => 'ack_o', - 'type' => 'output', - 'range' => '', - 'intfc_name' => 'plug:wb_slave[0]' - }, - 'mtxen_pad_o' => { + 'mtxerr_pad_o' => { 'intfc_port' => 'IO', + 'intfc_name' => 'IO', 'type' => 'output', - 'range' => '', - 'intfc_name' => 'IO' + 'range' => '' }, - 'wb_dat_i' => { - 'intfc_port' => 'dat_i', - 'type' => 'input', - 'range' => '31:0', - 'intfc_name' => 'plug:wb_slave[0]' - }, - 'wb_stb_i' => { - 'type' => 'input', - 'intfc_port' => 'stb_i', - 'intfc_name' => 'plug:wb_slave[0]', - 'range' => '' - }, - 'mcrs_pad_i' => { + 'md_pad_o' => { + 'intfc_port' => 'IO', + 'intfc_name' => 'IO', + 'type' => 'output', + 'range' => '' + }, + 'wb_adr_i' => { + 'intfc_port' => 'adr_i', + 'intfc_name' => 'plug:wb_slave[0]', + 'type' => 'input', + 'range' => '9:0' + }, + 'wb_dat_o' => { + 'intfc_port' => 'dat_o', + 'intfc_name' => 'plug:wb_slave[0]', + 'range' => '31:0', + 'type' => 'output' + }, + 'm_wb_err_i' => { + 'intfc_name' => 'plug:wb_master[0]', + 'type' => 'input', + 'range' => '', + 'intfc_port' => 'err_i' + }, + 'mtxen_pad_o' => { + 'intfc_port' => 'IO', 'intfc_name' => 'IO', 'range' => '', - 'type' => 'input', - 'intfc_port' => 'IO' + 'type' => 'output' }, - 'wb_rst_i' => { - 'type' => 'input', - 'intfc_port' => 'reset_i', - 'intfc_name' => 'plug:reset[0]', - 'range' => '' - }, - 'm_wb_dat_i' => { - 'range' => '31:0', - 'intfc_name' => 'plug:wb_master[0]', - 'intfc_port' => 'dat_i', - 'type' => 'input' - }, - 'md_pad_o' => { - 'range' => '', - 'intfc_name' => 'IO', - 'intfc_port' => 'IO', - 'type' => 'output' - }, - 'mcoll_pad_i' => { + 'mrxerr_pad_i' => { + 'type' => 'input', 'range' => '', 'intfc_name' => 'IO', - 'intfc_port' => 'IO', - 'type' => 'input' + 'intfc_port' => 'IO' }, - 'm_wb_stb_o' => { - 'range' => '', - 'intfc_name' => 'plug:wb_master[0]', - 'intfc_port' => 'stb_o', - 'type' => 'output' - }, - 'm_wb_err_i' => { - 'type' => 'input', - 'intfc_port' => 'err_i', - 'intfc_name' => 'plug:wb_master[0]', - 'range' => '' - }, - 'm_wb_cyc_o' => { - 'intfc_port' => 'cyc_o', - 'type' => 'output', - 'range' => '', - 'intfc_name' => 'plug:wb_master[0]' - }, - 'mtx_clk_pad_i' => { - 'intfc_port' => 'IO', - 'type' => 'input', - 'range' => '', - 'intfc_name' => 'IO' - }, - 'wb_err_o' => { - 'intfc_port' => 'err_o', + 'mtx_clk_pad_i' => { + 'type' => 'input', + 'range' => '', + 'intfc_name' => 'IO', + 'intfc_port' => 'IO' + }, + 'm_wb_stb_o' => { + 'intfc_port' => 'stb_o', + 'intfc_name' => 'plug:wb_master[0]', + 'type' => 'output', + 'range' => '' + }, + 'mcrs_pad_i' => { + 'type' => 'input', + 'range' => '', + 'intfc_name' => 'IO', + 'intfc_port' => 'IO' + }, + 'm_wb_dat_o' => { + 'intfc_port' => 'dat_o', + 'intfc_name' => 'plug:wb_master[0]', + 'type' => 'output', + 'range' => '31:0' + }, + 'm_wb_we_o' => { + 'intfc_port' => 'we_o', + 'range' => '', 'type' => 'output', - 'range' => '', - 'intfc_name' => 'plug:wb_slave[0]' + 'intfc_name' => 'plug:wb_master[0]' }, - 'wb_cyc_i' => { - 'intfc_name' => 'plug:wb_slave[0]', + 'mdc_pad_o' => { 'range' => '', - 'type' => 'input', - 'intfc_port' => 'cyc_i' + 'type' => 'output', + 'intfc_name' => 'IO', + 'intfc_port' => 'IO' }, - 'm_wb_dat_o' => { - 'range' => '31:0', - 'intfc_name' => 'plug:wb_master[0]', - 'intfc_port' => 'dat_o', - 'type' => 'output' - }, - 'mrxdv_pad_i' => { - 'intfc_port' => 'IO', - 'type' => 'input', - 'range' => '', - 'intfc_name' => 'IO' - }, - 'md_padoe_o' => { + 'mtxd_pad_o' => { + 'type' => 'output', + 'range' => '3:0', + 'intfc_name' => 'IO', + 'intfc_port' => 'IO' + }, + 'wb_stb_i' => { + 'intfc_port' => 'stb_i', + 'intfc_name' => 'plug:wb_slave[0]', + 'type' => 'input', + 'range' => '' + }, + 'md_pad_i' => { + 'intfc_name' => 'IO', + 'range' => '', + 'type' => 'input', + 'intfc_port' => 'IO' + }, + 'wb_ack_o' => { + 'range' => '', + 'type' => 'output', + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'ack_o' + }, + 'mcoll_pad_i' => { 'intfc_name' => 'IO', 'range' => '', - 'type' => 'output', + 'type' => 'input', 'intfc_port' => 'IO' }, - 'wb_dat_o' => { - 'range' => '31:0', - 'intfc_name' => 'plug:wb_slave[0]', - 'intfc_port' => 'dat_o', - 'type' => 'output' - }, - 'm_wb_ack_i' => { - 'range' => '', - 'intfc_name' => 'plug:wb_master[0]', - 'intfc_port' => 'ack_i', - 'type' => 'input' - }, - 'm_wb_we_o' => { - 'intfc_name' => 'plug:wb_master[0]', + 'm_wb_cyc_o' => { 'range' => '', 'type' => 'output', - 'intfc_port' => 'we_o' + 'intfc_name' => 'plug:wb_master[0]', + 'intfc_port' => 'cyc_o' }, - 'mrx_clk_pad_i' => { - 'intfc_port' => 'IO', - 'type' => 'input', - 'range' => '', - 'intfc_name' => 'IO' - }, - 'wb_sel_i' => { - 'intfc_name' => 'plug:wb_slave[0]', - 'range' => '3:0', - 'type' => 'input', - 'intfc_port' => 'sel_i' - }, - 'm_wb_sel_o' => { - 'type' => 'output', - 'intfc_port' => 'sel_o', - 'intfc_name' => 'plug:wb_master[0]', - 'range' => '3:0' - }, - 'mtxerr_pad_o' => { - 'range' => '', - 'intfc_name' => 'IO', - 'intfc_port' => 'IO', - 'type' => 'output' - }, - 'wb_we_i' => { + 'wb_cyc_i' => { 'intfc_name' => 'plug:wb_slave[0]', 'range' => '', 'type' => 'input', - 'intfc_port' => 'we_i' + 'intfc_port' => 'cyc_i' }, - 'mrxerr_pad_i' => { + 'wb_sel_i' => { + 'intfc_port' => 'sel_i', + 'intfc_name' => 'plug:wb_slave[0]', + 'range' => '3:0', + 'type' => 'input' + }, + 'wb_dat_i' => { + 'intfc_port' => 'dat_i', + 'intfc_name' => 'plug:wb_slave[0]', + 'range' => '31:0', + 'type' => 'input' + }, + 'md_padoe_o' => { + 'intfc_name' => 'IO', + 'type' => 'output', + 'range' => '', + 'intfc_port' => 'IO' + }, + 'mrx_clk_pad_i' => { + 'intfc_port' => 'IO', 'intfc_name' => 'IO', 'range' => '', - 'type' => 'input', - 'intfc_port' => 'IO' - }, - 'wb_adr_i' => { - 'type' => 'input', - 'intfc_port' => 'adr_i', - 'intfc_name' => 'plug:wb_slave[0]', - 'range' => '9:0' - }, - 'mrxd_pad_i' => { - 'type' => 'input', - 'intfc_port' => 'IO', - 'intfc_name' => 'IO', - 'range' => '3:0' - }, - 'md_pad_i' => { - 'intfc_name' => 'IO', - 'range' => '', - 'type' => 'input', - 'intfc_port' => 'IO' - } + 'type' => 'input' + } + }, + 'module_name' => 'ethtop', + 'unused' => { + 'plug:wb_master[0]' => [ + 'tag_o', + 'rty_i', + 'bte_o', + 'cti_o' + ], + 'plug:wb_slave[0]' => [ + 'cti_i', + 'bte_i', + 'rty_o', + 'tag_i' + ] }, - 'system_h' => ' + 'hdl_files' => [ + '/mpsoc/rtl/src_peripheral/ethmac' + ], + 'category' => 'Communication', + 'modules' => { + 'ethtop' => {} + }, + 'gui_status' => { + 'status' => 'ideal', + 'timeout' => 0 + }, + 'ports_order' => [ + 'wb_clk_i', + 'wb_rst_i', + 'wb_dat_i', + 'wb_dat_o', + 'wb_adr_i', + 'wb_sel_i', + 'wb_we_i', + 'wb_cyc_i', + 'wb_stb_i', + 'wb_ack_o', + 'wb_err_o', + 'm_wb_adr_o', + 'm_wb_sel_o', + 'm_wb_we_o', + 'm_wb_dat_o', + 'm_wb_dat_i', + 'm_wb_cyc_o', + 'm_wb_stb_o', + 'm_wb_ack_i', + 'm_wb_err_i', + 'mtx_clk_pad_i', + 'mtxd_pad_o', + 'mtxen_pad_o', + 'mtxerr_pad_o', + 'mrx_clk_pad_i', + 'mrxd_pad_i', + 'mrxdv_pad_i', + 'mrxerr_pad_i', + 'mcoll_pad_i', + 'mcrs_pad_i', + 'mdc_pad_o', + 'md_pad_i', + 'md_pad_o', + 'md_padoe_o', + 'int_o' + ], + 'system_c' => 'void ${IP}_recv_ack(void) +{ + ${IP}_rx_done = 0; + ${IP}_rx_len = 0; + //accept further data (reset RXBD to empty) + ${IP}_RXBD0L = RX_READY; //len = 0 | IRQ & WR = 1 | EMPTY = 1 +} -void ${IP}_init(); -void ${IP}_interrupt(); -void ${IP}_recv_ack(void); -int ${IP}_send(int length); //return (-1) or length (still processing previous) or asserted +void ${IP}_init() +{ + //TXEN & RXEN = 1; PAD & CRC = 1; FULLD = 1 + ${IP}_MODER = ETH_TXEN | ETH_RXEN | ETH_PAD | ETH_CRCEN | ETH_FULLD; + //PHY ADDR = 0x001 + ${IP}_MIIADDR = 0x00000001; -#define ${IP}_BASE_ADDR $BASE -#define ${IP}_MODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x00 ))) -#define ${IP}_INT_SOURCE (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x04 ))) -#define ${IP}_INT_MASK (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x08 ))) -#define ${IP}_IPGT (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x0C ))) -#define ${IP}_IPGR1 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x10 ))) -#define ${IP}_IPGR2 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x14 ))) -#define ${IP}_PACKETLEN (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x18 ))) -#define ${IP}_COLLCONF (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x1C ))) -#define ${IP}_TX_BD_NUM (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x20 ))) -#define ${IP}_CTRLMODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x24 ))) -#define ${IP}_MIIMODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x28 ))) -#define ${IP}_MIICOMMAND (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x2C ))) -#define ${IP}_MIIADDR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x30 ))) -#define ${IP}_MIITX_DATA (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x34 ))) -#define ${IP}_MIIRX_DATA (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x38 ))) -#define ${IP}_MIISTATUS (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x3C ))) -#define ${IP}_MAC_ADDR0 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x40 ))) -#define ${IP}_MAC_ADDR1 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x44 ))) -#define ${IP}_HASH0_ADR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x48 ))) -#define ${IP}_HASH1_ADR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x4C ))) -#define ${IP}_TXCTRL (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x50 ))) -#define ${IP}_TXBD0H (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x404 ))) -#define ${IP}_TXBD0L (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x400 ))) -#define ${IP}_RXBD0H (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x604 ))) //this depends on TX_BD_NUM but this is the standard value -#define ${IP}_RXBD0L (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x600 ))) //this depends on TX_BD_NUM but this is the standard value + //enable all interrupts + ${IP}_INT_MASK = ETH_RXB | ETH_TXB; + //set MAC ADDR + ${IP}_MAC_ADDR1 = (${IP}_MAC_ADDR_5 << 8) | ${IP}_MAC_ADDR_4; //low word = mac ADDR high word + ${IP}_MAC_ADDR0 = (${IP}_MAC_ADDR_3 << 24) | (${IP}_MAC_ADDR_2 << 16) + | (${IP}_MAC_ADDR_1 << 8) | ${IP}_MAC_ADDR_0; //mac ADDR rest -#include "${IP}.h"', - 'ip_name' => 'ethmac_100', - 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ethmac/ethtop.v', - 'ports_order' => [ - 'wb_clk_i', - 'wb_rst_i', - 'wb_dat_i', - 'wb_dat_o', - 'wb_adr_i', - 'wb_sel_i', - 'wb_we_i', - 'wb_cyc_i', - 'wb_stb_i', - 'wb_ack_o', - 'wb_err_o', - 'm_wb_adr_o', - 'm_wb_sel_o', - 'm_wb_we_o', - 'm_wb_dat_o', - 'm_wb_dat_i', - 'm_wb_cyc_o', - 'm_wb_stb_o', - 'm_wb_ack_i', - 'm_wb_err_i', - 'mtx_clk_pad_i', - 'mtxd_pad_o', - 'mtxen_pad_o', - 'mtxerr_pad_o', - 'mrx_clk_pad_i', - 'mrxd_pad_i', - 'mrxdv_pad_i', - 'mrxerr_pad_i', - 'mcoll_pad_i', - 'mcrs_pad_i', - 'mdc_pad_o', - 'md_pad_i', - 'md_pad_o', - 'md_padoe_o', - 'int_o' - ], - 'hdl_files' => [ - '/mpsoc/src_peripheral/ethmac/rtl/eth_clockgen.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_cop.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_crc.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_fifo.v', - '/mpsoc/src_peripheral/ethmac/rtl/ethmac.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_maccontrol.v', - '/mpsoc/src_peripheral/ethmac/rtl/ethmac_defines.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_macstatus.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_miim.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_outputcontrol.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_random.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_receivecontrol.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_register.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_registers.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_rxaddrcheck.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_rxcounters.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_rxethmac.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_rxstatem.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_shiftreg.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_spram_256x32.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_top.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_transmitcontrol.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_txcounters.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_txethmac.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_txstatem.v', - '/mpsoc/src_peripheral/ethmac/rtl/eth_wishbone.v', - '/mpsoc/src_peripheral/ethmac/rtl/timescale.v', - '/mpsoc/src_peripheral/ethmac/rtl/xilinx_dist_ram_16x32.v', - '/mpsoc/src_peripheral/ethmac/ethtop.v', - '/mpsoc/src_peripheral/ethmac/eth_generic_ram.v' - ], - 'parameters_order' => [ - 'TX_FIFO_DATA_WIDTH', - 'TX_FIFO_DEPTH', - 'TX_FIFO_CNT_WIDTH', - 'RX_FIFO_DATA_WIDTH', - 'RX_FIFO_DEPTH', - 'RX_FIFO_CNT_WIDTH' - ], - 'description' => 'The Ethernet MAC 10/100 Mbps. -For more information please check: https://opencores.org/project,ethmac', - 'gen_sw_files' => [ - '/mpsoc/src_peripheral/ethmac/ethfrename_sep_t${IP}.h' - ], - 'parameters' => { - 'RX_FIFO_DEPTH' => { - 'content' => '', - 'redefine_param' => 1, - 'default' => ' 16', - 'info' => undef, - 'type' => 'Fixed', - 'global_param' => 0 - }, - 'TX_FIFO_DEPTH' => { - 'content' => '', - 'redefine_param' => 1, - 'default' => ' 16', - 'info' => undef, - 'global_param' => 0, - 'type' => 'Fixed' - }, - 'RX_FIFO_DATA_WIDTH' => { - 'type' => 'Fixed', - 'global_param' => 0, - 'content' => '', - 'redefine_param' => 1, - 'info' => undef, - 'default' => ' 32' - }, - 'TX_FIFO_DATA_WIDTH' => { - 'redefine_param' => 1, - 'content' => '', - 'default' => ' 32', - 'info' => undef, - 'type' => 'Fixed', - 'global_param' => 0 - }, - 'RX_FIFO_CNT_WIDTH' => { - 'default' => ' 5', - 'redefine_param' => 1, - 'content' => '', - 'info' => undef, - 'global_param' => 0, - 'type' => 'Fixed' - }, - 'TX_FIFO_CNT_WIDTH' => { - 'type' => 'Fixed', - 'global_param' => 0, - 'info' => undef, - 'redefine_param' => 1, - 'content' => '', - 'default' => ' 5' - } - }, - 'sw_files' => [], - 'gui_status' => { - 'status' => 'ideal', - 'timeout' => 0 - }, - 'custom_file' => { - '0' => {} - }, - 'category' => 'Communication', - 'modules' => { - 'ethtop' => {} - } - }, 'ip_gen' ); + //configure TXBD0 + ${IP}_TXBD0H = (unsigned long) ${IP}_tx_packet; //ADDR used for tx_data + ${IP}_TXBD0L = TX_READY; //length = 0 | PAD & CRC = 1 | IRQ & WR = 1 + + //configure RXBD0 + ${IP}_RXBD0H = (unsigned long)${IP}_rx_packet; //ADDR used for tx_data + ${IP}_RXBD0L = RX_READY; //len = 0 | IRQ & WR = 1 | EMPTY = 1 + + //set txdata + ${IP}_tx_packet[0] = ${IP}_BROADCAST_ADDR_5; + ${IP}_tx_packet[1] = ${IP}_BROADCAST_ADDR_4; + ${IP}_tx_packet[2] = ${IP}_BROADCAST_ADDR_3; + ${IP}_tx_packet[3] = ${IP}_BROADCAST_ADDR_2; + ${IP}_tx_packet[4] = ${IP}_BROADCAST_ADDR_1; + ${IP}_tx_packet[5] = ${IP}_BROADCAST_ADDR_0; + + ${IP}_tx_packet[6] = ${IP}_MAC_ADDR_5; + ${IP}_tx_packet[7] = ${IP}_MAC_ADDR_4; + ${IP}_tx_packet[8] = ${IP}_MAC_ADDR_3; + ${IP}_tx_packet[9] = ${IP}_MAC_ADDR_2; + ${IP}_tx_packet[10] = ${IP}_MAC_ADDR_1; + ${IP}_tx_packet[11] = ${IP}_MAC_ADDR_0; + + //erase interrupts + ${IP}_INT_SOURCE = ETH_RXC | ETH_TXC | ETH_BUSY | ETH_RXE | ETH_RXB | ETH_TXE | ETH_TXB; + + ${IP}_tx_done = 1; + ${IP}_rx_done = 0; + ${IP}_rx_len = 0; + ${IP}_tx_data = & ${IP}_tx_packet[HDR_LEN]; + ${IP}_rx_data = & ${IP}_rx_packet[HDR_LEN]; +} + + +int ${IP}_send(int length) +{ + if (!${IP}_tx_done) //if previous command not fully processed, bail out + return -1; + + ${IP}_tx_done = 0; + ${IP}_tx_packet[12] = length >> 8; + ${IP}_tx_packet[13] = length; + + ${IP}_TXBD0L = (( 0x0000FFFF & ( length + HDR_LEN ) ) << 16) | BD_SND; + + return length; +} + +void ${IP}_interrupt() +{ + unsigned long source = ${IP}_INT_SOURCE; + if ( source & ETH_TXB ) + { + ${IP}_tx_done = 1; + //erase interrupt + ${IP}_INT_SOURCE |= ETH_TXB; + } + if ( source & ETH_RXB ) + { + ${IP}_rx_done = 1; + ${IP}_rx_len = (${IP}_RXBD0L >> 16) - HDR_LEN - CRC_LEN; + //erase interrupt + ${IP}_INT_SOURCE |= ETH_RXB; + } +}' + }, 'ip_gen' );

/source_probe.IP